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authorZhangfei Gao <zhangfei.gao@linaro.org>2017-06-14 23:04:02 -0400
committerWei Xu <xuwei5@hisilicon.com>2017-06-15 06:50:22 -0400
commit5f8a3b77a7cd4e80e2bd728718b8e1ebdd0b2c2c (patch)
tree1b699d68035a4673cb9c0025e45ff4bcaa4b9585
parenta4e36ae0fb33b0befbe0f102e38fd0f280825d65 (diff)
arm64: dts: Add I2C nodes for Hi3660
Add I2C nodes for Hi3660-hikey960. On HiKey960, I2C0, I2C7 are connected to Low Speed Expansion Connector. I2C1 is connected to ADV7535. I2C3 is connected to USB5734. Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts22
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3660.dtsi56
2 files changed, 78 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 64875a5166de..1a4d6c5bfd38 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -29,6 +29,28 @@
29 }; 29 };
30}; 30};
31 31
32&i2c0 {
33 /* On Low speed expansion */
34 label = "LS-I2C0";
35 status = "okay";
36};
37
38&i2c1 {
39 status = "okay";
40
41 adv7533: adv7533@39 {
42 status = "ok";
43 compatible = "adi,adv7533";
44 reg = <0x39>;
45 };
46};
47
48&i2c7 {
49 /* On Low speed expansion */
50 label = "LS-I2C1";
51 status = "okay";
52};
53
32&uart5 { 54&uart5 {
33 status = "okay"; 55 status = "okay";
34}; 56};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index f55710a355bf..9abe84e69726 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -186,6 +186,62 @@
186 #reset-cells = <2>; 186 #reset-cells = <2>;
187 }; 187 };
188 188
189 i2c0: i2c@ffd71000 {
190 compatible = "snps,designware-i2c";
191 reg = <0x0 0xffd71000 0x0 0x1000>;
192 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 clock-frequency = <400000>;
196 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
197 resets = <&iomcu_rst 0x20 3>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
200 status = "disabled";
201 };
202
203 i2c1: i2c@ffd72000 {
204 compatible = "snps,designware-i2c";
205 reg = <0x0 0xffd72000 0x0 0x1000>;
206 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 clock-frequency = <400000>;
210 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
211 resets = <&iomcu_rst 0x20 4>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
214 status = "disabled";
215 };
216
217 i2c3: i2c@fdf0c000 {
218 compatible = "snps,designware-i2c";
219 reg = <0x0 0xfdf0c000 0x0 0x1000>;
220 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
221 #address-cells = <1>;
222 #size-cells = <0>;
223 clock-frequency = <400000>;
224 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
225 resets = <&crg_rst 0x78 7>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
228 status = "disabled";
229 };
230
231 i2c7: i2c@fdf0b000 {
232 compatible = "snps,designware-i2c";
233 reg = <0x0 0xfdf0b000 0x0 0x1000>;
234 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 clock-frequency = <400000>;
238 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
239 resets = <&crg_rst 0x60 14>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
242 status = "disabled";
243 };
244
189 uart5: serial@fdf05000 { 245 uart5: serial@fdf05000 {
190 compatible = "arm,pl011", "arm,primecell"; 246 compatible = "arm,pl011", "arm,primecell";
191 reg = <0x0 0xfdf05000 0x0 0x1000>; 247 reg = <0x0 0xfdf05000 0x0 0x1000>;