Merge tag 'v4.10-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt64

For mt8173:
- set mm_sel clock to 400 MHz to support 4K HDMI
- adjust power efficiency between the little and big cores
- add a node for thermal calibration via e-fuse data

* tag 'v4.10-next-dts' of https://github.com/mbgg/linux-mediatek:
  arm64: dts: mt8173: add node for thermal calibration
  arm64: dts: mt8173: Fix cpu_thermal cooling-maps contributions
  arm64: dts: mt8173: add mmsel clocks for 4K support

Signed-off-by: Olof Johansson <olof@lixom.net>

1 files changed, 11 insertions, 2 deletions

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 12e702771f5c..d80ddb4a4a05 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -182,12 +182,12 @@
                                 map@0 {
                                         trip = <&target>;
                                         cooling-device = <&cpu0 0 0>;
-                                        contribution = <1024>;
+                                        contribution = <3072>;
                                 };
                                 map@1 {
                                         trip = <&target>;
                                         cooling-device = <&cpu2 0 0>;
-                                        contribution = <2048>;
+                                        contribution = <1024>;
                                 };
                         };
                 };
@@ -401,6 +401,11 @@
                 efuse: efuse@10206000 {
                         compatible = "mediatek,mt8173-efuse";
                         reg = <0 0x10206000 0 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        thermal_calibration: calib@528 {
+                                reg = <0x528 0xc>;
+                        };
                 };
 
                 apmixedsys: clock-controller@10209000 {
@@ -574,6 +579,8 @@
                         resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
                         mediatek,auxadc = <&auxadc>;
                         mediatek,apmixedsys = <&apmixedsys>;
+                        nvmem-cells = <&thermal_calibration>;
+                        nvmem-cell-names = "calibration-data";
                 };
 
                 nor_flash: spi@1100d000 {
@@ -778,6 +785,8 @@
                         compatible = "mediatek,mt8173-mmsys", "syscon";
                         reg = <0 0x14000000 0 0x1000>;
                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+                        assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
+                        assigned-clock-rates = <400000000>;
                         #clock-cells = <1>;
                 };