dmaengine: cppi41: init_sched(): Get number of channels from DT

Despite the driver is already using DT to get the number of channels,
init_sched() is using an hardcoded value to get it.
Use DT to get the number of channels.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

1 files changed, 12 insertions, 8 deletions

diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index 676228ff71de..54337cd0afcc 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -139,6 +139,8 @@ struct cppi41_dd {
         struct chan_queues td_queue;
         u16 first_completion_queue;
         u16 qmgr_num_pend;
+        u32 n_chans;
+        u8 platform;
 
         struct list_head pending;       /* Pending queued transfers */
         spinlock_t lock;                /* Lock for pending list */
@@ -742,13 +744,8 @@ static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
 {
         struct cppi41_channel *cchan;
         int i;
-        int ret;
-        u32 n_chans;
+        u32 n_chans = cdd->n_chans;
 
-        ret = of_property_read_u32(dev->of_node, "#dma-channels",
-                        &n_chans);
-        if (ret)
-                return ret;
         /*
          * The channels can only be used as TX or as RX. So we add twice
          * that much dma channels because USB can only do RX or TX.
@@ -862,7 +859,7 @@ static void init_sched(struct cppi41_dd *cdd)
 
         word = 0;
         cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
-        for (ch = 0; ch < 15 * 2; ch += 2) {
+        for (ch = 0; ch < cdd->n_chans; ch += 2) {
 
                 reg = SCHED_ENTRY0_CHAN(ch);
                 reg |= SCHED_ENTRY1_CHAN(ch) | SCHED_ENTRY1_IS_RX;
@@ -872,7 +869,7 @@ static void init_sched(struct cppi41_dd *cdd)
                 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word));
                 word++;
         }
-        reg = 15 * 2 * 2 - 1;
+        reg = cdd->n_chans * 2 - 1;
         reg |= DMA_SCHED_CTRL_EN;
         cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
 }
@@ -897,6 +894,7 @@ static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
 
         cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
         init_sched(cdd);
+
         return 0;
 err_td:
         deinit_cppi41(dev, cdd);
@@ -1058,6 +1056,11 @@ static int cppi41_dma_probe(struct platform_device *pdev)
         cdd->qmgr_num_pend = glue_info->qmgr_num_pend;
         cdd->first_completion_queue = glue_info->first_completion_queue;
 
+        ret = of_property_read_u32(dev->of_node,
+                                   "#dma-channels", &cdd->n_chans);
+        if (ret)
+                goto err_get_n_chans;
+
         ret = init_cppi41(dev, cdd);
         if (ret)
                 goto err_init_cppi;
@@ -1100,6 +1103,7 @@ err_chans:
         deinit_cppi41(dev, cdd);
 err_init_cppi:
         pm_runtime_dont_use_autosuspend(dev);
+err_get_n_chans:
 err_get_sync:
         pm_runtime_put_sync(dev);
         pm_runtime_disable(dev);