diff options
author | Christian Lamparter <chunkeey@gmail.com> | 2019-03-21 20:05:01 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2019-03-26 13:47:10 -0400 |
commit | 5e07321f3388e6f2b13c43ae9df3e09efa8418e0 (patch) | |
tree | 21713ad1326b2721b1b9e04089ac67d8984dccd0 | |
parent | fb1eb41a3dd4cfff274c98f3c3324ab329641298 (diff) |
dt-bindings: net: dsa: qca8k: support internal mdio-bus
This patch updates the qca8k's binding to document to the
approach for using the internal mdio-bus of the supported
qca8k switches.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | Documentation/devicetree/bindings/net/dsa/qca8k.txt | 69 |
1 files changed, 64 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 5eda99e6c86e..93a7469e70d4 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt | |||
@@ -12,10 +12,15 @@ Required properties: | |||
12 | Subnodes: | 12 | Subnodes: |
13 | 13 | ||
14 | The integrated switch subnode should be specified according to the binding | 14 | The integrated switch subnode should be specified according to the binding |
15 | described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of | 15 | described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external |
16 | port and PHY id, each subnode describing a port needs to have a valid phandle | 16 | mdio-bus each subnode describing a port needs to have a valid phandle |
17 | referencing the internal PHY connected to it. The CPU port of this switch is | 17 | referencing the internal PHY it is connected to. This is because there's no |
18 | always port 0. | 18 | N:N mapping of port and PHY id. |
19 | |||
20 | Don't use mixed external and internal mdio-bus configurations, as this is | ||
21 | not supported by the hardware. | ||
22 | |||
23 | The CPU port of this switch is always port 0. | ||
19 | 24 | ||
20 | A CPU port node has the following optional node: | 25 | A CPU port node has the following optional node: |
21 | 26 | ||
@@ -31,8 +36,9 @@ For QCA8K the 'fixed-link' sub-node supports only the following properties: | |||
31 | - 'full-duplex' (boolean, optional), to indicate that full duplex is | 36 | - 'full-duplex' (boolean, optional), to indicate that full duplex is |
32 | used. When absent, half duplex is assumed. | 37 | used. When absent, half duplex is assumed. |
33 | 38 | ||
34 | Example: | 39 | Examples: |
35 | 40 | ||
41 | for the external mdio-bus configuration: | ||
36 | 42 | ||
37 | &mdio0 { | 43 | &mdio0 { |
38 | phy_port1: phy@0 { | 44 | phy_port1: phy@0 { |
@@ -108,3 +114,56 @@ Example: | |||
108 | }; | 114 | }; |
109 | }; | 115 | }; |
110 | }; | 116 | }; |
117 | |||
118 | for the internal master mdio-bus configuration: | ||
119 | |||
120 | &mdio0 { | ||
121 | switch@10 { | ||
122 | compatible = "qca,qca8337"; | ||
123 | #address-cells = <1>; | ||
124 | #size-cells = <0>; | ||
125 | |||
126 | reg = <0x10>; | ||
127 | |||
128 | ports { | ||
129 | #address-cells = <1>; | ||
130 | #size-cells = <0>; | ||
131 | |||
132 | port@0 { | ||
133 | reg = <0>; | ||
134 | label = "cpu"; | ||
135 | ethernet = <&gmac1>; | ||
136 | phy-mode = "rgmii"; | ||
137 | fixed-link { | ||
138 | speed = 1000; | ||
139 | full-duplex; | ||
140 | }; | ||
141 | }; | ||
142 | |||
143 | port@1 { | ||
144 | reg = <1>; | ||
145 | label = "lan1"; | ||
146 | }; | ||
147 | |||
148 | port@2 { | ||
149 | reg = <2>; | ||
150 | label = "lan2"; | ||
151 | }; | ||
152 | |||
153 | port@3 { | ||
154 | reg = <3>; | ||
155 | label = "lan3"; | ||
156 | }; | ||
157 | |||
158 | port@4 { | ||
159 | reg = <4>; | ||
160 | label = "lan4"; | ||
161 | }; | ||
162 | |||
163 | port@5 { | ||
164 | reg = <5>; | ||
165 | label = "wan"; | ||
166 | }; | ||
167 | }; | ||
168 | }; | ||
169 | }; | ||