arm64: entry: Apply BP hardening for high-priority synchronous exceptions

Software-step and PC alignment fault exceptions have higher priority than
instruction abort exceptions, so apply the BP hardening hooks there too
if the user PC appears to reside in kernel space.

Reported-by: Dan Hettena <dhettena@nvidia.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

2 files changed, 13 insertions, 1 deletions

diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 4dd1b5a46642..af22793103af 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -767,7 +767,10 @@ el0_sp_pc:
          * Stack or PC alignment exception handling
          */
         mrs     x26, far_el1
-        enable_daif
+        enable_da_f
+#ifdef CONFIG_TRACE_IRQFLAGS
+        bl      trace_hardirqs_off
+#endif
         ct_user_exit
         mov     x0, x26
         mov     x1, x25
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index af530eb9f2ed..43b28a782ed4 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -732,6 +732,12 @@ asmlinkage void __exception do_sp_pc_abort(unsigned long addr,
         struct siginfo info;
         struct task_struct *tsk = current;
 
+        if (user_mode(regs)) {
+                if (instruction_pointer(regs) > TASK_SIZE)
+                        arm64_apply_bp_hardening();
+                local_irq_enable();
+        }
+
         if (show_unhandled_signals && unhandled_signal(tsk, SIGBUS))
                 pr_info_ratelimited("%s[%d]: %s exception: pc=%p sp=%p\n",
                                     tsk->comm, task_pid_nr(tsk),
@@ -791,6 +797,9 @@ asmlinkage int __exception do_debug_exception(unsigned long addr,
         if (interrupts_enabled(regs))
                 trace_hardirqs_off();
 
+        if (user_mode(regs) && instruction_pointer(regs) > TASK_SIZE)
+                arm64_apply_bp_hardening();
+
         if (!inf->fn(addr, esr, regs)) {
                 rv = 1;
         } else {