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authorStephen Boyd <stephen.boyd@linaro.org>2016-05-10 18:01:49 -0400
committerAndy Gross <andy.gross@linaro.org>2016-06-12 01:48:11 -0400
commit5daa7a6031bd04b7ff94e92ccc1fcb161df12686 (patch)
tree4e6544eb2170fd5d70b6a85c9e949fe71690ac54
parenta0df399feec49fb7d5cfef325d082ceefc6e613a (diff)
arm64: dts: qcom: Add msm8916 PMU node
Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 30297730545f..e3ff3ba5b3d3 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -115,6 +115,11 @@
115 method = "smc"; 115 method = "smc";
116 }; 116 };
117 117
118 pmu {
119 compatible = "arm,armv8-pmuv3";
120 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
121 };
122
118 timer { 123 timer {
119 compatible = "arm,armv8-timer"; 124 compatible = "arm,armv8-timer";
120 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 125 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,