Merge tag 'v3.19-rc2' into for-3.20/core

Linux 3.19-rc2

278 files changed, 7904 insertions, 4322 deletions

diff --git a/.gitignore b/.gitignore
index e213b27f3921..ce57b79670a5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -96,3 +96,6 @@ x509.genkey
 
 # Kconfig presets
 all.config
+
+# Kdevelop4
+*.kdev4
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index 1fee72f4d331..4ff84623d5e1 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -74,7 +74,7 @@ the operations defined in clk.h:
                 long            (*determine_rate)(struct clk_hw *hw,
                                                 unsigned long rate,
                                                 unsigned long *best_parent_rate,
-                                                struct clk **best_parent_clk);
+                                                struct clk_hw **best_parent_clk);
                 int             (*set_parent)(struct clk_hw *hw, u8 index);
                 u8              (*get_parent)(struct clk_hw *hw);
                 int             (*set_rate)(struct clk_hw *hw,
diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
new file mode 100644
index 000000000000..847d98bae8cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
@@ -0,0 +1,38 @@
+* Samsung Exynos4415 Clock Controller
+
+The Exynos4415 clock controller generates and supplies clock to various
+consumer devices within the Exynos4415 SoC.
+
+Required properties:
+
+- compatible: should be one of the following:
+  - "samsung,exynos4415-cmu" - for the main system clocks controller
+    (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
+  - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
+    Controller (DMC) domain clock controller.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos4415.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+        cmu: clock-controller@10030000 {
+                compatible = "samsung,exynos4415-cmu";
+                reg = <0x10030000 0x18000>;
+                #clock-cells = <1>;
+        };
+
+        cmu-dmc: clock-controller@105C0000 {
+                compatible = "samsung,exynos4415-cmu-dmc";
+                reg = <0x105C0000 0x3000>;
+                #clock-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
new file mode 100644
index 000000000000..6d3d5f80c1c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -0,0 +1,93 @@
+* Samsung Exynos7 Clock Controller
+
+Exynos7 clock controller has various blocks which are instantiated
+independently from the device-tree. These clock controllers
+generate and supply clocks to various hardware blocks within
+the SoC.
+
+Each clock is assigned an identifier and client nodes can use
+this identifier to specify the clock which they consume. All
+available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos7-clk.h header and can be used in
+device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - "fin_pll" - PLL input clock from XXTI
+
+Required Properties for Clock Controller:
+
+ - compatible: clock controllers will use one of the following
+        compatible strings to indicate the clock controller
+        functionality.
+
+        - "samsung,exynos7-clock-topc"
+        - "samsung,exynos7-clock-top0"
+        - "samsung,exynos7-clock-top1"
+        - "samsung,exynos7-clock-ccore"
+        - "samsung,exynos7-clock-peric0"
+        - "samsung,exynos7-clock-peric1"
+        - "samsung,exynos7-clock-peris"
+        - "samsung,exynos7-clock-fsys0"
+        - "samsung,exynos7-clock-fsys1"
+
+ - reg: physical base address of the controller and the length of
+        memory mapped region.
+
+ - #clock-cells: should be 1.
+
+ - clocks: list of clock identifiers which are fed as the input to
+        the given clock controller. Please refer the next section to
+        find the input clocks for a given controller.
+
+- clock-names: list of names of clocks which are fed as the input
+        to the given clock controller.
+
+Input clocks for top0 clock controller:
+        - fin_pll
+        - dout_sclk_bus0_pll
+        - dout_sclk_bus1_pll
+        - dout_sclk_cc_pll
+        - dout_sclk_mfc_pll
+
+Input clocks for top1 clock controller:
+        - fin_pll
+        - dout_sclk_bus0_pll
+        - dout_sclk_bus1_pll
+        - dout_sclk_cc_pll
+        - dout_sclk_mfc_pll
+
+Input clocks for ccore clock controller:
+        - fin_pll
+        - dout_aclk_ccore_133
+
+Input clocks for peric0 clock controller:
+        - fin_pll
+        - dout_aclk_peric0_66
+        - sclk_uart0
+
+Input clocks for peric1 clock controller:
+        - fin_pll
+        - dout_aclk_peric1_66
+        - sclk_uart1
+        - sclk_uart2
+        - sclk_uart3
+
+Input clocks for peris clock controller:
+        - fin_pll
+        - dout_aclk_peris_66
+
+Input clocks for fsys0 clock controller:
+        - fin_pll
+        - dout_aclk_fsys0_200
+        - dout_sclk_mmc2
+
+Input clocks for fsys1 clock controller:
+        - fin_pll
+        - dout_aclk_fsys1_200
+        - dout_sclk_mmc0
+        - dout_sclk_mmc1
diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt
new file mode 100644
index 000000000000..af376a01f2b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt
@@ -0,0 +1,21 @@
+* Marvell MMP2 Clock Controller
+
+The MMP2 clock subsystem generates and supplies clock to various
+controllers within the MMP2 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 3 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell-mmp2.h>.
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa168.txt b/Documentation/devicetree/bindings/clock/marvell,pxa168.txt
new file mode 100644
index 000000000000..c62eb1d173a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,pxa168.txt
@@ -0,0 +1,21 @@
+* Marvell PXA168 Clock Controller
+
+The PXA168 clock subsystem generates and supplies clock to various
+controllers within the PXA168 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,pxa168-clock" - controller compatible with PXA168 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 3 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>.
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa910.txt b/Documentation/devicetree/bindings/clock/marvell,pxa910.txt
new file mode 100644
index 000000000000..d9f41f3c03a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,pxa910.txt
@@ -0,0 +1,21 @@
+* Marvell PXA910 Clock Controller
+
+The PXA910 clock subsystem generates and supplies clock to various
+controllers within the PXA910 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 4 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
index 952e373178d2..054f65f9319c 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -7,11 +7,16 @@ to 64.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
+    - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
     - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
     - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
+    - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
     - "renesas,cpg-div6-clock" for generic DIV6 clocks
   - reg: Base address and length of the memory resource used by the DIV6 clock
-  - clocks: Reference to the parent clock
+  - clocks: Reference to the parent clock(s); either one, four, or eight
+    clocks must be specified.  For clocks with multiple parents, invalid
+    settings must be specified as "<0>".
   - #clock-cells: Must be 0
   - clock-output-names: The name of the clock as a free-form string
 
@@ -19,10 +24,11 @@ Required Properties:
 Example
 -------
 
-        sd2_clk: sd2_clk@e6150078 {
-                compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
-                reg = <0 0xe6150078 0 4>;
-                clocks = <&pll1_div2_clk>;
+        sdhi2_clk: sdhi2_clk@e615007c {
+                compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                reg = <0 0xe615007c 0 4>;
+                clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                         <0>, <&extal2_clk>;
                 #clock-cells = <0>;
-                clock-output-names = "sd2";
+                clock-output-names = "sdhi2ck";
         };
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index a5f52238c80d..2e18676bd4b5 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -26,11 +26,11 @@ Required Properties:
     must appear in the same order as the output clocks.
   - #clock-cells: Must be 1
   - clock-output-names: The name of the clocks as free-form strings
-  - renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
+  - clock-indices: Indices of the gate clocks into the group (0 to 31)
 
-The clocks, clock-output-names and renesas,clock-indices properties contain one
-entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
-gate clocks must not be declared.
+The clocks, clock-output-names and clock-indices properties contain one entry
+per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
+clocks must not be declared.
 
 
 Example
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index ed116df9c3e7..67b2b99f2b33 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -10,14 +10,17 @@ Required properties:
         "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
         "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+        "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
         "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
         "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
+        "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
         "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
         "allwinner,sun4i-a10-axi-clk" - for the AXI clock
         "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
         "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
         "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
+        "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
         "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
@@ -26,24 +29,29 @@ Required properties:
         "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
         "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
+        "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
+        "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
+        "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
         "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
         "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
         "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
+        "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
         "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
         "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
         "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
+        "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
         "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
-        "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
+        "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
         "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
         "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
         "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
-        "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
+        "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
         "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
         "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
@@ -63,8 +71,9 @@ Required properties for all clocks:
         multiplexed clocks, the list order must match the hardware
         programming order.
 - #clock-cells : from common clock binding; shall be set to 0 except for
-        "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
-        "allwinner,sun4i-pll6-clk" where it shall be set to 1
+        the following compatibles where it shall be set to 1:
+        "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
+        "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"
 - clock-output-names : shall be the corresponding names of the outputs.
         If the clock module only has one output, the name shall be the
         module name.
@@ -79,6 +88,12 @@ Clock consumers should specify the desired clocks they use with a
 "clocks" phandle cell. Consumers that are using a gated clock should
 provide an additional ID in their clock property. This ID is the
 offset of the bit controlling this particular gate in the register.
+For the other clocks with "#clock-cells" = 1, the additional ID shall
+refer to the index of the output.
+
+For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
+is the normal PLL6 output, or "pll6". The second output is rate doubled
+PLL6, or "pll6x2".
 
 For example:
 
@@ -106,6 +121,14 @@ pll5: clk@01c20020 {
         clock-output-names = "pll5_ddr", "pll5_other";
 };
 
+pll6: clk@01c20028 {
+        #clock-cells = <1>;
+        compatible = "allwinner,sun6i-a31-pll6-clk";
+        reg = <0x01c20028 0x4>;
+        clocks = <&osc24M>;
+        clock-output-names = "pll6", "pll6x2";
+};
+
 cpu: cpu@01c20054 {
         #clock-cells = <0>;
         compatible = "allwinner,sun4i-a10-cpu-clk";
diff --git a/MAINTAINERS b/MAINTAINERS
index 08f671dad3e9..ddb9ac8d32b3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2576,8 +2576,9 @@ F:	drivers/media/platform/coda/
 
 COMMON CLK FRAMEWORK
 M:      Mike Turquette <mturquette@linaro.org>
+M:      Stephen Boyd <sboyd@codeaurora.org>
 L:      linux-kernel@vger.kernel.org
-T:      git git://git.linaro.org/people/mturquette/linux.git
+T:      git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
 S:      Maintained
 F:      drivers/clk/
 X:      drivers/clk/clkdev.c
diff --git a/Makefile b/Makefile
index fd80c6e9bc23..ef748e17702f 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
-PATCHLEVEL = 18
+PATCHLEVEL = 19
 SUBLEVEL = 0
-EXTRAVERSION =
+EXTRAVERSION = -rc2
 NAME = Diseased Newt
 
 # *DOCUMENTATION*
@@ -481,9 +481,10 @@ asm-generic:
 # of make so .config is not included in this case either (for *config).
 
 version_h := include/generated/uapi/linux/version.h
+old_version_h := include/linux/version.h
 
 no-dot-config-targets := clean mrproper distclean \
-                         cscope gtags TAGS tags help %docs check% coccicheck \
+                         cscope gtags TAGS tags help% %docs check% coccicheck \
                          $(version_h) headers_% archheaders archscripts \
                          kernelversion %src-pkg
 
@@ -1005,6 +1006,7 @@ endef
 
 $(version_h): $(srctree)/Makefile FORCE
         $(call filechk,version.h)
+        $(Q)rm -f $(old_version_h)
 
 include/generated/utsrelease.h: include/config/kernel.release FORCE
         $(call filechk,utsrelease.h)
@@ -1036,8 +1038,6 @@ firmware_install: FORCE
 #Default location for installed headers
 export INSTALL_HDR_PATH = $(objtree)/usr
 
-hdr-inst := -rR -f $(srctree)/scripts/Makefile.headersinst obj
-
 # If we do an all arch process set dst to asm-$(hdr-arch)
 hdr-dst = $(if $(KBUILD_HEADERS), dst=include/asm-$(hdr-arch), dst=include/asm)
 
@@ -1175,7 +1175,7 @@ MRPROPER_FILES += .config .config.old .version .old_version $(version_h) \
                   Module.symvers tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
                   signing_key.priv signing_key.x509 x509.genkey         \
                   extra_certificates signing_key.x509.keyid             \
-                  signing_key.x509.signer include/linux/version.h
+                  signing_key.x509.signer
 
 # clean - Delete most, but leave enough to build external modules
 #
@@ -1235,7 +1235,7 @@ rpm: include/config/kernel.release FORCE
 # ---------------------------------------------------------------------------
 
 boards := $(wildcard $(srctree)/arch/$(SRCARCH)/configs/*_defconfig)
-boards := $(notdir $(boards))
+boards := $(sort $(notdir $(boards)))
 board-dirs := $(dir $(wildcard $(srctree)/arch/$(SRCARCH)/configs/*/*_defconfig))
 board-dirs := $(sort $(notdir $(board-dirs:/=)))
 
@@ -1326,7 +1326,7 @@ help-board-dirs := $(addprefix help-,$(board-dirs))
 
 help-boards: $(help-board-dirs)
 
-boards-per-dir = $(notdir $(wildcard $(srctree)/arch/$(SRCARCH)/configs/$*/*_defconfig))
+boards-per-dir = $(sort $(notdir $(wildcard $(srctree)/arch/$(SRCARCH)/configs/$*/*_defconfig)))
 
 $(help-board-dirs): help-%:
         @echo  'Architecture specific targets ($(SRCARCH) $*):'
@@ -1581,11 +1581,6 @@ ifneq ($(cmd_files),)
   include $(cmd_files)
 endif
 
-# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir
-# Usage:
-# $(Q)$(MAKE) $(clean)=dir
-clean := -f $(srctree)/scripts/Makefile.clean obj
-
 endif   # skip-makefile
 
 PHONY += FORCE
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6a3d9a6c4497..91bd5bd62857 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -177,6 +177,9 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
 dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
+dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \
+        pxa910-dkb.dtb \
+        mmp2-brownstone.dtb
 dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
 dtb-$(CONFIG_ARCH_MXC) += \
         imx1-ads.dtb \
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
index 7f70a39459f6..350208c5e1ed 100644
--- a/arch/arm/boot/dts/mmp2-brownstone.dts
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "mmp2.dtsi"
+#include "mmp2.dtsi"
 
 / {
         model = "Marvell MMP2 Brownstone Development Board";
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 4e8b08c628c7..766bbb8495b6 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -7,7 +7,8 @@
  *  publishhed by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/marvell,mmp2.h>
 
 / {
         aliases {
@@ -135,6 +136,8 @@
                                 compatible = "mrvl,mmp-uart";
                                 reg = <0xd4030000 0x1000>;
                                 interrupts = <27>;
+                                clocks = <&soc_clocks MMP2_CLK_UART0>;
+                                resets = <&soc_clocks MMP2_CLK_UART0>;
                                 status = "disabled";
                         };
 
@@ -142,6 +145,8 @@
                                 compatible = "mrvl,mmp-uart";
                                 reg = <0xd4017000 0x1000>;
                                 interrupts = <28>;
+                                clocks = <&soc_clocks MMP2_CLK_UART1>;
+                                resets = <&soc_clocks MMP2_CLK_UART1>;
                                 status = "disabled";
                         };
 
@@ -149,6 +154,8 @@
                                 compatible = "mrvl,mmp-uart";
                                 reg = <0xd4018000 0x1000>;
                                 interrupts = <24>;
+                                clocks = <&soc_clocks MMP2_CLK_UART2>;
+                                resets = <&soc_clocks MMP2_CLK_UART2>;
                                 status = "disabled";
                         };
 
@@ -156,6 +163,8 @@
                                 compatible = "mrvl,mmp-uart";
                                 reg = <0xd4016000 0x1000>;
                                 interrupts = <46>;
+                                clocks = <&soc_clocks MMP2_CLK_UART3>;
+                                resets = <&soc_clocks MMP2_CLK_UART3>;
                                 status = "disabled";
                         };
 
@@ -168,6 +177,8 @@
                                 #gpio-cells = <2>;
                                 interrupts = <49>;
                                 interrupt-names = "gpio_mux";
+                                clocks = <&soc_clocks MMP2_CLK_GPIO>;
+                                resets = <&soc_clocks MMP2_CLK_GPIO>;
                                 interrupt-controller;
                                 #interrupt-cells = <1>;
                                 ranges;
@@ -201,6 +212,8 @@
                                 compatible = "mrvl,mmp-twsi";
                                 reg = <0xd4011000 0x1000>;
                                 interrupts = <7>;
+                                clocks = <&soc_clocks MMP2_CLK_TWSI0>;
+                                resets = <&soc_clocks MMP2_CLK_TWSI0>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 mrvl,i2c-fast-mode;
@@ -211,6 +224,8 @@
                                 compatible = "mrvl,mmp-twsi";
                                 reg = <0xd4025000 0x1000>;
                                 interrupts = <58>;
+                                clocks = <&soc_clocks MMP2_CLK_TWSI1>;
+                                resets = <&soc_clocks MMP2_CLK_TWSI1>;
                                 status = "disabled";
                         };
 
@@ -220,8 +235,20 @@
                                 interrupts = <1 0>;
                                 interrupt-names = "rtc 1Hz", "rtc alarm";
                                 interrupt-parent = <&intcmux5>;
+                                clocks = <&soc_clocks MMP2_CLK_RTC>;
+                                resets = <&soc_clocks MMP2_CLK_RTC>;
                                 status = "disabled";
                         };
                 };
+
+                soc_clocks: clocks{
+                        compatible = "marvell,mmp2-clock";
+                        reg = <0xd4050000 0x1000>,
+                              <0xd4282800 0x400>,
+                              <0xd4015000 0x1000>;
+                        reg-names = "mpmu", "apmu", "apbc";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
index e762facb3fa4..0a988b3fb248 100644
--- a/arch/arm/boot/dts/pxa168-aspenite.dts
+++ b/arch/arm/boot/dts/pxa168-aspenite.dts
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "pxa168.dtsi"
+#include "pxa168.dtsi"
 
 / {
         model = "Marvell PXA168 Aspenite Development Board";
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index 975dad21ac38..b899e25cbb1b 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -7,7 +7,8 @@
  *  publishhed by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/marvell,pxa168.h>
 
 / {
         aliases {
@@ -59,6 +60,8 @@
                                 compatible = "mrvl,mmp-uart";
                                 reg = <0xd4017000 0x1000>;
                                 interrupts = <27>;
+                                clocks = <&soc_clocks PXA168_CLK_UART0>;
+                                resets = <&soc_clocks PXA168_CLK_UART0>;
                                 status = "disabled";
                         };
 
@@ -66,6 +69,8 @@
                                 compatible = "mrvl,mmp-uart";
                                 reg = <0xd4018000 0x1000>;
                                 interrupts = <28>;
+                                clocks = <&soc_clocks PXA168_CLK_UART1>;
+                                resets = <&soc_clocks PXA168_CLK_UART1>;
                                 status = "disabled";
                         };
 
@@ -73,6 +78,8 @@
                                 compatible = "mrvl,mmp-uart";
                                 reg = <0xd4026000 0x1000>;
                                 interrupts = <29>;
+                                clocks = <&soc_clocks PXA168_CLK_UART2>;
+                                resets = <&soc_clocks PXA168_CLK_UART2>;
                                 status = "disabled";
                         };
 
@@ -84,6 +91,8 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupts = <49>;
+                                clocks = <&soc_clocks PXA168_CLK_GPIO>;
+                                resets = <&soc_clocks PXA168_CLK_GPIO>;
                                 interrupt-names = "gpio_mux";
                                 interrupt-controller;
                                 #interrupt-cells = <1>;
@@ -110,6 +119,8 @@
                                 compatible = "mrvl,mmp-twsi";
                                 reg = <0xd4011000 0x1000>;
                                 interrupts = <7>;
+                                clocks = <&soc_clocks PXA168_CLK_TWSI0>;
+                                resets = <&soc_clocks PXA168_CLK_TWSI0>;
                                 mrvl,i2c-fast-mode;
                                 status = "disabled";
                         };
@@ -118,6 +129,8 @@
                                 compatible = "mrvl,mmp-twsi";
                                 reg = <0xd4025000 0x1000>;
                                 interrupts = <58>;
+                                clocks = <&soc_clocks PXA168_CLK_TWSI1>;
+                                resets = <&soc_clocks PXA168_CLK_TWSI1>;
                                 status = "disabled";
                         };
 
@@ -126,8 +139,20 @@
                                 reg = <0xd4010000 0x1000>;
                                 interrupts = <5 6>;
                                 interrupt-names = "rtc 1Hz", "rtc alarm";
+                                clocks = <&soc_clocks PXA168_CLK_RTC>;
+                                resets = <&soc_clocks PXA168_CLK_RTC>;
                                 status = "disabled";
                         };
                 };
+
+                soc_clocks: clocks{
+                        compatible = "marvell,pxa168-clock";
+                        reg = <0xd4050000 0x1000>,
+                              <0xd4282800 0x400>,
+                              <0xd4015000 0x1000>;
+                        reg-names = "mpmu", "apmu", "apbc";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
index 595492aa5053..c82f2810ec73 100644
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "pxa910.dtsi"
+#include "pxa910.dtsi"
 
 / {
         model = "Marvell PXA910 DKB Development Board";
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index 0247c622f580..0868f6729be1 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -7,7 +7,8 @@
  *  publishhed by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/marvell,pxa910.h>
 
 / {
         aliases {
@@ -71,6 +72,8 @@
                                 compatible = "mrvl,mmp-uart";
                                 reg = <0xd4017000 0x1000>;
                                 interrupts = <27>;
+                                clocks = <&soc_clocks PXA910_CLK_UART0>;
+                                resets = <&soc_clocks PXA910_CLK_UART0>;
                                 status = "disabled";
                         };
 
@@ -78,6 +81,8 @@
                                 compatible = "mrvl,mmp-uart";
                                 reg = <0xd4018000 0x1000>;
                                 interrupts = <28>;
+                                clocks = <&soc_clocks PXA910_CLK_UART1>;
+                                resets = <&soc_clocks PXA910_CLK_UART1>;
                                 status = "disabled";
                         };
 
@@ -85,6 +90,8 @@
                                 compatible = "mrvl,mmp-uart";
                                 reg = <0xd4036000 0x1000>;
                                 interrupts = <59>;
+                                clocks = <&soc_clocks PXA910_CLK_UART2>;
+                                resets = <&soc_clocks PXA910_CLK_UART2>;
                                 status = "disabled";
                         };
 
@@ -97,6 +104,8 @@
                                 #gpio-cells = <2>;
                                 interrupts = <49>;
                                 interrupt-names = "gpio_mux";
+                                clocks = <&soc_clocks PXA910_CLK_GPIO>;
+                                resets = <&soc_clocks PXA910_CLK_GPIO>;
                                 interrupt-controller;
                                 #interrupt-cells = <1>;
                                 ranges;
@@ -124,6 +133,8 @@
                                 #size-cells = <0>;
                                 reg = <0xd4011000 0x1000>;
                                 interrupts = <7>;
+                                clocks = <&soc_clocks PXA910_CLK_TWSI0>;
+                                resets = <&soc_clocks PXA910_CLK_TWSI0>;
                                 mrvl,i2c-fast-mode;
                                 status = "disabled";
                         };
@@ -134,6 +145,8 @@
                                 #size-cells = <0>;
                                 reg = <0xd4037000 0x1000>;
                                 interrupts = <54>;
+                                clocks = <&soc_clocks PXA910_CLK_TWSI1>;
+                                resets = <&soc_clocks PXA910_CLK_TWSI1>;
                                 status = "disabled";
                         };
 
@@ -142,8 +155,21 @@
                                 reg = <0xd4010000 0x1000>;
                                 interrupts = <5 6>;
                                 interrupt-names = "rtc 1Hz", "rtc alarm";
+                                clocks = <&soc_clocks PXA910_CLK_RTC>;
+                                resets = <&soc_clocks PXA910_CLK_RTC>;
                                 status = "disabled";
                         };
                 };
+
+                soc_clocks: clocks{
+                        compatible = "marvell,pxa910-clock";
+                        reg = <0xd4050000 0x1000>,
+                              <0xd4282800 0x400>,
+                              <0xd4015000 0x1000>,
+                              <0xd403b000 0x1000>;
+                        reg-names = "mpmu", "apmu", "apbc", "apbcp";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e3ab942fd148..7b4099fcf817 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -188,19 +188,11 @@
                                 "apb0_ir1", "apb0_keypad";
                 };
 
-                apb1_mux: apb1_mux@01c20058 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
-                        reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-                        clock-output-names = "apb1_mux";
-                };
-
-                apb1: apb1@01c20058 {
+                apb1: clk@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-apb1-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&apb1_mux>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                         clock-output-names = "apb1";
                 };
 
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 81ad4b94e812..1b76667f3182 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -176,19 +176,11 @@
                                 "apb0_ir", "apb0_keypad";
                 };
 
-                apb1_mux: apb1_mux@01c20058 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
-                        reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-                        clock-output-names = "apb1_mux";
-                };
-
-                apb1: apb1@01c20058 {
+                apb1: clk@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-apb1-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&apb1_mux>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                         clock-output-names = "apb1";
                 };
 
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index b131068f4f35..c35217ea1f64 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -161,19 +161,11 @@
                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
                 };
 
-                apb1_mux: apb1_mux@01c20058 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
-                        reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-                        clock-output-names = "apb1_mux";
-                };
-
-                apb1: apb1@01c20058 {
+                apb1: clk@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-apb1-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&apb1_mux>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                         clock-output-names = "apb1";
                 };
 
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index a400172a8a52..f47156b6572b 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -229,19 +229,11 @@
                                         "apb1_daudio1";
                 };
 
-                apb2_mux: apb2_mux@01c20058 {
+                apb2: clk@01c20058 {
                         #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-clk";
                         reg = <0x01c20058 0x4>;
                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
-                        clock-output-names = "apb2_mux";
-                };
-
-                apb2: apb2@01c20058 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun6i-a31-apb2-div-clk";
-                        reg = <0x01c20058 0x4>;
-                        clocks = <&apb2_mux>;
                         clock-output-names = "apb2";
                 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 82a524ce28ad..e21ce5992d56 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -236,19 +236,11 @@
                                 "apb0_iis2", "apb0_keypad";
                 };
 
-                apb1_mux: apb1_mux@01c20058 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
-                        reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-                        clock-output-names = "apb1_mux";
-                };
-
-                apb1: apb1@01c20058 {
+                apb1: clk@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-apb1-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&apb1_mux>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                         clock-output-names = "apb1";
                 };
 
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 6086adbf9d74..0746cd1024d7 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -189,19 +189,11 @@
                                         "apb1_daudio0", "apb1_daudio1";
                 };
 
-                apb2_mux: apb2_mux_clk@01c20058 {
+                apb2: clk@01c20058 {
                         #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-clk";
                         reg = <0x01c20058 0x4>;
                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
-                        clock-output-names = "apb2_mux";
-                };
-
-                apb2: apb2_clk@01c20058 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun6i-a31-apb2-div-clk";
-                        reg = <0x01c20058 0x4>;
-                        clocks = <&apb2_mux>;
                         clock-output-names = "apb2";
                 };
 
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
index db81d8ce4c03..9e9a72e3d30f 100644
--- a/arch/arm/configs/ape6evm_defconfig
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -33,7 +33,7 @@ CONFIG_ARM_APPENDED_DTB=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_BINFMT_MISC=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index d9675c68a399..5666e3700a82 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -43,7 +43,7 @@ CONFIG_KEXEC=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 83a87e48901c..7117662bab2e 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -39,7 +39,7 @@ CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_PACKET_DIAG=y
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index 1dde5daa84f9..3125e00f05ab 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -29,7 +29,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 759f9b0053e2..235842c9ba96 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -49,7 +49,7 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
 CONFIG_CPU_FREQ_GOV_POWERSAVE=m
 CONFIG_CPU_FREQ_GOV_ONDEMAND=m
 CONFIG_CPU_IDLE=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index c41990729024..5ef14de00a29 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -27,7 +27,7 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
 CONFIG_VFP=y
 CONFIG_NEON=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
index eb440aae4283..ea316c4b890e 100644
--- a/arch/arm/configs/ezx_defconfig
+++ b/arch/arm/configs/ezx_defconfig
@@ -39,7 +39,6 @@ CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
 CONFIG_PM=y
 CONFIG_APM_EMULATION=y
-CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 1fe3621faf65..112543665dd7 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -18,7 +18,7 @@ CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_NEON=y
 CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
index 182e54692664..18e59feaa307 100644
--- a/arch/arm/configs/imote2_defconfig
+++ b/arch/arm/configs/imote2_defconfig
@@ -31,7 +31,6 @@ CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
 CONFIG_PM=y
 CONFIG_APM_EMULATION=y
-CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index f707cd2691cf..7c2075a07eba 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -54,7 +54,7 @@ CONFIG_ARM_IMX6Q_CPUFREQ=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_BINFMT_MISC=m
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_PM_DEBUG=y
 CONFIG_PM_TEST_SUSPEND=y
 CONFIG_NET=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 20a3ff99fae2..a2067cbfe173 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -30,7 +30,7 @@ CONFIG_HIGHMEM=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_SUSPEND is not set
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 8cb115d74fdf..5d63fc5d2d48 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -43,7 +43,7 @@ CONFIG_KEXEC=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 929c571ea29b..a82afc916a89 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -37,7 +37,7 @@ CONFIG_AUTO_ZRELADDR=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 57ececba2ae6..05a529311b4d 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -28,7 +28,6 @@ CONFIG_KEXEC=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index ff91630d34e1..3c8b6d823189 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -33,7 +33,7 @@ CONFIG_ARM_APPENDED_DTB=y
 CONFIG_VFP=y
 CONFIG_KEXEC=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 115cda9f3260..a7dce674f1be 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -63,7 +63,6 @@ CONFIG_FPE_NWFPE=y
 CONFIG_BINFMT_MISC=y
 CONFIG_PM=y
 # CONFIG_SUSPEND is not set
-CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index 23591dba47a0..f610230b9c1f 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -18,7 +18,7 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_KEXEC=y
 CONFIG_BINFMT_MISC=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index b58fb32770a0..afa24799477a 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -32,7 +32,7 @@ CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_KERNEL_MODE_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_PM_DEBUG=y
 CONFIG_PM_ADVANCED_DEBUG=y
 CONFIG_NET=y
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index df2c0f514b0a..3df6ca0c1d1f 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -39,7 +39,7 @@ CONFIG_KEXEC=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index f7ac0379850f..7a342d2780a8 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -11,7 +11,7 @@ CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_VFP=y
 CONFIG_NEON=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 40750f93aa83..3ea9c3377ccb 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -46,7 +46,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index d219d6a43238..6a1c9898fd03 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -25,7 +25,7 @@ CONFIG_CPU_IDLE=y
 CONFIG_ARM_U8500_CPUIDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/vt8500_v6_v7_defconfig b/arch/arm/configs/vt8500_v6_v7_defconfig
index 9e7a25639690..1bfaa7bfc392 100644
--- a/arch/arm/configs/vt8500_v6_v7_defconfig
+++ b/arch/arm/configs/vt8500_v6_v7_defconfig
@@ -16,7 +16,7 @@ CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_VFP=y
 CONFIG_NEON=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index ac4bfae26702..0fa418463f49 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -120,12 +120,12 @@ static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
 
 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
-        return !arch_spin_value_unlocked(ACCESS_ONCE(*lock));
+        return !arch_spin_value_unlocked(READ_ONCE(*lock));
 }
 
 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 {
-        struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
+        struct __raw_tickets tickets = READ_ONCE(lock->tickets);
         return (tickets.next - tickets.owner) > 1;
 }
 #define arch_spin_is_contended  arch_spin_is_contended
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index ebdba87b9671..fdbfadf00c84 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -86,11 +86,12 @@ config MACH_GPLUGD
 
 config MACH_MMP_DT
         bool "Support MMP (ARMv5) platforms from device tree"
-        select CPU_PXA168
-        select CPU_PXA910
         select USE_OF
         select PINCTRL
         select PINCTRL_SINGLE
+        select COMMON_CLK
+        select ARCH_HAS_RESET_CONTROLLER
+        select CPU_MOHAWK
         help
           Include support for Marvell MMP2 based platforms using
           the device tree. Needn't select any other machine while
@@ -99,10 +100,12 @@ config MACH_MMP_DT
 config MACH_MMP2_DT
         bool "Support MMP2 (ARMv7) platforms from device tree"
         depends on !CPU_MOHAWK
-        select CPU_MMP2
         select USE_OF
         select PINCTRL
         select PINCTRL_SINGLE
+        select COMMON_CLK
+        select ARCH_HAS_RESET_CONTROLLER
+        select CPU_PJ4
         help
           Include support for Marvell MMP2 based platforms using
           the device tree.
@@ -111,21 +114,18 @@ endmenu
 
 config CPU_PXA168
         bool
-        select COMMON_CLK
         select CPU_MOHAWK
         help
           Select code specific to PXA168
 
 config CPU_PXA910
         bool
-        select COMMON_CLK
         select CPU_MOHAWK
         help
           Select code specific to PXA910
 
 config CPU_MMP2
         bool
-        select COMMON_CLK
         select CPU_PJ4
         help
           Select code specific to MMP2. MMP2 is ARMv7 compatible.
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index cca529ceecb7..b2296c9309b8 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -11,63 +11,42 @@
 
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/clk-provider.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/cache-tauros2.h>
 
 #include "common.h"
 
 extern void __init mmp_dt_init_timer(void);
 
-static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
-        OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
-        {}
+static const char *pxa168_dt_board_compat[] __initdata = {
+        "mrvl,pxa168-aspenite",
+        NULL,
 };
 
-static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
-        OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
-        {}
+static const char *pxa910_dt_board_compat[] __initdata = {
+        "mrvl,pxa910-dkb",
+        NULL,
 };
 
-static void __init pxa168_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             pxa168_auxdata_lookup, NULL);
-}
-
-static void __init pxa910_dt_init(void)
+static void __init mmp_init_time(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             pxa910_auxdata_lookup, NULL);
+#ifdef CONFIG_CACHE_TAUROS2
+        tauros2_init(0);
+#endif
+        mmp_dt_init_timer();
+        of_clk_init(NULL);
 }
 
-static const char *mmp_dt_board_compat[] __initdata = {
-        "mrvl,pxa168-aspenite",
-        "mrvl,pxa910-dkb",
-        NULL,
-};
-
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
         .map_io         = mmp_map_io,
-        .init_time      = mmp_dt_init_timer,
-        .init_machine   = pxa168_dt_init,
-        .dt_compat      = mmp_dt_board_compat,
+        .init_time      = mmp_init_time,
+        .dt_compat      = pxa168_dt_board_compat,
 MACHINE_END
 
 DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
         .map_io         = mmp_map_io,
-        .init_time      = mmp_dt_init_timer,
-        .init_machine   = pxa910_dt_init,
-        .dt_compat      = mmp_dt_board_compat,
+        .init_time      = mmp_init_time,
+        .dt_compat      = pxa910_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index 023cb453f157..998c0f533abc 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -12,29 +12,22 @@
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/clk-provider.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/cache-tauros2.h>
 
 #include "common.h"
 
 extern void __init mmp_dt_init_timer(void);
 
-static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
-        OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp2-gpio", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
-        {}
-};
-
-static void __init mmp2_dt_init(void)
+static void __init mmp_init_time(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             mmp2_auxdata_lookup, NULL);
+#ifdef CONFIG_CACHE_TAUROS2
+        tauros2_init(0);
+#endif
+        mmp_dt_init_timer();
+        of_clk_init(NULL);
 }
 
 static const char *mmp2_dt_board_compat[] __initdata = {
@@ -44,7 +37,6 @@ static const char *mmp2_dt_board_compat[] __initdata = {
 
 DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
         .map_io         = mmp_map_io,
-        .init_time      = mmp_dt_init_timer,
-        .init_machine   = mmp2_dt_init,
+        .init_time      = mmp_init_time,
         .dt_compat      = mmp2_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f0edec199cd4..6ab656cc4f16 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,7 +15,7 @@ config ARCH_OMAP3
         select ARM_CPU_SUSPEND if PM
         select OMAP_INTERCONNECT
         select PM_OPP if PM
-        select PM_RUNTIME if CPU_IDLE
+        select PM if CPU_IDLE
         select SOC_HAS_OMAP2_SDRC
 
 config ARCH_OMAP4
@@ -32,7 +32,7 @@ config ARCH_OMAP4
         select PL310_ERRATA_588369 if CACHE_L2X0
         select PL310_ERRATA_727915 if CACHE_L2X0
         select PM_OPP if PM
-        select PM_RUNTIME if CPU_IDLE
+        select PM if CPU_IDLE
         select ARM_ERRATA_754322
         select ARM_ERRATA_775420
 
@@ -103,7 +103,7 @@ config ARCH_OMAP2PLUS_TYPICAL
         select I2C_OMAP
         select MENELAUS if ARCH_OMAP2
         select NEON if CPU_V7
-        select PM_RUNTIME
+        select PM
         select REGULATOR
         select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
         select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 5c5ebb4db5f7..644ff3231bb8 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -111,6 +111,7 @@ static struct clk dpll3_ck;
 
 static const char *dpll3_ck_parent_names[] = {
         "sys_ck",
+        "sys_ck",
 };
 
 static const struct clk_ops dpll3_ck_ops = {
@@ -733,6 +734,10 @@ static const char *corex2_fck_parent_names[] = {
 DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
 DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
 
+static const char *cpefuse_fck_parent_names[] = {
+        "sys_ck",
+};
+
 static struct clk cpefuse_fck;
 
 static struct clk_hw_omap cpefuse_fck_hw = {
@@ -744,7 +749,7 @@ static struct clk_hw_omap cpefuse_fck_hw = {
         .clkdm_name     = "core_l4_clkdm",
 };
 
-DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(cpefuse_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk csi2_96m_fck;
 
@@ -775,7 +780,7 @@ static struct clk_hw_omap d2d_26m_fck_hw = {
         .clkdm_name     = "d2d_clkdm",
 };
 
-DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(d2d_26m_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk des1_ick;
 
@@ -1046,7 +1051,7 @@ static struct clk_hw_omap dss2_alwon_fck_hw = {
         .clkdm_name     = "dss_clkdm",
 };
 
-DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(dss2_alwon_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk dss_96m_fck;
 
@@ -1368,7 +1373,7 @@ DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
 static struct clk wkup_l4_ick;
 
 DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
-DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
+DEFINE_STRUCT_CLK(wkup_l4_ick, cpefuse_fck_parent_names, core_l4_ick_ops);
 
 static struct clk gpio1_ick;
 
@@ -1862,7 +1867,7 @@ static struct clk_hw_omap hecc_ck_hw = {
         .clkdm_name     = "core_l3_clkdm",
 };
 
-DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(hecc_ck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk hsotgusb_fck_am35xx;
 
@@ -1875,7 +1880,7 @@ static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
         .clkdm_name     = "core_l3_clkdm",
 };
 
-DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk hsotgusb_ick_3430es1;
 
@@ -2411,7 +2416,7 @@ static struct clk_hw_omap modem_fck_hw = {
         .clkdm_name     = "d2d_clkdm",
 };
 
-DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(modem_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk mspro_fck;
 
@@ -2710,7 +2715,7 @@ static struct clk_hw_omap sr1_fck_hw = {
         .clkdm_name     = "wkup_clkdm",
 };
 
-DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(sr1_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk sr2_fck;
 
@@ -2724,7 +2729,7 @@ static struct clk_hw_omap sr2_fck_hw = {
         .clkdm_name     = "wkup_clkdm",
 };
 
-DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(sr2_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk sr_l4_ick;
 
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 20e120d071dd..c2da2a0fe5ad 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -474,7 +474,7 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
  */
 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk)
+                                       struct clk_hw **best_parent_clk)
 {
         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
         struct dpll_data *dd;
@@ -488,10 +488,10 @@ long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
 
         if (__clk_get_rate(dd->clk_bypass) == rate &&
             (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-                *best_parent_clk = dd->clk_bypass;
+                *best_parent_clk = __clk_get_hw(dd->clk_bypass);
         } else {
                 rate = omap2_dpll_round_rate(hw, rate, best_parent_rate);
-                *best_parent_clk = dd->clk_ref;
+                *best_parent_clk = __clk_get_hw(dd->clk_ref);
         }
 
         *best_parent_rate = rate;
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 535822fcf4bb..0e58e5a85d53 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -223,7 +223,7 @@ out:
  */
 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
                                         unsigned long *best_parent_rate,
-                                        struct clk **best_parent_clk)
+                                        struct clk_hw **best_parent_clk)
 {
         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
         struct dpll_data *dd;
@@ -237,11 +237,11 @@ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
 
         if (__clk_get_rate(dd->clk_bypass) == rate &&
             (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-                *best_parent_clk = dd->clk_bypass;
+                *best_parent_clk = __clk_get_hw(dd->clk_bypass);
         } else {
                 rate = omap4_dpll_regm4xen_round_rate(hw, rate,
                                                       best_parent_rate);
-                *best_parent_clk = dd->clk_ref;
+                *best_parent_clk = __clk_get_hw(dd->clk_ref);
         }
 
         *best_parent_rate = rate;
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index dd301be89ecc..5376d908eabe 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1,6 +1,7 @@
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_AUDIT=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -13,14 +14,12 @@ CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RESOURCE_COUNTERS=y
 CONFIG_MEMCG=y
 CONFIG_MEMCG_SWAP=y
 CONFIG_MEMCG_KMEM=y
 CONFIG_CGROUP_HUGETLB=y
 # CONFIG_UTS_NS is not set
 # CONFIG_IPC_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_NET_NS is not set
 CONFIG_SCHED_AUTOGROUP=y
 CONFIG_BLK_DEV_INITRD=y
@@ -92,7 +91,6 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_VIRTIO_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
-# CONFIG_HMC_DRV is not set
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_PL061=y
@@ -133,6 +131,8 @@ CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+CONFIG_AUTOFS4_FS=y
 CONFIG_FUSE_FS=y
 CONFIG_CUSE=y
 CONFIG_VFAT_FS=y
@@ -152,14 +152,15 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_LOCKUP_DETECTOR=y
 # CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_FTRACE is not set
+CONFIG_KEYS=y
 CONFIG_SECURITY=y
 CONFIG_CRYPTO_ANSI_CPRNG=y
 CONFIG_ARM64_CRYPTO=y
 CONFIG_CRYPTO_SHA1_ARM64_CE=y
 CONFIG_CRYPTO_SHA2_ARM64_CE=y
 CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
 CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
 CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
 CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
diff --git a/arch/arm64/include/asm/dma-mapping.h b/arch/arm64/include/asm/dma-mapping.h
index d34189bceff7..9ce3e680ae1c 100644
--- a/arch/arm64/include/asm/dma-mapping.h
+++ b/arch/arm64/include/asm/dma-mapping.h
@@ -52,13 +52,14 @@ static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
         dev->archdata.dma_ops = ops;
 }
 
-static inline int set_arch_dma_coherent_ops(struct device *dev)
+static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
+                                      struct iommu_ops *iommu, bool coherent)
 {
-        dev->archdata.dma_coherent = true;
-        set_dma_ops(dev, &coherent_swiotlb_dma_ops);
-        return 0;
+        dev->archdata.dma_coherent = coherent;
+        if (coherent)
+                set_dma_ops(dev, &coherent_swiotlb_dma_ops);
 }
-#define set_arch_dma_coherent_ops       set_arch_dma_coherent_ops
+#define arch_setup_dma_ops      arch_setup_dma_ops
 
 /* do not use this function in a driver */
 static inline bool is_device_dma_coherent(struct device *dev)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index df22314f57cf..210d632aa5ad 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -298,7 +298,6 @@ void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
 #define pfn_pmd(pfn,prot)       (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
 #define mk_pmd(page,prot)       pfn_pmd(page_to_pfn(page),prot)
 
-#define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
 #define pud_write(pud)          pte_write(pud_pte(pud))
 #define pud_pfn(pud)            (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
 
@@ -401,7 +400,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
         return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
 }
 
-#define pud_page(pud)           pmd_page(pud_pmd(pud))
+#define pud_page(pud)           pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
 
 #endif  /* CONFIG_ARM64_PGTABLE_LEVELS > 2 */
 
@@ -437,6 +436,8 @@ static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
         return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr);
 }
 
+#define pgd_page(pgd)           pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK))
+
 #endif  /* CONFIG_ARM64_PGTABLE_LEVELS > 3 */
 
 #define pgd_ERROR(pgd)          __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
index c45b7b1b7197..cee128732435 100644
--- a/arch/arm64/include/asm/spinlock.h
+++ b/arch/arm64/include/asm/spinlock.h
@@ -99,12 +99,12 @@ static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
 
 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
-        return !arch_spin_value_unlocked(ACCESS_ONCE(*lock));
+        return !arch_spin_value_unlocked(READ_ONCE(*lock));
 }
 
 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 {
-        arch_spinlock_t lockval = ACCESS_ONCE(*lock);
+        arch_spinlock_t lockval = READ_ONCE(*lock);
         return (lockval.next - lockval.owner) > 1;
 }
 #define arch_spin_is_contended  arch_spin_is_contended
diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c
index 3771b72b6569..2d6b6065fe7f 100644
--- a/arch/arm64/kernel/suspend.c
+++ b/arch/arm64/kernel/suspend.c
@@ -5,6 +5,7 @@
 #include <asm/debug-monitors.h>
 #include <asm/pgtable.h>
 #include <asm/memory.h>
+#include <asm/mmu_context.h>
 #include <asm/smp_plat.h>
 #include <asm/suspend.h>
 #include <asm/tlbflush.h>
@@ -98,7 +99,18 @@ int __cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
          */
         ret = __cpu_suspend_enter(arg, fn);
         if (ret == 0) {
-                cpu_switch_mm(mm->pgd, mm);
+                /*
+                 * We are resuming from reset with TTBR0_EL1 set to the
+                 * idmap to enable the MMU; restore the active_mm mappings in
+                 * TTBR0_EL1 unless the active_mm == &init_mm, in which case
+                 * the thread entered __cpu_suspend with TTBR0_EL1 set to
+                 * reserved TTBR0 page tables and should be restored as such.
+                 */
+                if (mm == &init_mm)
+                        cpu_set_reserved_ttbr0();
+                else
+                        cpu_switch_mm(mm->pgd, mm);
+
                 flush_tlb_all();
 
                 /*
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 203e4403c366..48a9dfc55b51 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -374,7 +374,7 @@ static long alchemy_calc_div(unsigned long rate, unsigned long prate,
 
 static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
                                         unsigned long *best_parent_rate,
-                                        struct clk **best_parent_clk,
+                                        struct clk_hw **best_parent_clk,
                                         int scale, int maxdiv)
 {
         struct clk *pc, *bpc, *free;
@@ -453,7 +453,7 @@ static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
         }
 
         *best_parent_rate = bpr;
-        *best_parent_clk = bpc;
+        *best_parent_clk = __clk_get_hw(bpc);
         return br;
 }
 
@@ -547,7 +547,7 @@ static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
 
 static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,
                                         unsigned long *best_parent_rate,
-                                        struct clk **best_parent_clk)
+                                        struct clk_hw **best_parent_clk)
 {
         return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
                                      best_parent_clk, 2, 512);
@@ -679,7 +679,7 @@ static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
 
 static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,
                                         unsigned long *best_parent_rate,
-                                        struct clk **best_parent_clk)
+                                        struct clk_hw **best_parent_clk)
 {
         struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
         int scale, maxdiv;
@@ -898,7 +898,7 @@ static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
 
 static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,
                                         unsigned long *best_parent_rate,
-                                        struct clk **best_parent_clk)
+                                        struct clk_hw **best_parent_clk)
 {
         struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
         int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */
diff --git a/arch/mips/configs/db1xxx_defconfig b/arch/mips/configs/db1xxx_defconfig
index 46e8f7676a15..3bdb72a70364 100644
--- a/arch/mips/configs/db1xxx_defconfig
+++ b/arch/mips/configs/db1xxx_defconfig
@@ -36,7 +36,7 @@ CONFIG_PCI=y
 CONFIG_PCI_REALLOC_ENABLE_AUTO=y
 CONFIG_PCCARD=y
 CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_PACKET_DIAG=y
diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig
index 227a9de32246..e51aad9a94b1 100644
--- a/arch/mips/configs/lemote2f_defconfig
+++ b/arch/mips/configs/lemote2f_defconfig
@@ -37,7 +37,6 @@ CONFIG_MIPS32_N32=y
 CONFIG_PM=y
 CONFIG_HIBERNATION=y
 CONFIG_PM_STD_PARTITION="/dev/hda3"
-CONFIG_PM_RUNTIME=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEBUG=y
 CONFIG_CPU_FREQ_STAT=m
diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig
index 1c6191ebd583..7eabcd2031ea 100644
--- a/arch/mips/configs/loongson3_defconfig
+++ b/arch/mips/configs/loongson3_defconfig
@@ -58,7 +58,7 @@ CONFIG_BINFMT_MISC=m
 CONFIG_MIPS32_COMPAT=y
 CONFIG_MIPS32_O32=y
 CONFIG_MIPS32_N32=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig
index 70509a48df82..b3d1d37f85ea 100644
--- a/arch/mips/configs/nlm_xlp_defconfig
+++ b/arch/mips/configs/nlm_xlp_defconfig
@@ -61,7 +61,7 @@ CONFIG_BINFMT_MISC=y
 CONFIG_MIPS32_COMPAT=y
 CONFIG_MIPS32_O32=y
 CONFIG_MIPS32_N32=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_PM_DEBUG=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
index 82207e8079f3..3d8016d6cf3e 100644
--- a/arch/mips/configs/nlm_xlr_defconfig
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -41,7 +41,7 @@ CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_DEBUG=y
 CONFIG_BINFMT_MISC=m
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_PM_DEBUG=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c
index 7cba480568c8..70795a67a276 100644
--- a/arch/mips/mm/gup.c
+++ b/arch/mips/mm/gup.c
@@ -30,7 +30,7 @@ retry:
 
         return pte;
 #else
-        return ACCESS_ONCE(*ptep);
+        return READ_ONCE(*ptep);
 #endif
 }
 
diff --git a/arch/parisc/include/asm/ldcw.h b/arch/parisc/include/asm/ldcw.h
index d2d11b7055ba..8121aa6db2ff 100644
--- a/arch/parisc/include/asm/ldcw.h
+++ b/arch/parisc/include/asm/ldcw.h
@@ -33,11 +33,18 @@
 
 #endif /*!CONFIG_PA20*/
 
-/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.  */
+/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
+   We don't explicitly expose that "*a" may be written as reload
+   fails to find a register in class R1_REGS when "a" needs to be
+   reloaded when generating 64-bit PIC code.  Instead, we clobber
+   memory to indicate to the compiler that the assembly code reads
+   or writes to items other than those listed in the input and output
+   operands.  This may pessimize the code somewhat but __ldcw is
+   usually used within code blocks surrounded by memory barriors.  */
 #define __ldcw(a) ({                                            \
         unsigned __ret;                                         \
-        __asm__ __volatile__(__LDCW " 0(%2),%0"                 \
-                : "=r" (__ret), "+m" (*(a)) : "r" (a));         \
+        __asm__ __volatile__(__LDCW " 0(%1),%0"                 \
+                : "=r" (__ret) : "r" (a) : "memory");           \
         __ret;                                                  \
 })
 
diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig
index 2e637c881d2b..879de5efb073 100644
--- a/arch/powerpc/configs/ps3_defconfig
+++ b/arch/powerpc/configs/ps3_defconfig
@@ -36,7 +36,7 @@ CONFIG_KEXEC=y
 CONFIG_SCHED_SMT=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE=""
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_PM_DEBUG=y
 # CONFIG_SECCOMP is not set
 # CONFIG_PCI is not set
diff --git a/arch/s390/kvm/gaccess.c b/arch/s390/kvm/gaccess.c
index 8b9ccf02a2c5..8a1be9017730 100644
--- a/arch/s390/kvm/gaccess.c
+++ b/arch/s390/kvm/gaccess.c
@@ -227,12 +227,10 @@ static void ipte_lock_simple(struct kvm_vcpu *vcpu)
                 goto out;
         ic = &vcpu->kvm->arch.sca->ipte_control;
         do {
-                old = *ic;
-                barrier();
+                old = READ_ONCE(*ic);
                 while (old.k) {
                         cond_resched();
-                        old = *ic;
-                        barrier();
+                        old = READ_ONCE(*ic);
                 }
                 new = old;
                 new.k = 1;
@@ -251,8 +249,7 @@ static void ipte_unlock_simple(struct kvm_vcpu *vcpu)
                 goto out;
         ic = &vcpu->kvm->arch.sca->ipte_control;
         do {
-                old = *ic;
-                barrier();
+                old = READ_ONCE(*ic);
                 new = old;
                 new.k = 0;
         } while (cmpxchg(&ic->val, old.val, new.val) != old.val);
@@ -267,12 +264,10 @@ static void ipte_lock_siif(struct kvm_vcpu *vcpu)
 
         ic = &vcpu->kvm->arch.sca->ipte_control;
         do {
-                old = *ic;
-                barrier();
+                old = READ_ONCE(*ic);
                 while (old.kg) {
                         cond_resched();
-                        old = *ic;
-                        barrier();
+                        old = READ_ONCE(*ic);
                 }
                 new = old;
                 new.k = 1;
@@ -286,8 +281,7 @@ static void ipte_unlock_siif(struct kvm_vcpu *vcpu)
 
         ic = &vcpu->kvm->arch.sca->ipte_control;
         do {
-                old = *ic;
-                barrier();
+                old = READ_ONCE(*ic);
                 new = old;
                 new.kh--;
                 if (!new.kh)
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index c6b6ee5f38b2..0f09f5285d5e 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -223,7 +223,7 @@ config CPU_SHX3
 config ARCH_SHMOBILE
         bool
         select ARCH_SUSPEND_POSSIBLE
-        select PM_RUNTIME
+        select PM
 
 config CPU_HAS_PMU
        depends on CPU_SH4 || CPU_SH4A
diff --git a/arch/sh/configs/apsh4ad0a_defconfig b/arch/sh/configs/apsh4ad0a_defconfig
index ec70475da890..a8d975793b6d 100644
--- a/arch/sh/configs/apsh4ad0a_defconfig
+++ b/arch/sh/configs/apsh4ad0a_defconfig
@@ -47,7 +47,7 @@ CONFIG_PREEMPT=y
 CONFIG_BINFMT_MISC=y
 CONFIG_PM=y
 CONFIG_PM_DEBUG=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_CPU_IDLE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/sh/configs/sdk7786_defconfig b/arch/sh/configs/sdk7786_defconfig
index 76a76a295d74..e7e56a4131b4 100644
--- a/arch/sh/configs/sdk7786_defconfig
+++ b/arch/sh/configs/sdk7786_defconfig
@@ -82,7 +82,7 @@ CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_BINFMT_MISC=y
 CONFIG_PM=y
 CONFIG_PM_DEBUG=y
-CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_CPU_IDLE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index a4efe477ceab..625660f8a2fc 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -92,7 +92,7 @@ static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
                 unsigned count = SPIN_THRESHOLD;
 
                 do {
-                        if (ACCESS_ONCE(lock->tickets.head) == inc.tail)
+                        if (READ_ONCE(lock->tickets.head) == inc.tail)
                                 goto out;
                         cpu_relax();
                 } while (--count);
@@ -105,7 +105,7 @@ static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         arch_spinlock_t old, new;
 
-        old.tickets = ACCESS_ONCE(lock->tickets);
+        old.tickets = READ_ONCE(lock->tickets);
         if (old.tickets.head != (old.tickets.tail & ~TICKET_SLOWPATH_FLAG))
                 return 0;
 
@@ -162,14 +162,14 @@ static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
 
 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
-        struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
+        struct __raw_tickets tmp = READ_ONCE(lock->tickets);
 
         return tmp.tail != tmp.head;
 }
 
 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 {
-        struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
+        struct __raw_tickets tmp = READ_ONCE(lock->tickets);
 
         return (__ticket_t)(tmp.tail - tmp.head) > TICKET_LOCK_INC;
 }
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 10fbed126b11..f83fc6c5e0ba 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -4448,7 +4448,7 @@ void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm)
          * zap all shadow pages.
          */
         if (unlikely(kvm_current_mmio_generation(kvm) == 0)) {
-                printk_ratelimited(KERN_INFO "kvm: zapping shadow pages for mmio generation wraparound\n");
+                printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n");
                 kvm_mmu_invalidate_zap_all_pages(kvm);
         }
 }
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index feb852b04598..d4c58d884838 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -5840,53 +5840,10 @@ static __init int hardware_setup(void)
         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
 
-        vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
-        vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
-        vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
-        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
-        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
-        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
-        vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
-
-        memcpy(vmx_msr_bitmap_legacy_x2apic,
-                        vmx_msr_bitmap_legacy, PAGE_SIZE);
-        memcpy(vmx_msr_bitmap_longmode_x2apic,
-                        vmx_msr_bitmap_longmode, PAGE_SIZE);
-
-        if (enable_apicv) {
-                for (msr = 0x800; msr <= 0x8ff; msr++)
-                        vmx_disable_intercept_msr_read_x2apic(msr);
-
-                /* According SDM, in x2apic mode, the whole id reg is used.
-                 * But in KVM, it only use the highest eight bits. Need to
-                 * intercept it */
-                vmx_enable_intercept_msr_read_x2apic(0x802);
-                /* TMCCT */
-                vmx_enable_intercept_msr_read_x2apic(0x839);
-                /* TPR */
-                vmx_disable_intercept_msr_write_x2apic(0x808);
-                /* EOI */
-                vmx_disable_intercept_msr_write_x2apic(0x80b);
-                /* SELF-IPI */
-                vmx_disable_intercept_msr_write_x2apic(0x83f);
-        }
-
-        if (enable_ept) {
-                kvm_mmu_set_mask_ptes(0ull,
-                        (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
-                        (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
-                        0ull, VMX_EPT_EXECUTABLE_MASK);
-                ept_set_mmio_spte_mask();
-                kvm_enable_tdp();
-        } else
-                kvm_disable_tdp();
-
-        update_ple_window_actual_max();
-
         if (setup_vmcs_config(&vmcs_config) < 0) {
                 r = -EIO;
                 goto out7;
-    }
+        }
 
         if (boot_cpu_has(X86_FEATURE_NX))
                 kvm_enable_efer_bits(EFER_NX);
@@ -5945,6 +5902,49 @@ static __init int hardware_setup(void)
         if (nested)
                 nested_vmx_setup_ctls_msrs();
 
+        vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
+        vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
+        vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
+        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
+        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
+        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
+        vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
+
+        memcpy(vmx_msr_bitmap_legacy_x2apic,
+                        vmx_msr_bitmap_legacy, PAGE_SIZE);
+        memcpy(vmx_msr_bitmap_longmode_x2apic,
+                        vmx_msr_bitmap_longmode, PAGE_SIZE);
+
+        if (enable_apicv) {
+                for (msr = 0x800; msr <= 0x8ff; msr++)
+                        vmx_disable_intercept_msr_read_x2apic(msr);
+
+                /* According SDM, in x2apic mode, the whole id reg is used.
+                 * But in KVM, it only use the highest eight bits. Need to
+                 * intercept it */
+                vmx_enable_intercept_msr_read_x2apic(0x802);
+                /* TMCCT */
+                vmx_enable_intercept_msr_read_x2apic(0x839);
+                /* TPR */
+                vmx_disable_intercept_msr_write_x2apic(0x808);
+                /* EOI */
+                vmx_disable_intercept_msr_write_x2apic(0x80b);
+                /* SELF-IPI */
+                vmx_disable_intercept_msr_write_x2apic(0x83f);
+        }
+
+        if (enable_ept) {
+                kvm_mmu_set_mask_ptes(0ull,
+                        (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
+                        (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
+                        0ull, VMX_EPT_EXECUTABLE_MASK);
+                ept_set_mmio_spte_mask();
+                kvm_enable_tdp();
+        } else
+                kvm_disable_tdp();
+
+        update_ple_window_actual_max();
+
         return alloc_kvm_area();
 
 out7:
diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c
index 207d9aef662d..d7547824e763 100644
--- a/arch/x86/mm/gup.c
+++ b/arch/x86/mm/gup.c
@@ -15,7 +15,7 @@
 static inline pte_t gup_get_pte(pte_t *ptep)
 {
 #ifndef CONFIG_X86_PAE
-        return ACCESS_ONCE(*ptep);
+        return READ_ONCE(*ptep);
 #else
         /*
          * With get_user_pages_fast, we walk down the pagetables without taking
diff --git a/drivers/char/agp/ali-agp.c b/drivers/char/agp/ali-agp.c
index 19db03667650..dcbbb4ea3cc1 100644
--- a/drivers/char/agp/ali-agp.c
+++ b/drivers/char/agp/ali-agp.c
@@ -417,6 +417,6 @@ static void __exit agp_ali_cleanup(void)
 module_init(agp_ali_init);
 module_exit(agp_ali_cleanup);
 
-MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
+MODULE_AUTHOR("Dave Jones");
 MODULE_LICENSE("GPL and additional rights");
 
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index 3b47ed0310e1..0ef350010766 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -813,6 +813,6 @@ static void __exit agp_amd64_cleanup(void)
 module_init(agp_amd64_mod_init);
 module_exit(agp_amd64_cleanup);
 
-MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen");
+MODULE_AUTHOR("Dave Jones, Andi Kleen");
 module_param(agp_try_unsupported, bool, 0);
 MODULE_LICENSE("GPL");
diff --git a/drivers/char/agp/ati-agp.c b/drivers/char/agp/ati-agp.c
index 18a7a6baa304..75a9786a77e6 100644
--- a/drivers/char/agp/ati-agp.c
+++ b/drivers/char/agp/ati-agp.c
@@ -579,6 +579,6 @@ static void __exit agp_ati_cleanup(void)
 module_init(agp_ati_init);
 module_exit(agp_ati_cleanup);
 
-MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
+MODULE_AUTHOR("Dave Jones");
 MODULE_LICENSE("GPL and additional rights");
 
diff --git a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c
index 317c28ce8328..38ffb281df97 100644
--- a/drivers/char/agp/backend.c
+++ b/drivers/char/agp/backend.c
@@ -356,7 +356,7 @@ static __init int agp_setup(char *s)
 __setup("agp=", agp_setup);
 #endif
 
-MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
+MODULE_AUTHOR("Dave Jones, Jeff Hartmann");
 MODULE_DESCRIPTION("AGP GART driver");
 MODULE_LICENSE("GPL and additional rights");
 MODULE_ALIAS_MISCDEV(AGPGART_MINOR);
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index f9b9ca5d31b7..0a21daed5b62 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -920,5 +920,5 @@ static void __exit agp_intel_cleanup(void)
 module_init(agp_intel_init);
 module_exit(agp_intel_cleanup);
 
-MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
+MODULE_AUTHOR("Dave Jones, Various @Intel");
 MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index f3334829e55a..92aa43fa8d70 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1438,5 +1438,5 @@ void intel_gmch_remove(void)
 }
 EXPORT_SYMBOL(intel_gmch_remove);
 
-MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
+MODULE_AUTHOR("Dave Jones, Various @Intel");
 MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c
index a1861b75eb31..6c8d39cb566e 100644
--- a/drivers/char/agp/nvidia-agp.c
+++ b/drivers/char/agp/nvidia-agp.c
@@ -1,7 +1,7 @@
 /*
  * Nvidia AGPGART routines.
  * Based upon a 2.4 agpgart diff by the folks from NVIDIA, and hacked up
- * to work in 2.5 by Dave Jones <davej@redhat.com>
+ * to work in 2.5 by Dave Jones.
  */
 
 #include <linux/module.h>
diff --git a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c
index 228f20cddc05..a4961d35e940 100644
--- a/drivers/char/agp/via-agp.c
+++ b/drivers/char/agp/via-agp.c
@@ -595,4 +595,4 @@ module_init(agp_via_init);
 module_exit(agp_via_cleanup);
 
 MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
+MODULE_AUTHOR("Dave Jones");
diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c
index 5fa83f751378..6b65fa4e0c55 100644
--- a/drivers/char/ipmi/ipmi_msghandler.c
+++ b/drivers/char/ipmi/ipmi_msghandler.c
@@ -199,18 +199,6 @@ struct bmc_device {
         int                    guid_set;
         char                   name[16];
         struct kref            usecount;
-
-        /* bmc device attributes */
-        struct device_attribute device_id_attr;
-        struct device_attribute provides_dev_sdrs_attr;
-        struct device_attribute revision_attr;
-        struct device_attribute firmware_rev_attr;
-        struct device_attribute version_attr;
-        struct device_attribute add_dev_support_attr;
-        struct device_attribute manufacturer_id_attr;
-        struct device_attribute product_id_attr;
-        struct device_attribute guid_attr;
-        struct device_attribute aux_firmware_rev_attr;
 };
 #define to_bmc_device(x) container_of((x), struct bmc_device, pdev.dev)
 
@@ -2252,7 +2240,7 @@ static ssize_t device_id_show(struct device *dev,
 
         return snprintf(buf, 10, "%u\n", bmc->id.device_id);
 }
-DEVICE_ATTR(device_id, S_IRUGO, device_id_show, NULL);
+static DEVICE_ATTR(device_id, S_IRUGO, device_id_show, NULL);
 
 static ssize_t provides_device_sdrs_show(struct device *dev,
                                          struct device_attribute *attr,
@@ -2263,7 +2251,8 @@ static ssize_t provides_device_sdrs_show(struct device *dev,
         return snprintf(buf, 10, "%u\n",
                         (bmc->id.device_revision & 0x80) >> 7);
 }
-DEVICE_ATTR(provides_device_sdrs, S_IRUGO, provides_device_sdrs_show, NULL);
+static DEVICE_ATTR(provides_device_sdrs, S_IRUGO, provides_device_sdrs_show,
+                   NULL);
 
 static ssize_t revision_show(struct device *dev, struct device_attribute *attr,
                              char *buf)
@@ -2273,7 +2262,7 @@ static ssize_t revision_show(struct device *dev, struct device_attribute *attr,
         return snprintf(buf, 20, "%u\n",
                         bmc->id.device_revision & 0x0F);
 }
-DEVICE_ATTR(revision, S_IRUGO, revision_show, NULL);
+static DEVICE_ATTR(revision, S_IRUGO, revision_show, NULL);
 
 static ssize_t firmware_revision_show(struct device *dev,
                                       struct device_attribute *attr,
@@ -2284,7 +2273,7 @@ static ssize_t firmware_revision_show(struct device *dev,
         return snprintf(buf, 20, "%u.%x\n", bmc->id.firmware_revision_1,
                         bmc->id.firmware_revision_2);
 }
-DEVICE_ATTR(firmware_revision, S_IRUGO, firmware_revision_show, NULL);
+static DEVICE_ATTR(firmware_revision, S_IRUGO, firmware_revision_show, NULL);
 
 static ssize_t ipmi_version_show(struct device *dev,
                                  struct device_attribute *attr,
@@ -2296,7 +2285,7 @@ static ssize_t ipmi_version_show(struct device *dev,
                         ipmi_version_major(&bmc->id),
                         ipmi_version_minor(&bmc->id));
 }
-DEVICE_ATTR(ipmi_version, S_IRUGO, ipmi_version_show, NULL);
+static DEVICE_ATTR(ipmi_version, S_IRUGO, ipmi_version_show, NULL);
 
 static ssize_t add_dev_support_show(struct device *dev,
                                     struct device_attribute *attr,
@@ -2307,7 +2296,8 @@ static ssize_t add_dev_support_show(struct device *dev,
         return snprintf(buf, 10, "0x%02x\n",
                         bmc->id.additional_device_support);
 }
-DEVICE_ATTR(additional_device_support, S_IRUGO, add_dev_support_show, NULL);
+static DEVICE_ATTR(additional_device_support, S_IRUGO, add_dev_support_show,
+                   NULL);
 
 static ssize_t manufacturer_id_show(struct device *dev,
                                     struct device_attribute *attr,
@@ -2317,7 +2307,7 @@ static ssize_t manufacturer_id_show(struct device *dev,
 
         return snprintf(buf, 20, "0x%6.6x\n", bmc->id.manufacturer_id);
 }
-DEVICE_ATTR(manufacturer_id, S_IRUGO, manufacturer_id_show, NULL);
+static DEVICE_ATTR(manufacturer_id, S_IRUGO, manufacturer_id_show, NULL);
 
 static ssize_t product_id_show(struct device *dev,
                                struct device_attribute *attr,
@@ -2327,7 +2317,7 @@ static ssize_t product_id_show(struct device *dev,
 
         return snprintf(buf, 10, "0x%4.4x\n", bmc->id.product_id);
 }
-DEVICE_ATTR(product_id, S_IRUGO, product_id_show, NULL);
+static DEVICE_ATTR(product_id, S_IRUGO, product_id_show, NULL);
 
 static ssize_t aux_firmware_rev_show(struct device *dev,
                                      struct device_attribute *attr,
@@ -2341,7 +2331,7 @@ static ssize_t aux_firmware_rev_show(struct device *dev,
                         bmc->id.aux_firmware_revision[1],
                         bmc->id.aux_firmware_revision[0]);
 }
-DEVICE_ATTR(aux_firmware_revision, S_IRUGO, aux_firmware_rev_show, NULL);
+static DEVICE_ATTR(aux_firmware_revision, S_IRUGO, aux_firmware_rev_show, NULL);
 
 static ssize_t guid_show(struct device *dev, struct device_attribute *attr,
                          char *buf)
@@ -2352,7 +2342,7 @@ static ssize_t guid_show(struct device *dev, struct device_attribute *attr,
                         (long long) bmc->guid[0],
                         (long long) bmc->guid[8]);
 }
-DEVICE_ATTR(guid, S_IRUGO, guid_show, NULL);
+static DEVICE_ATTR(guid, S_IRUGO, guid_show, NULL);
 
 static struct attribute *bmc_dev_attrs[] = {
         &dev_attr_device_id.attr,
@@ -2392,10 +2382,10 @@ cleanup_bmc_device(struct kref *ref)
 
         if (bmc->id.aux_firmware_revision_set)
                 device_remove_file(&bmc->pdev.dev,
-                                   &bmc->aux_firmware_rev_attr);
+                                   &dev_attr_aux_firmware_revision);
         if (bmc->guid_set)
                 device_remove_file(&bmc->pdev.dev,
-                                   &bmc->guid_attr);
+                                   &dev_attr_guid);
 
         platform_device_unregister(&bmc->pdev);
 }
@@ -2422,16 +2412,14 @@ static int create_bmc_files(struct bmc_device *bmc)
         int err;
 
         if (bmc->id.aux_firmware_revision_set) {
-                bmc->aux_firmware_rev_attr.attr.name = "aux_firmware_revision";
                 err = device_create_file(&bmc->pdev.dev,
-                                   &bmc->aux_firmware_rev_attr);
+                                         &dev_attr_aux_firmware_revision);
                 if (err)
                         goto out;
         }
         if (bmc->guid_set) {
-                bmc->guid_attr.attr.name = "guid";
                 err = device_create_file(&bmc->pdev.dev,
-                                   &bmc->guid_attr);
+                                         &dev_attr_guid);
                 if (err)
                         goto out_aux_firm;
         }
@@ -2441,7 +2429,7 @@ static int create_bmc_files(struct bmc_device *bmc)
 out_aux_firm:
         if (bmc->id.aux_firmware_revision_set)
                 device_remove_file(&bmc->pdev.dev,
-                                   &bmc->aux_firmware_rev_attr);
+                                   &dev_attr_aux_firmware_revision);
 out:
         return err;
 }
diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c
index e178ac27e73c..fd5a5e85d7dc 100644
--- a/drivers/char/ipmi/ipmi_ssif.c
+++ b/drivers/char/ipmi/ipmi_ssif.c
@@ -52,6 +52,7 @@
 #include <linux/dmi.h>
 #include <linux/kthread.h>
 #include <linux/acpi.h>
+#include <linux/ctype.h>
 
 #define PFX "ipmi_ssif: "
 #define DEVICE_NAME "ipmi_ssif"
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
index 62e2509f9df1..bbdb1b985c91 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -57,7 +57,7 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
 static long clk_programmable_determine_rate(struct clk_hw *hw,
                                             unsigned long rate,
                                             unsigned long *best_parent_rate,
-                                            struct clk **best_parent_clk)
+                                            struct clk_hw **best_parent_hw)
 {
         struct clk *parent = NULL;
         long best_rate = -EINVAL;
@@ -84,7 +84,7 @@ static long clk_programmable_determine_rate(struct clk_hw *hw,
                 if (best_rate < 0 || (rate - tmp_rate) < (rate - best_rate)) {
                         best_rate = tmp_rate;
                         *best_parent_rate = parent_rate;
-                        *best_parent_clk = parent;
+                        *best_parent_hw = __clk_get_hw(parent);
                 }
 
                 if (!best_rate)
diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c
index 95af2e665dd3..1c06f6f3a8c5 100644
--- a/drivers/clk/bcm/clk-kona.c
+++ b/drivers/clk/bcm/clk-kona.c
@@ -1032,7 +1032,7 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 }
 
 static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long *best_parent_rate, struct clk **best_parent)
+                unsigned long *best_parent_rate, struct clk_hw **best_parent)
 {
         struct kona_clk *bcm_clk = to_kona_clk(hw);
         struct clk *clk = hw->clk;
@@ -1075,7 +1075,7 @@ static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
                 if (delta < best_delta) {
                         best_delta = delta;
                         best_rate = other_rate;
-                        *best_parent = parent;
+                        *best_parent = __clk_get_hw(parent);
                         *best_parent_rate = parent_rate;
                 }
         }
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index b9355daf8065..4386697236a7 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -57,7 +57,7 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
 
 static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
                                         unsigned long *best_parent_rate,
-                                        struct clk **best_parent_p)
+                                        struct clk_hw **best_parent_p)
 {
         struct clk_composite *composite = to_clk_composite(hw);
         const struct clk_ops *rate_ops = composite->rate_ops;
@@ -80,8 +80,9 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
                 *best_parent_p = NULL;
 
                 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) {
-                        *best_parent_p = clk_get_parent(mux_hw->clk);
-                        *best_parent_rate = __clk_get_rate(*best_parent_p);
+                        parent = clk_get_parent(mux_hw->clk);
+                        *best_parent_p = __clk_get_hw(parent);
+                        *best_parent_rate = __clk_get_rate(parent);
 
                         return rate_ops->round_rate(rate_hw, rate,
                                                     best_parent_rate);
@@ -103,7 +104,7 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
 
                         if (!rate_diff || !*best_parent_p
                                        || best_rate_diff > rate_diff) {
-                                *best_parent_p = parent;
+                                *best_parent_p = __clk_get_hw(parent);
                                 *best_parent_rate = parent_rate;
                                 best_rate_diff = rate_diff;
                                 best_rate = tmp_rate;
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 4f96ff3ba728..6e1ecf94bf58 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -77,7 +77,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 
         else {
                 if (mux->flags & CLK_MUX_INDEX_BIT)
-                        index = (1 << ffs(index));
+                        index = 1 << index;
 
                 if (mux->flags & CLK_MUX_INDEX_ONE)
                         index++;
diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c
index 87a41038237d..bfa1e64e267d 100644
--- a/drivers/clk/clk-s2mps11.c
+++ b/drivers/clk/clk-s2mps11.c
@@ -218,7 +218,7 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
         default:
                 dev_err(&pdev->dev, "Invalid device type\n");
                 return -EINVAL;
-        };
+        }
 
         /* Store clocks of_node in first element of s2mps11_clks array */
         s2mps11_clks->clk_np = s2mps11_clk_parse_dt(pdev, clks_init);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 4896ae9e23da..f4963b7d4e17 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -240,7 +240,6 @@ static const struct file_operations clk_dump_fops = {
         .release        = single_release,
 };
 
-/* caller must hold prepare_lock */
 static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
 {
         struct dentry *d;
@@ -354,13 +353,13 @@ out:
         mutex_unlock(&clk_debug_lock);
 }
 
-struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode,
+struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
                                 void *data, const struct file_operations *fops)
 {
         struct dentry *d = NULL;
 
-        if (clk->dentry)
-                d = debugfs_create_file(name, mode, clk->dentry, data, fops);
+        if (hw->clk->dentry)
+                d = debugfs_create_file(name, mode, hw->clk->dentry, data, fops);
 
         return d;
 }
@@ -574,11 +573,6 @@ unsigned int __clk_get_enable_count(struct clk *clk)
         return !clk ? 0 : clk->enable_count;
 }
 
-unsigned int __clk_get_prepare_count(struct clk *clk)
-{
-        return !clk ? 0 : clk->prepare_count;
-}
-
 unsigned long __clk_get_rate(struct clk *clk)
 {
         unsigned long ret;
@@ -601,7 +595,7 @@ out:
 }
 EXPORT_SYMBOL_GPL(__clk_get_rate);
 
-unsigned long __clk_get_accuracy(struct clk *clk)
+static unsigned long __clk_get_accuracy(struct clk *clk)
 {
         if (!clk)
                 return 0;
@@ -707,7 +701,7 @@ struct clk *__clk_lookup(const char *name)
  */
 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
                               unsigned long *best_parent_rate,
-                              struct clk **best_parent_p)
+                              struct clk_hw **best_parent_p)
 {
         struct clk *clk = hw->clk, *parent, *best_parent = NULL;
         int i, num_parents;
@@ -743,7 +737,7 @@ long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
 
 out:
         if (best_parent)
-                *best_parent_p = best_parent;
+                *best_parent_p = best_parent->hw;
         *best_parent_rate = best;
 
         return best;
@@ -951,6 +945,7 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
 {
         unsigned long parent_rate = 0;
         struct clk *parent;
+        struct clk_hw *parent_hw;
 
         if (!clk)
                 return 0;
@@ -959,10 +954,11 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
         if (parent)
                 parent_rate = parent->rate;
 
-        if (clk->ops->determine_rate)
+        if (clk->ops->determine_rate) {
+                parent_hw = parent ? parent->hw : NULL;
                 return clk->ops->determine_rate(clk->hw, rate, &parent_rate,
-                                                &parent);
-        else if (clk->ops->round_rate)
+                                                &parent_hw);
+        } else if (clk->ops->round_rate)
                 return clk->ops->round_rate(clk->hw, rate, &parent_rate);
         else if (clk->flags & CLK_SET_RATE_PARENT)
                 return __clk_round_rate(clk->parent, rate);
@@ -1350,6 +1346,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 {
         struct clk *top = clk;
         struct clk *old_parent, *parent;
+        struct clk_hw *parent_hw;
         unsigned long best_parent_rate = 0;
         unsigned long new_rate;
         int p_index = 0;
@@ -1365,9 +1362,11 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 
         /* find the closest rate and parent clk/rate */
         if (clk->ops->determine_rate) {
+                parent_hw = parent ? parent->hw : NULL;
                 new_rate = clk->ops->determine_rate(clk->hw, rate,
                                                     &best_parent_rate,
-                                                    &parent);
+                                                    &parent_hw);
+                parent = parent_hw->clk;
         } else if (clk->ops->round_rate) {
                 new_rate = clk->ops->round_rate(clk->hw, rate,
                                                 &best_parent_rate);
@@ -1614,7 +1613,7 @@ static struct clk *__clk_init_parent(struct clk *clk)
 
         if (clk->num_parents == 1) {
                 if (IS_ERR_OR_NULL(clk->parent))
-                        ret = clk->parent = __clk_lookup(clk->parent_names[0]);
+                        clk->parent = __clk_lookup(clk->parent_names[0]);
                 ret = clk->parent;
                 goto out;
         }
@@ -1944,7 +1943,6 @@ int __clk_init(struct device *dev, struct clk *clk)
         else
                 clk->rate = 0;
 
-        clk_debug_register(clk);
         /*
          * walk the list of orphan clocks and reparent any that are children of
          * this clock
@@ -1979,6 +1977,9 @@ int __clk_init(struct device *dev, struct clk *clk)
 out:
         clk_prepare_unlock();
 
+        if (!ret)
+                clk_debug_register(clk);
+
         return ret;
 }
 
@@ -2273,14 +2274,17 @@ int __clk_get(struct clk *clk)
 
 void __clk_put(struct clk *clk)
 {
+        struct module *owner;
+
         if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
                 return;
 
         clk_prepare_lock();
+        owner = clk->owner;
         kref_put(&clk->ref, __clk_release);
         clk_prepare_unlock();
 
-        module_put(clk->owner);
+        module_put(owner);
 }
 
 /***        clk rate change notifiers        ***/
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
index 339945d2503b..007144f81f50 100644
--- a/drivers/clk/hisilicon/clk-hi3620.c
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -38,44 +38,44 @@
 #include "clk.h"
 
 /* clock parent list */
-static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", };
-static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", };
-static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", };
-static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", };
-static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", };
-static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", };
-static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", };
-static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", };
-static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", };
-static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", };
-static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
-static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
-static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
+static const char *timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
+static const char *timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };
+static const char *timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };
+static const char *timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };
+static const char *timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };
+static const char *timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };
+static const char *timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };
+static const char *timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };
+static const char *timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };
+static const char *timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };
+static const char *uart0_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart1_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart2_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart3_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart4_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
+static const char *spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
+static const char *spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
 /* share axi parent */
-static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", };
-static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", };
-static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", };
-static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", };
-static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4",
+static const char *saxi_mux_p[] __initconst = { "armpll3", "armpll2", };
+static const char *pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };
+static const char *pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };
+static const char *sd_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *mmc1_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", };
+static const char *g2d_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *venc_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *vdec_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *vpp_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *edc0_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *ldi0_mux_p[] __initconst = { "armpll2", "armpll4",
                                              "armpll3", "armpll5", };
-static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4",
+static const char *edc1_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *ldi1_mux_p[] __initconst = { "armpll2", "armpll4",
                                              "armpll3", "armpll5", };
-static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", };
-static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", };
+static const char *rclk_hsic_p[] __initconst = { "armpll3", "armpll2", };
+static const char *mmc2_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *mmc3_mux_p[] __initconst = { "armpll2", "armpll3", };
 
 
 /* fixed rate clocks */
@@ -296,7 +296,7 @@ static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw,
 
 static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
                               unsigned long *best_parent_rate,
-                              struct clk **best_parent_p)
+                              struct clk_hw **best_parent_p)
 {
         struct clk_mmc *mclk = to_mmc(hw);
         unsigned long best = 0;
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 392d78044ce3..3caaf7cc169c 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -2,7 +2,12 @@
 # Makefile for mmp specific clk
 #
 
-obj-y += clk-apbc.o clk-apmu.o clk-frac.o
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
+
+obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+
+obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
+obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
 
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
index 23a56f561812..584a9927993b 100644
--- a/drivers/clk/mmp/clk-frac.c
+++ b/drivers/clk/mmp/clk-frac.c
@@ -22,19 +22,12 @@
  * numerator/denominator = Fin / (Fout * factor)
  */
 
-#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
-struct clk_factor {
-        struct clk_hw           hw;
-        void __iomem            *base;
-        struct clk_factor_masks *masks;
-        struct clk_factor_tbl   *ftbl;
-        unsigned int            ftbl_cnt;
-};
+#define to_clk_factor(hw) container_of(hw, struct mmp_clk_factor, hw)
 
 static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
                 unsigned long *prate)
 {
-        struct clk_factor *factor = to_clk_factor(hw);
+        struct mmp_clk_factor *factor = to_clk_factor(hw);
         unsigned long rate = 0, prev_rate;
         int i;
 
@@ -58,8 +51,8 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
 static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
                 unsigned long parent_rate)
 {
-        struct clk_factor *factor = to_clk_factor(hw);
-        struct clk_factor_masks *masks = factor->masks;
+        struct mmp_clk_factor *factor = to_clk_factor(hw);
+        struct mmp_clk_factor_masks *masks = factor->masks;
         unsigned int val, num, den;
 
         val = readl_relaxed(factor->base);
@@ -81,11 +74,12 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
 static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
                                 unsigned long prate)
 {
-        struct clk_factor *factor = to_clk_factor(hw);
-        struct clk_factor_masks *masks = factor->masks;
+        struct mmp_clk_factor *factor = to_clk_factor(hw);
+        struct mmp_clk_factor_masks *masks = factor->masks;
         int i;
         unsigned long val;
         unsigned long prev_rate, rate = 0;
+        unsigned long flags = 0;
 
         for (i = 0; i < factor->ftbl_cnt; i++) {
                 prev_rate = rate;
@@ -97,6 +91,9 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
         if (i > 0)
                 i--;
 
+        if (factor->lock)
+                spin_lock_irqsave(factor->lock, flags);
+
         val = readl_relaxed(factor->base);
 
         val &= ~(masks->num_mask << masks->num_shift);
@@ -107,21 +104,65 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
 
         writel_relaxed(val, factor->base);
 
+        if (factor->lock)
+                spin_unlock_irqrestore(factor->lock, flags);
+
         return 0;
 }
 
+static void clk_factor_init(struct clk_hw *hw)
+{
+        struct mmp_clk_factor *factor = to_clk_factor(hw);
+        struct mmp_clk_factor_masks *masks = factor->masks;
+        u32 val, num, den;
+        int i;
+        unsigned long flags = 0;
+
+        if (factor->lock)
+                spin_lock_irqsave(factor->lock, flags);
+
+        val = readl(factor->base);
+
+        /* calculate numerator */
+        num = (val >> masks->num_shift) & masks->num_mask;
+
+        /* calculate denominator */
+        den = (val >> masks->den_shift) & masks->den_mask;
+
+        for (i = 0; i < factor->ftbl_cnt; i++)
+                if (den == factor->ftbl[i].den && num == factor->ftbl[i].num)
+                        break;
+
+        if (i >= factor->ftbl_cnt) {
+                val &= ~(masks->num_mask << masks->num_shift);
+                val |= (factor->ftbl[0].num & masks->num_mask) <<
+                        masks->num_shift;
+
+                val &= ~(masks->den_mask << masks->den_shift);
+                val |= (factor->ftbl[0].den & masks->den_mask) <<
+                        masks->den_shift;
+
+                writel(val, factor->base);
+        }
+
+        if (factor->lock)
+                spin_unlock_irqrestore(factor->lock, flags);
+}
+
 static struct clk_ops clk_factor_ops = {
         .recalc_rate = clk_factor_recalc_rate,
         .round_rate = clk_factor_round_rate,
         .set_rate = clk_factor_set_rate,
+        .init = clk_factor_init,
 };
 
 struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
                 unsigned long flags, void __iomem *base,
-                struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
-                unsigned int ftbl_cnt)
+                struct mmp_clk_factor_masks *masks,
+                struct mmp_clk_factor_tbl *ftbl,
+                unsigned int ftbl_cnt, spinlock_t *lock)
 {
-        struct clk_factor *factor;
+        struct mmp_clk_factor *factor;
         struct clk_init_data init;
         struct clk *clk;
 
@@ -142,6 +183,7 @@ struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
         factor->ftbl = ftbl;
         factor->ftbl_cnt = ftbl_cnt;
         factor->hw.init = &init;
+        factor->lock = lock;
 
         init.name = name;
         init.ops = &clk_factor_ops;
diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
new file mode 100644
index 000000000000..adbd9d64ded2
--- /dev/null
+++ b/drivers/clk/mmp/clk-gate.c
@@ -0,0 +1,133 @@
+/*
+ * mmp gate clock operation source file
+ *
+ * Copyright (C) 2014 Marvell
+ * Chao Xie <chao.xie@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+
+#include "clk.h"
+
+/*
+ * Some clocks will have mutiple bits to enable the clocks, and
+ * the bits to disable the clock is not same as enabling bits.
+ */
+
+#define to_clk_mmp_gate(hw)     container_of(hw, struct mmp_clk_gate, hw)
+
+static int mmp_clk_gate_enable(struct clk_hw *hw)
+{
+        struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+        struct clk *clk = hw->clk;
+        unsigned long flags = 0;
+        unsigned long rate;
+        u32 tmp;
+
+        if (gate->lock)
+                spin_lock_irqsave(gate->lock, flags);
+
+        tmp = readl(gate->reg);
+        tmp &= ~gate->mask;
+        tmp |= gate->val_enable;
+        writel(tmp, gate->reg);
+
+        if (gate->lock)
+                spin_unlock_irqrestore(gate->lock, flags);
+
+        if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
+                rate = __clk_get_rate(clk);
+                /* Need delay 2 cycles. */
+                udelay(2000000/rate);
+        }
+
+        return 0;
+}
+
+static void mmp_clk_gate_disable(struct clk_hw *hw)
+{
+        struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+        unsigned long flags = 0;
+        u32 tmp;
+
+        if (gate->lock)
+                spin_lock_irqsave(gate->lock, flags);
+
+        tmp = readl(gate->reg);
+        tmp &= ~gate->mask;
+        tmp |= gate->val_disable;
+        writel(tmp, gate->reg);
+
+        if (gate->lock)
+                spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
+{
+        struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+        unsigned long flags = 0;
+        u32 tmp;
+
+        if (gate->lock)
+                spin_lock_irqsave(gate->lock, flags);
+
+        tmp = readl(gate->reg);
+
+        if (gate->lock)
+                spin_unlock_irqrestore(gate->lock, flags);
+
+        return (tmp & gate->mask) == gate->val_enable;
+}
+
+const struct clk_ops mmp_clk_gate_ops = {
+        .enable = mmp_clk_gate_enable,
+        .disable = mmp_clk_gate_disable,
+        .is_enabled = mmp_clk_gate_is_enabled,
+};
+
+struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
+                const char *parent_name, unsigned long flags,
+                void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
+                unsigned int gate_flags, spinlock_t *lock)
+{
+        struct mmp_clk_gate *gate;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        /* allocate the gate */
+        gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+        if (!gate) {
+                pr_err("%s:%s could not allocate gate clk\n", __func__, name);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        init.name = name;
+        init.ops = &mmp_clk_gate_ops;
+        init.flags = flags | CLK_IS_BASIC;
+        init.parent_names = (parent_name ? &parent_name : NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+
+        /* struct clk_gate assignments */
+        gate->reg = reg;
+        gate->mask = mask;
+        gate->val_enable = val_enable;
+        gate->val_disable = val_disable;
+        gate->flags = gate_flags;
+        gate->lock = lock;
+        gate->hw.init = &init;
+
+        clk = clk_register(dev, &gate->hw);
+
+        if (IS_ERR(clk))
+                kfree(gate);
+
+        return clk;
+}
diff --git a/drivers/clk/mmp/clk-mix.c b/drivers/clk/mmp/clk-mix.c
new file mode 100644
index 000000000000..48fa53c7ce5e
--- /dev/null
+++ b/drivers/clk/mmp/clk-mix.c
@@ -0,0 +1,513 @@
+/*
+ * mmp mix(div and mux) clock operation source file
+ *
+ * Copyright (C) 2014 Marvell
+ * Chao Xie <chao.xie@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include "clk.h"
+
+/*
+ * The mix clock is a clock combined mux and div type clock.
+ * Because the div field and mux field need to be set at same
+ * time, we can not divide it into 2 types of clock
+ */
+
+#define to_clk_mix(hw)  container_of(hw, struct mmp_clk_mix, hw)
+
+static unsigned int _get_maxdiv(struct mmp_clk_mix *mix)
+{
+        unsigned int div_mask = (1 << mix->reg_info.width_div) - 1;
+        unsigned int maxdiv = 0;
+        struct clk_div_table *clkt;
+
+        if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
+                return div_mask;
+        if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+                return 1 << div_mask;
+        if (mix->div_table) {
+                for (clkt = mix->div_table; clkt->div; clkt++)
+                        if (clkt->div > maxdiv)
+                                maxdiv = clkt->div;
+                return maxdiv;
+        }
+        return div_mask + 1;
+}
+
+static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)
+{
+        struct clk_div_table *clkt;
+
+        if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
+                return val;
+        if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+                return 1 << val;
+        if (mix->div_table) {
+                for (clkt = mix->div_table; clkt->div; clkt++)
+                        if (clkt->val == val)
+                                return clkt->div;
+                if (clkt->div == 0)
+                        return 0;
+        }
+        return val + 1;
+}
+
+static unsigned int _get_mux(struct mmp_clk_mix *mix, unsigned int val)
+{
+        int num_parents = __clk_get_num_parents(mix->hw.clk);
+        int i;
+
+        if (mix->mux_flags & CLK_MUX_INDEX_BIT)
+                return ffs(val) - 1;
+        if (mix->mux_flags & CLK_MUX_INDEX_ONE)
+                return val - 1;
+        if (mix->mux_table) {
+                for (i = 0; i < num_parents; i++)
+                        if (mix->mux_table[i] == val)
+                                return i;
+                if (i == num_parents)
+                        return 0;
+        }
+
+        return val;
+}
+static unsigned int _get_div_val(struct mmp_clk_mix *mix, unsigned int div)
+{
+        struct clk_div_table *clkt;
+
+        if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
+                return div;
+        if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+                return __ffs(div);
+        if (mix->div_table) {
+                for (clkt = mix->div_table; clkt->div; clkt++)
+                        if (clkt->div == div)
+                                return clkt->val;
+                if (clkt->div == 0)
+                        return 0;
+        }
+
+        return div - 1;
+}
+
+static unsigned int _get_mux_val(struct mmp_clk_mix *mix, unsigned int mux)
+{
+        if (mix->mux_table)
+                return mix->mux_table[mux];
+
+        return mux;
+}
+
+static void _filter_clk_table(struct mmp_clk_mix *mix,
+                                struct mmp_clk_mix_clk_table *table,
+                                unsigned int table_size)
+{
+        int i;
+        struct mmp_clk_mix_clk_table *item;
+        struct clk *parent, *clk;
+        unsigned long parent_rate;
+
+        clk = mix->hw.clk;
+
+        for (i = 0; i < table_size; i++) {
+                item = &table[i];
+                parent = clk_get_parent_by_index(clk, item->parent_index);
+                parent_rate = __clk_get_rate(parent);
+                if (parent_rate % item->rate) {
+                        item->valid = 0;
+                } else {
+                        item->divisor = parent_rate / item->rate;
+                        item->valid = 1;
+                }
+        }
+}
+
+static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val,
+                        unsigned int change_mux, unsigned int change_div)
+{
+        struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
+        u8 width, shift;
+        u32 mux_div, fc_req;
+        int ret, timeout = 50;
+        unsigned long flags = 0;
+
+        if (!change_mux && !change_div)
+                return -EINVAL;
+
+        if (mix->lock)
+                spin_lock_irqsave(mix->lock, flags);
+
+        if (mix->type == MMP_CLK_MIX_TYPE_V1
+                || mix->type == MMP_CLK_MIX_TYPE_V2)
+                mux_div = readl(ri->reg_clk_ctrl);
+        else
+                mux_div = readl(ri->reg_clk_sel);
+
+        if (change_div) {
+                width = ri->width_div;
+                shift = ri->shift_div;
+                mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
+                mux_div |= MMP_CLK_BITS_SET_VAL(div_val, width, shift);
+        }
+
+        if (change_mux) {
+                width = ri->width_mux;
+                shift = ri->shift_mux;
+                mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
+                mux_div |= MMP_CLK_BITS_SET_VAL(mux_val, width, shift);
+        }
+
+        if (mix->type == MMP_CLK_MIX_TYPE_V1) {
+                writel(mux_div, ri->reg_clk_ctrl);
+        } else if (mix->type == MMP_CLK_MIX_TYPE_V2) {
+                mux_div |= (1 << ri->bit_fc);
+                writel(mux_div, ri->reg_clk_ctrl);
+
+                do {
+                        fc_req = readl(ri->reg_clk_ctrl);
+                        timeout--;
+                        if (!(fc_req & (1 << ri->bit_fc)))
+                                break;
+                } while (timeout);
+
+                if (timeout == 0) {
+                        pr_err("%s:%s cannot do frequency change\n",
+                                __func__, __clk_get_name(mix->hw.clk));
+                        ret = -EBUSY;
+                        goto error;
+                }
+        } else {
+                fc_req = readl(ri->reg_clk_ctrl);
+                fc_req |= 1 << ri->bit_fc;
+                writel(fc_req, ri->reg_clk_ctrl);
+                writel(mux_div, ri->reg_clk_sel);
+                fc_req &= ~(1 << ri->bit_fc);
+        }
+
+        ret = 0;
+error:
+        if (mix->lock)
+                spin_unlock_irqrestore(mix->lock, flags);
+
+        return ret;
+}
+
+static long mmp_clk_mix_determine_rate(struct clk_hw *hw, unsigned long rate,
+                                        unsigned long *best_parent_rate,
+                                        struct clk_hw **best_parent_clk)
+{
+        struct mmp_clk_mix *mix = to_clk_mix(hw);
+        struct mmp_clk_mix_clk_table *item;
+        struct clk *parent, *parent_best, *mix_clk;
+        unsigned long parent_rate, mix_rate, mix_rate_best, parent_rate_best;
+        unsigned long gap, gap_best;
+        u32 div_val_max;
+        unsigned int div;
+        int i, j;
+
+        mix_clk = hw->clk;
+
+        parent = NULL;
+        mix_rate_best = 0;
+        parent_rate_best = 0;
+        gap_best = rate;
+        parent_best = NULL;
+
+        if (mix->table) {
+                for (i = 0; i < mix->table_size; i++) {
+                        item = &mix->table[i];
+                        if (item->valid == 0)
+                                continue;
+                        parent = clk_get_parent_by_index(mix_clk,
+                                                        item->parent_index);
+                        parent_rate = __clk_get_rate(parent);
+                        mix_rate = parent_rate / item->divisor;
+                        gap = abs(mix_rate - rate);
+                        if (parent_best == NULL || gap < gap_best) {
+                                parent_best = parent;
+                                parent_rate_best = parent_rate;
+                                mix_rate_best = mix_rate;
+                                gap_best = gap;
+                                if (gap_best == 0)
+                                        goto found;
+                        }
+                }
+        } else {
+                for (i = 0; i < __clk_get_num_parents(mix_clk); i++) {
+                        parent = clk_get_parent_by_index(mix_clk, i);
+                        parent_rate = __clk_get_rate(parent);
+                        div_val_max = _get_maxdiv(mix);
+                        for (j = 0; j < div_val_max; j++) {
+                                div = _get_div(mix, j);
+                                mix_rate = parent_rate / div;
+                                gap = abs(mix_rate - rate);
+                                if (parent_best == NULL || gap < gap_best) {
+                                        parent_best = parent;
+                                        parent_rate_best = parent_rate;
+                                        mix_rate_best = mix_rate;
+                                        gap_best = gap;
+                                        if (gap_best == 0)
+                                                goto found;
+                                }
+                        }
+                }
+        }
+
+found:
+        *best_parent_rate = parent_rate_best;
+        *best_parent_clk = __clk_get_hw(parent_best);
+
+        return mix_rate_best;
+}
+
+static int mmp_clk_mix_set_rate_and_parent(struct clk_hw *hw,
+                                                unsigned long rate,
+                                                unsigned long parent_rate,
+                                                u8 index)
+{
+        struct mmp_clk_mix *mix = to_clk_mix(hw);
+        unsigned int div;
+        u32 div_val, mux_val;
+
+        div = parent_rate / rate;
+        div_val = _get_div_val(mix, div);
+        mux_val = _get_mux_val(mix, index);
+
+        return _set_rate(mix, mux_val, div_val, 1, 1);
+}
+
+static u8 mmp_clk_mix_get_parent(struct clk_hw *hw)
+{
+        struct mmp_clk_mix *mix = to_clk_mix(hw);
+        struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
+        unsigned long flags = 0;
+        u32 mux_div = 0;
+        u8 width, shift;
+        u32 mux_val;
+
+        if (mix->lock)
+                spin_lock_irqsave(mix->lock, flags);
+
+        if (mix->type == MMP_CLK_MIX_TYPE_V1
+                || mix->type == MMP_CLK_MIX_TYPE_V2)
+                mux_div = readl(ri->reg_clk_ctrl);
+        else
+                mux_div = readl(ri->reg_clk_sel);
+
+        if (mix->lock)
+                spin_unlock_irqrestore(mix->lock, flags);
+
+        width = mix->reg_info.width_mux;
+        shift = mix->reg_info.shift_mux;
+
+        mux_val = MMP_CLK_BITS_GET_VAL(mux_div, width, shift);
+
+        return _get_mux(mix, mux_val);
+}
+
+static unsigned long mmp_clk_mix_recalc_rate(struct clk_hw *hw,
+                                        unsigned long parent_rate)
+{
+        struct mmp_clk_mix *mix = to_clk_mix(hw);
+        struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
+        unsigned long flags = 0;
+        u32 mux_div = 0;
+        u8 width, shift;
+        unsigned int div;
+
+        if (mix->lock)
+                spin_lock_irqsave(mix->lock, flags);
+
+        if (mix->type == MMP_CLK_MIX_TYPE_V1
+                || mix->type == MMP_CLK_MIX_TYPE_V2)
+                mux_div = readl(ri->reg_clk_ctrl);
+        else
+                mux_div = readl(ri->reg_clk_sel);
+
+        if (mix->lock)
+                spin_unlock_irqrestore(mix->lock, flags);
+
+        width = mix->reg_info.width_div;
+        shift = mix->reg_info.shift_div;
+
+        div = _get_div(mix, MMP_CLK_BITS_GET_VAL(mux_div, width, shift));
+
+        return parent_rate / div;
+}
+
+static int mmp_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct mmp_clk_mix *mix = to_clk_mix(hw);
+        struct mmp_clk_mix_clk_table *item;
+        int i;
+        u32 div_val, mux_val;
+
+        if (mix->table) {
+                for (i = 0; i < mix->table_size; i++) {
+                        item = &mix->table[i];
+                        if (item->valid == 0)
+                                continue;
+                        if (item->parent_index == index)
+                                break;
+                }
+                if (i < mix->table_size) {
+                        div_val = _get_div_val(mix, item->divisor);
+                        mux_val = _get_mux_val(mix, item->parent_index);
+                } else
+                        return -EINVAL;
+        } else {
+                mux_val = _get_mux_val(mix, index);
+                div_val = 0;
+        }
+
+        return _set_rate(mix, mux_val, div_val, 1, div_val ? 1 : 0);
+}
+
+static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long best_parent_rate)
+{
+        struct mmp_clk_mix *mix = to_clk_mix(hw);
+        struct mmp_clk_mix_clk_table *item;
+        unsigned long parent_rate;
+        unsigned int best_divisor;
+        struct clk *mix_clk, *parent;
+        int i;
+
+        best_divisor = best_parent_rate / rate;
+
+        mix_clk = hw->clk;
+        if (mix->table) {
+                for (i = 0; i < mix->table_size; i++) {
+                        item = &mix->table[i];
+                        if (item->valid == 0)
+                                continue;
+                        parent = clk_get_parent_by_index(mix_clk,
+                                                        item->parent_index);
+                        parent_rate = __clk_get_rate(parent);
+                        if (parent_rate == best_parent_rate
+                                && item->divisor == best_divisor)
+                                break;
+                }
+                if (i < mix->table_size)
+                        return _set_rate(mix,
+                                        _get_mux_val(mix, item->parent_index),
+                                        _get_div_val(mix, item->divisor),
+                                        1, 1);
+                else
+                        return -EINVAL;
+        } else {
+                for (i = 0; i < __clk_get_num_parents(mix_clk); i++) {
+                        parent = clk_get_parent_by_index(mix_clk, i);
+                        parent_rate = __clk_get_rate(parent);
+                        if (parent_rate == best_parent_rate)
+                                break;
+                }
+                if (i < __clk_get_num_parents(mix_clk))
+                        return _set_rate(mix, _get_mux_val(mix, i),
+                                        _get_div_val(mix, best_divisor), 1, 1);
+                else
+                        return -EINVAL;
+        }
+}
+
+static void mmp_clk_mix_init(struct clk_hw *hw)
+{
+        struct mmp_clk_mix *mix = to_clk_mix(hw);
+
+        if (mix->table)
+                _filter_clk_table(mix, mix->table, mix->table_size);
+}
+
+const struct clk_ops mmp_clk_mix_ops = {
+        .determine_rate = mmp_clk_mix_determine_rate,
+        .set_rate_and_parent = mmp_clk_mix_set_rate_and_parent,
+        .set_rate = mmp_clk_set_rate,
+        .set_parent = mmp_clk_set_parent,
+        .get_parent = mmp_clk_mix_get_parent,
+        .recalc_rate = mmp_clk_mix_recalc_rate,
+        .init = mmp_clk_mix_init,
+};
+
+struct clk *mmp_clk_register_mix(struct device *dev,
+                                        const char *name,
+                                        const char **parent_names,
+                                        u8 num_parents,
+                                        unsigned long flags,
+                                        struct mmp_clk_mix_config *config,
+                                        spinlock_t *lock)
+{
+        struct mmp_clk_mix *mix;
+        struct clk *clk;
+        struct clk_init_data init;
+        size_t table_bytes;
+
+        mix = kzalloc(sizeof(*mix), GFP_KERNEL);
+        if (!mix) {
+                pr_err("%s:%s: could not allocate mmp mix clk\n",
+                        __func__, name);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        init.name = name;
+        init.flags = flags | CLK_GET_RATE_NOCACHE;
+        init.parent_names = parent_names;
+        init.num_parents = num_parents;
+        init.ops = &mmp_clk_mix_ops;
+
+        memcpy(&mix->reg_info, &config->reg_info, sizeof(config->reg_info));
+        if (config->table) {
+                table_bytes = sizeof(*config->table) * config->table_size;
+                mix->table = kzalloc(table_bytes, GFP_KERNEL);
+                if (!mix->table) {
+                        pr_err("%s:%s: could not allocate mmp mix table\n",
+                                __func__, name);
+                        kfree(mix);
+                        return ERR_PTR(-ENOMEM);
+                }
+                memcpy(mix->table, config->table, table_bytes);
+                mix->table_size = config->table_size;
+        }
+
+        if (config->mux_table) {
+                table_bytes = sizeof(u32) * num_parents;
+                mix->mux_table = kzalloc(table_bytes, GFP_KERNEL);
+                if (!mix->mux_table) {
+                        pr_err("%s:%s: could not allocate mmp mix mux-table\n",
+                                __func__, name);
+                        kfree(mix->table);
+                        kfree(mix);
+                        return ERR_PTR(-ENOMEM);
+                }
+                memcpy(mix->mux_table, config->mux_table, table_bytes);
+        }
+
+        mix->div_flags = config->div_flags;
+        mix->mux_flags = config->mux_flags;
+        mix->lock = lock;
+        mix->hw.init = &init;
+
+        if (config->reg_info.bit_fc >= 32)
+                mix->type = MMP_CLK_MIX_TYPE_V1;
+        else if (config->reg_info.reg_clk_sel)
+                mix->type = MMP_CLK_MIX_TYPE_V3;
+        else
+                mix->type = MMP_CLK_MIX_TYPE_V2;
+        clk = clk_register(dev, &mix->hw);
+
+        if (IS_ERR(clk)) {
+                kfree(mix->mux_table);
+                kfree(mix->table);
+                kfree(mix);
+        }
+
+        return clk;
+}
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index b2721cae257a..5c90a4230fa3 100644
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -54,7 +54,7 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
-static struct clk_factor_masks uart_factor_masks = {
+static struct mmp_clk_factor_masks uart_factor_masks = {
         .factor = 2,
         .num_mask = 0x1fff,
         .den_mask = 0x1fff,
@@ -62,7 +62,7 @@ static struct clk_factor_masks uart_factor_masks = {
         .den_shift = 0,
 };
 
-static struct clk_factor_tbl uart_factor_tbl[] = {
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
         {.num = 14634, .den = 2165},    /*14.745MHZ */
         {.num = 3521, .den = 689},      /*19.23MHZ */
         {.num = 9679, .den = 5728},     /*58.9824MHZ */
@@ -191,7 +191,7 @@ void __init mmp2_clk_init(void)
         clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                 mpmu_base + MPMU_UART_PLL,
                                 &uart_factor_masks, uart_factor_tbl,
-                                ARRAY_SIZE(uart_factor_tbl));
+                                ARRAY_SIZE(uart_factor_tbl), &clk_lock);
         clk_set_rate(clk, 14745600);
         clk_register_clkdev(clk, "uart_pll", NULL);
 
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
new file mode 100644
index 000000000000..2cbc2b43ae52
--- /dev/null
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -0,0 +1,334 @@
+/*
+ * mmp2 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/marvell,mmp2.h>
+
+#include "clk.h"
+#include "reset.h"
+
+#define APBC_RTC        0x0
+#define APBC_TWSI0      0x4
+#define APBC_TWSI1      0x8
+#define APBC_TWSI2      0xc
+#define APBC_TWSI3      0x10
+#define APBC_TWSI4      0x7c
+#define APBC_TWSI5      0x80
+#define APBC_KPC        0x18
+#define APBC_UART0      0x2c
+#define APBC_UART1      0x30
+#define APBC_UART2      0x34
+#define APBC_UART3      0x88
+#define APBC_GPIO       0x38
+#define APBC_PWM0       0x3c
+#define APBC_PWM1       0x40
+#define APBC_PWM2       0x44
+#define APBC_PWM3       0x48
+#define APBC_SSP0       0x50
+#define APBC_SSP1       0x54
+#define APBC_SSP2       0x58
+#define APBC_SSP3       0x5c
+#define APMU_SDH0       0x54
+#define APMU_SDH1       0x58
+#define APMU_SDH2       0xe8
+#define APMU_SDH3       0xec
+#define APMU_USB        0x5c
+#define APMU_DISP0      0x4c
+#define APMU_DISP1      0x110
+#define APMU_CCIC0      0x50
+#define APMU_CCIC1      0xf4
+#define MPMU_UART_PLL   0x14
+
+struct mmp2_clk_unit {
+        struct mmp_clk_unit unit;
+        void __iomem *mpmu_base;
+        void __iomem *apmu_base;
+        void __iomem *apbc_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+        {MMP2_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
+        {MMP2_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
+        {MMP2_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 800000000},
+        {MMP2_CLK_PLL2, "pll2", NULL, CLK_IS_ROOT, 960000000},
+        {MMP2_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+        {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
+        {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
+        {MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
+        {MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
+        {MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0},
+        {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
+        {MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0},
+        {MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
+        {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
+        {MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0},
+        {MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0},
+        {MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0},
+        {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
+        {MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0},
+        {MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0},
+        {MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0},
+        {MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+        .factor = 2,
+        .num_mask = 0x1fff,
+        .den_mask = 0x1fff,
+        .num_shift = 16,
+        .den_shift = 0,
+};
+
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
+        {.num = 14634, .den = 2165},    /*14.745MHZ */
+        {.num = 3521, .den = 689},      /*19.23MHZ */
+        {.num = 9679, .den = 5728},     /*58.9824MHZ */
+        {.num = 15850, .den = 9451},    /*59.429MHZ */
+};
+
+static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)
+{
+        struct clk *clk;
+        struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+        mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+                                        ARRAY_SIZE(fixed_rate_clks));
+
+        mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+                                        ARRAY_SIZE(fixed_factor_clks));
+
+        clk = mmp_clk_register_factor("uart_pll", "pll1_4",
+                                CLK_SET_RATE_PARENT,
+                                pxa_unit->mpmu_base + MPMU_UART_PLL,
+                                &uart_factor_masks, uart_factor_tbl,
+                                ARRAY_SIZE(uart_factor_tbl), NULL);
+        mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk);
+}
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
+
+static DEFINE_SPINLOCK(ssp0_lock);
+static DEFINE_SPINLOCK(ssp1_lock);
+static DEFINE_SPINLOCK(ssp2_lock);
+static DEFINE_SPINLOCK(ssp3_lock);
+static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
+
+static DEFINE_SPINLOCK(reset_lock);
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+        {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+        {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+        {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
+        {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock},
+        {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
+        {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
+        {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
+        {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
+};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+        {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
+        {MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
+        {MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
+        {MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
+        {MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
+        {MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock},
+        {MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
+        {MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
+        {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
+        {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
+        {MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock},
+        {MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock},
+        {MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock},
+        /* The gate clocks has mux parent. */
+        {MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock},
+        {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock},
+        {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
+        {MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock},
+        {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock},
+        {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock},
+        {MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock},
+        {MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock},
+};
+
+static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
+{
+        struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+        mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+                                ARRAY_SIZE(apbc_mux_clks));
+
+        mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+                                ARRAY_SIZE(apbc_gate_clks));
+}
+
+static DEFINE_SPINLOCK(sdh_lock);
+static const char *sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
+static struct mmp_clk_mix_config sdh_mix_config = {
+        .reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32),
+};
+
+static DEFINE_SPINLOCK(usb_lock);
+
+static DEFINE_SPINLOCK(disp0_lock);
+static DEFINE_SPINLOCK(disp1_lock);
+static const char *disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
+
+static DEFINE_SPINLOCK(ccic0_lock);
+static DEFINE_SPINLOCK(ccic1_lock);
+static const char *ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
+static struct mmp_clk_mix_config ccic0_mix_config = {
+        .reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32),
+};
+static struct mmp_clk_mix_config ccic1_mix_config = {
+        .reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),
+};
+
+static struct mmp_param_mux_clk apmu_mux_clks[] = {
+        {MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
+        {MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
+};
+
+static struct mmp_param_div_clk apmu_div_clks[] = {
+        {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, 0, &disp0_lock},
+        {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
+        {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, 0, &disp1_lock},
+        {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
+        {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+        {MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
+        /* The gate clocks has mux parent. */
+        {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+        {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+        {MMP2_CLK_SDH1, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+        {MMP2_CLK_SDH1, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+        {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+        {MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
+        {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x1b, 0x1b, 0x0, 0, &disp1_lock},
+        {MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
+        {MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
+        {MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
+        {MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
+        {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
+        {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
+        {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
+};
+
+static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
+{
+        struct clk *clk;
+        struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+        sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
+        clk = mmp_clk_register_mix(NULL, "sdh_mix_clk", sdh_parent_names,
+                                        ARRAY_SIZE(sdh_parent_names),
+                                        CLK_SET_RATE_PARENT,
+                                        &sdh_mix_config, &sdh_lock);
+
+        ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0;
+        clk = mmp_clk_register_mix(NULL, "ccic0_mix_clk", ccic_parent_names,
+                                        ARRAY_SIZE(ccic_parent_names),
+                                        CLK_SET_RATE_PARENT,
+                                        &ccic0_mix_config, &ccic0_lock);
+        mmp_clk_add(unit, MMP2_CLK_CCIC0_MIX, clk);
+
+        ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1;
+        clk = mmp_clk_register_mix(NULL, "ccic1_mix_clk", ccic_parent_names,
+                                        ARRAY_SIZE(ccic_parent_names),
+                                        CLK_SET_RATE_PARENT,
+                                        &ccic1_mix_config, &ccic1_lock);
+        mmp_clk_add(unit, MMP2_CLK_CCIC1_MIX, clk);
+
+        mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
+                                ARRAY_SIZE(apmu_mux_clks));
+
+        mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
+                                ARRAY_SIZE(apmu_div_clks));
+
+        mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+                                ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void mmp2_clk_reset_init(struct device_node *np,
+                                struct mmp2_clk_unit *pxa_unit)
+{
+        struct mmp_clk_reset_cell *cells;
+        int i, nr_resets;
+
+        nr_resets = ARRAY_SIZE(apbc_gate_clks);
+        cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
+        if (!cells)
+                return;
+
+        for (i = 0; i < nr_resets; i++) {
+                cells[i].clk_id = apbc_gate_clks[i].id;
+                cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+                cells[i].flags = 0;
+                cells[i].lock = apbc_gate_clks[i].lock;
+                cells[i].bits = 0x4;
+        }
+
+        mmp_clk_reset_register(np, cells, nr_resets);
+}
+
+static void __init mmp2_clk_init(struct device_node *np)
+{
+        struct mmp2_clk_unit *pxa_unit;
+
+        pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+        if (!pxa_unit)
+                return;
+
+        pxa_unit->mpmu_base = of_iomap(np, 0);
+        if (!pxa_unit->mpmu_base) {
+                pr_err("failed to map mpmu registers\n");
+                return;
+        }
+
+        pxa_unit->apmu_base = of_iomap(np, 1);
+        if (!pxa_unit->mpmu_base) {
+                pr_err("failed to map apmu registers\n");
+                return;
+        }
+
+        pxa_unit->apbc_base = of_iomap(np, 2);
+        if (!pxa_unit->apbc_base) {
+                pr_err("failed to map apbc registers\n");
+                return;
+        }
+
+        mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
+
+        mmp2_pll_init(pxa_unit);
+
+        mmp2_apb_periph_clk_init(pxa_unit);
+
+        mmp2_axi_periph_clk_init(pxa_unit);
+
+        mmp2_clk_reset_init(np, pxa_unit);
+}
+
+CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c
new file mode 100644
index 000000000000..5b1810dc4bd2
--- /dev/null
+++ b/drivers/clk/mmp/clk-of-pxa168.c
@@ -0,0 +1,279 @@
+/*
+ * pxa168 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/marvell,pxa168.h>
+
+#include "clk.h"
+#include "reset.h"
+
+#define APBC_RTC        0x28
+#define APBC_TWSI0      0x2c
+#define APBC_KPC        0x30
+#define APBC_UART0      0x0
+#define APBC_UART1      0x4
+#define APBC_GPIO       0x8
+#define APBC_PWM0       0xc
+#define APBC_PWM1       0x10
+#define APBC_PWM2       0x14
+#define APBC_PWM3       0x18
+#define APBC_SSP0       0x81c
+#define APBC_SSP1       0x820
+#define APBC_SSP2       0x84c
+#define APBC_SSP3       0x858
+#define APBC_SSP4       0x85c
+#define APBC_TWSI1      0x6c
+#define APBC_UART2      0x70
+#define APMU_SDH0       0x54
+#define APMU_SDH1       0x58
+#define APMU_USB        0x5c
+#define APMU_DISP0      0x4c
+#define APMU_CCIC0      0x50
+#define APMU_DFC        0x60
+#define MPMU_UART_PLL   0x14
+
+struct pxa168_clk_unit {
+        struct mmp_clk_unit unit;
+        void __iomem *mpmu_base;
+        void __iomem *apmu_base;
+        void __iomem *apbc_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+        {PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
+        {PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
+        {PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+        {PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
+        {PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
+        {PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
+        {PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
+        {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
+        {PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
+        {PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
+        {PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
+        {PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
+        {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
+        {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
+        {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
+        {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+        .factor = 2,
+        .num_mask = 0x1fff,
+        .den_mask = 0x1fff,
+        .num_shift = 16,
+        .den_shift = 0,
+};
+
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
+        {.num = 8125, .den = 1536},     /*14.745MHZ */
+};
+
+static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
+{
+        struct clk *clk;
+        struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+        mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+                                        ARRAY_SIZE(fixed_rate_clks));
+
+        mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+                                        ARRAY_SIZE(fixed_factor_clks));
+
+        clk = mmp_clk_register_factor("uart_pll", "pll1_4",
+                                CLK_SET_RATE_PARENT,
+                                pxa_unit->mpmu_base + MPMU_UART_PLL,
+                                &uart_factor_masks, uart_factor_tbl,
+                                ARRAY_SIZE(uart_factor_tbl), NULL);
+        mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk);
+}
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
+
+static DEFINE_SPINLOCK(ssp0_lock);
+static DEFINE_SPINLOCK(ssp1_lock);
+static DEFINE_SPINLOCK(ssp2_lock);
+static DEFINE_SPINLOCK(ssp3_lock);
+static DEFINE_SPINLOCK(ssp4_lock);
+static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+
+static DEFINE_SPINLOCK(reset_lock);
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+        {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+        {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+        {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
+        {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
+        {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
+        {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
+        {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
+        {0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4, 3, 0, &ssp4_lock},
+};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+        {PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA168_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA168_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+        {PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+        {PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
+        /* The gate clocks has mux parent. */
+        {PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
+        {PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
+        {PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
+        {PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
+        {PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
+        {PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_lock},
+        {PXA168_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x3, 0x3, 0x0, 0, &ssp3_lock},
+        {PXA168_CLK_SSP4, "ssp4_clk", "ssp4_mux", CLK_SET_RATE_PARENT, APBC_SSP4, 0x3, 0x3, 0x0, 0, &ssp4_lock},
+};
+
+static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
+{
+        struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+        mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+                                ARRAY_SIZE(apbc_mux_clks));
+
+        mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+                                ARRAY_SIZE(apbc_gate_clks));
+
+}
+
+static DEFINE_SPINLOCK(sdh0_lock);
+static DEFINE_SPINLOCK(sdh1_lock);
+static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
+
+static DEFINE_SPINLOCK(usb_lock);
+
+static DEFINE_SPINLOCK(disp0_lock);
+static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
+
+static DEFINE_SPINLOCK(ccic0_lock);
+static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
+
+static struct mmp_param_mux_clk apmu_mux_clks[] = {
+        {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
+        {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
+        {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
+        {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
+        {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
+};
+
+static struct mmp_param_div_clk apmu_div_clks[] = {
+        {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+        {PXA168_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
+        {PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
+        {PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
+        /* The gate clocks has mux parent. */
+        {PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
+        {PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
+        {PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+        {PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
+        {PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
+        {PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
+};
+
+static void pxa168_axi_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
+{
+        struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+        mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
+                                ARRAY_SIZE(apmu_mux_clks));
+
+        mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
+                                ARRAY_SIZE(apmu_div_clks));
+
+        mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+                                ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void pxa168_clk_reset_init(struct device_node *np,
+                                struct pxa168_clk_unit *pxa_unit)
+{
+        struct mmp_clk_reset_cell *cells;
+        int i, nr_resets;
+
+        nr_resets = ARRAY_SIZE(apbc_gate_clks);
+        cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
+        if (!cells)
+                return;
+
+        for (i = 0; i < nr_resets; i++) {
+                cells[i].clk_id = apbc_gate_clks[i].id;
+                cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+                cells[i].flags = 0;
+                cells[i].lock = apbc_gate_clks[i].lock;
+                cells[i].bits = 0x4;
+        }
+
+        mmp_clk_reset_register(np, cells, nr_resets);
+}
+
+static void __init pxa168_clk_init(struct device_node *np)
+{
+        struct pxa168_clk_unit *pxa_unit;
+
+        pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+        if (!pxa_unit)
+                return;
+
+        pxa_unit->mpmu_base = of_iomap(np, 0);
+        if (!pxa_unit->mpmu_base) {
+                pr_err("failed to map mpmu registers\n");
+                return;
+        }
+
+        pxa_unit->apmu_base = of_iomap(np, 1);
+        if (!pxa_unit->mpmu_base) {
+                pr_err("failed to map apmu registers\n");
+                return;
+        }
+
+        pxa_unit->apbc_base = of_iomap(np, 2);
+        if (!pxa_unit->apbc_base) {
+                pr_err("failed to map apbc registers\n");
+                return;
+        }
+
+        mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS);
+
+        pxa168_pll_init(pxa_unit);
+
+        pxa168_apb_periph_clk_init(pxa_unit);
+
+        pxa168_axi_periph_clk_init(pxa_unit);
+
+        pxa168_clk_reset_init(np, pxa_unit);
+}
+
+CLK_OF_DECLARE(pxa168_clk, "marvell,pxa168-clock", pxa168_clk_init);
diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c
new file mode 100644
index 000000000000..5e3c80dad336
--- /dev/null
+++ b/drivers/clk/mmp/clk-of-pxa910.c
@@ -0,0 +1,301 @@
+/*
+ * pxa910 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/marvell,pxa910.h>
+
+#include "clk.h"
+#include "reset.h"
+
+#define APBC_RTC        0x28
+#define APBC_TWSI0      0x2c
+#define APBC_KPC        0x18
+#define APBC_UART0      0x0
+#define APBC_UART1      0x4
+#define APBC_GPIO       0x8
+#define APBC_PWM0       0xc
+#define APBC_PWM1       0x10
+#define APBC_PWM2       0x14
+#define APBC_PWM3       0x18
+#define APBC_SSP0       0x1c
+#define APBC_SSP1       0x20
+#define APBC_SSP2       0x4c
+#define APBCP_TWSI1     0x28
+#define APBCP_UART2     0x1c
+#define APMU_SDH0       0x54
+#define APMU_SDH1       0x58
+#define APMU_USB        0x5c
+#define APMU_DISP0      0x4c
+#define APMU_CCIC0      0x50
+#define APMU_DFC        0x60
+#define MPMU_UART_PLL   0x14
+
+struct pxa910_clk_unit {
+        struct mmp_clk_unit unit;
+        void __iomem *mpmu_base;
+        void __iomem *apmu_base;
+        void __iomem *apbc_base;
+        void __iomem *apbcp_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+        {PXA910_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
+        {PXA910_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
+        {PXA910_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+        {PXA910_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
+        {PXA910_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
+        {PXA910_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
+        {PXA910_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
+        {PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
+        {PXA910_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
+        {PXA910_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
+        {PXA910_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
+        {PXA910_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
+        {PXA910_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
+        {PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
+        {PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
+        {PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+        .factor = 2,
+        .num_mask = 0x1fff,
+        .den_mask = 0x1fff,
+        .num_shift = 16,
+        .den_shift = 0,
+};
+
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
+        {.num = 8125, .den = 1536},     /*14.745MHZ */
+};
+
+static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
+{
+        struct clk *clk;
+        struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+        mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+                                        ARRAY_SIZE(fixed_rate_clks));
+
+        mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+                                        ARRAY_SIZE(fixed_factor_clks));
+
+        clk = mmp_clk_register_factor("uart_pll", "pll1_4",
+                                CLK_SET_RATE_PARENT,
+                                pxa_unit->mpmu_base + MPMU_UART_PLL,
+                                &uart_factor_masks, uart_factor_tbl,
+                                ARRAY_SIZE(uart_factor_tbl), NULL);
+        mmp_clk_add(unit, PXA910_CLK_UART_PLL, clk);
+}
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
+
+static DEFINE_SPINLOCK(ssp0_lock);
+static DEFINE_SPINLOCK(ssp1_lock);
+static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+
+static DEFINE_SPINLOCK(reset_lock);
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+        {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+        {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+        {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
+        {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
+};
+
+static struct mmp_param_mux_clk apbcp_mux_clks[] = {
+        {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
+};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+        {PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+        {PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+        {PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
+        {PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
+        /* The gate clocks has mux parent. */
+        {PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
+        {PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
+        {PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
+        {PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
+};
+
+static struct mmp_param_gate_clk apbcp_gate_clks[] = {
+        {PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
+        /* The gate clocks has mux parent. */
+        {PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
+};
+
+static void pxa910_apb_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
+{
+        struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+        mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+                                ARRAY_SIZE(apbc_mux_clks));
+
+        mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
+                                ARRAY_SIZE(apbcp_mux_clks));
+
+        mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+                                ARRAY_SIZE(apbc_gate_clks));
+
+        mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
+                                ARRAY_SIZE(apbcp_gate_clks));
+}
+
+static DEFINE_SPINLOCK(sdh0_lock);
+static DEFINE_SPINLOCK(sdh1_lock);
+static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
+
+static DEFINE_SPINLOCK(usb_lock);
+
+static DEFINE_SPINLOCK(disp0_lock);
+static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
+
+static DEFINE_SPINLOCK(ccic0_lock);
+static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
+
+static struct mmp_param_mux_clk apmu_mux_clks[] = {
+        {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
+        {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
+        {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
+        {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
+        {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
+};
+
+static struct mmp_param_div_clk apmu_div_clks[] = {
+        {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+        {PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
+        {PXA910_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
+        {PXA910_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
+        /* The gate clocks has mux parent. */
+        {PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
+        {PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
+        {PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+        {PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
+        {PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
+        {PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
+};
+
+static void pxa910_axi_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
+{
+        struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+        mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
+                                ARRAY_SIZE(apmu_mux_clks));
+
+        mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
+                                ARRAY_SIZE(apmu_div_clks));
+
+        mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+                                ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void pxa910_clk_reset_init(struct device_node *np,
+                                struct pxa910_clk_unit *pxa_unit)
+{
+        struct mmp_clk_reset_cell *cells;
+        int i, base, nr_resets_apbc, nr_resets_apbcp, nr_resets;
+
+        nr_resets_apbc = ARRAY_SIZE(apbc_gate_clks);
+        nr_resets_apbcp = ARRAY_SIZE(apbcp_gate_clks);
+        nr_resets = nr_resets_apbc + nr_resets_apbcp;
+        cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
+        if (!cells)
+                return;
+
+        base = 0;
+        for (i = 0; i < nr_resets_apbc; i++) {
+                cells[base + i].clk_id = apbc_gate_clks[i].id;
+                cells[base + i].reg =
+                        pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+                cells[base + i].flags = 0;
+                cells[base + i].lock = apbc_gate_clks[i].lock;
+                cells[base + i].bits = 0x4;
+        }
+
+        base = nr_resets_apbc;
+        for (i = 0; i < nr_resets_apbcp; i++) {
+                cells[base + i].clk_id = apbcp_gate_clks[i].id;
+                cells[base + i].reg =
+                        pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+                cells[base + i].flags = 0;
+                cells[base + i].lock = apbc_gate_clks[i].lock;
+                cells[base + i].bits = 0x4;
+        }
+
+        mmp_clk_reset_register(np, cells, nr_resets);
+}
+
+static void __init pxa910_clk_init(struct device_node *np)
+{
+        struct pxa910_clk_unit *pxa_unit;
+
+        pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+        if (!pxa_unit)
+                return;
+
+        pxa_unit->mpmu_base = of_iomap(np, 0);
+        if (!pxa_unit->mpmu_base) {
+                pr_err("failed to map mpmu registers\n");
+                return;
+        }
+
+        pxa_unit->apmu_base = of_iomap(np, 1);
+        if (!pxa_unit->mpmu_base) {
+                pr_err("failed to map apmu registers\n");
+                return;
+        }
+
+        pxa_unit->apbc_base = of_iomap(np, 2);
+        if (!pxa_unit->apbc_base) {
+                pr_err("failed to map apbc registers\n");
+                return;
+        }
+
+        pxa_unit->apbcp_base = of_iomap(np, 3);
+        if (!pxa_unit->mpmu_base) {
+                pr_err("failed to map apbcp registers\n");
+                return;
+        }
+
+        mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS);
+
+        pxa910_pll_init(pxa_unit);
+
+        pxa910_apb_periph_clk_init(pxa_unit);
+
+        pxa910_axi_periph_clk_init(pxa_unit);
+
+        pxa910_clk_reset_init(np, pxa_unit);
+}
+
+CLK_OF_DECLARE(pxa910_clk, "marvell,pxa910-clock", pxa910_clk_init);
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index 014396b028a2..93e967c0f972 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -47,7 +47,7 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
-static struct clk_factor_masks uart_factor_masks = {
+static struct mmp_clk_factor_masks uart_factor_masks = {
         .factor = 2,
         .num_mask = 0x1fff,
         .den_mask = 0x1fff,
@@ -55,7 +55,7 @@ static struct clk_factor_masks uart_factor_masks = {
         .den_shift = 0,
 };
 
-static struct clk_factor_tbl uart_factor_tbl[] = {
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
         {.num = 8125, .den = 1536},     /*14.745MHZ */
 };
 
@@ -158,7 +158,7 @@ void __init pxa168_clk_init(void)
         uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                 mpmu_base + MPMU_UART_PLL,
                                 &uart_factor_masks, uart_factor_tbl,
-                                ARRAY_SIZE(uart_factor_tbl));
+                                ARRAY_SIZE(uart_factor_tbl), &clk_lock);
         clk_set_rate(uart_pll, 14745600);
         clk_register_clkdev(uart_pll, "uart_pll", NULL);
 
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index 9efc6a47535d..993abcdb32cc 100644
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -45,7 +45,7 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
-static struct clk_factor_masks uart_factor_masks = {
+static struct mmp_clk_factor_masks uart_factor_masks = {
         .factor = 2,
         .num_mask = 0x1fff,
         .den_mask = 0x1fff,
@@ -53,7 +53,7 @@ static struct clk_factor_masks uart_factor_masks = {
         .den_shift = 0,
 };
 
-static struct clk_factor_tbl uart_factor_tbl[] = {
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
         {.num = 8125, .den = 1536},     /*14.745MHZ */
 };
 
@@ -163,7 +163,7 @@ void __init pxa910_clk_init(void)
         uart_pll =  mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                 mpmu_base + MPMU_UART_PLL,
                                 &uart_factor_masks, uart_factor_tbl,
-                                ARRAY_SIZE(uart_factor_tbl));
+                                ARRAY_SIZE(uart_factor_tbl), &clk_lock);
         clk_set_rate(uart_pll, 14745600);
         clk_register_clkdev(uart_pll, "uart_pll", NULL);
 
diff --git a/drivers/clk/mmp/clk.c b/drivers/clk/mmp/clk.c
new file mode 100644
index 000000000000..cf038ef54c59
--- /dev/null
+++ b/drivers/clk/mmp/clk.c
@@ -0,0 +1,192 @@
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk.h"
+
+void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
+                int nr_clks)
+{
+        static struct clk **clk_table;
+
+        clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
+        if (!clk_table)
+                return;
+
+        unit->clk_table = clk_table;
+        unit->nr_clks = nr_clks;
+        unit->clk_data.clks = clk_table;
+        unit->clk_data.clk_num = nr_clks;
+        of_clk_add_provider(np, of_clk_src_onecell_get, &unit->clk_data);
+}
+
+void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
+                                struct mmp_param_fixed_rate_clk *clks,
+                                int size)
+{
+        int i;
+        struct clk *clk;
+
+        for (i = 0; i < size; i++) {
+                clk = clk_register_fixed_rate(NULL, clks[i].name,
+                                        clks[i].parent_name,
+                                        clks[i].flags,
+                                        clks[i].fixed_rate);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n",
+                               __func__, clks[i].name);
+                        continue;
+                }
+                if (clks[i].id)
+                        unit->clk_table[clks[i].id] = clk;
+        }
+}
+
+void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
+                                struct mmp_param_fixed_factor_clk *clks,
+                                int size)
+{
+        struct clk *clk;
+        int i;
+
+        for (i = 0; i < size; i++) {
+                clk = clk_register_fixed_factor(NULL, clks[i].name,
+                                                clks[i].parent_name,
+                                                clks[i].flags, clks[i].mult,
+                                                clks[i].div);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n",
+                               __func__, clks[i].name);
+                        continue;
+                }
+                if (clks[i].id)
+                        unit->clk_table[clks[i].id] = clk;
+        }
+}
+
+void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
+                                struct mmp_param_general_gate_clk *clks,
+                                void __iomem *base, int size)
+{
+        struct clk *clk;
+        int i;
+
+        for (i = 0; i < size; i++) {
+                clk = clk_register_gate(NULL, clks[i].name,
+                                        clks[i].parent_name,
+                                        clks[i].flags,
+                                        base + clks[i].offset,
+                                        clks[i].bit_idx,
+                                        clks[i].gate_flags,
+                                        clks[i].lock);
+
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n",
+                               __func__, clks[i].name);
+                        continue;
+                }
+                if (clks[i].id)
+                        unit->clk_table[clks[i].id] = clk;
+        }
+}
+
+void mmp_register_gate_clks(struct mmp_clk_unit *unit,
+                        struct mmp_param_gate_clk *clks,
+                        void __iomem *base, int size)
+{
+        struct clk *clk;
+        int i;
+
+        for (i = 0; i < size; i++) {
+                clk = mmp_clk_register_gate(NULL, clks[i].name,
+                                        clks[i].parent_name,
+                                        clks[i].flags,
+                                        base + clks[i].offset,
+                                        clks[i].mask,
+                                        clks[i].val_enable,
+                                        clks[i].val_disable,
+                                        clks[i].gate_flags,
+                                        clks[i].lock);
+
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n",
+                               __func__, clks[i].name);
+                        continue;
+                }
+                if (clks[i].id)
+                        unit->clk_table[clks[i].id] = clk;
+        }
+}
+
+void mmp_register_mux_clks(struct mmp_clk_unit *unit,
+                        struct mmp_param_mux_clk *clks,
+                        void __iomem *base, int size)
+{
+        struct clk *clk;
+        int i;
+
+        for (i = 0; i < size; i++) {
+                clk = clk_register_mux(NULL, clks[i].name,
+                                        clks[i].parent_name,
+                                        clks[i].num_parents,
+                                        clks[i].flags,
+                                        base + clks[i].offset,
+                                        clks[i].shift,
+                                        clks[i].width,
+                                        clks[i].mux_flags,
+                                        clks[i].lock);
+
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n",
+                               __func__, clks[i].name);
+                        continue;
+                }
+                if (clks[i].id)
+                        unit->clk_table[clks[i].id] = clk;
+        }
+}
+
+void mmp_register_div_clks(struct mmp_clk_unit *unit,
+                        struct mmp_param_div_clk *clks,
+                        void __iomem *base, int size)
+{
+        struct clk *clk;
+        int i;
+
+        for (i = 0; i < size; i++) {
+                clk = clk_register_divider(NULL, clks[i].name,
+                                        clks[i].parent_name,
+                                        clks[i].flags,
+                                        base + clks[i].offset,
+                                        clks[i].shift,
+                                        clks[i].width,
+                                        clks[i].div_flags,
+                                        clks[i].lock);
+
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n",
+                               __func__, clks[i].name);
+                        continue;
+                }
+                if (clks[i].id)
+                        unit->clk_table[clks[i].id] = clk;
+        }
+}
+
+void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
+                        struct clk *clk)
+{
+        if (IS_ERR_OR_NULL(clk)) {
+                pr_err("CLK %d has invalid pointer %p\n", id, clk);
+                return;
+        }
+        if (id > unit->nr_clks) {
+                pr_err("CLK %d is invalid\n", id);
+                return;
+        }
+
+        unit->clk_table[id] = clk;
+}
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
index ab86dd4a416a..adf9b711b037 100644
--- a/drivers/clk/mmp/clk.h
+++ b/drivers/clk/mmp/clk.h
@@ -7,19 +7,123 @@
 #define APBC_NO_BUS_CTRL        BIT(0)
 #define APBC_POWER_CTRL         BIT(1)
 
-struct clk_factor_masks {
-        unsigned int    factor;
-        unsigned int    num_mask;
-        unsigned int    den_mask;
-        unsigned int    num_shift;
-        unsigned int    den_shift;
+
+/* Clock type "factor" */
+struct mmp_clk_factor_masks {
+        unsigned int factor;
+        unsigned int num_mask;
+        unsigned int den_mask;
+        unsigned int num_shift;
+        unsigned int den_shift;
 };
 
-struct clk_factor_tbl {
+struct mmp_clk_factor_tbl {
         unsigned int num;
         unsigned int den;
 };
 
+struct mmp_clk_factor {
+        struct clk_hw hw;
+        void __iomem *base;
+        struct mmp_clk_factor_masks *masks;
+        struct mmp_clk_factor_tbl *ftbl;
+        unsigned int ftbl_cnt;
+        spinlock_t *lock;
+};
+
+extern struct clk *mmp_clk_register_factor(const char *name,
+                const char *parent_name, unsigned long flags,
+                void __iomem *base, struct mmp_clk_factor_masks *masks,
+                struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
+                spinlock_t *lock);
+
+/* Clock type "mix" */
+#define MMP_CLK_BITS_MASK(width, shift)                 \
+                (((1 << (width)) - 1) << (shift))
+#define MMP_CLK_BITS_GET_VAL(data, width, shift)        \
+                ((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
+#define MMP_CLK_BITS_SET_VAL(val, width, shift)         \
+                (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
+
+enum {
+        MMP_CLK_MIX_TYPE_V1,
+        MMP_CLK_MIX_TYPE_V2,
+        MMP_CLK_MIX_TYPE_V3,
+};
+
+/* The register layout */
+struct mmp_clk_mix_reg_info {
+        void __iomem *reg_clk_ctrl;
+        void __iomem *reg_clk_sel;
+        u8 width_div;
+        u8 shift_div;
+        u8 width_mux;
+        u8 shift_mux;
+        u8 bit_fc;
+};
+
+/* The suggested clock table from user. */
+struct mmp_clk_mix_clk_table {
+        unsigned long rate;
+        u8 parent_index;
+        unsigned int divisor;
+        unsigned int valid;
+};
+
+struct mmp_clk_mix_config {
+        struct mmp_clk_mix_reg_info reg_info;
+        struct mmp_clk_mix_clk_table *table;
+        unsigned int table_size;
+        u32 *mux_table;
+        struct clk_div_table *div_table;
+        u8 div_flags;
+        u8 mux_flags;
+};
+
+struct mmp_clk_mix {
+        struct clk_hw hw;
+        struct mmp_clk_mix_reg_info reg_info;
+        struct mmp_clk_mix_clk_table *table;
+        u32 *mux_table;
+        struct clk_div_table *div_table;
+        unsigned int table_size;
+        u8 div_flags;
+        u8 mux_flags;
+        unsigned int type;
+        spinlock_t *lock;
+};
+
+extern const struct clk_ops mmp_clk_mix_ops;
+extern struct clk *mmp_clk_register_mix(struct device *dev,
+                                        const char *name,
+                                        const char **parent_names,
+                                        u8 num_parents,
+                                        unsigned long flags,
+                                        struct mmp_clk_mix_config *config,
+                                        spinlock_t *lock);
+
+
+/* Clock type "gate". MMP private gate */
+#define MMP_CLK_GATE_NEED_DELAY         BIT(0)
+
+struct mmp_clk_gate {
+        struct clk_hw hw;
+        void __iomem *reg;
+        u32 mask;
+        u32 val_enable;
+        u32 val_disable;
+        unsigned int flags;
+        spinlock_t *lock;
+};
+
+extern const struct clk_ops mmp_clk_gate_ops;
+extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
+                        const char *parent_name, unsigned long flags,
+                        void __iomem *reg, u32 mask, u32 val_enable,
+                        u32 val_disable, unsigned int gate_flags,
+                        spinlock_t *lock);
+
+
 extern struct clk *mmp_clk_register_pll2(const char *name,
                 const char *parent_name, unsigned long flags);
 extern struct clk *mmp_clk_register_apbc(const char *name,
@@ -28,8 +132,108 @@ extern struct clk *mmp_clk_register_apbc(const char *name,
 extern struct clk *mmp_clk_register_apmu(const char *name,
                 const char *parent_name, void __iomem *base, u32 enable_mask,
                 spinlock_t *lock);
-extern struct clk *mmp_clk_register_factor(const char *name,
-                const char *parent_name, unsigned long flags,
-                void __iomem *base, struct clk_factor_masks *masks,
-                struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
+
+struct mmp_clk_unit {
+        unsigned int nr_clks;
+        struct clk **clk_table;
+        struct clk_onecell_data clk_data;
+};
+
+struct mmp_param_fixed_rate_clk {
+        unsigned int id;
+        char *name;
+        const char *parent_name;
+        unsigned long flags;
+        unsigned long fixed_rate;
+};
+void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
+                                struct mmp_param_fixed_rate_clk *clks,
+                                int size);
+
+struct mmp_param_fixed_factor_clk {
+        unsigned int id;
+        char *name;
+        const char *parent_name;
+        unsigned long mult;
+        unsigned long div;
+        unsigned long flags;
+};
+void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
+                                struct mmp_param_fixed_factor_clk *clks,
+                                int size);
+
+struct mmp_param_general_gate_clk {
+        unsigned int id;
+        const char *name;
+        const char *parent_name;
+        unsigned long flags;
+        unsigned long offset;
+        u8 bit_idx;
+        u8 gate_flags;
+        spinlock_t *lock;
+};
+void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
+                                struct mmp_param_general_gate_clk *clks,
+                                void __iomem *base, int size);
+
+struct mmp_param_gate_clk {
+        unsigned int id;
+        char *name;
+        const char *parent_name;
+        unsigned long flags;
+        unsigned long offset;
+        u32 mask;
+        u32 val_enable;
+        u32 val_disable;
+        unsigned int gate_flags;
+        spinlock_t *lock;
+};
+void mmp_register_gate_clks(struct mmp_clk_unit *unit,
+                        struct mmp_param_gate_clk *clks,
+                        void __iomem *base, int size);
+
+struct mmp_param_mux_clk {
+        unsigned int id;
+        char *name;
+        const char **parent_name;
+        u8 num_parents;
+        unsigned long flags;
+        unsigned long offset;
+        u8 shift;
+        u8 width;
+        u8 mux_flags;
+        spinlock_t *lock;
+};
+void mmp_register_mux_clks(struct mmp_clk_unit *unit,
+                        struct mmp_param_mux_clk *clks,
+                        void __iomem *base, int size);
+
+struct mmp_param_div_clk {
+        unsigned int id;
+        char *name;
+        const char *parent_name;
+        unsigned long flags;
+        unsigned long offset;
+        u8 shift;
+        u8 width;
+        u8 div_flags;
+        spinlock_t *lock;
+};
+void mmp_register_div_clks(struct mmp_clk_unit *unit,
+                        struct mmp_param_div_clk *clks,
+                        void __iomem *base, int size);
+
+#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc)     \
+{                                                       \
+        .width_div = (w_d),                             \
+        .shift_div = (s_d),                             \
+        .width_mux = (w_m),                             \
+        .shift_mux = (s_m),                             \
+        .bit_fc = (fc),                                 \
+}
+
+void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
+                int nr_clks);
+void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
+                struct clk *clk);
 #endif
diff --git a/drivers/clk/mmp/reset.c b/drivers/clk/mmp/reset.c
new file mode 100644
index 000000000000..b54da1fe73f0
--- /dev/null
+++ b/drivers/clk/mmp/reset.c
@@ -0,0 +1,99 @@
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
+
+#include "reset.h"
+
+#define rcdev_to_unit(rcdev) container_of(rcdev, struct mmp_clk_reset_unit, rcdev)
+
+static int mmp_of_reset_xlate(struct reset_controller_dev *rcdev,
+                          const struct of_phandle_args *reset_spec)
+{
+        struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
+        struct mmp_clk_reset_cell *cell;
+        int i;
+
+        if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+                return -EINVAL;
+
+        for (i = 0; i < rcdev->nr_resets; i++) {
+                cell = &unit->cells[i];
+                if (cell->clk_id == reset_spec->args[0])
+                        break;
+        }
+
+        if (i == rcdev->nr_resets)
+                return -EINVAL;
+
+        return i;
+}
+
+static int mmp_clk_reset_assert(struct reset_controller_dev *rcdev,
+                                unsigned long id)
+{
+        struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
+        struct mmp_clk_reset_cell *cell;
+        unsigned long flags = 0;
+        u32 val;
+
+        cell = &unit->cells[id];
+        if (cell->lock)
+                spin_lock_irqsave(cell->lock, flags);
+
+        val = readl(cell->reg);
+        val |= cell->bits;
+        writel(val, cell->reg);
+
+        if (cell->lock)
+                spin_unlock_irqrestore(cell->lock, flags);
+
+        return 0;
+}
+
+static int mmp_clk_reset_deassert(struct reset_controller_dev *rcdev,
+                                unsigned long id)
+{
+        struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
+        struct mmp_clk_reset_cell *cell;
+        unsigned long flags = 0;
+        u32 val;
+
+        cell = &unit->cells[id];
+        if (cell->lock)
+                spin_lock_irqsave(cell->lock, flags);
+
+        val = readl(cell->reg);
+        val &= ~cell->bits;
+        writel(val, cell->reg);
+
+        if (cell->lock)
+                spin_unlock_irqrestore(cell->lock, flags);
+
+        return 0;
+}
+
+static struct reset_control_ops mmp_clk_reset_ops = {
+        .assert         = mmp_clk_reset_assert,
+        .deassert       = mmp_clk_reset_deassert,
+};
+
+void mmp_clk_reset_register(struct device_node *np,
+                        struct mmp_clk_reset_cell *cells, int nr_resets)
+{
+        struct mmp_clk_reset_unit *unit;
+
+        unit = kzalloc(sizeof(*unit), GFP_KERNEL);
+        if (!unit)
+                return;
+
+        unit->cells = cells;
+        unit->rcdev.of_reset_n_cells = 1;
+        unit->rcdev.nr_resets = nr_resets;
+        unit->rcdev.ops = &mmp_clk_reset_ops;
+        unit->rcdev.of_node = np;
+        unit->rcdev.of_xlate = mmp_of_reset_xlate;
+
+        reset_controller_register(&unit->rcdev);
+}
diff --git a/drivers/clk/mmp/reset.h b/drivers/clk/mmp/reset.h
new file mode 100644
index 000000000000..be8b1a7000f7
--- /dev/null
+++ b/drivers/clk/mmp/reset.h
@@ -0,0 +1,31 @@
+#ifndef __MACH_MMP_CLK_RESET_H
+#define __MACH_MMP_CLK_RESET_H
+
+#include <linux/reset-controller.h>
+
+#define MMP_RESET_INVERT        1
+
+struct mmp_clk_reset_cell {
+        unsigned int clk_id;
+        void __iomem *reg;
+        u32 bits;
+        unsigned int flags;
+        spinlock_t *lock;
+};
+
+struct mmp_clk_reset_unit {
+        struct reset_controller_dev rcdev;
+        struct mmp_clk_reset_cell *cells;
+};
+
+#ifdef CONFIG_RESET_CONTROLLER
+void mmp_clk_reset_register(struct device_node *np,
+                        struct mmp_clk_reset_cell *cells, int nr_resets);
+#else
+static inline void mmp_clk_reset_register(struct device_node *np,
+                        struct mmp_clk_reset_cell *cells, int nr_resets)
+{
+}
+#endif
+
+#endif
diff --git a/drivers/clk/pxa/Makefile b/drivers/clk/pxa/Makefile
index 4ff2abcd500b..38e915344605 100644
--- a/drivers/clk/pxa/Makefile
+++ b/drivers/clk/pxa/Makefile
@@ -1,2 +1,3 @@
 obj-y                           += clk-pxa.o
+obj-$(CONFIG_PXA25x)            += clk-pxa25x.o
 obj-$(CONFIG_PXA27x)            += clk-pxa27x.o
diff --git a/drivers/clk/pxa/clk-pxa.c b/drivers/clk/pxa/clk-pxa.c
index ef3c05389c0a..4e834753ab09 100644
--- a/drivers/clk/pxa/clk-pxa.c
+++ b/drivers/clk/pxa/clk-pxa.c
@@ -26,12 +26,20 @@ static struct clk_onecell_data onecell_data = {
         .clk_num = CLK_MAX,
 };
 
-#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk_cken, hw)
+struct pxa_clk {
+        struct clk_hw hw;
+        struct clk_fixed_factor lp;
+        struct clk_fixed_factor hp;
+        struct clk_gate gate;
+        bool (*is_in_low_power)(void);
+};
+
+#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk, hw)
 
 static unsigned long cken_recalc_rate(struct clk_hw *hw,
                                       unsigned long parent_rate)
 {
-        struct pxa_clk_cken *pclk = to_pxa_clk(hw);
+        struct pxa_clk *pclk = to_pxa_clk(hw);
         struct clk_fixed_factor *fix;
 
         if (!pclk->is_in_low_power || pclk->is_in_low_power())
@@ -48,7 +56,7 @@ static struct clk_ops cken_rate_ops = {
 
 static u8 cken_get_parent(struct clk_hw *hw)
 {
-        struct pxa_clk_cken *pclk = to_pxa_clk(hw);
+        struct pxa_clk *pclk = to_pxa_clk(hw);
 
         if (!pclk->is_in_low_power)
                 return 0;
@@ -69,29 +77,32 @@ void __init clkdev_pxa_register(int ckid, const char *con_id,
                 clk_register_clkdev(clk, con_id, dev_id);
 }
 
-int __init clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks)
+int __init clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks)
 {
         int i;
-        struct pxa_clk_cken *pclk;
+        struct pxa_clk *pxa_clk;
         struct clk *clk;
 
         for (i = 0; i < nb_clks; i++) {
-                pclk = clks + i;
-                pclk->gate.lock = &lock;
-                clk = clk_register_composite(NULL, pclk->name,
-                                             pclk->parent_names, 2,
-                                             &pclk->hw, &cken_mux_ops,
-                                             &pclk->hw, &cken_rate_ops,
-                                             &pclk->gate.hw, &clk_gate_ops,
-                                             pclk->flags);
-                clkdev_pxa_register(pclk->ckid, pclk->con_id, pclk->dev_id,
-                                    clk);
+                pxa_clk = kzalloc(sizeof(*pxa_clk), GFP_KERNEL);
+                pxa_clk->is_in_low_power = clks[i].is_in_low_power;
+                pxa_clk->lp = clks[i].lp;
+                pxa_clk->hp = clks[i].hp;
+                pxa_clk->gate = clks[i].gate;
+                pxa_clk->gate.lock = &lock;
+                clk = clk_register_composite(NULL, clks[i].name,
+                                             clks[i].parent_names, 2,
+                                             &pxa_clk->hw, &cken_mux_ops,
+                                             &pxa_clk->hw, &cken_rate_ops,
+                                             &pxa_clk->gate.hw, &clk_gate_ops,
+                                             clks[i].flags);
+                clkdev_pxa_register(clks[i].ckid, clks[i].con_id,
+                                    clks[i].dev_id, clk);
         }
         return 0;
 }
 
-static void __init pxa_dt_clocks_init(struct device_node *np)
+void __init clk_pxa_dt_common_init(struct device_node *np)
 {
         of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
 }
-CLK_OF_DECLARE(pxa_clks, "marvell,pxa-clocks", pxa_dt_clocks_init);
diff --git a/drivers/clk/pxa/clk-pxa.h b/drivers/clk/pxa/clk-pxa.h
index 5fe219d06b49..323965430111 100644
--- a/drivers/clk/pxa/clk-pxa.h
+++ b/drivers/clk/pxa/clk-pxa.h
@@ -25,7 +25,7 @@
         static struct clk_ops name ## _rate_ops = {             \
                 .recalc_rate = name ## _get_rate,               \
         };                                                      \
-        static struct clk *clk_register_ ## name(void)          \
+        static struct clk * __init clk_register_ ## name(void)  \
         {                                                       \
                 return clk_register_composite(NULL, clk_name,   \
                         name ## _parents,                       \
@@ -40,7 +40,7 @@
         static struct clk_ops name ## _rate_ops = {             \
                 .recalc_rate = name ## _get_rate,               \
         };                                                      \
-        static struct clk *clk_register_ ## name(void)          \
+        static struct clk * __init clk_register_ ## name(void)  \
         {                                                       \
                 return clk_register_composite(NULL, clk_name,   \
                         name ## _parents,                       \
@@ -66,7 +66,7 @@
  *  |    Clock   | --- | / div_hp  |
  *  +------------+     +-----------+
  */
-struct pxa_clk_cken {
+struct desc_clk_cken {
         struct clk_hw hw;
         int ckid;
         const char *name;
@@ -102,6 +102,7 @@ static int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
 
 extern void clkdev_pxa_register(int ckid, const char *con_id,
                                 const char *dev_id, struct clk *clk);
-extern int clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks);
+extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks);
+void clk_pxa_dt_common_init(struct device_node *np);
 
 #endif
diff --git a/drivers/clk/pxa/clk-pxa25x.c b/drivers/clk/pxa/clk-pxa25x.c
new file mode 100644
index 000000000000..6cd88d963a7f
--- /dev/null
+++ b/drivers/clk/pxa/clk-pxa25x.c
@@ -0,0 +1,273 @@
+/*
+ * Marvell PXA25x family clocks
+ *
+ * Copyright (C) 2014 Robert Jarzmik
+ *
+ * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
+ * should go away.
+ */
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <mach/pxa25x.h>
+#include <mach/pxa2xx-regs.h>
+
+#include <dt-bindings/clock/pxa-clock.h>
+#include "clk-pxa.h"
+
+#define KHz 1000
+#define MHz (1000 * 1000)
+
+enum {
+        PXA_CORE_RUN = 0,
+        PXA_CORE_TURBO,
+};
+
+/*
+ * Various clock factors driven by the CCCR register.
+ */
+
+/* Crystal Frequency to Memory Frequency Multiplier (L) */
+static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
+
+/* Memory Frequency to Run Mode Frequency Multiplier (M) */
+static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
+
+/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
+/* Note: we store the value N * 2 here. */
+static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
+
+static const char * const get_freq_khz[] = {
+        "core", "run", "cpll", "memory"
+};
+
+/*
+ * Get the clock frequency as reflected by CCCR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
+ */
+unsigned int pxa25x_get_clk_frequency_khz(int info)
+{
+        struct clk *clk;
+        unsigned long clks[5];
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
+                clk = clk_get(NULL, get_freq_khz[i]);
+                if (IS_ERR(clk)) {
+                        clks[i] = 0;
+                } else {
+                        clks[i] = clk_get_rate(clk);
+                        clk_put(clk);
+                }
+        }
+
+        if (info) {
+                pr_info("Run Mode clock: %ld.%02ldMHz\n",
+                        clks[1] / 1000000, (clks[1] % 1000000) / 10000);
+                pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
+                        clks[2] / 1000000, (clks[2] % 1000000) / 10000);
+                pr_info("Memory clock: %ld.%02ldMHz\n",
+                        clks[3] / 1000000, (clks[3] % 1000000) / 10000);
+        }
+
+        return (unsigned int)clks[0];
+}
+
+static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
+                                                unsigned long parent_rate)
+{
+        unsigned long cccr = CCCR;
+        unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
+
+        return parent_rate / m;
+}
+PARENTS(clk_pxa25x_memory) = { "run" };
+RATE_RO_OPS(clk_pxa25x_memory, "memory");
+
+PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
+PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
+PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
+
+#define PXA25X_CKEN(dev_id, con_id, parents, mult, div,                 \
+                    bit, is_lp, flags)                                  \
+        PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div,    \
+                 is_lp,  &CKEN, CKEN_ ## bit, flags)
+#define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
+        PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp,     \
+                    div_hp, bit, NULL, 0)
+#define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
+        PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp,    \
+                    div_hp, bit, NULL, 0)
+#define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)   \
+        PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp,       \
+                    div_hp, bit, NULL, 0)
+
+#define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay)          \
+        PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
+                       &CKEN, CKEN_ ## bit, 0)
+#define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay)       \
+        PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
+                       &CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
+
+static struct desc_clk_cken pxa25x_clocks[] __initdata = {
+        PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
+        PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
+        PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
+        PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
+        PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
+        PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
+        PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
+        PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
+        PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
+        PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
+        PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
+        PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
+        PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
+        PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
+        PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
+
+        PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
+        PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
+                             clk_pxa25x_memory_parents, 0),
+};
+
+static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
+{
+        unsigned long clkcfg;
+        unsigned int t;
+
+        asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
+        t  = clkcfg & (1 << 0);
+        if (t)
+                return PXA_CORE_TURBO;
+        return PXA_CORE_RUN;
+}
+
+static unsigned long clk_pxa25x_core_get_rate(struct clk_hw *hw,
+                                              unsigned long parent_rate)
+{
+        return parent_rate;
+}
+PARENTS(clk_pxa25x_core) = { "run", "cpll" };
+MUX_RO_RATE_RO_OPS(clk_pxa25x_core, "core");
+
+static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
+                                             unsigned long parent_rate)
+{
+        unsigned long cccr = CCCR;
+        unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
+
+        return (parent_rate / n2) * 2;
+}
+PARENTS(clk_pxa25x_run) = { "cpll" };
+RATE_RO_OPS(clk_pxa25x_run, "run");
+
+static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
+        unsigned long parent_rate)
+{
+        unsigned long clkcfg, cccr = CCCR;
+        unsigned int l, m, n2, t;
+
+        asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
+        t = clkcfg & (1 << 0);
+        l  =  L_clk_mult[(cccr >> 0) & 0x1f];
+        m = M_clk_mult[(cccr >> 5) & 0x03];
+        n2 = N2_clk_mult[(cccr >> 7) & 0x07];
+
+        if (t)
+                return m * l * n2 * parent_rate / 2;
+        return m * l * parent_rate;
+}
+PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
+RATE_RO_OPS(clk_pxa25x_cpll, "cpll");
+
+static void __init pxa25x_register_core(void)
+{
+        clk_register_clk_pxa25x_cpll();
+        clk_register_clk_pxa25x_run();
+        clkdev_pxa_register(CLK_CORE, "core", NULL,
+                            clk_register_clk_pxa25x_core());
+}
+
+static void __init pxa25x_register_plls(void)
+{
+        clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
+                                CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
+                                3686400);
+        clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
+                                CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
+                                32768);
+        clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
+        clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
+                                  0, 26, 1);
+        clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
+                                  0, 40, 1);
+}
+
+static void __init pxa25x_base_clocks_init(void)
+{
+        pxa25x_register_plls();
+        pxa25x_register_core();
+        clk_register_clk_pxa25x_memory();
+}
+
+#define DUMMY_CLK(_con_id, _dev_id, _parent) \
+        { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
+struct dummy_clk {
+        const char *con_id;
+        const char *dev_id;
+        const char *parent;
+};
+static struct dummy_clk dummy_clks[] __initdata = {
+        DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
+        DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
+        DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
+        DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
+        DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
+        DUMMY_CLK("OSTIMER0", NULL, "osc_32_768khz"),
+        DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
+};
+
+static void __init pxa25x_dummy_clocks_init(void)
+{
+        struct clk *clk;
+        struct dummy_clk *d;
+        const char *name;
+        int i;
+
+        /*
+         * All pinctrl logic has been wiped out of the clock driver, especially
+         * for gpio11 and gpio12 outputs. Machine code should ensure proper pin
+         * control (ie. pxa2xx_mfp_config() invocation).
+         */
+        for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
+                d = &dummy_clks[i];
+                name = d->dev_id ? d->dev_id : d->con_id;
+                clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
+                clk_register_clkdev(clk, d->con_id, d->dev_id);
+        }
+}
+
+int __init pxa25x_clocks_init(void)
+{
+        pxa25x_base_clocks_init();
+        pxa25x_dummy_clocks_init();
+        return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks));
+}
+
+static void __init pxa25x_dt_clocks_init(struct device_node *np)
+{
+        pxa25x_clocks_init();
+        clk_pxa_dt_common_init(np);
+}
+CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
+               pxa25x_dt_clocks_init);
diff --git a/drivers/clk/pxa/clk-pxa27x.c b/drivers/clk/pxa/clk-pxa27x.c
index 88b9fe13fa44..5f9b54b024b9 100644
--- a/drivers/clk/pxa/clk-pxa27x.c
+++ b/drivers/clk/pxa/clk-pxa27x.c
@@ -111,7 +111,7 @@ PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
         PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
                        &CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
 
-static struct pxa_clk_cken pxa27x_clocks[] = {
+static struct desc_clk_cken pxa27x_clocks[] __initdata = {
         PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
         PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
         PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
@@ -368,3 +368,10 @@ static int __init pxa27x_clocks_init(void)
         return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
 }
 postcore_initcall(pxa27x_clocks_init);
+
+static void __init pxa27x_dt_clocks_init(struct device_node *np)
+{
+        pxa27x_clocks_init();
+        clk_pxa_dt_common_init(np);
+}
+CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index b823bc3b6250..60873a7f45d9 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -141,7 +141,7 @@ struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
 
 static long
 clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate,
-                       unsigned long *p_rate, struct clk **p)
+                       unsigned long *p_rate, struct clk_hw **p)
 {
         struct clk_pll *pll = to_clk_pll(hw);
         const struct pll_freq_tbl *f;
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index b6e6959e89aa..0b93972c8807 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -368,16 +368,17 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 
 static long _freq_tbl_determine_rate(struct clk_hw *hw,
                 const struct freq_tbl *f, unsigned long rate,
-                unsigned long *p_rate, struct clk **p)
+                unsigned long *p_rate, struct clk_hw **p_hw)
 {
         unsigned long clk_flags;
+        struct clk *p;
 
         f = qcom_find_freq(f, rate);
         if (!f)
                 return -EINVAL;
 
         clk_flags = __clk_get_flags(hw->clk);
-        *p = clk_get_parent_by_index(hw->clk, f->src);
+        p = clk_get_parent_by_index(hw->clk, f->src);
         if (clk_flags & CLK_SET_RATE_PARENT) {
                 rate = rate * f->pre_div;
                 if (f->n) {
@@ -387,15 +388,16 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
                         rate = tmp;
                 }
         } else {
-                rate =  __clk_get_rate(*p);
+                rate =  __clk_get_rate(p);
         }
+        *p_hw = __clk_get_hw(p);
         *p_rate = rate;
 
         return f->freq;
 }
 
 static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long *p_rate, struct clk **p)
+                unsigned long *p_rate, struct clk_hw **p)
 {
         struct clk_rcg *rcg = to_clk_rcg(hw);
 
@@ -403,7 +405,7 @@ static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
 }
 
 static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long *p_rate, struct clk **p)
+                unsigned long *p_rate, struct clk_hw **p)
 {
         struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
 
@@ -411,13 +413,15 @@ static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
 }
 
 static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long *p_rate, struct clk **p)
+                unsigned long *p_rate, struct clk_hw **p_hw)
 {
         struct clk_rcg *rcg = to_clk_rcg(hw);
         const struct freq_tbl *f = rcg->freq_tbl;
+        struct clk *p;
 
-        *p = clk_get_parent_by_index(hw->clk, f->src);
-        *p_rate = __clk_round_rate(*p, rate);
+        p = clk_get_parent_by_index(hw->clk, f->src);
+        *p_hw = __clk_get_hw(p);
+        *p_rate = __clk_round_rate(p, rate);
 
         return *p_rate;
 }
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index cfa9eb4fe9ca..08b8b3729f53 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -175,16 +175,17 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 
 static long _freq_tbl_determine_rate(struct clk_hw *hw,
                 const struct freq_tbl *f, unsigned long rate,
-                unsigned long *p_rate, struct clk **p)
+                unsigned long *p_rate, struct clk_hw **p_hw)
 {
         unsigned long clk_flags;
+        struct clk *p;
 
         f = qcom_find_freq(f, rate);
         if (!f)
                 return -EINVAL;
 
         clk_flags = __clk_get_flags(hw->clk);
-        *p = clk_get_parent_by_index(hw->clk, f->src);
+        p = clk_get_parent_by_index(hw->clk, f->src);
         if (clk_flags & CLK_SET_RATE_PARENT) {
                 if (f->pre_div) {
                         rate /= 2;
@@ -198,15 +199,16 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
                         rate = tmp;
                 }
         } else {
-                rate =  __clk_get_rate(*p);
+                rate =  __clk_get_rate(p);
         }
+        *p_hw = __clk_get_hw(p);
         *p_rate = rate;
 
         return f->freq;
 }
 
 static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long *p_rate, struct clk **p)
+                unsigned long *p_rate, struct clk_hw **p)
 {
         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 
@@ -359,7 +361,7 @@ static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
 }
 
 static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
-                                 unsigned long *p_rate, struct clk **p)
+                                 unsigned long *p_rate, struct clk_hw **p)
 {
         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
         const struct freq_tbl *f = rcg->freq_tbl;
@@ -371,7 +373,7 @@ static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
         u32 hid_div;
 
         /* Force the correct parent */
-        *p = clk_get_parent_by_index(hw->clk, f->src);
+        *p = __clk_get_hw(clk_get_parent_by_index(hw->clk, f->src));
 
         if (src_rate == 810000000)
                 frac = frac_table_810m;
@@ -410,18 +412,20 @@ const struct clk_ops clk_edp_pixel_ops = {
 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
 
 static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
-                         unsigned long *p_rate, struct clk **p)
+                         unsigned long *p_rate, struct clk_hw **p_hw)
 {
         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
         const struct freq_tbl *f = rcg->freq_tbl;
         unsigned long parent_rate, div;
         u32 mask = BIT(rcg->hid_width) - 1;
+        struct clk *p;
 
         if (rate == 0)
                 return -EINVAL;
 
-        *p = clk_get_parent_by_index(hw->clk, f->src);
-        *p_rate = parent_rate = __clk_round_rate(*p, rate);
+        p = clk_get_parent_by_index(hw->clk, f->src);
+        *p_hw = __clk_get_hw(p);
+        *p_rate = parent_rate = __clk_round_rate(p, rate);
 
         div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
         div = min_t(u32, div, mask);
@@ -472,14 +476,16 @@ static const struct frac_entry frac_table_pixel[] = {
 };
 
 static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
-                                 unsigned long *p_rate, struct clk **p)
+                                 unsigned long *p_rate, struct clk_hw **p)
 {
         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
         unsigned long request, src_rate;
         int delta = 100000;
         const struct freq_tbl *f = rcg->freq_tbl;
         const struct frac_entry *frac = frac_table_pixel;
-        struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src);
+        struct clk *parent = clk_get_parent_by_index(hw->clk, f->src);
+
+        *p = __clk_get_hw(parent);
 
         for (; frac->num; frac++) {
                 request = (rate * frac->den) / frac->num;
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index bd8514d63634..2714097f90db 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -6,6 +6,7 @@ obj-y	+= clk-rockchip.o
 obj-y   += clk.o
 obj-y   += clk-pll.o
 obj-y   += clk-cpu.o
+obj-y   += clk-mmc-phase.o
 obj-$(CONFIG_RESET_CONTROLLER)  += softrst.o
 
 obj-y   += clk-rk3188.o
diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c
new file mode 100644
index 000000000000..c842e3b60f21
--- /dev/null
+++ b/drivers/clk/rockchip/clk-mmc-phase.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2014 Google, Inc
+ * Author: Alexandru M Stan <amstan@chromium.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include "clk.h"
+
+struct rockchip_mmc_clock {
+        struct clk_hw   hw;
+        void __iomem    *reg;
+        int             id;
+        int             shift;
+};
+
+#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
+
+#define RK3288_MMC_CLKGEN_DIV 2
+
+static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+        return parent_rate / RK3288_MMC_CLKGEN_DIV;
+}
+
+#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
+#define ROCKCHIP_MMC_DEGREE_MASK 0x3
+#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
+#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
+
+#define PSECS_PER_SEC 1000000000000LL
+
+/*
+ * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to
+ * simplify calculations. So 45degs could be anywhere between 33deg and 66deg.
+ */
+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
+
+static int rockchip_mmc_get_phase(struct clk_hw *hw)
+{
+        struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
+        unsigned long rate = clk_get_rate(hw->clk);
+        u32 raw_value;
+        u16 degrees;
+        u32 delay_num = 0;
+
+        raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
+
+        degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
+
+        if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
+                /* degrees/delaynum * 10000 */
+                unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
+                                        36 * (rate / 1000000);
+
+                delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
+                delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
+                degrees += delay_num * factor / 10000;
+        }
+
+        return degrees % 360;
+}
+
+static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
+{
+        struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
+        unsigned long rate = clk_get_rate(hw->clk);
+        u8 nineties, remainder;
+        u8 delay_num;
+        u32 raw_value;
+        u64 delay;
+
+        /* allow 22 to be 22.5 */
+        degrees++;
+        /* floor to 22.5 increment */
+        degrees -= ((degrees) * 10 % 225) / 10;
+
+        nineties = degrees / 90;
+        /* 22.5 multiples */
+        remainder = (degrees % 90) / 22;
+
+        delay = PSECS_PER_SEC;
+        do_div(delay, rate);
+        /* / 360 / 22.5 */
+        do_div(delay, 16);
+        do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);
+
+        delay *= remainder;
+        delay_num = (u8) min(delay, 255ULL);
+
+        raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
+        raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
+        raw_value |= nineties;
+        writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg);
+
+        pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
+                __clk_get_name(hw->clk), degrees, delay_num,
+                mmc_clock->reg, raw_value>>(mmc_clock->shift),
+                rockchip_mmc_get_phase(hw)
+        );
+
+        return 0;
+}
+
+static const struct clk_ops rockchip_mmc_clk_ops = {
+        .recalc_rate    = rockchip_mmc_recalc,
+        .get_phase      = rockchip_mmc_get_phase,
+        .set_phase      = rockchip_mmc_set_phase,
+};
+
+struct clk *rockchip_clk_register_mmc(const char *name,
+                                const char **parent_names, u8 num_parents,
+                                void __iomem *reg, int shift)
+{
+        struct clk_init_data init;
+        struct rockchip_mmc_clock *mmc_clock;
+        struct clk *clk;
+
+        mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
+        if (!mmc_clock)
+                return NULL;
+
+        init.num_parents = num_parents;
+        init.parent_names = parent_names;
+        init.ops = &rockchip_mmc_clk_ops;
+
+        mmc_clock->hw.init = &init;
+        mmc_clock->reg = reg;
+        mmc_clock->shift = shift;
+
+        if (name)
+                init.name = name;
+
+        clk = clk_register(NULL, &mmc_clock->hw);
+        if (IS_ERR(clk))
+                goto err_free;
+
+        return clk;
+
+err_free:
+        kfree(mmc_clock);
+        return NULL;
+}
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index a3e886a38480..f8d3baf275b2 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -39,6 +39,7 @@ struct rockchip_clk_pll {
         int                     lock_offset;
         unsigned int            lock_shift;
         enum rockchip_pll_type  type;
+        u8                      flags;
         const struct rockchip_pll_rate_table *rate_table;
         unsigned int            rate_count;
         spinlock_t              *lock;
@@ -257,6 +258,55 @@ static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
         return !(pllcon & RK3066_PLLCON3_PWRDOWN);
 }
 
+static void rockchip_rk3066_pll_init(struct clk_hw *hw)
+{
+        struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+        const struct rockchip_pll_rate_table *rate;
+        unsigned int nf, nr, no, bwadj;
+        unsigned long drate;
+        u32 pllcon;
+
+        if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
+                return;
+
+        drate = __clk_get_rate(hw->clk);
+        rate = rockchip_get_pll_settings(pll, drate);
+
+        /* when no rate setting for the current rate, rely on clk_set_rate */
+        if (!rate)
+                return;
+
+        pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
+        nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK) + 1;
+        no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK) + 1;
+
+        pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
+        nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1;
+
+        pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
+        bwadj = (pllcon >> RK3066_PLLCON2_BWADJ_SHIFT) & RK3066_PLLCON2_BWADJ_MASK;
+
+        pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), bwadj(%d:%d)\n",
+                 __func__, __clk_get_name(hw->clk), drate, rate->nr, nr,
+                rate->no, no, rate->nf, nf, rate->bwadj, bwadj);
+        if (rate->nr != nr || rate->no != no || rate->nf != nf
+                                             || rate->bwadj != bwadj) {
+                struct clk *parent = __clk_get_parent(hw->clk);
+                unsigned long prate;
+
+                if (!parent) {
+                        pr_warn("%s: parent of %s not available\n",
+                                __func__, __clk_get_name(hw->clk));
+                        return;
+                }
+
+                pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
+                         __func__, __clk_get_name(hw->clk));
+                prate = __clk_get_rate(parent);
+                rockchip_rk3066_pll_set_rate(hw, drate, prate);
+        }
+}
+
 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
         .enable = rockchip_rk3066_pll_enable,
@@ -271,6 +321,7 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
         .enable = rockchip_rk3066_pll_enable,
         .disable = rockchip_rk3066_pll_disable,
         .is_enabled = rockchip_rk3066_pll_is_enabled,
+        .init = rockchip_rk3066_pll_init,
 };
 
 /*
@@ -282,7 +333,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
                 void __iomem *base, int con_offset, int grf_lock_offset,
                 int lock_shift, int mode_offset, int mode_shift,
                 struct rockchip_pll_rate_table *rate_table,
-                spinlock_t *lock)
+                u8 clk_pll_flags, spinlock_t *lock)
 {
         const char *pll_parents[3];
         struct clk_init_data init;
@@ -345,8 +396,22 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
         pll->reg_base = base + con_offset;
         pll->lock_offset = grf_lock_offset;
         pll->lock_shift = lock_shift;
+        pll->flags = clk_pll_flags;
         pll->lock = lock;
 
+        /* create the mux on top of the real pll */
+        pll->pll_mux_ops = &clk_mux_ops;
+        pll_mux = &pll->pll_mux;
+        pll_mux->reg = base + mode_offset;
+        pll_mux->shift = mode_shift;
+        pll_mux->mask = PLL_MODE_MASK;
+        pll_mux->flags = 0;
+        pll_mux->lock = lock;
+        pll_mux->hw.init = &init;
+
+        if (pll_type == pll_rk3066)
+                pll_mux->flags |= CLK_MUX_HIWORD_MASK;
+
         pll_clk = clk_register(NULL, &pll->hw);
         if (IS_ERR(pll_clk)) {
                 pr_err("%s: failed to register pll clock %s : %ld\n",
@@ -355,10 +420,6 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
                 goto err_pll;
         }
 
-        /* create the mux on top of the real pll */
-        pll->pll_mux_ops = &clk_mux_ops;
-        pll_mux = &pll->pll_mux;
-
         /* the actual muxing is xin24m, pll-output, xin32k */
         pll_parents[0] = parent_names[0];
         pll_parents[1] = pll_name;
@@ -370,16 +431,6 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
         init.parent_names = pll_parents;
         init.num_parents = ARRAY_SIZE(pll_parents);
 
-        pll_mux->reg = base + mode_offset;
-        pll_mux->shift = mode_shift;
-        pll_mux->mask = PLL_MODE_MASK;
-        pll_mux->flags = 0;
-        pll_mux->lock = lock;
-        pll_mux->hw.init = &init;
-
-        if (pll_type == pll_rk3066)
-                pll_mux->flags |= CLK_MUX_HIWORD_MASK;
-
         mux_clk = clk_register(NULL, &pll_mux->hw);
         if (IS_ERR(mux_clk))
                 goto err_mux;
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index beed49c79126..c54078960847 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -212,13 +212,13 @@ PNAME(mux_sclk_macref_p)	= { "mac_src", "ext_rmii" };
 
 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
         [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
-                     RK2928_MODE_CON, 0, 6, rk3188_pll_rates),
+                     RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
         [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
-                     RK2928_MODE_CON, 4, 5, NULL),
+                     RK2928_MODE_CON, 4, 5, 0, NULL),
         [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
-                     RK2928_MODE_CON, 8, 7, rk3188_pll_rates),
+                     RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
         [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
-                     RK2928_MODE_CON, 12, 8, rk3188_pll_rates),
+                     RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
 };
 
 #define MFLAGS CLK_MUX_HIWORD_MASK
@@ -257,9 +257,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
         GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
                         RK2928_CLKGATE_CON(3), 12, GFLAGS),
 
-        GATE(0, "gpll_ddr", "gpll", 0,
+        GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
                         RK2928_CLKGATE_CON(1), 7, GFLAGS),
-        COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,
+        COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                         RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                         RK2928_CLKGATE_CON(0), 2, GFLAGS),
 
@@ -270,10 +270,10 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
                         RK2928_CLKGATE_CON(0), 6, GFLAGS),
         GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
                         RK2928_CLKGATE_CON(0), 5, GFLAGS),
-        GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,
+        GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
                         RK2928_CLKGATE_CON(0), 4, GFLAGS),
 
-        COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,
+        COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
                         RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
                         RK2928_CLKGATE_CON(3), 0, GFLAGS),
         COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
@@ -304,9 +304,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
          * the 480m are generated inside the usb block from these clocks,
          * but they are also a source for the hsicphy clock.
          */
-        GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
+        GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
                         RK2928_CLKGATE_CON(1), 5, GFLAGS),
-        GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
+        GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
                         RK2928_CLKGATE_CON(1), 6, GFLAGS),
 
         COMPOSITE(0, "mac_src", mux_mac_p, 0,
@@ -320,9 +320,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
         COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
                         RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
                         RK2928_CLKGATE_CON(2), 6, GFLAGS),
-        COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src",
+        COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0,
                         RK2928_CLKSEL_CON(23), 0,
-                        RK2928_CLKGATE_CON(2), 7, 0, GFLAGS),
+                        RK2928_CLKGATE_CON(2), 7, GFLAGS),
         MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,
                         RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),
 
@@ -330,6 +330,15 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
                         RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
                         RK2928_CLKGATE_CON(2), 8, GFLAGS),
 
+        COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
+                        RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
+                        RK2928_CLKGATE_CON(0), 13, GFLAGS),
+        COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
+                        RK2928_CLKSEL_CON(9), 0,
+                        RK2928_CLKGATE_CON(0), 14, GFLAGS),
+        MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
+                        RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
+
         /*
          * Clock-Architecture Diagram 4
          */
@@ -399,8 +408,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
 
         /* aclk_cpu gates */
         GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
-        GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, GFLAGS),
-        GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, GFLAGS),
+        GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
+        GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
 
         /* hclk_cpu gates */
         GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
@@ -410,14 +419,14 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
         /* hclk_ahb2apb is part of a clk branch */
         GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
         GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
-        GATE(HCLK_LCDC1, "hclk_lcdc1", "aclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
+        GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
         GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
         GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
         GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
 
         /* hclk_peri gates */
-        GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 0, GFLAGS),
-        GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, GFLAGS),
+        GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
+        GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
         GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
         GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
         GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
@@ -457,18 +466,18 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
         GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
         GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
         GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
-        GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 4, GFLAGS),
-        GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 5, GFLAGS),
+        GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
+        GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
 
         /* aclk_peri */
         GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
         GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
-        GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 4, GFLAGS),
-        GATE(0, "aclk_cpu_peri", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 2, GFLAGS),
-        GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 3, GFLAGS),
+        GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
+        GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
+        GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
 
         /* pclk_peri gates */
-        GATE(0, "pclk_peri_axi_matrix", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 1, GFLAGS),
+        GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
         GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
         GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
         GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
@@ -511,7 +520,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
                                                             | CLK_DIVIDER_READ_ONLY,
                         RK2928_CLKGATE_CON(4), 9, GFLAGS),
 
-        GATE(CORE_L2C, "core_l2c", "aclk_cpu", 0,
+        GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
                         RK2928_CLKGATE_CON(9), 4, GFLAGS),
 
         COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
@@ -577,14 +586,6 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
                         RK2928_CLKGATE_CON(0), 12, GFLAGS),
         MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
                         RK2928_CLKSEL_CON(4), 8, 2, MFLAGS),
-        COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
-                        RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
-                        RK2928_CLKGATE_CON(0), 13, GFLAGS),
-        COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
-                        RK2928_CLKSEL_CON(9), 0,
-                        RK2928_CLKGATE_CON(0), 14, GFLAGS),
-        MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
-                        RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
 
         GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
         GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
@@ -618,7 +619,7 @@ PNAME(mux_hsicphy_p)		= { "sclk_otgphy0", "sclk_otgphy1",
                                     "gpll", "cpll" };
 
 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
-        COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0,
+        COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
                         RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
 
@@ -633,7 +634,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
                         RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                         RK2928_CLKGATE_CON(4), 9, GFLAGS),
 
-        GATE(CORE_L2C, "core_l2c", "armclk", 0,
+        GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
                         RK2928_CLKGATE_CON(9), 4, GFLAGS),
 
         COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
@@ -663,7 +664,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
                         RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
                         RK2928_CLKGATE_CON(3), 6, GFLAGS),
         DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
-                        RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),
+                        RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
 
         MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
                         RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
@@ -675,14 +676,6 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
                         RK2928_CLKGATE_CON(0), 10, GFLAGS),
         MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
                         RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
-        COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
-                        RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
-                        RK2928_CLKGATE_CON(13), 13, GFLAGS),
-        COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
-                        RK2928_CLKSEL_CON(9), 0,
-                        RK2928_CLKGATE_CON(0), 14, GFLAGS),
-        MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
-                        RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
 
         GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
         GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 23278291da44..ac6be7c0132d 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -16,6 +16,7 @@
 #include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/syscore_ops.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 #include "clk.h"
 
@@ -83,11 +84,13 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
         RK3066_PLL_RATE( 742500000, 8, 495, 2),
         RK3066_PLL_RATE( 696000000, 1, 58, 2),
         RK3066_PLL_RATE( 600000000, 1, 50, 2),
-        RK3066_PLL_RATE( 594000000, 2, 198, 4),
+        RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
         RK3066_PLL_RATE( 552000000, 1, 46, 2),
         RK3066_PLL_RATE( 504000000, 1, 84, 4),
+        RK3066_PLL_RATE( 500000000, 3, 125, 2),
         RK3066_PLL_RATE( 456000000, 1, 76, 4),
         RK3066_PLL_RATE( 408000000, 1, 68, 4),
+        RK3066_PLL_RATE( 400000000, 3, 100, 2),
         RK3066_PLL_RATE( 384000000, 2, 128, 4),
         RK3066_PLL_RATE( 360000000, 1, 60, 4),
         RK3066_PLL_RATE( 312000000, 1, 52, 4),
@@ -173,14 +176,14 @@ PNAME(mux_aclk_cpu_src_p)	= { "cpll_aclk_cpu", "gpll_aclk_cpu" };
 PNAME(mux_pll_src_cpll_gpll_p)          = { "cpll", "gpll" };
 PNAME(mux_pll_src_npll_cpll_gpll_p)     = { "npll", "cpll", "gpll" };
 PNAME(mux_pll_src_cpll_gpll_npll_p)     = { "cpll", "gpll", "npll" };
-PNAME(mux_pll_src_cpll_gpll_usb480m_p)  = { "cpll", "gpll", "usb480m" };
+PNAME(mux_pll_src_cpll_gpll_usb480m_p)  = { "cpll", "gpll", "usbphy480m_src" };
+PNAME(mux_pll_src_cpll_gll_usb_npll_p)  = { "cpll", "gpll", "usbphy480m_src", "npll" };
 
 PNAME(mux_mmc_src_p)    = { "cpll", "gpll", "xin24m", "xin24m" };
 PNAME(mux_i2s_pre_p)    = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
 PNAME(mux_spdif_p)      = { "spdif_pre", "spdif_frac", "xin12m" };
 PNAME(mux_spdif_8ch_p)  = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
-PNAME(mux_uart0_pll_p)  = { "cpll", "gpll", "usbphy_480m_src", "npll" };
 PNAME(mux_uart0_p)      = { "uart0_src", "uart0_frac", "xin24m" };
 PNAME(mux_uart1_p)      = { "uart1_src", "uart1_frac", "xin24m" };
 PNAME(mux_uart2_p)      = { "uart2_src", "uart2_frac", "xin24m" };
@@ -192,22 +195,22 @@ PNAME(mux_hsadcout_p)	= { "hsadc_src", "ext_hsadc" };
 PNAME(mux_edp_24m_p)    = { "ext_edp_24m", "xin24m" };
 PNAME(mux_tspout_p)     = { "cpll", "gpll", "npll", "xin27m" };
 
-PNAME(mux_usbphy480m_p)         = { "sclk_otgphy0", "sclk_otgphy1",
-                                    "sclk_otgphy2" };
+PNAME(mux_usbphy480m_p)         = { "sclk_otgphy1", "sclk_otgphy2",
+                                    "sclk_otgphy0" };
 PNAME(mux_hsicphy480m_p)        = { "cpll", "gpll", "usbphy480m_src" };
 PNAME(mux_hsicphy12m_p)         = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
 
 static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
         [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
-                     RK3288_MODE_CON, 0, 6, rk3288_pll_rates),
+                     RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
         [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
-                     RK3288_MODE_CON, 4, 5, NULL),
+                     RK3288_MODE_CON, 4, 5, 0, NULL),
         [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
-                     RK3288_MODE_CON, 8, 7, rk3288_pll_rates),
+                     RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
         [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
-                     RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
+                     RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
         [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),
-                     RK3288_MODE_CON, 14, 9, rk3288_pll_rates),
+                     RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 };
 
 static struct clk_div_table div_hclk_cpu_t[] = {
@@ -226,67 +229,67 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
          * Clock-Architecture Diagram 1
          */
 
-        GATE(0, "apll_core", "apll", 0,
+        GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(0), 1, GFLAGS),
-        GATE(0, "gpll_core", "gpll", 0,
+        GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(0), 2, GFLAGS),
 
-        COMPOSITE_NOMUX(0, "armcore0", "armclk", 0,
+        COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 0, GFLAGS),
-        COMPOSITE_NOMUX(0, "armcore1", "armclk", 0,
+        COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 1, GFLAGS),
-        COMPOSITE_NOMUX(0, "armcore2", "armclk", 0,
+        COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 2, GFLAGS),
-        COMPOSITE_NOMUX(0, "armcore3", "armclk", 0,
+        COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 3, GFLAGS),
-        COMPOSITE_NOMUX(0, "l2ram", "armclk", 0,
+        COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 4, GFLAGS),
-        COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", 0,
+        COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 5, GFLAGS),
-        COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", 0,
+        COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 6, GFLAGS),
         COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
                         RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 7, GFLAGS),
-        COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", 0,
+        COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 8, GFLAGS),
         GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
                         RK3288_CLKGATE_CON(12), 9, GFLAGS),
-        GATE(0, "cs_dbg", "pclk_dbg_pre", 0,
+        GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(12), 10, GFLAGS),
         GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
                         RK3288_CLKGATE_CON(12), 11, GFLAGS),
 
-        GATE(0, "dpll_ddr", "dpll", 0,
+        GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(0), 8, GFLAGS),
         GATE(0, "gpll_ddr", "gpll", 0,
                         RK3288_CLKGATE_CON(0), 9, GFLAGS),
-        COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, 0,
+        COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
                                         DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 
-        GATE(0, "gpll_aclk_cpu", "gpll", 0,
+        GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(0), 10, GFLAGS),
-        GATE(0, "cpll_aclk_cpu", "cpll", 0,
+        GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(0), 11, GFLAGS),
-        COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
+        COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
-        DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
+        DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
-        GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
+        GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(0), 3, GFLAGS),
-        COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0,
+        COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
                         RK3288_CLKGATE_CON(0), 5, GFLAGS),
-        COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0,
+        COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
                         RK3288_CLKGATE_CON(0), 4, GFLAGS),
         GATE(0, "c2c_host", "aclk_cpu_src", 0,
@@ -294,7 +297,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
                         RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
                         RK3288_CLKGATE_CON(5), 4, GFLAGS),
-        GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0,
+        GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(0), 7, GFLAGS),
 
         COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
@@ -305,7 +308,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                         RK3288_CLKGATE_CON(4), 2, GFLAGS),
         MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
-        COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
+        COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
                         RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
                         RK3288_CLKGATE_CON(4), 0, GFLAGS),
         GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
@@ -325,7 +328,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
                         RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
                         RK3288_CLKGATE_CON(4), 7, GFLAGS),
-        COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", 0,
+        COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_pre", 0,
                         RK3288_CLKSEL_CON(41), 0,
                         RK3288_CLKGATE_CON(4), 8, GFLAGS),
         COMPOSITE_NODIV(SCLK_SPDIF8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
@@ -373,12 +376,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
                 RK3288_CLKGATE_CON(9), 1, GFLAGS),
 
-        COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
+        COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
         DIV(0, "hclk_vio", "aclk_vio0", 0,
                         RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
-        COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, 0,
+        COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
 
@@ -436,24 +439,24 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
         DIV(0, "pclk_pd_alive", "gpll", 0,
                         RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
-        COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", 0,
+        COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
                         RK3288_CLKGATE_CON(5), 8, GFLAGS),
 
-        COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
+        COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
                         RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
                         RK3288_CLKGATE_CON(5), 7, GFLAGS),
 
-        COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0,
+        COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
                         RK3288_CLKGATE_CON(2), 0, GFLAGS),
         COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
                         RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                         RK3288_CLKGATE_CON(2), 3, GFLAGS),
-        COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
+        COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                         RK3288_CLKGATE_CON(2), 2, GFLAGS),
-        GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
+        GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(2), 1, GFLAGS),
 
         /*
@@ -483,6 +486,18 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                         RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
                         RK3288_CLKGATE_CON(13), 3, GFLAGS),
 
+        MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
+        MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
+
+        MMC(SCLK_SDIO0_DRV,    "sdio0_drv",    "sclk_sdio0", RK3288_SDIO0_CON0, 1),
+        MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
+
+        MMC(SCLK_SDIO1_DRV,    "sdio1_drv",    "sclk_sdio1", RK3288_SDIO1_CON0, 1),
+        MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
+
+        MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3288_EMMC_CON0,  1),
+        MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3288_EMMC_CON1,  0),
+
         COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
                         RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
                         RK3288_CLKGATE_CON(4), 11, GFLAGS),
@@ -490,13 +505,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                         RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
                         RK3288_CLKGATE_CON(4), 10, GFLAGS),
 
-        GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
+        GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(13), 4, GFLAGS),
-        GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
+        GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(13), 5, GFLAGS),
-        GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", 0,
+        GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(13), 6, GFLAGS),
-        GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 0,
+        GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(13), 7, GFLAGS),
 
         COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
@@ -517,7 +532,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                         RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
                         RK3288_CLKGATE_CON(5), 6, GFLAGS),
 
-        COMPOSITE(0, "uart0_src", mux_uart0_pll_p, 0,
+        COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
                         RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
                         RK3288_CLKGATE_CON(1), 8, GFLAGS),
         COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", 0,
@@ -585,7 +600,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
         COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
                         RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
-                        RK3288_CLKGATE_CON(5), 15, GFLAGS),
+                        RK3288_CLKGATE_CON(5), 14, GFLAGS),
         COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
                         RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
                         RK3288_CLKGATE_CON(3), 6, GFLAGS),
@@ -601,19 +616,19 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
          */
 
         /* aclk_cpu gates */
-        GATE(0, "sclk_intmem0", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 5, GFLAGS),
-        GATE(0, "sclk_intmem1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 6, GFLAGS),
-        GATE(0, "sclk_intmem2", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 7, GFLAGS),
+        GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
+        GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
+        GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
         GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
-        GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 13, GFLAGS),
-        GATE(0, "aclk_intmem", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 4, GFLAGS),
+        GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
+        GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
         GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
         GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
 
         /* hclk_cpu gates */
         GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
         GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
-        GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 9, GFLAGS),
+        GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
         GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
         GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
 
@@ -622,42 +637,42 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
-        GATE(0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
-        GATE(0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
-        GATE(0, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
-        GATE(0, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
+        GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
+        GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
+        GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
+        GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
         GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
         GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
         GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
         GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
-        GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
+        GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
 
         /* ddrctrl [DDR Controller PHY clock] gates */
-        GATE(0, "nclk_ddrupctl0", "ddrphy", 0, RK3288_CLKGATE_CON(11), 4, GFLAGS),
-        GATE(0, "nclk_ddrupctl1", "ddrphy", 0, RK3288_CLKGATE_CON(11), 5, GFLAGS),
+        GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
+        GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
 
         /* ddrphy gates */
-        GATE(0, "sclk_ddrphy0", "ddrphy", 0, RK3288_CLKGATE_CON(4), 12, GFLAGS),
-        GATE(0, "sclk_ddrphy1", "ddrphy", 0, RK3288_CLKGATE_CON(4), 13, GFLAGS),
+        GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
+        GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
 
         /* aclk_peri gates */
-        GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 2, GFLAGS),
+        GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
         GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
-        GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
-        GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 12, GFLAGS),
+        GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 11, GFLAGS),
+        GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
         GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
         GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
 
         /* hclk_peri gates */
-        GATE(0, "hclk_peri_matrix", "hclk_peri", 0, RK3288_CLKGATE_CON(6), 0, GFLAGS),
-        GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 4, GFLAGS),
+        GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
+        GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
         GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
-        GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 7, GFLAGS),
+        GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
         GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
-        GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 9, GFLAGS),
-        GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 10, GFLAGS),
-        GATE(0, "hclk_emem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 12, GFLAGS),
-        GATE(0, "hclk_mem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 13, GFLAGS),
+        GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
+        GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
+        GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
+        GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
         GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
         GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
         GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
@@ -669,7 +684,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
 
         /* pclk_peri gates */
-        GATE(0, "pclk_peri_matrix", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 1, GFLAGS),
+        GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
         GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
         GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
         GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
@@ -705,48 +720,48 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
         GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
         GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
-        GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 11, GFLAGS),
-        GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
+        GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
+        GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 12, GFLAGS),
 
         /* pclk_pd_pmu gates */
-        GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 0, GFLAGS),
-        GATE(0, "pclk_intmem1", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 1, GFLAGS),
-        GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
-        GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 3, GFLAGS),
+        GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
+        GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
+        GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 2, GFLAGS),
+        GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
 
         /* hclk_vio gates */
         GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
         GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
         GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
-        GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
-        GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
+        GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
+        GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 10, GFLAGS),
         GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
         GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
         GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
-        GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
+        GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
         GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
         GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
         GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
         GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
-        GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
+        GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
         GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
-        GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
+        GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
 
         /* aclk_vio0 gates */
         GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
         GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
-        GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
+        GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 11, GFLAGS),
         GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
 
         /* aclk_vio1 gates */
         GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
         GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
-        GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
+        GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 12, GFLAGS),
 
         /* aclk_rga_pre gates */
         GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
-        GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
+        GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 13, GFLAGS),
 
         /*
          * Other ungrouped clocks.
@@ -762,6 +777,64 @@ static const char *rk3288_critical_clocks[] __initconst = {
         "hclk_peri",
 };
 
+#ifdef CONFIG_PM_SLEEP
+static void __iomem *rk3288_cru_base;
+
+/* Some CRU registers will be reset in maskrom when the system
+ * wakes up from fastboot.
+ * So save them before suspend, restore them after resume.
+ */
+static const int rk3288_saved_cru_reg_ids[] = {
+        RK3288_MODE_CON,
+        RK3288_CLKSEL_CON(0),
+        RK3288_CLKSEL_CON(1),
+        RK3288_CLKSEL_CON(10),
+        RK3288_CLKSEL_CON(33),
+        RK3288_CLKSEL_CON(37),
+};
+
+static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
+
+static int rk3288_clk_suspend(void)
+{
+        int i, reg_id;
+
+        for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
+                reg_id = rk3288_saved_cru_reg_ids[i];
+
+                rk3288_saved_cru_regs[i] =
+                                readl_relaxed(rk3288_cru_base + reg_id);
+        }
+        return 0;
+}
+
+static void rk3288_clk_resume(void)
+{
+        int i, reg_id;
+
+        for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
+                reg_id = rk3288_saved_cru_reg_ids[i];
+
+                writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
+                               rk3288_cru_base + reg_id);
+        }
+}
+
+static struct syscore_ops rk3288_clk_syscore_ops = {
+        .suspend = rk3288_clk_suspend,
+        .resume = rk3288_clk_resume,
+};
+
+static void rk3288_clk_sleep_init(void __iomem *reg_base)
+{
+        rk3288_cru_base = reg_base;
+        register_syscore_ops(&rk3288_clk_syscore_ops);
+}
+
+#else /* CONFIG_PM_SLEEP */
+static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
+#endif
+
 static void __init rk3288_clk_init(struct device_node *np)
 {
         void __iomem *reg_base;
@@ -810,5 +883,6 @@ static void __init rk3288_clk_init(struct device_node *np)
                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 
         rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
+        rk3288_clk_sleep_init(reg_base);
 }
 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 880a266f0143..20e05bbb3a67 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -197,7 +197,8 @@ void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
                                 list->parent_names, list->num_parents,
                                 reg_base, list->con_offset, grf_lock_offset,
                                 list->lock_shift, list->mode_offset,
-                                list->mode_shift, list->rate_table, &clk_lock);
+                                list->mode_shift, list->rate_table,
+                                list->pll_flags, &clk_lock);
                 if (IS_ERR(clk)) {
                         pr_err("%s: failed to register clock %s\n", __func__,
                                 list->name);
@@ -244,9 +245,6 @@ void __init rockchip_clk_register_branches(
                                         list->div_flags, &clk_lock);
                         break;
                 case branch_fraction_divider:
-                        /* keep all gates untouched for now */
-                        flags |= CLK_IGNORE_UNUSED;
-
                         clk = rockchip_clk_register_frac_branch(list->name,
                                 list->parent_names, list->num_parents,
                                 reg_base, list->muxdiv_offset, list->div_flags,
@@ -256,18 +254,12 @@ void __init rockchip_clk_register_branches(
                 case branch_gate:
                         flags |= CLK_SET_RATE_PARENT;
 
-                        /* keep all gates untouched for now */
-                        flags |= CLK_IGNORE_UNUSED;
-
                         clk = clk_register_gate(NULL, list->name,
                                 list->parent_names[0], flags,
                                 reg_base + list->gate_offset,
                                 list->gate_shift, list->gate_flags, &clk_lock);
                         break;
                 case branch_composite:
-                        /* keep all gates untouched for now */
-                        flags |= CLK_IGNORE_UNUSED;
-
                         clk = rockchip_clk_register_branch(list->name,
                                 list->parent_names, list->num_parents,
                                 reg_base, list->muxdiv_offset, list->mux_shift,
@@ -277,6 +269,14 @@ void __init rockchip_clk_register_branches(
                                 list->gate_offset, list->gate_shift,
                                 list->gate_flags, flags, &clk_lock);
                         break;
+                case branch_mmc:
+                        clk = rockchip_clk_register_mmc(
+                                list->name,
+                                list->parent_names, list->num_parents,
+                                reg_base + list->muxdiv_offset,
+                                list->div_shift
+                        );
+                        break;
                 }
 
                 /* none of the cases above matched */
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index ca009ab0a33a..58d2e3bdf22f 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -48,6 +48,14 @@
 #define RK3288_GLB_SRST_SND             0x1b4
 #define RK3288_SOFTRST_CON(x)           (x * 0x4 + 0x1b8)
 #define RK3288_MISC_CON                 0x1e8
+#define RK3288_SDMMC_CON0               0x200
+#define RK3288_SDMMC_CON1               0x204
+#define RK3288_SDIO0_CON0               0x208
+#define RK3288_SDIO0_CON1               0x20c
+#define RK3288_SDIO1_CON0               0x210
+#define RK3288_SDIO1_CON1               0x214
+#define RK3288_EMMC_CON0                0x218
+#define RK3288_EMMC_CON1                0x21c
 
 enum rockchip_pll_type {
         pll_rk3066,
@@ -62,6 +70,15 @@ enum rockchip_pll_type {
         .bwadj = (_nf >> 1),                    \
 }
 
+#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw)        \
+{                                                               \
+        .rate   = _rate##U,                                     \
+        .nr = _nr,                                              \
+        .nf = _nf,                                              \
+        .no = _no,                                              \
+        .bwadj = _bw,                                           \
+}
+
 struct rockchip_pll_rate_table {
         unsigned long rate;
         unsigned int nr;
@@ -81,7 +98,12 @@ struct rockchip_pll_rate_table {
  * @mode_shift: offset inside the mode-register for the mode of this pll.
  * @lock_shift: offset inside the lock register for the lock status.
  * @type: Type of PLL to be registered.
+ * @pll_flags: hardware-specific flags
  * @rate_table: Table of usable pll rates
+ *
+ * Flags:
+ * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
+ *      rate_table parameters and ajust them if necessary.
  */
 struct rockchip_pll_clock {
         unsigned int            id;
@@ -94,11 +116,14 @@ struct rockchip_pll_clock {
         int                     mode_shift;
         int                     lock_shift;
         enum rockchip_pll_type  type;
+        u8                      pll_flags;
         struct rockchip_pll_rate_table *rate_table;
 };
 
+#define ROCKCHIP_PLL_SYNC_RATE          BIT(0)
+
 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,   \
-                _lshift, _rtable)                                       \
+                _lshift, _pflags, _rtable)                              \
         {                                                               \
                 .id             = _id,                                  \
                 .type           = _type,                                \
@@ -110,6 +135,7 @@ struct rockchip_pll_clock {
                 .mode_offset    = _mode,                                \
                 .mode_shift     = _mshift,                              \
                 .lock_shift     = _lshift,                              \
+                .pll_flags      = _pflags,                              \
                 .rate_table     = _rtable,                              \
         }
 
@@ -118,7 +144,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
                 void __iomem *base, int con_offset, int grf_lock_offset,
                 int lock_shift, int reg_mode, int mode_shift,
                 struct rockchip_pll_rate_table *rate_table,
-                spinlock_t *lock);
+                u8 clk_pll_flags, spinlock_t *lock);
 
 struct rockchip_cpuclk_clksel {
         int reg;
@@ -152,6 +178,10 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
                         const struct rockchip_cpuclk_rate_table *rates,
                         int nrates, void __iomem *reg_base, spinlock_t *lock);
 
+struct clk *rockchip_clk_register_mmc(const char *name,
+                                const char **parent_names, u8 num_parents,
+                                void __iomem *reg, int shift);
+
 #define PNAME(x) static const char *x[] __initconst
 
 enum rockchip_clk_branch_type {
@@ -160,6 +190,7 @@ enum rockchip_clk_branch_type {
         branch_divider,
         branch_fraction_divider,
         branch_gate,
+        branch_mmc,
 };
 
 struct rockchip_clk_branch {
@@ -352,6 +383,16 @@ struct rockchip_clk_branch {
                 .gate_flags     = gf,                           \
         }
 
+#define MMC(_id, cname, pname, offset, shift)                   \
+        {                                                       \
+                .id             = _id,                          \
+                .branch_type    = branch_mmc,                   \
+                .name           = cname,                        \
+                .parent_names   = (const char *[]){ pname },    \
+                .num_parents    = 1,                            \
+                .muxdiv_offset  = offset,                       \
+                .div_shift      = shift,                        \
+        }
 
 void rockchip_clk_init(struct device_node *np, void __iomem *base,
                        unsigned long nr_clks);
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc602e8a..006c6f294310 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_COMMON_CLK)        += clk.o clk-pll.o
 obj-$(CONFIG_SOC_EXYNOS3250)    += clk-exynos3250.o
 obj-$(CONFIG_ARCH_EXYNOS4)      += clk-exynos4.o
+obj-$(CONFIG_SOC_EXYNOS4415)    += clk-exynos4415.o
 obj-$(CONFIG_SOC_EXYNOS5250)    += clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5260)    += clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5410)    += clk-exynos5410.o
@@ -12,6 +13,7 @@ obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)    += clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)       += clk-exynos-audss.o
 obj-$(CONFIG_ARCH_EXYNOS)       += clk-exynos-clkout.o
+obj-$(CONFIG_ARCH_EXYNOS7)      += clk-exynos7.o
 obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
 obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
 obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index acce708ace18..f2c2ccce49bb 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -29,6 +29,13 @@ static DEFINE_SPINLOCK(lock);
 static struct clk **clk_table;
 static void __iomem *reg_base;
 static struct clk_onecell_data clk_data;
+/*
+ * On Exynos5420 this will be a clock which has to be enabled before any
+ * access to audss registers. Typically a child of EPLL.
+ *
+ * On other platforms this will be -ENODEV.
+ */
+static struct clk *epll;
 
 #define ASS_CLK_SRC 0x0
 #define ASS_CLK_DIV 0x4
@@ -98,6 +105,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
                 dev_err(&pdev->dev, "failed to map audss registers\n");
                 return PTR_ERR(reg_base);
         }
+        /* EPLL don't have to be enabled for boards other than Exynos5420 */
+        epll = ERR_PTR(-ENODEV);
 
         clk_table = devm_kzalloc(&pdev->dev,
                                 sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
@@ -115,8 +124,20 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
         pll_in = devm_clk_get(&pdev->dev, "pll_in");
         if (!IS_ERR(pll_ref))
                 mout_audss_p[0] = __clk_get_name(pll_ref);
-        if (!IS_ERR(pll_in))
+        if (!IS_ERR(pll_in)) {
                 mout_audss_p[1] = __clk_get_name(pll_in);
+
+                if (variant == TYPE_EXYNOS5420) {
+                        epll = pll_in;
+
+                        ret = clk_prepare_enable(epll);
+                        if (ret) {
+                                dev_err(&pdev->dev,
+                                                "failed to prepare the epll clock\n");
+                                return ret;
+                        }
+                }
+        }
         clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
                                 mout_audss_p, ARRAY_SIZE(mout_audss_p),
                                 CLK_SET_RATE_NO_REPARENT,
@@ -203,6 +224,9 @@ unregister:
                         clk_unregister(clk_table[i]);
         }
 
+        if (!IS_ERR(epll))
+                clk_disable_unprepare(epll);
+
         return ret;
 }
 
@@ -210,6 +234,10 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
 {
         int i;
 
+#ifdef CONFIG_PM_SLEEP
+        unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
+#endif
+
         of_clk_del_provider(pdev->dev.of_node);
 
         for (i = 0; i < clk_data.clk_num; i++) {
@@ -217,6 +245,9 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
                         clk_unregister(clk_table[i]);
         }
 
+        if (!IS_ERR(epll))
+                clk_disable_unprepare(epll);
+
         return 0;
 }
 
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 940f02837b82..88e8c6bbd77f 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -505,7 +505,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
 /* fixed rate clocks generated inside the soc */
 static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
         FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
-        FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+        FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
         FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
 };
 
diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c
new file mode 100644
index 000000000000..2123fc251e0f
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4415.c
@@ -0,0 +1,1144 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos4415 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clock/exynos4415.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#define SRC_LEFTBUS             0x4200
+#define DIV_LEFTBUS             0x4500
+#define GATE_IP_LEFTBUS         0x4800
+#define GATE_IP_IMAGE           0x4930
+#define SRC_RIGHTBUS            0x8200
+#define DIV_RIGHTBUS            0x8500
+#define GATE_IP_RIGHTBUS        0x8800
+#define GATE_IP_PERIR           0x8960
+#define EPLL_LOCK               0xc010
+#define G3D_PLL_LOCK            0xc020
+#define DISP_PLL_LOCK           0xc030
+#define ISP_PLL_LOCK            0xc040
+#define EPLL_CON0               0xc110
+#define EPLL_CON1               0xc114
+#define EPLL_CON2               0xc118
+#define G3D_PLL_CON0            0xc120
+#define G3D_PLL_CON1            0xc124
+#define G3D_PLL_CON2            0xc128
+#define ISP_PLL_CON0            0xc130
+#define ISP_PLL_CON1            0xc134
+#define ISP_PLL_CON2            0xc138
+#define DISP_PLL_CON0           0xc140
+#define DISP_PLL_CON1           0xc144
+#define DISP_PLL_CON2           0xc148
+#define SRC_TOP0                0xc210
+#define SRC_TOP1                0xc214
+#define SRC_CAM                 0xc220
+#define SRC_TV                  0xc224
+#define SRC_MFC                 0xc228
+#define SRC_G3D                 0xc22c
+#define SRC_LCD                 0xc234
+#define SRC_ISP                 0xc238
+#define SRC_MAUDIO              0xc23c
+#define SRC_FSYS                0xc240
+#define SRC_PERIL0              0xc250
+#define SRC_PERIL1              0xc254
+#define SRC_CAM1                0xc258
+#define SRC_TOP_ISP0            0xc25c
+#define SRC_TOP_ISP1            0xc260
+#define SRC_MASK_TOP            0xc310
+#define SRC_MASK_CAM            0xc320
+#define SRC_MASK_TV             0xc324
+#define SRC_MASK_LCD            0xc334
+#define SRC_MASK_ISP            0xc338
+#define SRC_MASK_MAUDIO         0xc33c
+#define SRC_MASK_FSYS           0xc340
+#define SRC_MASK_PERIL0         0xc350
+#define SRC_MASK_PERIL1         0xc354
+#define DIV_TOP                 0xc510
+#define DIV_CAM                 0xc520
+#define DIV_TV                  0xc524
+#define DIV_MFC                 0xc528
+#define DIV_G3D                 0xc52c
+#define DIV_LCD                 0xc534
+#define DIV_ISP                 0xc538
+#define DIV_MAUDIO              0xc53c
+#define DIV_FSYS0               0xc540
+#define DIV_FSYS1               0xc544
+#define DIV_FSYS2               0xc548
+#define DIV_PERIL0              0xc550
+#define DIV_PERIL1              0xc554
+#define DIV_PERIL2              0xc558
+#define DIV_PERIL3              0xc55c
+#define DIV_PERIL4              0xc560
+#define DIV_PERIL5              0xc564
+#define DIV_CAM1                0xc568
+#define DIV_TOP_ISP1            0xc56c
+#define DIV_TOP_ISP0            0xc570
+#define CLKDIV2_RATIO           0xc580
+#define GATE_SCLK_CAM           0xc820
+#define GATE_SCLK_TV            0xc824
+#define GATE_SCLK_MFC           0xc828
+#define GATE_SCLK_G3D           0xc82c
+#define GATE_SCLK_LCD           0xc834
+#define GATE_SCLK_MAUDIO        0xc83c
+#define GATE_SCLK_FSYS          0xc840
+#define GATE_SCLK_PERIL         0xc850
+#define GATE_IP_CAM             0xc920
+#define GATE_IP_TV              0xc924
+#define GATE_IP_MFC             0xc928
+#define GATE_IP_G3D             0xc92c
+#define GATE_IP_LCD             0xc934
+#define GATE_IP_FSYS            0xc940
+#define GATE_IP_PERIL           0xc950
+#define GATE_BLOCK              0xc970
+#define APLL_LOCK               0x14000
+#define APLL_CON0               0x14100
+#define SRC_CPU                 0x14200
+#define DIV_CPU0                0x14500
+#define DIV_CPU1                0x14504
+
+enum exynos4415_plls {
+        apll, epll, g3d_pll, isp_pll, disp_pll,
+        nr_plls,
+};
+
+static struct samsung_clk_provider *exynos4415_ctx;
+
+/*
+ * Support for CMU save/restore across system suspends
+ */
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos4415_clk_regs;
+
+static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
+        SRC_LEFTBUS,
+        DIV_LEFTBUS,
+        GATE_IP_LEFTBUS,
+        GATE_IP_IMAGE,
+        SRC_RIGHTBUS,
+        DIV_RIGHTBUS,
+        GATE_IP_RIGHTBUS,
+        GATE_IP_PERIR,
+        EPLL_LOCK,
+        G3D_PLL_LOCK,
+        DISP_PLL_LOCK,
+        ISP_PLL_LOCK,
+        EPLL_CON0,
+        EPLL_CON1,
+        EPLL_CON2,
+        G3D_PLL_CON0,
+        G3D_PLL_CON1,
+        G3D_PLL_CON2,
+        ISP_PLL_CON0,
+        ISP_PLL_CON1,
+        ISP_PLL_CON2,
+        DISP_PLL_CON0,
+        DISP_PLL_CON1,
+        DISP_PLL_CON2,
+        SRC_TOP0,
+        SRC_TOP1,
+        SRC_CAM,
+        SRC_TV,
+        SRC_MFC,
+        SRC_G3D,
+        SRC_LCD,
+        SRC_ISP,
+        SRC_MAUDIO,
+        SRC_FSYS,
+        SRC_PERIL0,
+        SRC_PERIL1,
+        SRC_CAM1,
+        SRC_TOP_ISP0,
+        SRC_TOP_ISP1,
+        SRC_MASK_TOP,
+        SRC_MASK_CAM,
+        SRC_MASK_TV,
+        SRC_MASK_LCD,
+        SRC_MASK_ISP,
+        SRC_MASK_MAUDIO,
+        SRC_MASK_FSYS,
+        SRC_MASK_PERIL0,
+        SRC_MASK_PERIL1,
+        DIV_TOP,
+        DIV_CAM,
+        DIV_TV,
+        DIV_MFC,
+        DIV_G3D,
+        DIV_LCD,
+        DIV_ISP,
+        DIV_MAUDIO,
+        DIV_FSYS0,
+        DIV_FSYS1,
+        DIV_FSYS2,
+        DIV_PERIL0,
+        DIV_PERIL1,
+        DIV_PERIL2,
+        DIV_PERIL3,
+        DIV_PERIL4,
+        DIV_PERIL5,
+        DIV_CAM1,
+        DIV_TOP_ISP1,
+        DIV_TOP_ISP0,
+        CLKDIV2_RATIO,
+        GATE_SCLK_CAM,
+        GATE_SCLK_TV,
+        GATE_SCLK_MFC,
+        GATE_SCLK_G3D,
+        GATE_SCLK_LCD,
+        GATE_SCLK_MAUDIO,
+        GATE_SCLK_FSYS,
+        GATE_SCLK_PERIL,
+        GATE_IP_CAM,
+        GATE_IP_TV,
+        GATE_IP_MFC,
+        GATE_IP_G3D,
+        GATE_IP_LCD,
+        GATE_IP_FSYS,
+        GATE_IP_PERIL,
+        GATE_BLOCK,
+        APLL_LOCK,
+        APLL_CON0,
+        SRC_CPU,
+        DIV_CPU0,
+        DIV_CPU1,
+};
+
+static int exynos4415_clk_suspend(void)
+{
+        samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs,
+                                ARRAY_SIZE(exynos4415_cmu_clk_regs));
+
+        return 0;
+}
+
+static void exynos4415_clk_resume(void)
+{
+        samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs,
+                                ARRAY_SIZE(exynos4415_cmu_clk_regs));
+}
+
+static struct syscore_ops exynos4415_clk_syscore_ops = {
+        .suspend = exynos4415_clk_suspend,
+        .resume = exynos4415_clk_resume,
+};
+
+static void exynos4415_clk_sleep_init(void)
+{
+        exynos4415_clk_regs =
+                samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs,
+                                        ARRAY_SIZE(exynos4415_cmu_clk_regs));
+        if (!exynos4415_clk_regs) {
+                pr_warn("%s: Failed to allocate sleep save data\n", __func__);
+                return;
+        }
+
+        register_syscore_ops(&exynos4415_clk_syscore_ops);
+}
+#else
+static inline void exynos4415_clk_sleep_init(void) { }
+#endif
+
+/* list of all parent clock list */
+PNAME(mout_g3d_pllsrc_p)        = { "fin_pll", };
+
+PNAME(mout_apll_p)              = { "fin_pll", "fout_apll", };
+PNAME(mout_g3d_pll_p)           = { "fin_pll", "fout_g3d_pll", };
+PNAME(mout_isp_pll_p)           = { "fin_pll", "fout_isp_pll", };
+PNAME(mout_disp_pll_p)          = { "fin_pll", "fout_disp_pll", };
+
+PNAME(mout_mpll_user_p)         = { "fin_pll", "div_mpll_pre", };
+PNAME(mout_epll_p)              = { "fin_pll", "fout_epll", };
+PNAME(mout_core_p)              = { "mout_apll", "mout_mpll_user_c", };
+PNAME(mout_hpm_p)               = { "mout_apll", "mout_mpll_user_c", };
+
+PNAME(mout_ebi_p)               = { "div_aclk_200", "div_aclk_160", };
+PNAME(mout_ebi_1_p)             = { "mout_ebi", "mout_g3d_pll", };
+
+PNAME(mout_gdl_p)               = { "mout_mpll_user_l", };
+PNAME(mout_gdr_p)               = { "mout_mpll_user_r", };
+
+PNAME(mout_aclk_266_p)          = { "mout_mpll_user_t", "mout_g3d_pll", };
+
+PNAME(group_epll_g3dpll_p)      = { "mout_epll", "mout_g3d_pll" };
+PNAME(group_sclk_p)             = { "xxti", "xusbxti",
+                                    "none", "mout_isp_pll",
+                                    "none", "none", "div_mpll_pre",
+                                    "mout_epll", "mout_g3d_pll", };
+PNAME(group_spdif_p)            = { "mout_audio0", "mout_audio1",
+                                    "mout_audio2", "spdif_extclk", };
+PNAME(group_sclk_audio2_p)      = { "audiocdclk2", "none",
+                                    "none", "mout_isp_pll",
+                                    "mout_disp_pll", "xusbxti",
+                                    "div_mpll_pre", "mout_epll",
+                                    "mout_g3d_pll", };
+PNAME(group_sclk_audio1_p)      = { "audiocdclk1", "none",
+                                    "none", "mout_isp_pll",
+                                    "mout_disp_pll", "xusbxti",
+                                    "div_mpll_pre", "mout_epll",
+                                    "mout_g3d_pll", };
+PNAME(group_sclk_audio0_p)      = { "audiocdclk0", "none",
+                                    "none", "mout_isp_pll",
+                                    "mout_disp_pll", "xusbxti",
+                                    "div_mpll_pre", "mout_epll",
+                                    "mout_g3d_pll", };
+PNAME(group_fimc_lclk_p)        = { "xxti", "xusbxti",
+                                    "none", "mout_isp_pll",
+                                    "none", "mout_disp_pll",
+                                    "mout_mpll_user_t", "mout_epll",
+                                    "mout_g3d_pll", };
+PNAME(group_sclk_fimd0_p)       = { "xxti", "xusbxti",
+                                    "m_bitclkhsdiv4_4l", "mout_isp_pll",
+                                    "mout_disp_pll", "sclk_hdmiphy",
+                                    "div_mpll_pre", "mout_epll",
+                                    "mout_g3d_pll", };
+PNAME(mout_hdmi_p)              = { "sclk_pixel", "sclk_hdmiphy" };
+PNAME(mout_mfc_p)               = { "mout_mfc_0", "mout_mfc_1" };
+PNAME(mout_g3d_p)               = { "mout_g3d_0", "mout_g3d_1" };
+PNAME(mout_jpeg_p)              = { "mout_jpeg_0", "mout_jpeg_1" };
+PNAME(mout_jpeg1_p)             = { "mout_epll", "mout_g3d_pll" };
+PNAME(group_aclk_isp0_300_p)    = { "mout_isp_pll", "div_mpll_pre" };
+PNAME(group_aclk_isp0_400_user_p) = { "fin_pll", "div_aclk_400_mcuisp" };
+PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" };
+PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" };
+PNAME(group_mout_mpll_user_t_p) = { "mout_mpll_user_t" };
+
+static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initdata = {
+        /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
+        FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
+};
+
+static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = {
+        FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+};
+
+static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = {
+        /*
+         * NOTE: Following table is sorted by register address in ascending
+         * order and then bitfield shift in descending order, as it is done
+         * in the User's Manual. When adding new entries, please make sure
+         * that the order is preserved, to avoid merge conflicts and make
+         * further work with defined data easier.
+         */
+
+        /* SRC_LEFTBUS */
+        MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
+                SRC_LEFTBUS, 4, 1),
+        MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
+
+        /* SRC_RIGHTBUS */
+        MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
+                SRC_RIGHTBUS, 4, 1),
+        MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
+
+        /* SRC_TOP0 */
+        MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
+        MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_mout_mpll_user_t_p,
+                SRC_TOP0, 24, 1),
+        MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_mout_mpll_user_t_p,
+                SRC_TOP0, 20, 1),
+        MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_mout_mpll_user_t_p,
+                SRC_TOP0, 16, 1),
+        MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p,
+                SRC_TOP0, 12, 1),
+        MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
+                SRC_TOP0, 8, 1),
+        MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_TOP0, 4, 1),
+        MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
+
+        /* SRC_TOP1 */
+        MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p,
+                SRC_TOP1, 28, 1),
+        MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
+                SRC_TOP1, 16, 1),
+        MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p,
+                SRC_TOP1, 12, 1),
+        MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp",
+                group_mout_mpll_user_t_p, SRC_TOP1, 8, 1),
+        MUX(CLK_MOUT_G3D_PLLSRC, "mout_g3d_pllsrc", mout_g3d_pllsrc_p,
+                SRC_TOP1, 0, 1),
+
+        /* SRC_CAM */
+        MUX(CLK_MOUT_CSIS1, "mout_csis1", group_fimc_lclk_p, SRC_CAM, 28, 4),
+        MUX(CLK_MOUT_CSIS0, "mout_csis0", group_fimc_lclk_p, SRC_CAM, 24, 4),
+        MUX(CLK_MOUT_CAM1, "mout_cam1", group_fimc_lclk_p, SRC_CAM, 20, 4),
+        MUX(CLK_MOUT_FIMC3_LCLK, "mout_fimc3_lclk", group_fimc_lclk_p, SRC_CAM,
+                12, 4),
+        MUX(CLK_MOUT_FIMC2_LCLK, "mout_fimc2_lclk", group_fimc_lclk_p, SRC_CAM,
+                8, 4),
+        MUX(CLK_MOUT_FIMC1_LCLK, "mout_fimc1_lclk", group_fimc_lclk_p, SRC_CAM,
+                4, 4),
+        MUX(CLK_MOUT_FIMC0_LCLK, "mout_fimc0_lclk", group_fimc_lclk_p, SRC_CAM,
+                0, 4),
+
+        /* SRC_TV */
+        MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
+
+        /* SRC_MFC */
+        MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
+        MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_g3dpll_p, SRC_MFC, 4, 1),
+        MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_mout_mpll_user_t_p, SRC_MFC, 0,
+                1),
+
+        /* SRC_G3D */
+        MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
+        MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_g3dpll_p, SRC_G3D, 4, 1),
+        MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_mout_mpll_user_t_p, SRC_G3D, 0,
+                1),
+
+        /* SRC_LCD */
+        MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_fimc_lclk_p, SRC_LCD, 12, 4),
+        MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
+
+        /* SRC_ISP */
+        MUX(CLK_MOUT_TSADC_ISP, "mout_tsadc_isp", group_fimc_lclk_p, SRC_ISP,
+                16, 4),
+        MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_fimc_lclk_p, SRC_ISP,
+                12, 4),
+        MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_fimc_lclk_p, SRC_ISP,
+                8, 4),
+        MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_fimc_lclk_p, SRC_ISP,
+                4, 4),
+        MUX(CLK_MOUT_PWM_ISP, "mout_pwm_isp", group_fimc_lclk_p, SRC_ISP,
+                0, 4),
+
+        /* SRC_MAUDIO */
+        MUX(CLK_MOUT_AUDIO0, "mout_audio0", group_sclk_audio0_p, SRC_MAUDIO,
+                0, 4),
+
+        /* SRC_FSYS */
+        MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+        MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
+        MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
+        MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
+
+        /* SRC_PERIL0 */
+        MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
+        MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
+        MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
+        MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
+
+        /* SRC_PERIL1 */
+        MUX(CLK_MOUT_SPI2, "mout_spi2", group_sclk_p, SRC_PERIL1, 24, 4),
+        MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
+        MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
+        MUX(CLK_MOUT_SPDIF, "mout_spdif", group_spdif_p, SRC_PERIL1, 8, 4),
+        MUX(CLK_MOUT_AUDIO2, "mout_audio2", group_sclk_audio2_p, SRC_PERIL1,
+                4, 4),
+        MUX(CLK_MOUT_AUDIO1, "mout_audio1", group_sclk_audio1_p, SRC_PERIL1,
+                0, 4),
+
+        /* SRC_CPU */
+        MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
+                SRC_CPU, 24, 1),
+        MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
+        MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 0,
+                CLK_MUX_READ_ONLY),
+        MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+                CLK_SET_RATE_PARENT, 0),
+
+        /* SRC_CAM1 */
+        MUX(CLK_MOUT_PXLASYNC_CSIS1_FIMC, "mout_pxlasync_csis1",
+                group_fimc_lclk_p, SRC_CAM1, 20, 1),
+        MUX(CLK_MOUT_PXLASYNC_CSIS0_FIMC, "mout_pxlasync_csis0",
+                group_fimc_lclk_p, SRC_CAM1, 16, 1),
+        MUX(CLK_MOUT_JPEG, "mout_jpeg", mout_jpeg_p, SRC_CAM1, 8, 1),
+        MUX(CLK_MOUT_JPEG1, "mout_jpeg_1", mout_jpeg1_p, SRC_CAM1, 4, 1),
+        MUX(CLK_MOUT_JPEG0, "mout_jpeg_0", group_mout_mpll_user_t_p, SRC_CAM1,
+                0, 1),
+
+        /* SRC_TOP_ISP0 */
+        MUX(CLK_MOUT_ACLK_ISP0_300, "mout_aclk_isp0_300",
+                group_aclk_isp0_300_p, SRC_TOP_ISP0, 8, 1),
+        MUX(CLK_MOUT_ACLK_ISP0_400, "mout_aclk_isp0_400_user",
+                group_aclk_isp0_400_user_p, SRC_TOP_ISP0, 4, 1),
+        MUX(CLK_MOUT_ACLK_ISP0_300_USER, "mout_aclk_isp0_300_user",
+                group_aclk_isp0_300_user_p, SRC_TOP_ISP0, 0, 1),
+
+        /* SRC_TOP_ISP1 */
+        MUX(CLK_MOUT_ACLK_ISP1_300, "mout_aclk_isp1_300",
+                group_aclk_isp0_300_p, SRC_TOP_ISP1, 4, 1),
+        MUX(CLK_MOUT_ACLK_ISP1_300_USER, "mout_aclk_isp1_300_user",
+                group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1),
+};
+
+static struct samsung_div_clock exynos4415_div_clks[] __initdata = {
+        /*
+         * NOTE: Following table is sorted by register address in ascending
+         * order and then bitfield shift in descending order, as it is done
+         * in the User's Manual. When adding new entries, please make sure
+         * that the order is preserved, to avoid merge conflicts and make
+         * further work with defined data easier.
+         */
+
+        /* DIV_LEFTBUS */
+        DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
+        DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
+
+        /* DIV_RIGHTBUS */
+        DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
+        DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
+
+        /* DIV_TOP */
+        DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
+                "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
+        DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
+        DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
+        DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
+        DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
+        DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
+
+        /* DIV_CAM */
+        DIV(CLK_DIV_CSIS1, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
+        DIV(CLK_DIV_CSIS0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
+        DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+        DIV(CLK_DIV_FIMC3_LCLK, "div_fimc3_lclk", "mout_fimc3_lclk", DIV_CAM,
+                12, 4),
+        DIV(CLK_DIV_FIMC2_LCLK, "div_fimc2_lclk", "mout_fimc2_lclk", DIV_CAM,
+                8, 4),
+        DIV(CLK_DIV_FIMC1_LCLK, "div_fimc1_lclk", "mout_fimc1_lclk", DIV_CAM,
+                4, 4),
+        DIV(CLK_DIV_FIMC0_LCLK, "div_fimc0_lclk", "mout_fimc0_lclk", DIV_CAM,
+                0, 4),
+
+        /* DIV_TV */
+        DIV(CLK_DIV_TV_BLK, "div_tv_blk", "mout_g3d_pll", DIV_TV, 0, 4),
+
+        /* DIV_MFC */
+        DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
+
+        /* DIV_G3D */
+        DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
+
+        /* DIV_LCD */
+        DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
+                CLK_SET_RATE_PARENT, 0),
+        DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
+        DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
+
+        /* DIV_ISP */
+        DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
+        DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
+                DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
+        DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
+        DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
+                DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
+        DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
+        DIV(CLK_DIV_PWM_ISP, "div_pwm_isp", "mout_pwm_isp", DIV_ISP, 0, 4),
+
+        /* DIV_MAUDIO */
+        DIV(CLK_DIV_PCM0, "div_pcm0", "div_audio0", DIV_MAUDIO, 4, 8),
+        DIV(CLK_DIV_AUDIO0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
+
+        /* DIV_FSYS0 */
+        DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
+                CLK_SET_RATE_PARENT, 0),
+        DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
+
+        /* DIV_FSYS1 */
+        DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
+                CLK_SET_RATE_PARENT, 0),
+        DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+        DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
+                CLK_SET_RATE_PARENT, 0),
+        DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+
+        /* DIV_FSYS2 */
+        DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+                CLK_SET_RATE_PARENT, 0),
+        DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4,
+                CLK_SET_RATE_PARENT, 0),
+
+        /* DIV_PERIL0 */
+        DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+        DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
+        DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+        DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+
+        /* DIV_PERIL1 */
+        DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
+                CLK_SET_RATE_PARENT, 0),
+        DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+        DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
+                CLK_SET_RATE_PARENT, 0),
+        DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+
+        /* DIV_PERIL2 */
+        DIV_F(CLK_DIV_SPI2_PRE, "div_spi2_pre", "div_spi2", DIV_PERIL2, 8, 8,
+                CLK_SET_RATE_PARENT, 0),
+        DIV(CLK_DIV_SPI2, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
+
+        /* DIV_PERIL4 */
+        DIV(CLK_DIV_PCM2, "div_pcm2", "div_audio2", DIV_PERIL4, 20, 8),
+        DIV(CLK_DIV_AUDIO2, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
+        DIV(CLK_DIV_PCM1, "div_pcm1", "div_audio1", DIV_PERIL4, 20, 8),
+        DIV(CLK_DIV_AUDIO1, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
+
+        /* DIV_PERIL5 */
+        DIV(CLK_DIV_I2S1, "div_i2s1", "div_audio1", DIV_PERIL5, 0, 6),
+
+        /* DIV_CAM1 */
+        DIV(CLK_DIV_PXLASYNC_CSIS1_FIMC, "div_pxlasync_csis1_fimc",
+                "mout_pxlasync_csis1", DIV_CAM1, 24, 4),
+        DIV(CLK_DIV_PXLASYNC_CSIS0_FIMC, "div_pxlasync_csis0_fimc",
+                "mout_pxlasync_csis0", DIV_CAM1, 20, 4),
+        DIV(CLK_DIV_JPEG, "div_jpeg", "mout_jpeg", DIV_CAM1, 0, 4),
+
+        /* DIV_CPU0 */
+        DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
+        DIV_F(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
+                        CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+        DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
+        DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
+        DIV(CLK_DIV_PERIPH, "div_periph", "div_core2", DIV_CPU0, 12, 3),
+        DIV(CLK_DIV_COREM1, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
+        DIV(CLK_DIV_COREM0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
+        DIV_F(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3,
+                CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+
+        /* DIV_CPU1 */
+        DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
+        DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
+};
+
+static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = {
+        /*
+         * NOTE: Following table is sorted by register address in ascending
+         * order and then bitfield shift in descending order, as it is done
+         * in the User's Manual. When adding new entries, please make sure
+         * that the order is preserved, to avoid merge conflicts and make
+         * further work with defined data easier.
+         */
+
+        /* GATE_IP_LEFTBUS */
+        GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ASYNC_TVX, "async_tvx", "div_aclk_100", GATE_IP_LEFTBUS, 3,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
+                CLK_IGNORE_UNUSED, 0),
+
+        /* GATE_IP_IMAGE */
+        GATE(CLK_PPMUIMAGE, "ppmuimage", "div_aclk_100", GATE_IP_IMAGE,
+                9, 0, 0),
+        GATE(CLK_QEMDMA2, "qe_mdma2", "div_aclk_100", GATE_IP_IMAGE,
+                8, 0, 0),
+        GATE(CLK_QEROTATOR, "qe_rotator", "div_aclk_100", GATE_IP_IMAGE,
+                7, 0, 0),
+        GATE(CLK_SMMUMDMA2, "smmu_mdam2", "div_aclk_100", GATE_IP_IMAGE,
+                5, 0, 0),
+        GATE(CLK_SMMUROTATOR, "smmu_rotator", "div_aclk_100", GATE_IP_IMAGE,
+                4, 0, 0),
+        GATE(CLK_MDMA2, "mdma2", "div_aclk_100", GATE_IP_IMAGE, 2, 0, 0),
+        GATE(CLK_ROTATOR, "rotator", "div_aclk_100", GATE_IP_IMAGE, 1, 0, 0),
+
+        /* GATE_IP_RIGHTBUS */
+        GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
+                GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ASYNC_MAUDIOX, "async_maudiox", "div_aclk_100",
+                GATE_IP_RIGHTBUS, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ASYNC_MFCR, "async_mfcr", "div_aclk_100",
+                GATE_IP_RIGHTBUS, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
+                GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
+                GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100",
+                GATE_IP_RIGHTBUS, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100",
+                GATE_IP_RIGHTBUS, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100",
+                GATE_IP_RIGHTBUS, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* GATE_IP_PERIR */
+        GATE(CLK_ANTIRBK_APBIF, "antirbk_apbif", "div_aclk_100",
+                GATE_IP_PERIR, 24, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_EFUSE_WRITER_APBIF, "efuse_writer_apbif", "div_aclk_100",
+                GATE_IP_PERIR, 23, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
+                GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
+                GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
+                GATE_IP_PERIR, 17, 0, 0),
+        GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
+        GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
+        GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
+        GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
+        GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk_100", GATE_IP_PERIR, 11,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
+                CLK_IGNORE_UNUSED, 0),
+
+        /* GATE_SCLK_CAM - non-completed */
+        GATE(CLK_SCLK_PXLAYSNC_CSIS1_FIMC, "sclk_pxlasync_csis1_fimc",
+                "div_pxlasync_csis1_fimc", GATE_SCLK_CAM, 11,
+                CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_PXLAYSNC_CSIS0_FIMC, "sclk_pxlasync_csis0_fimc",
+                "div_pxlasync_csis0_fimc", GATE_SCLK_CAM,
+                10, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
+                GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1",
+                GATE_SCLK_CAM, 7, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0",
+                GATE_SCLK_CAM, 6, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
+                GATE_SCLK_CAM, 5, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_FIMC3_LCLK, "sclk_fimc3_lclk", "div_fimc3_lclk",
+                GATE_SCLK_CAM, 3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_FIMC2_LCLK, "sclk_fimc2_lclk", "div_fimc2_lclk",
+                GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_FIMC1_LCLK, "sclk_fimc1_lclk", "div_fimc1_lclk",
+                GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_FIMC0_LCLK, "sclk_fimc0_lclk", "div_fimc0_lclk",
+                GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
+
+        /* GATE_SCLK_TV */
+        GATE(CLK_SCLK_PIXEL, "sclk_pixel", "div_tv_blk",
+                GATE_SCLK_TV, 3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
+                GATE_SCLK_TV, 2, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MIXER, "sclk_mixer", "div_tv_blk",
+                GATE_SCLK_TV, 0, CLK_SET_RATE_PARENT, 0),
+
+        /* GATE_SCLK_MFC */
+        GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
+                GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
+
+        /* GATE_SCLK_G3D */
+        GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
+                GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
+
+        /* GATE_SCLK_LCD */
+        GATE(CLK_SCLK_MIPIDPHY4L, "sclk_mipidphy4l", "div_mipi0",
+                GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
+                GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_fimd0",
+                GATE_SCLK_LCD, 1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
+                GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
+
+        /* GATE_SCLK_MAUDIO */
+        GATE(CLK_SCLK_PCM0, "sclk_pcm0", "div_pcm0",
+                GATE_SCLK_MAUDIO, 1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
+                GATE_SCLK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0),
+
+        /* GATE_SCLK_FSYS */
+        GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
+                GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
+                GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+                GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
+                GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
+                GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+
+        /* GATE_SCLK_PERIL */
+        GATE(CLK_SCLK_I2S, "sclk_i2s1", "div_i2s1",
+                GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_PCM2, "sclk_pcm2", "div_pcm2",
+                GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_PCM1, "sclk_pcm1", "div_pcm1",
+                GATE_SCLK_PERIL, 15, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
+                GATE_SCLK_PERIL, 14, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
+                GATE_SCLK_PERIL, 13, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
+                GATE_SCLK_PERIL, 10, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi2_pre",
+                GATE_SCLK_PERIL, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
+                GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
+                GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
+                GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+                GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+                GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+                GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
+
+        /* GATE_IP_CAM */
+        GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
+                22, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_FIMC_LITE2, "fimc_lite2", "div_aclk_160", GATE_IP_CAM,
+                20, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_aclk_160", GATE_IP_CAM,
+                18, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_aclk_160", GATE_IP_CAM,
+                17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PPMUCAMIF, "ppmucamif", "div_aclk_160", GATE_IP_CAM,
+                16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SMMUJPEG, "smmujpeg", "div_aclk_160", GATE_IP_CAM, 11, 0, 0),
+        GATE(CLK_SMMUFIMC3, "smmufimc3", "div_aclk_160", GATE_IP_CAM, 10, 0, 0),
+        GATE(CLK_SMMUFIMC2, "smmufimc2", "div_aclk_160", GATE_IP_CAM, 9, 0, 0),
+        GATE(CLK_SMMUFIMC1, "smmufimc1", "div_aclk_160", GATE_IP_CAM, 8, 0, 0),
+        GATE(CLK_SMMUFIMC0, "smmufimc0", "div_aclk_160", GATE_IP_CAM, 7, 0, 0),
+        GATE(CLK_JPEG, "jpeg", "div_aclk_160", GATE_IP_CAM, 6, 0, 0),
+        GATE(CLK_CSIS1, "csis1", "div_aclk_160", GATE_IP_CAM, 5, 0, 0),
+        GATE(CLK_CSIS0, "csis0", "div_aclk_160", GATE_IP_CAM, 4, 0, 0),
+        GATE(CLK_FIMC3, "fimc3", "div_aclk_160", GATE_IP_CAM, 3, 0, 0),
+        GATE(CLK_FIMC2, "fimc2", "div_aclk_160", GATE_IP_CAM, 2, 0, 0),
+        GATE(CLK_FIMC1, "fimc1", "div_aclk_160", GATE_IP_CAM, 1, 0, 0),
+        GATE(CLK_FIMC0, "fimc0", "div_aclk_160", GATE_IP_CAM, 0, 0, 0),
+
+        /* GATE_IP_TV */
+        GATE(CLK_PPMUTV, "ppmutv", "div_aclk_100", GATE_IP_TV, 5, 0, 0),
+        GATE(CLK_SMMUTV, "smmutv", "div_aclk_100", GATE_IP_TV, 4, 0, 0),
+        GATE(CLK_HDMI, "hdmi", "div_aclk_100", GATE_IP_TV, 3, 0, 0),
+        GATE(CLK_MIXER, "mixer", "div_aclk_100", GATE_IP_TV, 1, 0, 0),
+        GATE(CLK_VP, "vp", "div_aclk_100", GATE_IP_TV, 0, 0, 0),
+
+        /* GATE_IP_MFC */
+        GATE(CLK_PPMUMFC_R, "ppmumfc_r", "div_aclk_200", GATE_IP_MFC, 4,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SMMUMFC_R, "smmumfc_r", "div_aclk_200", GATE_IP_MFC, 2, 0, 0),
+        GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
+        GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
+
+        /* GATE_IP_G3D */
+        GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
+
+        /* GATE_IP_LCD */
+        GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
+        GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
+        GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
+        GATE(CLK_MIE0, "mie0", "div_aclk_160", GATE_IP_LCD, 1, 0, 0),
+        GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
+
+        /* GATE_IP_FSYS */
+        GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
+        GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
+                CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_NFCON, "nfcon", "div_aclk_200", GATE_IP_FSYS, 16, 0, 0),
+        GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13,
+                0, 0),
+        GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
+        GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+        GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
+        GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
+        GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
+        GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
+        GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
+
+        /* GATE_IP_PERIL */
+        GATE(CLK_SPDIF, "spdif", "div_aclk_100", GATE_IP_PERIL, 26, 0, 0),
+        GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
+        GATE(CLK_PCM2, "pcm2", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
+        GATE(CLK_PCM1, "pcm1", "div_aclk_100", GATE_IP_PERIL, 22, 0, 0),
+        GATE(CLK_I2S1, "i2s1", "div_aclk_100", GATE_IP_PERIL, 20, 0, 0),
+        GATE(CLK_SPI2, "spi2", "div_aclk_100", GATE_IP_PERIL, 18, 0, 0),
+        GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
+        GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
+        GATE(CLK_I2CHDMI, "i2chdmi", "div_aclk_100", GATE_IP_PERIL, 14, 0, 0),
+        GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
+        GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
+        GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
+        GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
+        GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
+        GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
+        GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
+        GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+        GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
+        GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
+        GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
+        GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
+};
+
+/*
+ * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
+ */
+static struct samsung_pll_rate_table exynos4415_pll_rates[] = {
+        PLL_35XX_RATE(1600000000, 400, 3,  1),
+        PLL_35XX_RATE(1500000000, 250, 2,  1),
+        PLL_35XX_RATE(1400000000, 175, 3,  0),
+        PLL_35XX_RATE(1300000000, 325, 3,  1),
+        PLL_35XX_RATE(1200000000, 400, 4,  1),
+        PLL_35XX_RATE(1100000000, 275, 3,  1),
+        PLL_35XX_RATE(1066000000, 533, 6,  1),
+        PLL_35XX_RATE(1000000000, 250, 3,  1),
+        PLL_35XX_RATE(960000000,  320, 4,  1),
+        PLL_35XX_RATE(900000000,  300, 4,  1),
+        PLL_35XX_RATE(850000000,  425, 6,  1),
+        PLL_35XX_RATE(800000000,  200, 3,  1),
+        PLL_35XX_RATE(700000000,  175, 3,  1),
+        PLL_35XX_RATE(667000000,  667, 12, 1),
+        PLL_35XX_RATE(600000000,  400, 4,  2),
+        PLL_35XX_RATE(550000000,  275, 3,  2),
+        PLL_35XX_RATE(533000000,  533, 6,  2),
+        PLL_35XX_RATE(520000000,  260, 3,  2),
+        PLL_35XX_RATE(500000000,  250, 3,  2),
+        PLL_35XX_RATE(440000000,  220, 3,  2),
+        PLL_35XX_RATE(400000000,  200, 3,  2),
+        PLL_35XX_RATE(350000000,  175, 3,  2),
+        PLL_35XX_RATE(300000000,  300, 3,  3),
+        PLL_35XX_RATE(266000000,  266, 3,  3),
+        PLL_35XX_RATE(200000000,  200, 3,  3),
+        PLL_35XX_RATE(160000000,  160, 3,  3),
+        PLL_35XX_RATE(100000000,  200, 3,  4),
+        { /* sentinel */ }
+};
+
+/* EPLL */
+static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
+        PLL_36XX_RATE(800000000, 200, 3, 1,     0),
+        PLL_36XX_RATE(288000000,  96, 2, 2,     0),
+        PLL_36XX_RATE(192000000, 128, 2, 3,     0),
+        PLL_36XX_RATE(144000000,  96, 2, 3,     0),
+        PLL_36XX_RATE(96000000,  128, 2, 4,     0),
+        PLL_36XX_RATE(84000000,  112, 2, 4,     0),
+        PLL_36XX_RATE(80750011,  107, 2, 4, 43691),
+        PLL_36XX_RATE(73728004,   98, 2, 4, 19923),
+        PLL_36XX_RATE(67987602,  271, 3, 5, 62285),
+        PLL_36XX_RATE(65911004,  175, 2, 5, 49982),
+        PLL_36XX_RATE(50000000,  200, 3, 5,     0),
+        PLL_36XX_RATE(49152003,  131, 2, 5,  4719),
+        PLL_36XX_RATE(48000000,  128, 2, 5,     0),
+        PLL_36XX_RATE(45250000,  181, 3, 5,     0),
+        { /* sentinel */ }
+};
+
+static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = {
+        [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
+                        APLL_LOCK, APLL_CON0, NULL),
+        [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
+                        EPLL_LOCK, EPLL_CON0, NULL),
+        [g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll",
+                        "mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL),
+        [isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
+                        ISP_PLL_LOCK, ISP_PLL_CON0, NULL),
+        [disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
+                        "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL),
+};
+
+static void __init exynos4415_cmu_init(struct device_node *np)
+{
+        void __iomem *reg_base;
+
+        reg_base = of_iomap(np, 0);
+        if (!reg_base)
+                panic("%s: failed to map registers\n", __func__);
+
+        exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+        if (!exynos4415_ctx)
+                panic("%s: unable to allocate context.\n", __func__);
+
+        exynos4415_plls[apll].rate_table = exynos4415_pll_rates;
+        exynos4415_plls[epll].rate_table = exynos4415_epll_rates;
+        exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates;
+        exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates;
+        exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates;
+
+        samsung_clk_register_fixed_factor(exynos4415_ctx,
+                                exynos4415_fixed_factor_clks,
+                                ARRAY_SIZE(exynos4415_fixed_factor_clks));
+        samsung_clk_register_fixed_rate(exynos4415_ctx,
+                                exynos4415_fixed_rate_clks,
+                                ARRAY_SIZE(exynos4415_fixed_rate_clks));
+
+        samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls,
+                                ARRAY_SIZE(exynos4415_plls), reg_base);
+        samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks,
+                                ARRAY_SIZE(exynos4415_mux_clks));
+        samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks,
+                                ARRAY_SIZE(exynos4415_div_clks));
+        samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks,
+                                ARRAY_SIZE(exynos4415_gate_clks));
+
+        exynos4415_clk_sleep_init();
+
+        samsung_clk_of_add_provider(np, exynos4415_ctx);
+}
+CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
+
+/*
+ * CMU DMC
+ */
+
+#define MPLL_LOCK               0x008
+#define MPLL_CON0               0x108
+#define MPLL_CON1               0x10c
+#define MPLL_CON2               0x110
+#define BPLL_LOCK               0x118
+#define BPLL_CON0               0x218
+#define BPLL_CON1               0x21c
+#define BPLL_CON2               0x220
+#define SRC_DMC                 0x300
+#define DIV_DMC1                0x504
+
+enum exynos4415_dmc_plls {
+        mpll, bpll,
+        nr_dmc_plls,
+};
+
+static struct samsung_clk_provider *exynos4415_dmc_ctx;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs;
+
+static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
+        MPLL_LOCK,
+        MPLL_CON0,
+        MPLL_CON1,
+        MPLL_CON2,
+        BPLL_LOCK,
+        BPLL_CON0,
+        BPLL_CON1,
+        BPLL_CON2,
+        SRC_DMC,
+        DIV_DMC1,
+};
+
+static int exynos4415_dmc_clk_suspend(void)
+{
+        samsung_clk_save(exynos4415_dmc_ctx->reg_base,
+                                exynos4415_dmc_clk_regs,
+                                ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
+        return 0;
+}
+
+static void exynos4415_dmc_clk_resume(void)
+{
+        samsung_clk_restore(exynos4415_dmc_ctx->reg_base,
+                                exynos4415_dmc_clk_regs,
+                                ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
+}
+
+static struct syscore_ops exynos4415_dmc_clk_syscore_ops = {
+        .suspend = exynos4415_dmc_clk_suspend,
+        .resume = exynos4415_dmc_clk_resume,
+};
+
+static void exynos4415_dmc_clk_sleep_init(void)
+{
+        exynos4415_dmc_clk_regs =
+                samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs,
+                                ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
+        if (!exynos4415_dmc_clk_regs) {
+                pr_warn("%s: Failed to allocate sleep save data\n", __func__);
+                return;
+        }
+
+        register_syscore_ops(&exynos4415_dmc_clk_syscore_ops);
+}
+#else
+static inline void exynos4415_dmc_clk_sleep_init(void) { }
+#endif /* CONFIG_PM_SLEEP */
+
+PNAME(mout_mpll_p)              = { "fin_pll", "fout_mpll", };
+PNAME(mout_bpll_p)              = { "fin_pll", "fout_bpll", };
+PNAME(mbpll_p)                  = { "mout_mpll", "mout_bpll", };
+
+static struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initdata = {
+        MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1),
+        MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
+        MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1),
+        MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1),
+};
+
+static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
+        DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
+        DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
+        DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus",
+                DIV_DMC1, 19, 2),
+        DIV(CLK_DMC_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
+        DIV(CLK_DMC_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
+        DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
+};
+
+static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = {
+        [mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
+                MPLL_LOCK, MPLL_CON0, NULL),
+        [bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
+                BPLL_LOCK, BPLL_CON0, NULL),
+};
+
+static void __init exynos4415_cmu_dmc_init(struct device_node *np)
+{
+        void __iomem *reg_base;
+
+        reg_base = of_iomap(np, 0);
+        if (!reg_base)
+                panic("%s: failed to map registers\n", __func__);
+
+        exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC);
+        if (!exynos4415_dmc_ctx)
+                panic("%s: unable to allocate context.\n", __func__);
+
+        exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates;
+        exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates;
+
+        samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls,
+                                ARRAY_SIZE(exynos4415_dmc_plls), reg_base);
+        samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks,
+                                ARRAY_SIZE(exynos4415_dmc_mux_clks));
+        samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks,
+                                ARRAY_SIZE(exynos4415_dmc_div_clks));
+
+        exynos4415_dmc_clk_sleep_init();
+
+        samsung_clk_of_add_provider(np, exynos4415_dmc_ctx);
+}
+CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
+                exynos4415_cmu_dmc_init);
diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
index 2527e39aadcf..e2e5193d1049 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -11,10 +11,8 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/syscore_ops.h>
 
 #include "clk-exynos5260.h"
 #include "clk.h"
@@ -22,39 +20,6 @@
 
 #include <dt-bindings/clock/exynos5260-clk.h>
 
-static LIST_HEAD(clock_reg_cache_list);
-
-struct exynos5260_clock_reg_cache {
-        struct list_head node;
-        void __iomem *reg_base;
-        struct samsung_clk_reg_dump *rdump;
-        unsigned int rd_num;
-};
-
-struct exynos5260_cmu_info {
-        /* list of pll clocks and respective count */
-        struct samsung_pll_clock *pll_clks;
-        unsigned int nr_pll_clks;
-        /* list of mux clocks and respective count */
-        struct samsung_mux_clock *mux_clks;
-        unsigned int nr_mux_clks;
-        /* list of div clocks and respective count */
-        struct samsung_div_clock *div_clks;
-        unsigned int nr_div_clks;
-        /* list of gate clocks and respective count */
-        struct samsung_gate_clock *gate_clks;
-        unsigned int nr_gate_clks;
-        /* list of fixed clocks and respective count */
-        struct samsung_fixed_rate_clock *fixed_clks;
-        unsigned int nr_fixed_clks;
-        /* total number of clocks with IDs assigned*/
-        unsigned int nr_clk_ids;
-
-        /* list and number of clocks registers */
-        unsigned long *clk_regs;
-        unsigned int nr_clk_regs;
-};
-
 /*
  * Applicable for all 2550 Type PLLS for Exynos5260, listed below
  * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@@ -113,104 +78,6 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = {
         PLL_36XX_RATE(66000000, 176, 2, 5, 0),
 };
 
-#ifdef CONFIG_PM_SLEEP
-
-static int exynos5260_clk_suspend(void)
-{
-        struct exynos5260_clock_reg_cache *cache;
-
-        list_for_each_entry(cache, &clock_reg_cache_list, node)
-                samsung_clk_save(cache->reg_base, cache->rdump,
-                                cache->rd_num);
-
-        return 0;
-}
-
-static void exynos5260_clk_resume(void)
-{
-        struct exynos5260_clock_reg_cache *cache;
-
-        list_for_each_entry(cache, &clock_reg_cache_list, node)
-                samsung_clk_restore(cache->reg_base, cache->rdump,
-                                cache->rd_num);
-}
-
-static struct syscore_ops exynos5260_clk_syscore_ops = {
-        .suspend = exynos5260_clk_suspend,
-        .resume = exynos5260_clk_resume,
-};
-
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
-                        unsigned long *rdump,
-                        unsigned long nr_rdump)
-{
-        struct exynos5260_clock_reg_cache *reg_cache;
-
-        reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
-                        GFP_KERNEL);
-        if (!reg_cache)
-                panic("could not allocate register cache.\n");
-
-        reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
-
-        if (!reg_cache->rdump)
-                panic("could not allocate register dump storage.\n");
-
-        if (list_empty(&clock_reg_cache_list))
-                register_syscore_ops(&exynos5260_clk_syscore_ops);
-
-        reg_cache->rd_num = nr_rdump;
-        reg_cache->reg_base = reg_base;
-        list_add_tail(&reg_cache->node, &clock_reg_cache_list);
-}
-
-#else
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
-                        unsigned long *rdump,
-                        unsigned long nr_rdump){}
-#endif
-
-/*
- * Common function which registers plls, muxes, dividers and gates
- * for each CMU. It also add CMU register list to register cache.
- */
-
-void __init exynos5260_cmu_register_one(struct device_node *np,
-                        struct exynos5260_cmu_info *cmu)
-{
-        void __iomem *reg_base;
-        struct samsung_clk_provider *ctx;
-
-        reg_base = of_iomap(np, 0);
-        if (!reg_base)
-                panic("%s: failed to map registers\n", __func__);
-
-        ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
-        if (!ctx)
-                panic("%s: unable to alllocate ctx\n", __func__);
-
-        if (cmu->pll_clks)
-                samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
-                        reg_base);
-        if (cmu->mux_clks)
-                samsung_clk_register_mux(ctx,  cmu->mux_clks,
-                        cmu->nr_mux_clks);
-        if (cmu->div_clks)
-                samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
-        if (cmu->gate_clks)
-                samsung_clk_register_gate(ctx, cmu->gate_clks,
-                        cmu->nr_gate_clks);
-        if (cmu->fixed_clks)
-                samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
-                        cmu->nr_fixed_clks);
-        if (cmu->clk_regs)
-                exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
-                        cmu->nr_clk_regs);
-
-        samsung_clk_of_add_provider(np, ctx);
-}
-
-
 /* CMU_AUD */
 
 static unsigned long aud_clk_regs[] __initdata = {
@@ -268,7 +135,7 @@ struct samsung_gate_clock aud_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_aud_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.mux_clks = aud_mux_clks;
         cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks);
@@ -280,7 +147,7 @@ static void __init exynos5260_clk_aud_init(struct device_node *np)
         cmu.clk_regs = aud_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
@@ -458,7 +325,7 @@ struct samsung_gate_clock disp_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_disp_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.mux_clks = disp_mux_clks;
         cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks);
@@ -470,7 +337,7 @@ static void __init exynos5260_clk_disp_init(struct device_node *np)
         cmu.clk_regs = disp_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
@@ -522,7 +389,7 @@ static struct samsung_pll_clock egl_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_egl_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.pll_clks = egl_pll_clks;
         cmu.nr_pll_clks =  ARRAY_SIZE(egl_pll_clks);
@@ -534,7 +401,7 @@ static void __init exynos5260_clk_egl_init(struct device_node *np)
         cmu.clk_regs = egl_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(egl_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
@@ -624,7 +491,7 @@ struct samsung_gate_clock fsys_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_fsys_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.mux_clks = fsys_mux_clks;
         cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks);
@@ -634,7 +501,7 @@ static void __init exynos5260_clk_fsys_init(struct device_node *np)
         cmu.clk_regs = fsys_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
@@ -713,7 +580,7 @@ struct samsung_gate_clock g2d_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_g2d_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.mux_clks = g2d_mux_clks;
         cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks);
@@ -725,7 +592,7 @@ static void __init exynos5260_clk_g2d_init(struct device_node *np)
         cmu.clk_regs = g2d_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
@@ -774,7 +641,7 @@ static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_g3d_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.pll_clks = g3d_pll_clks;
         cmu.nr_pll_clks =  ARRAY_SIZE(g3d_pll_clks);
@@ -788,7 +655,7 @@ static void __init exynos5260_clk_g3d_init(struct device_node *np)
         cmu.clk_regs = g3d_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
@@ -909,7 +776,7 @@ struct samsung_gate_clock gscl_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_gscl_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.mux_clks = gscl_mux_clks;
         cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks);
@@ -921,7 +788,7 @@ static void __init exynos5260_clk_gscl_init(struct device_node *np)
         cmu.clk_regs = gscl_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
@@ -1028,7 +895,7 @@ struct samsung_gate_clock isp_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_isp_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.mux_clks = isp_mux_clks;
         cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks);
@@ -1040,7 +907,7 @@ static void __init exynos5260_clk_isp_init(struct device_node *np)
         cmu.clk_regs = isp_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(isp_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
@@ -1092,7 +959,7 @@ static struct samsung_pll_clock kfc_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_kfc_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.pll_clks = kfc_pll_clks;
         cmu.nr_pll_clks =  ARRAY_SIZE(kfc_pll_clks);
@@ -1104,7 +971,7 @@ static void __init exynos5260_clk_kfc_init(struct device_node *np)
         cmu.clk_regs = kfc_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
@@ -1148,7 +1015,7 @@ struct samsung_gate_clock mfc_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_mfc_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.mux_clks = mfc_mux_clks;
         cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks);
@@ -1160,7 +1027,7 @@ static void __init exynos5260_clk_mfc_init(struct device_node *np)
         cmu.clk_regs = mfc_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
@@ -1295,7 +1162,7 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_mif_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.pll_clks = mif_pll_clks;
         cmu.nr_pll_clks =  ARRAY_SIZE(mif_pll_clks);
@@ -1309,7 +1176,7 @@ static void __init exynos5260_clk_mif_init(struct device_node *np)
         cmu.clk_regs = mif_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(mif_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
@@ -1503,7 +1370,7 @@ struct samsung_gate_clock peri_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_peri_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.mux_clks = peri_mux_clks;
         cmu.nr_mux_clks = ARRAY_SIZE(peri_mux_clks);
@@ -1515,7 +1382,7 @@ static void __init exynos5260_clk_peri_init(struct device_node *np)
         cmu.clk_regs = peri_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(peri_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
@@ -1959,7 +1826,7 @@ static struct samsung_pll_clock top_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_top_init(struct device_node *np)
 {
-        struct exynos5260_cmu_info cmu = {0};
+        struct samsung_cmu_info cmu = {0};
 
         cmu.pll_clks = top_pll_clks;
         cmu.nr_pll_clks =  ARRAY_SIZE(top_pll_clks);
@@ -1975,7 +1842,7 @@ static void __init exynos5260_clk_top_init(struct device_node *np)
         cmu.clk_regs = top_clk_regs;
         cmu.nr_clk_regs = ARRAY_SIZE(top_clk_regs);
 
-        exynos5260_cmu_register_one(np, &cmu);
+        samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
new file mode 100644
index 000000000000..ea4483b8d62e
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -0,0 +1,743 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#include "clk.h"
+#include <dt-bindings/clock/exynos7-clk.h>
+
+/* Register Offset definitions for CMU_TOPC (0x10570000) */
+#define CC_PLL_LOCK             0x0000
+#define BUS0_PLL_LOCK           0x0004
+#define BUS1_DPLL_LOCK          0x0008
+#define MFC_PLL_LOCK            0x000C
+#define AUD_PLL_LOCK            0x0010
+#define CC_PLL_CON0             0x0100
+#define BUS0_PLL_CON0           0x0110
+#define BUS1_DPLL_CON0          0x0120
+#define MFC_PLL_CON0            0x0130
+#define AUD_PLL_CON0            0x0140
+#define MUX_SEL_TOPC0           0x0200
+#define MUX_SEL_TOPC1           0x0204
+#define MUX_SEL_TOPC2           0x0208
+#define MUX_SEL_TOPC3           0x020C
+#define DIV_TOPC0               0x0600
+#define DIV_TOPC1               0x0604
+#define DIV_TOPC3               0x060C
+
+static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
+        FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
+        FFACTOR(0, "ffac_topc_bus0_pll_div4",
+                "ffac_topc_bus0_pll_div2", 1, 2, 0),
+        FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
+        FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
+        FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
+};
+
+/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_bus0_pll_ctrl_p)     = { "fin_pll", "fout_bus0_pll" };
+PNAME(mout_bus1_pll_ctrl_p)     = { "fin_pll", "fout_bus1_pll" };
+PNAME(mout_cc_pll_ctrl_p)       = { "fin_pll", "fout_cc_pll" };
+PNAME(mout_mfc_pll_ctrl_p)      = { "fin_pll", "fout_mfc_pll" };
+
+PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
+        "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
+        "mout_sclk_mfc_pll_cmuc" };
+
+PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
+        "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
+PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
+        "ffac_topc_bus1_pll_div2"};
+PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
+        "ffac_topc_cc_pll_div2"};
+PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
+        "ffac_topc_mfc_pll_div2"};
+
+
+PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
+        "ffac_topc_bus0_pll_div2"};
+
+static unsigned long topc_clk_regs[] __initdata = {
+        CC_PLL_LOCK,
+        BUS0_PLL_LOCK,
+        BUS1_DPLL_LOCK,
+        MFC_PLL_LOCK,
+        AUD_PLL_LOCK,
+        CC_PLL_CON0,
+        BUS0_PLL_CON0,
+        BUS1_DPLL_CON0,
+        MFC_PLL_CON0,
+        AUD_PLL_CON0,
+        MUX_SEL_TOPC0,
+        MUX_SEL_TOPC1,
+        MUX_SEL_TOPC2,
+        MUX_SEL_TOPC3,
+        DIV_TOPC0,
+        DIV_TOPC1,
+        DIV_TOPC3,
+};
+
+static struct samsung_mux_clock topc_mux_clks[] __initdata = {
+        MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
+        MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
+        MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
+        MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
+
+        MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
+                MUX_SEL_TOPC0, 16, 2),
+        MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
+                MUX_SEL_TOPC0, 20, 1),
+        MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
+                MUX_SEL_TOPC0, 24, 1),
+        MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
+                MUX_SEL_TOPC0, 28, 1),
+
+        MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
+                MUX_SEL_TOPC1, 16, 1),
+
+        MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
+
+        MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
+};
+
+static struct samsung_div_clock topc_div_clks[] __initdata = {
+        DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
+                DIV_TOPC0, 4, 4),
+
+        DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
+                DIV_TOPC1, 24, 4),
+
+        DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
+                DIV_TOPC3, 0, 3),
+        DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
+                DIV_TOPC3, 8, 3),
+        DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
+                DIV_TOPC3, 12, 3),
+        DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
+                DIV_TOPC3, 16, 3),
+};
+
+static struct samsung_pll_clock topc_pll_clks[] __initdata = {
+        PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
+                BUS0_PLL_CON0, NULL),
+        PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
+                CC_PLL_CON0, NULL),
+        PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
+                BUS1_DPLL_CON0, NULL),
+        PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
+                MFC_PLL_CON0, NULL),
+        PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
+                AUD_PLL_CON0, NULL),
+};
+
+static struct samsung_cmu_info topc_cmu_info __initdata = {
+        .pll_clks               = topc_pll_clks,
+        .nr_pll_clks            = ARRAY_SIZE(topc_pll_clks),
+        .mux_clks               = topc_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(topc_mux_clks),
+        .div_clks               = topc_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(topc_div_clks),
+        .fixed_factor_clks      = topc_fixed_factor_clks,
+        .nr_fixed_factor_clks   = ARRAY_SIZE(topc_fixed_factor_clks),
+        .nr_clk_ids             = TOPC_NR_CLK,
+        .clk_regs               = topc_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(topc_clk_regs),
+};
+
+static void __init exynos7_clk_topc_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &topc_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
+        exynos7_clk_topc_init);
+
+/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
+#define MUX_SEL_TOP00                   0x0200
+#define MUX_SEL_TOP01                   0x0204
+#define MUX_SEL_TOP03                   0x020C
+#define MUX_SEL_TOP0_PERIC3             0x023C
+#define DIV_TOP03                       0x060C
+#define DIV_TOP0_PERIC3                 0x063C
+#define ENABLE_SCLK_TOP0_PERIC3         0x0A3C
+
+/* List of parent clocks for Muxes in CMU_TOP0 */
+PNAME(mout_bus0_pll_p)  = { "fin_pll", "dout_sclk_bus0_pll" };
+PNAME(mout_bus1_pll_p)  = { "fin_pll", "dout_sclk_bus1_pll" };
+PNAME(mout_cc_pll_p)    = { "fin_pll", "dout_sclk_cc_pll" };
+PNAME(mout_mfc_pll_p)   = { "fin_pll", "dout_sclk_mfc_pll" };
+
+PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
+        "ffac_top0_bus0_pll_div2"};
+PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
+        "ffac_top0_bus1_pll_div2"};
+PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
+        "ffac_top0_cc_pll_div2"};
+PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
+        "ffac_top0_mfc_pll_div2"};
+
+PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
+        "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
+        "mout_top0_half_mfc_pll"};
+
+static unsigned long top0_clk_regs[] __initdata = {
+        MUX_SEL_TOP00,
+        MUX_SEL_TOP01,
+        MUX_SEL_TOP03,
+        MUX_SEL_TOP0_PERIC3,
+        DIV_TOP03,
+        DIV_TOP0_PERIC3,
+        ENABLE_SCLK_TOP0_PERIC3,
+};
+
+static struct samsung_mux_clock top0_mux_clks[] __initdata = {
+        MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
+        MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
+        MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
+        MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
+
+        MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
+                MUX_SEL_TOP01, 4, 1),
+        MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
+                MUX_SEL_TOP01, 8, 1),
+        MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
+                MUX_SEL_TOP01, 12, 1),
+        MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
+                MUX_SEL_TOP01, 16, 1),
+
+        MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
+        MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
+
+        MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
+        MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
+        MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
+        MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+};
+
+static struct samsung_div_clock top0_div_clks[] __initdata = {
+        DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
+                DIV_TOP03, 12, 6),
+        DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
+                DIV_TOP03, 20, 6),
+
+        DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
+        DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
+        DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
+        DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
+};
+
+static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+        GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
+                ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
+        GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
+                ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
+        GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
+                ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
+        GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
+                ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
+};
+
+static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
+        FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
+        FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
+        FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
+        FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
+};
+
+static struct samsung_cmu_info top0_cmu_info __initdata = {
+        .mux_clks               = top0_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(top0_mux_clks),
+        .div_clks               = top0_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(top0_div_clks),
+        .gate_clks              = top0_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(top0_gate_clks),
+        .fixed_factor_clks      = top0_fixed_factor_clks,
+        .nr_fixed_factor_clks   = ARRAY_SIZE(top0_fixed_factor_clks),
+        .nr_clk_ids             = TOP0_NR_CLK,
+        .clk_regs               = top0_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(top0_clk_regs),
+};
+
+static void __init exynos7_clk_top0_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &top0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
+        exynos7_clk_top0_init);
+
+/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
+#define MUX_SEL_TOP10                   0x0200
+#define MUX_SEL_TOP11                   0x0204
+#define MUX_SEL_TOP13                   0x020C
+#define MUX_SEL_TOP1_FSYS0              0x0224
+#define MUX_SEL_TOP1_FSYS1              0x0228
+#define DIV_TOP13                       0x060C
+#define DIV_TOP1_FSYS0                  0x0624
+#define DIV_TOP1_FSYS1                  0x0628
+#define ENABLE_ACLK_TOP13               0x080C
+#define ENABLE_SCLK_TOP1_FSYS0          0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1          0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)     = { "fin_pll", "dout_sclk_bus0_pll" };
+PNAME(mout_top1_bus1_pll_p)     = { "fin_pll", "dout_sclk_bus1_pll_b" };
+PNAME(mout_top1_cc_pll_p)       = { "fin_pll", "dout_sclk_cc_pll_b" };
+PNAME(mout_top1_mfc_pll_p)      = { "fin_pll", "dout_sclk_mfc_pll_b" };
+
+PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
+        "ffac_top1_bus0_pll_div2"};
+PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
+        "ffac_top1_bus1_pll_div2"};
+PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
+        "ffac_top1_cc_pll_div2"};
+PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
+        "ffac_top1_mfc_pll_div2"};
+
+PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
+        "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
+        "mout_top1_half_mfc_pll"};
+
+static unsigned long top1_clk_regs[] __initdata = {
+        MUX_SEL_TOP10,
+        MUX_SEL_TOP11,
+        MUX_SEL_TOP13,
+        MUX_SEL_TOP1_FSYS0,
+        MUX_SEL_TOP1_FSYS1,
+        DIV_TOP13,
+        DIV_TOP1_FSYS0,
+        DIV_TOP1_FSYS1,
+        ENABLE_ACLK_TOP13,
+        ENABLE_SCLK_TOP1_FSYS0,
+        ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+        MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+        MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+        MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
+                MUX_SEL_TOP10, 12, 1),
+        MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
+                MUX_SEL_TOP10, 16, 1),
+
+        MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
+                MUX_SEL_TOP11, 4, 1),
+        MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
+                MUX_SEL_TOP11, 8, 1),
+        MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
+                MUX_SEL_TOP11, 12, 1),
+        MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
+                MUX_SEL_TOP11, 16, 1),
+
+        MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
+        MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
+
+        MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+
+        MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
+        MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
+};
+
+static struct samsung_div_clock top1_div_clks[] __initdata = {
+        DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
+                DIV_TOP13, 24, 4),
+        DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
+                DIV_TOP13, 28, 4),
+
+        DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
+                DIV_TOP1_FSYS0, 24, 4),
+
+        DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
+                DIV_TOP1_FSYS1, 24, 4),
+        DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
+                DIV_TOP1_FSYS1, 28, 4),
+};
+
+static struct samsung_gate_clock top1_gate_clks[] __initdata = {
+        GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
+                ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
+
+        GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
+                ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
+                ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
+        FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
+        FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
+        FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
+        FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
+};
+
+static struct samsung_cmu_info top1_cmu_info __initdata = {
+        .mux_clks               = top1_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(top1_mux_clks),
+        .div_clks               = top1_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(top1_div_clks),
+        .gate_clks              = top1_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(top1_gate_clks),
+        .fixed_factor_clks      = top1_fixed_factor_clks,
+        .nr_fixed_factor_clks   = ARRAY_SIZE(top1_fixed_factor_clks),
+        .nr_clk_ids             = TOP1_NR_CLK,
+        .clk_regs               = top1_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(top1_clk_regs),
+};
+
+static void __init exynos7_clk_top1_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &top1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
+        exynos7_clk_top1_init);
+
+/* Register Offset definitions for CMU_CCORE (0x105B0000) */
+#define MUX_SEL_CCORE                   0x0200
+#define DIV_CCORE                       0x0600
+#define ENABLE_ACLK_CCORE0              0x0800
+#define ENABLE_ACLK_CCORE1              0x0804
+#define ENABLE_PCLK_CCORE               0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_133_p)    = { "fin_pll", "dout_aclk_ccore_133" };
+
+static unsigned long ccore_clk_regs[] __initdata = {
+        MUX_SEL_CCORE,
+        ENABLE_PCLK_CCORE,
+};
+
+static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
+        MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
+                MUX_SEL_CCORE, 1, 1),
+};
+
+static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
+        GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
+                ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static struct samsung_cmu_info ccore_cmu_info __initdata = {
+        .mux_clks               = ccore_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(ccore_mux_clks),
+        .gate_clks              = ccore_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(ccore_gate_clks),
+        .nr_clk_ids             = CCORE_NR_CLK,
+        .clk_regs               = ccore_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(ccore_clk_regs),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &ccore_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
+        exynos7_clk_ccore_init);
+
+/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
+#define MUX_SEL_PERIC0                  0x0200
+#define ENABLE_PCLK_PERIC0              0x0900
+#define ENABLE_SCLK_PERIC0              0x0A00
+
+/* List of parent clocks for Muxes in CMU_PERIC0 */
+PNAME(mout_aclk_peric0_66_p)    = { "fin_pll", "dout_aclk_peric0_66" };
+PNAME(mout_sclk_uart0_p)        = { "fin_pll", "sclk_uart0" };
+
+static unsigned long peric0_clk_regs[] __initdata = {
+        MUX_SEL_PERIC0,
+        ENABLE_PCLK_PERIC0,
+        ENABLE_SCLK_PERIC0,
+};
+
+static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
+        MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
+                MUX_SEL_PERIC0, 0, 1),
+        MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
+                MUX_SEL_PERIC0, 16, 1),
+};
+
+static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+        GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 8, 0, 0),
+        GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 9, 0, 0),
+        GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 10, 0, 0),
+        GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 11, 0, 0),
+        GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 12, 0, 0),
+        GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 13, 0, 0),
+        GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 14, 0, 0),
+        GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 16, 0, 0),
+        GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 20, 0, 0),
+        GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 21, 0, 0),
+
+        GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
+                ENABLE_SCLK_PERIC0, 16, 0, 0),
+        GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
+};
+
+static struct samsung_cmu_info peric0_cmu_info __initdata = {
+        .mux_clks               = peric0_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(peric0_mux_clks),
+        .gate_clks              = peric0_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(peric0_gate_clks),
+        .nr_clk_ids             = PERIC0_NR_CLK,
+        .clk_regs               = peric0_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(peric0_clk_regs),
+};
+
+static void __init exynos7_clk_peric0_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &peric0_cmu_info);
+}
+
+/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
+#define MUX_SEL_PERIC10                 0x0200
+#define MUX_SEL_PERIC11                 0x0204
+#define ENABLE_PCLK_PERIC1              0x0900
+#define ENABLE_SCLK_PERIC10             0x0A00
+
+CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
+        exynos7_clk_peric0_init);
+
+/* List of parent clocks for Muxes in CMU_PERIC1 */
+PNAME(mout_aclk_peric1_66_p)    = { "fin_pll", "dout_aclk_peric1_66" };
+PNAME(mout_sclk_uart1_p)        = { "fin_pll", "sclk_uart1" };
+PNAME(mout_sclk_uart2_p)        = { "fin_pll", "sclk_uart2" };
+PNAME(mout_sclk_uart3_p)        = { "fin_pll", "sclk_uart3" };
+
+static unsigned long peric1_clk_regs[] __initdata = {
+        MUX_SEL_PERIC10,
+        MUX_SEL_PERIC11,
+        ENABLE_PCLK_PERIC1,
+        ENABLE_SCLK_PERIC10,
+};
+
+static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
+        MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
+                MUX_SEL_PERIC10, 0, 1),
+
+        MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
+                MUX_SEL_PERIC11, 20, 1),
+        MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
+                MUX_SEL_PERIC11, 24, 1),
+        MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
+                MUX_SEL_PERIC11, 28, 1),
+};
+
+static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+        GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 4, 0, 0),
+        GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 5, 0, 0),
+        GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 6, 0, 0),
+        GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 7, 0, 0),
+        GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 8, 0, 0),
+        GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 9, 0, 0),
+        GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 10, 0, 0),
+        GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 11, 0, 0),
+
+        GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
+                ENABLE_SCLK_PERIC10, 9, 0, 0),
+        GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
+                ENABLE_SCLK_PERIC10, 10, 0, 0),
+        GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
+                ENABLE_SCLK_PERIC10, 11, 0, 0),
+};
+
+static struct samsung_cmu_info peric1_cmu_info __initdata = {
+        .mux_clks               = peric1_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(peric1_mux_clks),
+        .gate_clks              = peric1_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(peric1_gate_clks),
+        .nr_clk_ids             = PERIC1_NR_CLK,
+        .clk_regs               = peric1_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(peric1_clk_regs),
+};
+
+static void __init exynos7_clk_peric1_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &peric1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
+        exynos7_clk_peric1_init);
+
+/* Register Offset definitions for CMU_PERIS (0x10040000) */
+#define MUX_SEL_PERIS                   0x0200
+#define ENABLE_PCLK_PERIS               0x0900
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
+#define ENABLE_SCLK_PERIS               0x0A00
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
+
+/* List of parent clocks for Muxes in CMU_PERIS */
+PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
+
+static unsigned long peris_clk_regs[] __initdata = {
+        MUX_SEL_PERIS,
+        ENABLE_PCLK_PERIS,
+        ENABLE_PCLK_PERIS_SECURE_CHIPID,
+        ENABLE_SCLK_PERIS,
+        ENABLE_SCLK_PERIS_SECURE_CHIPID,
+};
+
+static struct samsung_mux_clock peris_mux_clks[] __initdata = {
+        MUX(0, "mout_aclk_peris_66_user",
+                mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
+};
+
+static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+        GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
+                ENABLE_PCLK_PERIS, 6, 0, 0),
+        GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
+                ENABLE_PCLK_PERIS, 10, 0, 0),
+
+        GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
+                ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+        GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
+                ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+        GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
+};
+
+static struct samsung_cmu_info peris_cmu_info __initdata = {
+        .mux_clks               = peris_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(peris_mux_clks),
+        .gate_clks              = peris_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
+        .nr_clk_ids             = PERIS_NR_CLK,
+        .clk_regs               = peris_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
+};
+
+static void __init exynos7_clk_peris_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &peris_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
+        exynos7_clk_peris_init);
+
+/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
+#define MUX_SEL_FSYS00                  0x0200
+#define MUX_SEL_FSYS01                  0x0204
+#define ENABLE_ACLK_FSYS01              0x0804
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS0
+ */
+PNAME(mout_aclk_fsys0_200_p)    = { "fin_pll", "dout_aclk_fsys0_200" };
+PNAME(mout_sclk_mmc2_p)         = { "fin_pll", "sclk_mmc2" };
+
+static unsigned long fsys0_clk_regs[] __initdata = {
+        MUX_SEL_FSYS00,
+        MUX_SEL_FSYS01,
+        ENABLE_ACLK_FSYS01,
+};
+
+static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
+        MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
+                MUX_SEL_FSYS00, 24, 1),
+
+        MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
+};
+
+static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
+        GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
+                ENABLE_ACLK_FSYS01, 31, 0, 0),
+};
+
+static struct samsung_cmu_info fsys0_cmu_info __initdata = {
+        .mux_clks               = fsys0_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(fsys0_mux_clks),
+        .gate_clks              = fsys0_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(fsys0_gate_clks),
+        .nr_clk_ids             = TOP1_NR_CLK,
+        .clk_regs               = fsys0_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(fsys0_clk_regs),
+};
+
+static void __init exynos7_clk_fsys0_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &fsys0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
+        exynos7_clk_fsys0_init);
+
+/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
+#define MUX_SEL_FSYS10                  0x0200
+#define MUX_SEL_FSYS11                  0x0204
+#define ENABLE_ACLK_FSYS1               0x0800
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS1
+ */
+PNAME(mout_aclk_fsys1_200_p)    = { "fin_pll",  "dout_aclk_fsys1_200" };
+PNAME(mout_sclk_mmc0_p)         = { "fin_pll", "sclk_mmc0" };
+PNAME(mout_sclk_mmc1_p)         = { "fin_pll", "sclk_mmc1" };
+
+static unsigned long fsys1_clk_regs[] __initdata = {
+        MUX_SEL_FSYS10,
+        MUX_SEL_FSYS11,
+        ENABLE_ACLK_FSYS1,
+};
+
+static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
+        MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
+                MUX_SEL_FSYS10, 28, 1),
+
+        MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
+        MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
+};
+
+static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
+        GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
+                ENABLE_ACLK_FSYS1, 29, 0, 0),
+        GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
+                ENABLE_ACLK_FSYS1, 30, 0, 0),
+};
+
+static struct samsung_cmu_info fsys1_cmu_info __initdata = {
+        .mux_clks               = fsys1_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(fsys1_mux_clks),
+        .gate_clks              = fsys1_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(fsys1_gate_clks),
+        .nr_clk_ids             = TOP1_NR_CLK,
+        .clk_regs               = fsys1_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(fsys1_clk_regs),
+};
+
+static void __init exynos7_clk_fsys1_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &fsys1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
+        exynos7_clk_fsys1_init);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b07fad2a9167..9d70e5c03804 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
 
 #define PLL46XX_VSEL_MASK       (1)
 #define PLL46XX_MDIV_MASK       (0x1FF)
+#define PLL1460X_MDIV_MASK      (0x3FF)
+
 #define PLL46XX_PDIV_MASK       (0x3F)
 #define PLL46XX_SDIV_MASK       (0x7)
 #define PLL46XX_VSEL_SHIFT      (27)
@@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
 
         pll_con0 = __raw_readl(pll->con_reg);
         pll_con1 = __raw_readl(pll->con_reg + 4);
-        mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+        mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
+                                PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
         pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
         sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
         kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
                                         pll_con1 & PLL46XX_KDIV_MASK;
 
-        shift = pll->type == pll_4600 ? 16 : 10;
+        shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
+
         fvco *= (mdiv << shift) + kdiv;
         do_div(fvco, (pdiv << sdiv));
         fvco >>= shift;
@@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
                 lock = 0xffff;
 
         /* Set PLL PMS and VSEL values. */
-        con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+        if (pll->type == pll_1460x) {
+                con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+                        (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
+                        (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
+        } else {
+                con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
                         (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
                         (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
                         (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
+                con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
+        }
+
         con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
                         (rate->pdiv << PLL46XX_PDIV_SHIFT) |
-                        (rate->sdiv << PLL46XX_SDIV_SHIFT) |
-                        (rate->vsel << PLL46XX_VSEL_SHIFT);
+                        (rate->sdiv << PLL46XX_SDIV_SHIFT);
 
         /* Set PLL K, MFR and MRR values. */
         con1 = __raw_readl(pll->con_reg + 0x4);
@@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
         /* clk_ops for 35xx and 2550 are similar */
         case pll_35xx:
         case pll_2550:
+        case pll_1450x:
+        case pll_1451x:
+        case pll_1452x:
                 if (!pll->rate_table)
                         init.ops = &samsung_pll35xx_clk_min_ops;
                 else
@@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
         case pll_4600:
         case pll_4650:
         case pll_4650c:
+        case pll_1460x:
                 if (!pll->rate_table)
                         init.ops = &samsung_pll46xx_clk_min_ops;
                 else
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index c0ed4d41fd90..213de9af8b4f 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -33,6 +33,10 @@ enum samsung_pll_type {
         pll_s3c2440_mpll,
         pll_2550xx,
         pll_2650xx,
+        pll_1450x,
+        pll_1451x,
+        pll_1452x,
+        pll_1460x,
 };
 
 #define PLL_35XX_RATE(_rate, _m, _p, _s)                        \
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index deab84d9f37d..4bda54095a16 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -11,9 +11,13 @@
  * clock framework for Samsung platforms.
 */
 
+#include <linux/of_address.h>
 #include <linux/syscore_ops.h>
+
 #include "clk.h"
 
+static LIST_HEAD(clock_reg_cache_list);
+
 void samsung_clk_save(void __iomem *base,
                                     struct samsung_clk_reg_dump *rd,
                                     unsigned int num_regs)
@@ -281,7 +285,6 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
  * obtain the clock speed of all external fixed clock sources from device
  * tree and register it
  */
-#ifdef CONFIG_OF
 void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
                         struct samsung_fixed_rate_clock *fixed_rate_clk,
                         unsigned int nr_fixed_rate_clk,
@@ -298,7 +301,6 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
         }
         samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
 }
-#endif
 
 /* utility function to get the rate of a specified clock */
 unsigned long _get_rate(const char *clk_name)
@@ -313,3 +315,99 @@ unsigned long _get_rate(const char *clk_name)
 
         return clk_get_rate(clk);
 }
+
+#ifdef CONFIG_PM_SLEEP
+static int samsung_clk_suspend(void)
+{
+        struct samsung_clock_reg_cache *reg_cache;
+
+        list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
+                samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
+                                reg_cache->rd_num);
+        return 0;
+}
+
+static void samsung_clk_resume(void)
+{
+        struct samsung_clock_reg_cache *reg_cache;
+
+        list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
+                samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump,
+                                reg_cache->rd_num);
+}
+
+static struct syscore_ops samsung_clk_syscore_ops = {
+        .suspend = samsung_clk_suspend,
+        .resume = samsung_clk_resume,
+};
+
+static void samsung_clk_sleep_init(void __iomem *reg_base,
+                const unsigned long *rdump,
+                unsigned long nr_rdump)
+{
+        struct samsung_clock_reg_cache *reg_cache;
+
+        reg_cache = kzalloc(sizeof(struct samsung_clock_reg_cache),
+                        GFP_KERNEL);
+        if (!reg_cache)
+                panic("could not allocate register reg_cache.\n");
+        reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
+
+        if (!reg_cache->rdump)
+                panic("could not allocate register dump storage.\n");
+
+        if (list_empty(&clock_reg_cache_list))
+                register_syscore_ops(&samsung_clk_syscore_ops);
+
+        reg_cache->reg_base = reg_base;
+        reg_cache->rd_num = nr_rdump;
+        list_add_tail(&reg_cache->node, &clock_reg_cache_list);
+}
+
+#else
+static void samsung_clk_sleep_init(void __iomem *reg_base,
+                const unsigned long *rdump,
+                unsigned long nr_rdump) {}
+#endif
+
+/*
+ * Common function which registers plls, muxes, dividers and gates
+ * for each CMU. It also add CMU register list to register cache.
+ */
+void __init samsung_cmu_register_one(struct device_node *np,
+                        struct samsung_cmu_info *cmu)
+{
+        void __iomem *reg_base;
+        struct samsung_clk_provider *ctx;
+
+        reg_base = of_iomap(np, 0);
+        if (!reg_base)
+                panic("%s: failed to map registers\n", __func__);
+
+        ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
+        if (!ctx)
+                panic("%s: unable to alllocate ctx\n", __func__);
+
+        if (cmu->pll_clks)
+                samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
+                        reg_base);
+        if (cmu->mux_clks)
+                samsung_clk_register_mux(ctx, cmu->mux_clks,
+                        cmu->nr_mux_clks);
+        if (cmu->div_clks)
+                samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
+        if (cmu->gate_clks)
+                samsung_clk_register_gate(ctx, cmu->gate_clks,
+                        cmu->nr_gate_clks);
+        if (cmu->fixed_clks)
+                samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
+                        cmu->nr_fixed_clks);
+        if (cmu->fixed_factor_clks)
+                samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
+                        cmu->nr_fixed_factor_clks);
+        if (cmu->clk_regs)
+                samsung_clk_sleep_init(reg_base, cmu->clk_regs,
+                        cmu->nr_clk_regs);
+
+        samsung_clk_of_add_provider(np, ctx);
+}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 66ab36b5cef1..8acabe1f32c4 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -13,19 +13,15 @@
 #ifndef __SAMSUNG_CLK_H
 #define __SAMSUNG_CLK_H
 
-#include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/io.h>
 #include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
 #include "clk-pll.h"
 
 /**
  * struct samsung_clk_provider: information about clock provider
  * @reg_base: virtual address for the register base.
  * @clk_data: holds clock related data like clk* and number of clocks.
- * @lock: maintains exclusion bwtween callbacks for a given clock-provider.
+ * @lock: maintains exclusion between callbacks for a given clock-provider.
  */
 struct samsung_clk_provider {
         void __iomem *reg_base;
@@ -324,6 +320,40 @@ struct samsung_pll_clock {
         __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,     \
                 _lock, _con, _rtable, _alias)
 
+struct samsung_clock_reg_cache {
+        struct list_head node;
+        void __iomem *reg_base;
+        struct samsung_clk_reg_dump *rdump;
+        unsigned int rd_num;
+};
+
+struct samsung_cmu_info {
+        /* list of pll clocks and respective count */
+        struct samsung_pll_clock *pll_clks;
+        unsigned int nr_pll_clks;
+        /* list of mux clocks and respective count */
+        struct samsung_mux_clock *mux_clks;
+        unsigned int nr_mux_clks;
+        /* list of div clocks and respective count */
+        struct samsung_div_clock *div_clks;
+        unsigned int nr_div_clks;
+        /* list of gate clocks and respective count */
+        struct samsung_gate_clock *gate_clks;
+        unsigned int nr_gate_clks;
+        /* list of fixed clocks and respective count */
+        struct samsung_fixed_rate_clock *fixed_clks;
+        unsigned int nr_fixed_clks;
+        /* list of fixed factor clocks and respective count */
+        struct samsung_fixed_factor_clock *fixed_factor_clks;
+        unsigned int nr_fixed_factor_clks;
+        /* total number of clocks with IDs assigned*/
+        unsigned int nr_clk_ids;
+
+        /* list and number of clocks registers */
+        unsigned long *clk_regs;
+        unsigned int nr_clk_regs;
+};
+
 extern struct samsung_clk_provider *__init samsung_clk_init(
                         struct device_node *np, void __iomem *base,
                         unsigned long nr_clks);
@@ -362,6 +392,9 @@ extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
                         struct samsung_pll_clock *pll_list,
                         unsigned int nr_clk, void __iomem *base);
 
+extern void __init samsung_cmu_register_one(struct device_node *,
+                        struct samsung_cmu_info *);
+
 extern unsigned long _get_rate(const char *clk_name);
 
 extern void samsung_clk_save(void __iomem *base,
diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c
index f065f694cb65..639241e31e03 100644
--- a/drivers/clk/shmobile/clk-div6.c
+++ b/drivers/clk/shmobile/clk-div6.c
@@ -32,6 +32,9 @@ struct div6_clock {
         struct clk_hw hw;
         void __iomem *reg;
         unsigned int div;
+        u32 src_shift;
+        u32 src_width;
+        u8 *parents;
 };
 
 #define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
@@ -39,8 +42,11 @@ struct div6_clock {
 static int cpg_div6_clock_enable(struct clk_hw *hw)
 {
         struct div6_clock *clock = to_div6_clock(hw);
+        u32 val;
 
-        clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
+        val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
+            | CPG_DIV6_DIV(clock->div - 1);
+        clk_writel(val, clock->reg);
 
         return 0;
 }
@@ -52,7 +58,7 @@ static void cpg_div6_clock_disable(struct clk_hw *hw)
         /* DIV6 clocks require the divisor field to be non-zero when stopping
          * the clock.
          */
-        clk_writel(CPG_DIV6_CKSTP | CPG_DIV6_DIV(CPG_DIV6_DIV_MASK),
+        clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK,
                    clock->reg);
 }
 
@@ -94,12 +100,53 @@ static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
 {
         struct div6_clock *clock = to_div6_clock(hw);
         unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
+        u32 val;
 
         clock->div = div;
 
+        val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
         /* Only program the new divisor if the clock isn't stopped. */
-        if (!(clk_readl(clock->reg) & CPG_DIV6_CKSTP))
-                clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
+        if (!(val & CPG_DIV6_CKSTP))
+                clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
+
+        return 0;
+}
+
+static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
+{
+        struct div6_clock *clock = to_div6_clock(hw);
+        unsigned int i;
+        u8 hw_index;
+
+        if (clock->src_width == 0)
+                return 0;
+
+        hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
+                   (BIT(clock->src_width) - 1);
+        for (i = 0; i < __clk_get_num_parents(hw->clk); i++) {
+                if (clock->parents[i] == hw_index)
+                        return i;
+        }
+
+        pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
+               __func__, __clk_get_name(hw->clk), hw_index);
+        return 0;
+}
+
+static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct div6_clock *clock = to_div6_clock(hw);
+        u8 hw_index;
+        u32 mask;
+
+        if (index >= __clk_get_num_parents(hw->clk))
+                return -EINVAL;
+
+        mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
+        hw_index = clock->parents[index];
+
+        clk_writel((clk_readl(clock->reg) & mask) |
+                (hw_index << clock->src_shift), clock->reg);
 
         return 0;
 }
@@ -108,6 +155,8 @@ static const struct clk_ops cpg_div6_clock_ops = {
         .enable = cpg_div6_clock_enable,
         .disable = cpg_div6_clock_disable,
         .is_enabled = cpg_div6_clock_is_enabled,
+        .get_parent = cpg_div6_clock_get_parent,
+        .set_parent = cpg_div6_clock_set_parent,
         .recalc_rate = cpg_div6_clock_recalc_rate,
         .round_rate = cpg_div6_clock_round_rate,
         .set_rate = cpg_div6_clock_set_rate,
@@ -115,20 +164,33 @@ static const struct clk_ops cpg_div6_clock_ops = {
 
 static void __init cpg_div6_clock_init(struct device_node *np)
 {
+        unsigned int num_parents, valid_parents;
+        const char **parent_names;
         struct clk_init_data init;
         struct div6_clock *clock;
-        const char *parent_name;
         const char *name;
         struct clk *clk;
+        unsigned int i;
         int ret;
 
         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
-        if (!clock) {
-                pr_err("%s: failed to allocate %s DIV6 clock\n",
+        if (!clock)
+                return;
+
+        num_parents = of_clk_get_parent_count(np);
+        if (num_parents < 1) {
+                pr_err("%s: no parent found for %s DIV6 clock\n",
                        __func__, np->name);
                 return;
         }
 
+        clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
+                GFP_KERNEL);
+        parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
+                                GFP_KERNEL);
+        if (!parent_names)
+                return;
+
         /* Remap the clock register and read the divisor. Disabling the
          * clock overwrites the divisor, so we need to cache its value for the
          * enable operation.
@@ -150,9 +212,34 @@ static void __init cpg_div6_clock_init(struct device_node *np)
                 goto error;
         }
 
-        parent_name = of_clk_get_parent_name(np, 0);
-        if (parent_name == NULL) {
-                pr_err("%s: failed to get %s DIV6 clock parent name\n",
+
+        for (i = 0, valid_parents = 0; i < num_parents; i++) {
+                const char *name = of_clk_get_parent_name(np, i);
+
+                if (name) {
+                        parent_names[valid_parents] = name;
+                        clock->parents[valid_parents] = i;
+                        valid_parents++;
+                }
+        }
+
+        switch (num_parents) {
+        case 1:
+                /* fixed parent clock */
+                clock->src_shift = clock->src_width = 0;
+                break;
+        case 4:
+                /* clock with EXSRC bits 6-7 */
+                clock->src_shift = 6;
+                clock->src_width = 2;
+                break;
+        case 8:
+                /* VCLK with EXSRC bits 12-14 */
+                clock->src_shift = 12;
+                clock->src_width = 3;
+                break;
+        default:
+                pr_err("%s: invalid number of parents for DIV6 clock %s\n",
                        __func__, np->name);
                 goto error;
         }
@@ -161,8 +248,8 @@ static void __init cpg_div6_clock_init(struct device_node *np)
         init.name = name;
         init.ops = &cpg_div6_clock_ops;
         init.flags = CLK_IS_BASIC;
-        init.parent_names = &parent_name;
-        init.num_parents = 1;
+        init.parent_names = parent_names;
+        init.num_parents = valid_parents;
 
         clock->hw.init = &init;
 
@@ -175,11 +262,13 @@ static void __init cpg_div6_clock_init(struct device_node *np)
 
         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 
+        kfree(parent_names);
         return;
 
 error:
         if (clock->reg)
                 iounmap(clock->reg);
+        kfree(parent_names);
         kfree(clock);
 }
 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 7ddc2b553846..a66953c0f430 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -7,6 +7,7 @@ obj-y += clk-a10-hosc.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-sun8i-mbus.o
+obj-y += clk-sun9i-core.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
         clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
diff --git a/drivers/clk/sunxi/clk-a20-gmac.c b/drivers/clk/sunxi/clk-a20-gmac.c
index 5296fd6dd7b3..0dcf4f205fb8 100644
--- a/drivers/clk/sunxi/clk-a20-gmac.c
+++ b/drivers/clk/sunxi/clk-a20-gmac.c
@@ -53,6 +53,11 @@ static DEFINE_SPINLOCK(gmac_lock);
 #define SUN7I_A20_GMAC_MASK     0x3
 #define SUN7I_A20_GMAC_PARENTS  2
 
+static u32 sun7i_a20_gmac_mux_table[SUN7I_A20_GMAC_PARENTS] = {
+        0x00, /* Select mii_phy_tx_clk */
+        0x02, /* Select gmac_int_tx_clk */
+};
+
 static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
 {
         struct clk *clk;
@@ -90,7 +95,7 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
         gate->lock = &gmac_lock;
         mux->reg = reg;
         mux->mask = SUN7I_A20_GMAC_MASK;
-        mux->flags = CLK_MUX_INDEX_BIT;
+        mux->table = sun7i_a20_gmac_mux_table;
         mux->lock = &gmac_lock;
 
         clk = clk_register_composite(NULL, clk_name,
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index f83ba097126c..62e08fb58554 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -81,7 +81,7 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
 
 static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_p)
+                                       struct clk_hw **best_parent_p)
 {
         struct clk *clk = hw->clk, *parent, *best_parent = NULL;
         int i, num_parents;
@@ -108,7 +108,7 @@ static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
         }
 
         if (best_parent)
-                *best_parent_p = best_parent;
+                *best_parent_p = __clk_get_hw(best_parent);
         *best_parent_rate = best;
 
         return best_child_rate;
@@ -224,7 +224,7 @@ struct clk * __init sunxi_factors_register(struct device_node *node,
                 /* set up gate properties */
                 mux->reg = reg;
                 mux->shift = data->mux;
-                mux->mask = SUNXI_FACTORS_MUX_MASK;
+                mux->mask = data->muxmask;
                 mux->lock = factors->lock;
                 mux_hw = &mux->hw;
         }
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index 9913840018d3..912238fde132 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -7,8 +7,6 @@
 
 #define SUNXI_FACTORS_NOT_APPLICABLE    (0)
 
-#define SUNXI_FACTORS_MUX_MASK 0x3
-
 struct clk_factors_config {
         u8 nshift;
         u8 nwidth;
@@ -24,6 +22,7 @@ struct clk_factors_config {
 struct factors_data {
         int enable;
         int mux;
+        int muxmask;
         struct clk_factors_config *table;
         void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
         const char *name;
diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index 4a563850ee6e..da0524eaee94 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -70,6 +70,7 @@ static struct clk_factors_config sun4i_a10_mod0_config = {
 static const struct factors_data sun4i_a10_mod0_data __initconst = {
         .enable = 31,
         .mux = 24,
+        .muxmask = BIT(1) | BIT(0),
         .table = &sun4i_a10_mod0_config,
         .getter = sun4i_a10_get_mod0_factors,
 };
diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c
index acca53290be2..3d282fb8f85c 100644
--- a/drivers/clk/sunxi/clk-sun6i-ar100.c
+++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
@@ -46,7 +46,7 @@ static unsigned long ar100_recalc_rate(struct clk_hw *hw,
 
 static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate,
                                  unsigned long *best_parent_rate,
-                                 struct clk **best_parent_clk)
+                                 struct clk_hw **best_parent_clk)
 {
         int nparents = __clk_get_num_parents(hw->clk);
         long best_rate = -EINVAL;
@@ -100,7 +100,7 @@ static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate,
 
                 tmp_rate = (parent_rate >> shift) / div;
                 if (!*best_parent_clk || tmp_rate > best_rate) {
-                        *best_parent_clk = parent;
+                        *best_parent_clk = __clk_get_hw(parent);
                         *best_parent_rate = parent_rate;
                         best_rate = tmp_rate;
                 }
diff --git a/drivers/clk/sunxi/clk-sun8i-mbus.c b/drivers/clk/sunxi/clk-sun8i-mbus.c
index 8e49b44cee41..ef49786eefd3 100644
--- a/drivers/clk/sunxi/clk-sun8i-mbus.c
+++ b/drivers/clk/sunxi/clk-sun8i-mbus.c
@@ -60,6 +60,7 @@ static struct clk_factors_config sun8i_a23_mbus_config = {
 static const struct factors_data sun8i_a23_mbus_data __initconst = {
         .enable = 31,
         .mux = 24,
+        .muxmask = BIT(1) | BIT(0),
         .table = &sun8i_a23_mbus_config,
         .getter = sun8i_a23_get_mbus_factors,
 };
diff --git a/drivers/clk/sunxi/clk-sun9i-core.c b/drivers/clk/sunxi/clk-sun9i-core.c
new file mode 100644
index 000000000000..3cb9036d91bb
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun9i-core.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/log2.h>
+
+#include "clk-factors.h"
+
+
+/**
+ * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL1
+ * PLL4 rate is calculated as follows
+ * rate = (parent_rate * n >> p) / (m + 1);
+ * parent_rate is always 24Mhz
+ *
+ * p and m are named div1 and div2 in Allwinner's SDK
+ */
+
+static void sun9i_a80_get_pll4_factors(u32 *freq, u32 parent_rate,
+                                       u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        int div;
+
+        /* Normalize value to a 6M multiple */
+        div = DIV_ROUND_UP(*freq, 6000000);
+
+        /* divs above 256 cannot be odd */
+        if (div > 256)
+                div = round_up(div, 2);
+
+        /* divs above 512 must be a multiple of 4 */
+        if (div > 512)
+                div = round_up(div, 4);
+
+        *freq = 6000000 * div;
+
+        /* we were called to round the frequency, we can now return */
+        if (n == NULL)
+                return;
+
+        /* p will be 1 for divs under 512 */
+        if (div < 512)
+                *p = 1;
+        else
+                *p = 0;
+
+        /* m will be 1 if div is odd */
+        if (div & 1)
+                *m = 1;
+        else
+                *m = 0;
+
+        /* calculate a suitable n based on m and p */
+        *n = div / (*p + 1) / (*m + 1);
+}
+
+static struct clk_factors_config sun9i_a80_pll4_config = {
+        .mshift = 18,
+        .mwidth = 1,
+        .nshift = 8,
+        .nwidth = 8,
+        .pshift = 16,
+        .pwidth = 1,
+};
+
+static const struct factors_data sun9i_a80_pll4_data __initconst = {
+        .enable = 31,
+        .table = &sun9i_a80_pll4_config,
+        .getter = sun9i_a80_get_pll4_factors,
+};
+
+static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
+
+static void __init sun9i_a80_pll4_setup(struct device_node *node)
+{
+        sunxi_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
+
+
+/**
+ * sun9i_a80_get_gt_factors() - calculates m factor for GT
+ * GT rate is calculated as follows
+ * rate = parent_rate / (m + 1);
+ */
+
+static void sun9i_a80_get_gt_factors(u32 *freq, u32 parent_rate,
+                                     u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        u32 div;
+
+        if (parent_rate < *freq)
+                *freq = parent_rate;
+
+        div = DIV_ROUND_UP(parent_rate, *freq);
+
+        /* maximum divider is 4 */
+        if (div > 4)
+                div = 4;
+
+        *freq = parent_rate / div;
+
+        /* we were called to round the frequency, we can now return */
+        if (!m)
+                return;
+
+        *m = div;
+}
+
+static struct clk_factors_config sun9i_a80_gt_config = {
+        .mshift = 0,
+        .mwidth = 2,
+};
+
+static const struct factors_data sun9i_a80_gt_data __initconst = {
+        .mux = 24,
+        .muxmask = BIT(1) | BIT(0),
+        .table = &sun9i_a80_gt_config,
+        .getter = sun9i_a80_get_gt_factors,
+};
+
+static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
+
+static void __init sun9i_a80_gt_setup(struct device_node *node)
+{
+        struct clk *gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
+                                                &sun9i_a80_gt_lock);
+
+        /* The GT bus clock needs to be always enabled */
+        __clk_get(gt);
+        clk_prepare_enable(gt);
+}
+CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
+
+
+/**
+ * sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2
+ * AHB rate is calculated as follows
+ * rate = parent_rate >> p;
+ */
+
+static void sun9i_a80_get_ahb_factors(u32 *freq, u32 parent_rate,
+                                      u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        u32 _p;
+
+        if (parent_rate < *freq)
+                *freq = parent_rate;
+
+        _p = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
+
+        /* maximum p is 3 */
+        if (_p > 3)
+                _p = 3;
+
+        *freq = parent_rate >> _p;
+
+        /* we were called to round the frequency, we can now return */
+        if (!p)
+                return;
+
+        *p = _p;
+}
+
+static struct clk_factors_config sun9i_a80_ahb_config = {
+        .pshift = 0,
+        .pwidth = 2,
+};
+
+static const struct factors_data sun9i_a80_ahb_data __initconst = {
+        .mux = 24,
+        .muxmask = BIT(1) | BIT(0),
+        .table = &sun9i_a80_ahb_config,
+        .getter = sun9i_a80_get_ahb_factors,
+};
+
+static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
+
+static void __init sun9i_a80_ahb_setup(struct device_node *node)
+{
+        sunxi_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);
+
+
+static const struct factors_data sun9i_a80_apb0_data __initconst = {
+        .mux = 24,
+        .muxmask = BIT(0),
+        .table = &sun9i_a80_ahb_config,
+        .getter = sun9i_a80_get_ahb_factors,
+};
+
+static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
+
+static void __init sun9i_a80_apb0_setup(struct device_node *node)
+{
+        sunxi_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
+
+
+/**
+ * sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1
+ * APB1 rate is calculated as follows
+ * rate = (parent_rate >> p) / (m + 1);
+ */
+
+static void sun9i_a80_get_apb1_factors(u32 *freq, u32 parent_rate,
+                                       u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        u32 div;
+        u8 calcm, calcp;
+
+        if (parent_rate < *freq)
+                *freq = parent_rate;
+
+        div = DIV_ROUND_UP(parent_rate, *freq);
+
+        /* Highest possible divider is 256 (p = 3, m = 31) */
+        if (div > 256)
+                div = 256;
+
+        calcp = order_base_2(div);
+        calcm = (parent_rate >> calcp) - 1;
+        *freq = (parent_rate >> calcp) / (calcm + 1);
+
+        /* we were called to round the frequency, we can now return */
+        if (n == NULL)
+                return;
+
+        *m = calcm;
+        *p = calcp;
+}
+
+static struct clk_factors_config sun9i_a80_apb1_config = {
+        .mshift = 0,
+        .mwidth = 5,
+        .pshift = 16,
+        .pwidth = 2,
+};
+
+static const struct factors_data sun9i_a80_apb1_data __initconst = {
+        .mux = 24,
+        .muxmask = BIT(0),
+        .table = &sun9i_a80_apb1_config,
+        .getter = sun9i_a80_get_apb1_factors,
+};
+
+static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
+
+static void __init sun9i_a80_apb1_setup(struct device_node *node)
+{
+        sunxi_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index d5dc951264ca..570202582dcf 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -245,9 +245,9 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
 }
 
 /**
- * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
- * PLL6 rate is calculated as follows
- * rate = parent_rate * n * (k + 1) / 2
+ * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
+ * PLL6x2 rate is calculated as follows
+ * rate = parent_rate * (n + 1) * (k + 1)
  * parent_rate is always 24Mhz
  */
 
@@ -256,13 +256,7 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
 {
         u8 div;
 
-        /*
-         * We always have 24MHz / 2, so we can just say that our
-         * parent clock is 12MHz.
-         */
-        parent_rate = parent_rate / 2;
-
-        /* Normalize value to a parent_rate multiple (24M / 2) */
+        /* Normalize value to a parent_rate multiple (24M) */
         div = *freq / parent_rate;
         *freq = parent_rate * div;
 
@@ -274,7 +268,7 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
         if (*k > 3)
                 *k = 3;
 
-        *n = DIV_ROUND_UP(div, (*k+1));
+        *n = DIV_ROUND_UP(div, (*k+1)) - 1;
 }
 
 /**
@@ -445,6 +439,7 @@ static struct clk_factors_config sun6i_a31_pll6_config = {
         .nwidth = 5,
         .kshift = 4,
         .kwidth = 2,
+        .n_start = 1,
 };
 
 static struct clk_factors_config sun4i_apb1_config = {
@@ -504,9 +499,12 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
         .enable = 31,
         .table = &sun6i_a31_pll6_config,
         .getter = sun6i_a31_get_pll6_factors,
+        .name = "pll6x2",
 };
 
 static const struct factors_data sun4i_apb1_data __initconst = {
+        .mux = 24,
+        .muxmask = BIT(1) | BIT(0),
         .table = &sun4i_apb1_config,
         .getter = sun4i_get_apb1_factors,
 };
@@ -514,6 +512,7 @@ static const struct factors_data sun4i_apb1_data __initconst = {
 static const struct factors_data sun7i_a20_out_data __initconst = {
         .enable = 31,
         .mux = 24,
+        .muxmask = BIT(1) | BIT(0),
         .table = &sun7i_a20_out_config,
         .getter = sun7i_a20_get_out_factors,
 };
@@ -544,10 +543,6 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
         .shift = 12,
 };
 
-static const struct mux_data sun4i_apb1_mux_data __initconst = {
-        .shift = 24,
-};
-
 static void __init sunxi_mux_clk_setup(struct device_node *node,
                                        struct mux_data *data)
 {
@@ -633,12 +628,6 @@ static const struct div_data sun4i_apb0_data __initconst = {
         .table  = sun4i_apb0_table,
 };
 
-static const struct div_data sun6i_a31_apb2_div_data __initconst = {
-        .shift  = 0,
-        .pow    = 0,
-        .width  = 4,
-};
-
 static void __init sunxi_divider_clk_setup(struct device_node *node,
                                            struct div_data *data)
 {
@@ -757,6 +746,18 @@ static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
         .mask = {0x25386742, 0x2505111},
 };
 
+static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
+        .mask = {0xF5F12B},
+};
+
+static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
+        .mask = {0x1E20003},
+};
+
+static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
+        .mask = {0x9B7},
+};
+
 static const struct gates_data sun4i_apb0_gates_data __initconst = {
         .mask = {0x4EF},
 };
@@ -773,6 +774,10 @@ static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
         .mask = { 0x4ff },
 };
 
+static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
+        .mask = {0xEB822},
+};
+
 static const struct gates_data sun4i_apb1_gates_data __initconst = {
         .mask = {0xFF00F7},
 };
@@ -801,6 +806,10 @@ static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
         .mask = { 0xff80ff },
 };
 
+static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
+        .mask = {0x3F001F},
+};
+
 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
         .mask = {0x1F0007},
 };
@@ -893,6 +902,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
 
 struct divs_data {
         const struct factors_data *factors; /* data for the factor clock */
+        int ndivs; /* number of children */
         struct {
                 u8 fixed; /* is it a fixed divisor? if not... */
                 struct clk_div_table *table; /* is it a table based divisor? */
@@ -912,6 +922,7 @@ static struct clk_div_table pll6_sata_tbl[] = {
 
 static const struct divs_data pll5_divs_data __initconst = {
         .factors = &sun4i_pll5_data,
+        .ndivs = 2,
         .div = {
                 { .shift = 0, .pow = 0, }, /* M, DDR */
                 { .shift = 16, .pow = 1, }, /* P, other */
@@ -920,12 +931,21 @@ static const struct divs_data pll5_divs_data __initconst = {
 
 static const struct divs_data pll6_divs_data __initconst = {
         .factors = &sun4i_pll6_data,
+        .ndivs = 2,
         .div = {
                 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
                 { .fixed = 2 }, /* P, other */
         }
 };
 
+static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
+        .factors = &sun6i_a31_pll6_data,
+        .ndivs = 1,
+        .div = {
+                { .fixed = 2 }, /* normal output */
+        }
+};
+
 /**
  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
  *
@@ -950,7 +970,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
         struct clk_fixed_factor *fix_factor;
         struct clk_divider *divider;
         void __iomem *reg;
-        int i = 0;
+        int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
         int flags, clkflags;
 
         /* Set up factor clock that we will be dividing */
@@ -973,7 +993,11 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
          * our RAM clock! */
         clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
 
-        for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
+        /* if number of children known, use it */
+        if (data->ndivs)
+                ndivs = data->ndivs;
+
+        for (i = 0; i < ndivs; i++) {
                 if (of_property_read_string_index(node, "clock-output-names",
                                                   i, &clk_name) != 0)
                         break;
@@ -1062,7 +1086,6 @@ static const struct of_device_id clk_factors_match[] __initconst = {
         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
         {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
         {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
-        {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
         {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
         {}
@@ -1074,7 +1097,6 @@ static const struct of_device_id clk_div_match[] __initconst = {
         {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
         {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
         {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
-        {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
         {}
 };
 
@@ -1082,13 +1104,13 @@ static const struct of_device_id clk_div_match[] __initconst = {
 static const struct of_device_id clk_divs_match[] __initconst = {
         {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
         {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
+        {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
         {}
 };
 
 /* Matches for mux clocks */
 static const struct of_device_id clk_mux_match[] __initconst = {
         {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
-        {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
         {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
         {}
 };
@@ -1102,16 +1124,21 @@ static const struct of_device_id clk_gates_match[] __initconst = {
         {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
         {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
         {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
+        {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
+        {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
+        {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
         {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
         {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
         {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
         {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
+        {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
         {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
         {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
         {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
         {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
         {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
+        {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
         {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
         {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
         {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
@@ -1200,3 +1227,9 @@ static void __init sun6i_init_clocks(struct device_node *node)
 }
 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
+
+static void __init sun9i_init_clocks(struct device_node *node)
+{
+        sunxi_init_clocks(NULL, 0);
+}
+CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 4f7b275f2f7b..7d4974b83af7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -121,13 +121,9 @@ static int kfd_open(struct inode *inode, struct file *filep)
         if (IS_ERR(process))
                 return PTR_ERR(process);
 
-        process->is_32bit_user_mode = is_32bit_user_mode;
-
         dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
                 process->pasid, process->is_32bit_user_mode);
 
-        kfd_init_apertures(process);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 66df4da01c29..e64aa99e5e41 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -299,13 +299,13 @@ int kfd_init_apertures(struct kfd_process *process)
         struct kfd_dev *dev;
         struct kfd_process_device *pdd;
 
-        mutex_lock(&process->mutex);
-
         /*Iterating over all devices*/
         while ((dev = kfd_topology_enum_kfd_devices(id)) != NULL &&
                 id < NUM_OF_SUPPORTED_GPUS) {
 
                 pdd = kfd_get_process_device_data(dev, process, 1);
+                if (!pdd)
+                        return -1;
 
                 /*
                  * For 64 bit process aperture will be statically reserved in
@@ -348,8 +348,6 @@ int kfd_init_apertures(struct kfd_process *process)
                 id++;
         }
 
-        mutex_unlock(&process->mutex);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index b85eb0b830b4..3c76ef05cbcf 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -26,6 +26,8 @@
 #include <linux/slab.h>
 #include <linux/amd-iommu.h>
 #include <linux/notifier.h>
+#include <linux/compat.h>
+
 struct mm_struct;
 
 #include "kfd_priv.h"
@@ -285,8 +287,15 @@ static struct kfd_process *create_process(const struct task_struct *thread)
         if (err != 0)
                 goto err_process_pqm_init;
 
+        /* init process apertures*/
+        process->is_32bit_user_mode = is_compat_task();
+        if (kfd_init_apertures(process) != 0)
+                goto err_init_apretures;
+
         return process;
 
+err_init_apretures:
+        pqm_uninit(&process->pqm);
 err_process_pqm_init:
         hash_del_rcu(&process->kfd_processes);
         synchronize_rcu();
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 5733e2859e8a..b11792d7e70e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -700,8 +700,6 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
                                 dev->node_props.simd_per_cu);
                 sysfs_show_32bit_prop(buffer, "max_slots_scratch_cu",
                                 dev->node_props.max_slots_scratch_cu);
-                sysfs_show_32bit_prop(buffer, "engine_id",
-                                dev->node_props.engine_id);
                 sysfs_show_32bit_prop(buffer, "vendor_id",
                                 dev->node_props.vendor_id);
                 sysfs_show_32bit_prop(buffer, "device_id",
@@ -715,6 +713,12 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
                                                 dev->gpu->kgd));
                         sysfs_show_64bit_prop(buffer, "local_mem_size",
                                         kfd2kgd->get_vmem_size(dev->gpu->kgd));
+
+                        sysfs_show_32bit_prop(buffer, "fw_version",
+                                        kfd2kgd->get_fw_version(
+                                                        dev->gpu->kgd,
+                                                        KGD_ENGINE_MEC1));
+
                 }
 
                 ret = sysfs_show_32bit_prop(buffer, "max_engine_clk_ccompute",
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 9c729dd8dd50..47b551970a14 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -45,6 +45,17 @@ enum kgd_memory_pool {
         KGD_POOL_FRAMEBUFFER = 3,
 };
 
+enum kgd_engine_type {
+        KGD_ENGINE_PFP = 1,
+        KGD_ENGINE_ME,
+        KGD_ENGINE_CE,
+        KGD_ENGINE_MEC1,
+        KGD_ENGINE_MEC2,
+        KGD_ENGINE_RLC,
+        KGD_ENGINE_SDMA,
+        KGD_ENGINE_MAX
+};
+
 struct kgd2kfd_shared_resources {
         /* Bit n == 1 means VMID n is available for KFD. */
         unsigned int compute_vmid_bitmap;
@@ -137,6 +148,8 @@ struct kgd2kfd_calls {
  *
  * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
  *
+ * @get_fw_version: Returns FW versions from the header
+ *
  * This structure contains function pointers to services that the kgd driver
  * provides to amdkfd driver.
  *
@@ -176,6 +189,8 @@ struct kfd2kgd_calls {
         int (*hqd_destroy)(struct kgd_dev *kgd, uint32_t reset_type,
                                 unsigned int timeout, uint32_t pipe_id,
                                 uint32_t queue_id);
+        uint16_t (*get_fw_version)(struct kgd_dev *kgd,
+                                enum kgd_engine_type type);
 };
 
 bool kgd2kfd_init(unsigned interface_version,
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index 4a78a773151c..bbdbe4721573 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -61,7 +61,7 @@ drm_atomic_helper_plane_changed(struct drm_atomic_state *state,
         struct drm_crtc_state *crtc_state;
 
         if (plane->state->crtc) {
-                crtc_state = state->crtc_states[drm_crtc_index(plane->crtc)];
+                crtc_state = state->crtc_states[drm_crtc_index(plane->state->crtc)];
 
                 if (WARN_ON(!crtc_state))
                         return;
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index f5a5f18efa5b..4d79dad9d44f 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -830,6 +830,8 @@ drm_get_last_vbltimestamp(struct drm_device *dev, int crtc,
  * vblank events since the system was booted, including lost events due to
  * modesetting activity.
  *
+ * This is the legacy version of drm_crtc_vblank_count().
+ *
  * Returns:
  * The software vblank counter.
  */
@@ -844,6 +846,25 @@ u32 drm_vblank_count(struct drm_device *dev, int crtc)
 EXPORT_SYMBOL(drm_vblank_count);
 
 /**
+ * drm_crtc_vblank_count - retrieve "cooked" vblank counter value
+ * @crtc: which counter to retrieve
+ *
+ * Fetches the "cooked" vblank count value that represents the number of
+ * vblank events since the system was booted, including lost events due to
+ * modesetting activity.
+ *
+ * This is the native KMS version of drm_vblank_count().
+ *
+ * Returns:
+ * The software vblank counter.
+ */
+u32 drm_crtc_vblank_count(struct drm_crtc *crtc)
+{
+        return drm_vblank_count(crtc->dev, drm_crtc_index(crtc));
+}
+EXPORT_SYMBOL(drm_crtc_vblank_count);
+
+/**
  * drm_vblank_count_and_time - retrieve "cooked" vblank counter value
  * and the system timestamp corresponding to that vblank counter value.
  *
@@ -904,6 +925,8 @@ static void send_vblank_event(struct drm_device *dev,
  *
  * Updates sequence # and timestamp on event, and sends it to userspace.
  * Caller must hold event lock.
+ *
+ * This is the legacy version of drm_crtc_send_vblank_event().
  */
 void drm_send_vblank_event(struct drm_device *dev, int crtc,
                 struct drm_pending_vblank_event *e)
@@ -923,6 +946,23 @@ void drm_send_vblank_event(struct drm_device *dev, int crtc,
 EXPORT_SYMBOL(drm_send_vblank_event);
 
 /**
+ * drm_crtc_send_vblank_event - helper to send vblank event after pageflip
+ * @crtc: the source CRTC of the vblank event
+ * @e: the event to send
+ *
+ * Updates sequence # and timestamp on event, and sends it to userspace.
+ * Caller must hold event lock.
+ *
+ * This is the native KMS version of drm_send_vblank_event().
+ */
+void drm_crtc_send_vblank_event(struct drm_crtc *crtc,
+                                struct drm_pending_vblank_event *e)
+{
+        drm_send_vblank_event(crtc->dev, drm_crtc_index(crtc), e);
+}
+EXPORT_SYMBOL(drm_crtc_send_vblank_event);
+
+/**
  * drm_vblank_enable - enable the vblank interrupt on a CRTC
  * @dev: DRM device
  * @crtc: CRTC in question
@@ -1594,6 +1634,8 @@ static void drm_handle_vblank_events(struct drm_device *dev, int crtc)
  *
  * Drivers should call this routine in their vblank interrupt handlers to
  * update the vblank counter and send any signals that may be pending.
+ *
+ * This is the legacy version of drm_crtc_handle_vblank().
  */
 bool drm_handle_vblank(struct drm_device *dev, int crtc)
 {
@@ -1670,3 +1712,21 @@ bool drm_handle_vblank(struct drm_device *dev, int crtc)
         return true;
 }
 EXPORT_SYMBOL(drm_handle_vblank);
+
+/**
+ * drm_crtc_handle_vblank - handle a vblank event
+ * @crtc: where this event occurred
+ *
+ * Drivers should call this routine in their vblank interrupt handlers to
+ * update the vblank counter and send any signals that may be pending.
+ *
+ * This is the native KMS version of drm_handle_vblank().
+ *
+ * Returns:
+ * True if the event was successfully handled, false on failure.
+ */
+bool drm_crtc_handle_vblank(struct drm_crtc *crtc)
+{
+        return drm_handle_vblank(crtc->dev, drm_crtc_index(crtc));
+}
+EXPORT_SYMBOL(drm_crtc_handle_vblank);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f990ab4c3efb..574057cd1d09 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -811,6 +811,8 @@ int i915_reset(struct drm_device *dev)
         if (!i915.reset)
                 return 0;
 
+        intel_reset_gt_powersave(dev);
+
         mutex_lock(&dev->struct_mutex);
 
         i915_gem_reset(dev);
@@ -880,7 +882,7 @@ int i915_reset(struct drm_device *dev)
                  * of re-init after reset.
                  */
                 if (INTEL_INFO(dev)->gen > 5)
-                        intel_reset_gt_powersave(dev);
+                        intel_enable_gt_powersave(dev);
         } else {
                 mutex_unlock(&dev->struct_mutex);
         }
@@ -1584,7 +1586,7 @@ static struct drm_driver driver = {
         .gem_prime_import = i915_gem_prime_import,
 
         .dumb_create = i915_gem_dumb_create,
-        .dumb_map_offset = i915_gem_dumb_map_offset,
+        .dumb_map_offset = i915_gem_mmap_gtt,
         .dumb_destroy = drm_gem_dumb_destroy,
         .ioctls = i915_ioctls,
         .fops = &i915_driver_fops,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 63bcda5541ec..70d0f0f06f1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2501,9 +2501,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,
 int i915_gem_dumb_create(struct drm_file *file_priv,
                          struct drm_device *dev,
                          struct drm_mode_create_dumb *args);
-int i915_gem_dumb_map_offset(struct drm_file *file_priv,
-                             struct drm_device *dev, uint32_t handle,
-                             uint64_t *offset);
+int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
+                      uint32_t handle, uint64_t *offset);
 /**
  * Returns true if seq1 is later than seq2.
  */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4a9faea626db..52adcb680be3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -401,7 +401,6 @@ static int
 i915_gem_create(struct drm_file *file,
                 struct drm_device *dev,
                 uint64_t size,
-                bool dumb,
                 uint32_t *handle_p)
 {
         struct drm_i915_gem_object *obj;
@@ -417,7 +416,6 @@ i915_gem_create(struct drm_file *file,
         if (obj == NULL)
                 return -ENOMEM;
 
-        obj->base.dumb = dumb;
         ret = drm_gem_handle_create(file, &obj->base, &handle);
         /* drop reference from allocate - handle holds it now */
         drm_gem_object_unreference_unlocked(&obj->base);
@@ -437,7 +435,7 @@ i915_gem_dumb_create(struct drm_file *file,
         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
         args->size = args->pitch * args->height;
         return i915_gem_create(file, dev,
-                               args->size, true, &args->handle);
+                               args->size, &args->handle);
 }
 
 /**
@@ -450,7 +448,7 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
         struct drm_i915_gem_create *args = data;
 
         return i915_gem_create(file, dev,
-                               args->size, false, &args->handle);
+                               args->size, &args->handle);
 }
 
 static inline int
@@ -1840,10 +1838,10 @@ static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
         drm_gem_free_mmap_offset(&obj->base);
 }
 
-static int
+int
 i915_gem_mmap_gtt(struct drm_file *file,
                   struct drm_device *dev,
-                  uint32_t handle, bool dumb,
+                  uint32_t handle,
                   uint64_t *offset)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1860,13 +1858,6 @@ i915_gem_mmap_gtt(struct drm_file *file,
                 goto unlock;
         }
 
-        /*
-         * We don't allow dumb mmaps on objects created using another
-         * interface.
-         */
-        WARN_ONCE(dumb && !(obj->base.dumb || obj->base.import_attach),
-                  "Illegal dumb map of accelerated buffer.\n");
-
         if (obj->base.size > dev_priv->gtt.mappable_end) {
                 ret = -E2BIG;
                 goto out;
@@ -1891,15 +1882,6 @@ unlock:
         return ret;
 }
 
-int
-i915_gem_dumb_map_offset(struct drm_file *file,
-                         struct drm_device *dev,
-                         uint32_t handle,
-                         uint64_t *offset)
-{
-        return i915_gem_mmap_gtt(file, dev, handle, true, offset);
-}
-
 /**
  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
  * @dev: DRM device
@@ -1921,7 +1903,7 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
 {
         struct drm_i915_gem_mmap_gtt *args = data;
 
-        return i915_gem_mmap_gtt(file, dev, args->handle, false, &args->offset);
+        return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
 }
 
 static inline int
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index d17ff435f276..d011ec82ef1e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -473,7 +473,12 @@ mi_set_context(struct intel_engine_cs *ring,
                u32 hw_flags)
 {
         u32 flags = hw_flags | MI_MM_SPACE_GTT;
-        int ret;
+        const int num_rings =
+                /* Use an extended w/a on ivb+ if signalling from other rings */
+                i915_semaphore_is_enabled(ring->dev) ?
+                hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
+                0;
+        int len, i, ret;
 
         /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
          * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
@@ -490,15 +495,31 @@ mi_set_context(struct intel_engine_cs *ring,
         if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8)
                 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
 
-        ret = intel_ring_begin(ring, 6);
+
+        len = 4;
+        if (INTEL_INFO(ring->dev)->gen >= 7)
+                len += 2 + (num_rings ? 4*num_rings + 2 : 0);
+
+        ret = intel_ring_begin(ring, len);
         if (ret)
                 return ret;
 
         /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
-        if (INTEL_INFO(ring->dev)->gen >= 7)
+        if (INTEL_INFO(ring->dev)->gen >= 7) {
                 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
-        else
-                intel_ring_emit(ring, MI_NOOP);
+                if (num_rings) {
+                        struct intel_engine_cs *signaller;
+
+                        intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
+                        for_each_ring(signaller, to_i915(ring->dev), i) {
+                                if (signaller == ring)
+                                        continue;
+
+                                intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
+                                intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
+                        }
+                }
+        }
 
         intel_ring_emit(ring, MI_NOOP);
         intel_ring_emit(ring, MI_SET_CONTEXT);
@@ -510,10 +531,21 @@ mi_set_context(struct intel_engine_cs *ring,
          */
         intel_ring_emit(ring, MI_NOOP);
 
-        if (INTEL_INFO(ring->dev)->gen >= 7)
+        if (INTEL_INFO(ring->dev)->gen >= 7) {
+                if (num_rings) {
+                        struct intel_engine_cs *signaller;
+
+                        intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
+                        for_each_ring(signaller, to_i915(ring->dev), i) {
+                                if (signaller == ring)
+                                        continue;
+
+                                intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
+                                intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
+                        }
+                }
                 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
-        else
-                intel_ring_emit(ring, MI_NOOP);
+        }
 
         intel_ring_advance(ring);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index f06027ba3ee5..11738316394a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -121,9 +121,6 @@ eb_lookup_vmas(struct eb_vmas *eb,
                         goto err;
                 }
 
-                WARN_ONCE(obj->base.dumb,
-                          "GPU use of dumb buffer is illegal.\n");
-
                 drm_gem_object_reference(&obj->base);
                 list_add_tail(&obj->obj_exec_link, &objects);
         }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 981834b0f9b6..996c2931c499 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -281,10 +281,14 @@ void gen6_enable_rps_interrupts(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
 
         spin_lock_irq(&dev_priv->irq_lock);
+
         WARN_ON(dev_priv->rps.pm_iir);
         WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
         dev_priv->rps.interrupts_enabled = true;
+        I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
+                                dev_priv->pm_rps_events);
         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
+
         spin_unlock_irq(&dev_priv->irq_lock);
 }
 
@@ -3307,8 +3311,10 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
 
         if (INTEL_INFO(dev)->gen >= 6) {
-                pm_irqs |= dev_priv->pm_rps_events;
-
+                /*
+                 * RPS interrupts will get enabled/disabled on demand when RPS
+                 * itself is enabled/disabled.
+                 */
                 if (HAS_VEBOX(dev))
                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
 
@@ -3520,7 +3526,11 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
         dev_priv->pm_irq_mask = 0xffffffff;
         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
-        GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events);
+        /*
+         * RPS interrupts will get enabled/disabled on demand when RPS itself
+         * is enabled/disabled.
+         */
+        GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
 }
 
@@ -3609,7 +3619,7 @@ static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
 
         vlv_display_irq_reset(dev_priv);
 
-        dev_priv->irq_mask = 0;
+        dev_priv->irq_mask = ~0;
 }
 
 static void valleyview_irq_uninstall(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eefdc238f70b..172de3b3433b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -395,6 +395,7 @@
 #define   PIPE_CONTROL_STORE_DATA_INDEX                 (1<<21)
 #define   PIPE_CONTROL_CS_STALL                         (1<<20)
 #define   PIPE_CONTROL_TLB_INVALIDATE                   (1<<18)
+#define   PIPE_CONTROL_MEDIA_STATE_CLEAR                (1<<16)
 #define   PIPE_CONTROL_QW_WRITE                         (1<<14)
 #define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
 #define   PIPE_CONTROL_DEPTH_STALL                      (1<<13)
@@ -1128,6 +1129,7 @@ enum punit_power_well {
 #define GEN6_VERSYNC    (RING_SYNC_1(VEBOX_RING_BASE))
 #define GEN6_VEVSYNC    (RING_SYNC_2(VEBOX_RING_BASE))
 #define GEN6_NOSYNC 0
+#define RING_PSMI_CTL(base)     ((base)+0x50)
 #define RING_MAX_IDLE(base)     ((base)+0x54)
 #define RING_HWS_PGA(base)      ((base)+0x80)
 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
@@ -1458,6 +1460,7 @@ enum punit_power_well {
 #define   GEN6_BLITTER_FBC_NOTIFY                       (1<<3)
 
 #define GEN6_RC_SLEEP_PSMI_CONTROL      0x2050
+#define   GEN6_PSMI_SLEEP_MSG_DISABLE   (1 << 0)
 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE        (1<<10)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1f4b56e273c8..964b28e3c630 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6191,6 +6191,20 @@ void intel_cleanup_gt_powersave(struct drm_device *dev)
                 valleyview_cleanup_gt_powersave(dev);
 }
 
+static void gen6_suspend_rps(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+
+        /*
+         * TODO: disable RPS interrupts on GEN9+ too once RPS support
+         * is added for it.
+         */
+        if (INTEL_INFO(dev)->gen < 9)
+                gen6_disable_rps_interrupts(dev);
+}
+
 /**
  * intel_suspend_gt_powersave - suspend PM work and helper threads
  * @dev: drm device
@@ -6206,14 +6220,7 @@ void intel_suspend_gt_powersave(struct drm_device *dev)
         if (INTEL_INFO(dev)->gen < 6)
                 return;
 
-        flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
-        /*
-         * TODO: disable RPS interrupts on GEN9+ too once RPS support
-         * is added for it.
-         */
-        if (INTEL_INFO(dev)->gen < 9)
-                gen6_disable_rps_interrupts(dev);
+        gen6_suspend_rps(dev);
 
         /* Force GPU to min freq during suspend */
         gen6_rps_idle(dev_priv);
@@ -6316,8 +6323,11 @@ void intel_reset_gt_powersave(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
+        if (INTEL_INFO(dev)->gen < 6)
+                return;
+
+        gen6_suspend_rps(dev);
         dev_priv->rps.enabled = false;
-        intel_enable_gt_powersave(dev);
 }
 
 static void ibx_init_clock_gating(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9f445e9a75d1..c7bc93d28d84 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -362,12 +362,15 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
                 /*
                  * TLB invalidate requires a post-sync write.
                  */
                 flags |= PIPE_CONTROL_QW_WRITE;
                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 
+                flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
+
                 /* Workaround: we must issue a pipe_control with CS-stall bit
                  * set before a pipe_control command that has the state cache
                  * invalidate bit set. */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index aa873048308b..94a5bee69fe7 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -386,9 +386,7 @@ void adreno_gpu_cleanup(struct adreno_gpu *gpu)
                         msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
                 drm_gem_object_unreference(gpu->memptrs_bo);
         }
-        if (gpu->pm4)
-                release_firmware(gpu->pm4);
-        if (gpu->pfp)
-                release_firmware(gpu->pfp);
+        release_firmware(gpu->pm4);
+        release_firmware(gpu->pfp);
         msm_gpu_cleanup(&gpu->base);
 }
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index fbebb0405d76..b4e70e0e3cfa 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -141,6 +141,15 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
         uint32_t hpd_ctrl;
         int i, ret;
 
+        for (i = 0; i < config->hpd_reg_cnt; i++) {
+                ret = regulator_enable(hdmi->hpd_regs[i]);
+                if (ret) {
+                        dev_err(dev->dev, "failed to enable hpd regulator: %s (%d)\n",
+                                        config->hpd_reg_names[i], ret);
+                        goto fail;
+                }
+        }
+
         ret = gpio_config(hdmi, true);
         if (ret) {
                 dev_err(dev->dev, "failed to configure GPIOs: %d\n", ret);
@@ -164,15 +173,6 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
                 }
         }
 
-        for (i = 0; i < config->hpd_reg_cnt; i++) {
-                ret = regulator_enable(hdmi->hpd_regs[i]);
-                if (ret) {
-                        dev_err(dev->dev, "failed to enable hpd regulator: %s (%d)\n",
-                                        config->hpd_reg_names[i], ret);
-                        goto fail;
-                }
-        }
-
         hdmi_set_mode(hdmi, false);
         phy->funcs->reset(phy);
         hdmi_set_mode(hdmi, true);
@@ -200,7 +200,7 @@ fail:
         return ret;
 }
 
-static int hdp_disable(struct hdmi_connector *hdmi_connector)
+static void hdp_disable(struct hdmi_connector *hdmi_connector)
 {
         struct hdmi *hdmi = hdmi_connector->hdmi;
         const struct hdmi_platform_config *config = hdmi->config;
@@ -212,28 +212,19 @@ static int hdp_disable(struct hdmi_connector *hdmi_connector)
 
         hdmi_set_mode(hdmi, false);
 
-        for (i = 0; i < config->hpd_reg_cnt; i++) {
-                ret = regulator_disable(hdmi->hpd_regs[i]);
-                if (ret) {
-                        dev_err(dev->dev, "failed to disable hpd regulator: %s (%d)\n",
-                                        config->hpd_reg_names[i], ret);
-                        goto fail;
-                }
-        }
-
         for (i = 0; i < config->hpd_clk_cnt; i++)
                 clk_disable_unprepare(hdmi->hpd_clks[i]);
 
         ret = gpio_config(hdmi, false);
-        if (ret) {
-                dev_err(dev->dev, "failed to unconfigure GPIOs: %d\n", ret);
-                goto fail;
-        }
-
-        return 0;
+        if (ret)
+                dev_warn(dev->dev, "failed to unconfigure GPIOs: %d\n", ret);
 
-fail:
-        return ret;
+        for (i = 0; i < config->hpd_reg_cnt; i++) {
+                ret = regulator_disable(hdmi->hpd_regs[i]);
+                if (ret)
+                        dev_warn(dev->dev, "failed to disable hpd regulator: %s (%d)\n",
+                                        config->hpd_reg_names[i], ret);
+        }
 }
 
 static void
@@ -260,11 +251,11 @@ void hdmi_connector_irq(struct drm_connector *connector)
                         (hpd_int_status & HDMI_HPD_INT_STATUS_INT)) {
                 bool detected = !!(hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED);
 
-                DBG("status=%04x, ctrl=%04x", hpd_int_status, hpd_int_ctrl);
-
-                /* ack the irq: */
+                /* ack & disable (temporarily) HPD events: */
                 hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL,
-                                hpd_int_ctrl | HDMI_HPD_INT_CTRL_INT_ACK);
+                        HDMI_HPD_INT_CTRL_INT_ACK);
+
+                DBG("status=%04x, ctrl=%04x", hpd_int_status, hpd_int_ctrl);
 
                 /* detect disconnect if we are connected or visa versa: */
                 hpd_int_ctrl = HDMI_HPD_INT_CTRL_INT_EN;
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
index a7672e100d8b..3449213f1e76 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
@@ -331,17 +331,8 @@ static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
                 struct drm_crtc_state *state)
 {
         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
-        struct drm_device *dev = crtc->dev;
-
         DBG("%s: check", mdp4_crtc->name);
-
-        if (mdp4_crtc->event) {
-                dev_err(dev->dev, "already pending flip!\n");
-                return -EBUSY;
-        }
-
         // TODO anything else to check?
-
         return 0;
 }
 
@@ -357,7 +348,7 @@ static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc)
         struct drm_device *dev = crtc->dev;
         unsigned long flags;
 
-        DBG("%s: flush", mdp4_crtc->name);
+        DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
 
         WARN_ON(mdp4_crtc->event);
 
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 0e9a2e3a82d7..f021f960a8a2 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -303,11 +303,6 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
 
         DBG("%s: check", mdp5_crtc->name);
 
-        if (mdp5_crtc->event) {
-                dev_err(dev->dev, "already pending flip!\n");
-                return -EBUSY;
-        }
-
         /* request a free CTL, if none is already allocated for this CRTC */
         if (state->enable && !mdp5_crtc->ctl) {
                 mdp5_crtc->ctl = mdp5_ctlm_request(mdp5_kms->ctlm, crtc);
@@ -364,7 +359,7 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc)
         struct drm_device *dev = crtc->dev;
         unsigned long flags;
 
-        DBG("%s: flush", mdp5_crtc->name);
+        DBG("%s: event: %p", mdp5_crtc->name, crtc->state->event);
 
         WARN_ON(mdp5_crtc->event);
 
@@ -460,10 +455,7 @@ void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
         /* now that we know what irq's we want: */
         mdp5_crtc->err.irqmask = intf2err(intf);
         mdp5_crtc->vblank.irqmask = intf2vblank(intf);
-
-        /* when called from modeset_init(), skip the rest until later: */
-        if (!mdp5_kms)
-                return;
+        mdp_irq_update(&mdp5_kms->base);
 
         spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
         intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index a11f1b80c488..9f01a4f21af2 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -216,17 +216,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
                 goto fail;
         }
 
-        /* NOTE: the vsync and error irq's are actually associated with
-         * the INTF/encoder.. the easiest way to deal with this (ie. what
-         * we do now) is assume a fixed relationship between crtc's and
-         * encoders.  I'm not sure if there is ever a need to more freely
-         * assign crtcs to encoders, but if there is then we need to take
-         * care of error and vblank irq's that the crtc has registered,
-         * and also update user-requested vblank_mask.
-         */
-        encoder->possible_crtcs = BIT(0);
-        mdp5_crtc_set_intf(priv->crtcs[0], 3, INTF_HDMI);
-
+        encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;;
         priv->encoders[priv->num_encoders++] = encoder;
 
         /* Construct bridge/connector for HDMI: */
diff --git a/drivers/gpu/drm/msm/mdp/mdp_kms.c b/drivers/gpu/drm/msm/mdp/mdp_kms.c
index 03455b64a245..2a731722d840 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp_kms.c
@@ -42,7 +42,10 @@ static void update_irq(struct mdp_kms *mdp_kms)
         mdp_kms->funcs->set_irqmask(mdp_kms, irqmask);
 }
 
-static void update_irq_unlocked(struct mdp_kms *mdp_kms)
+/* if an mdp_irq's irqmask has changed, such as when mdp5 crtc<->encoder
+ * link changes, this must be called to figure out the new global irqmask
+ */
+void mdp_irq_update(struct mdp_kms *mdp_kms)
 {
         unsigned long flags;
         spin_lock_irqsave(&list_lock, flags);
@@ -122,7 +125,7 @@ void mdp_irq_register(struct mdp_kms *mdp_kms, struct mdp_irq *irq)
         spin_unlock_irqrestore(&list_lock, flags);
 
         if (needs_update)
-                update_irq_unlocked(mdp_kms);
+                mdp_irq_update(mdp_kms);
 }
 
 void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq)
@@ -141,5 +144,5 @@ void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq)
         spin_unlock_irqrestore(&list_lock, flags);
 
         if (needs_update)
-                update_irq_unlocked(mdp_kms);
+                mdp_irq_update(mdp_kms);
 }
diff --git a/drivers/gpu/drm/msm/mdp/mdp_kms.h b/drivers/gpu/drm/msm/mdp/mdp_kms.h
index 99557b5ad4fd..b268ce95d394 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp_kms.h
@@ -75,7 +75,7 @@ void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable)
 void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask);
 void mdp_irq_register(struct mdp_kms *mdp_kms, struct mdp_irq *irq);
 void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq);
-
+void mdp_irq_update(struct mdp_kms *mdp_kms);
 
 /*
  * pixel format helpers:
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index f0de412e13dc..191968256c58 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -23,10 +23,41 @@ struct msm_commit {
         struct drm_atomic_state *state;
         uint32_t fence;
         struct msm_fence_cb fence_cb;
+        uint32_t crtc_mask;
 };
 
 static void fence_cb(struct msm_fence_cb *cb);
 
+/* block until specified crtcs are no longer pending update, and
+ * atomically mark them as pending update
+ */
+static int start_atomic(struct msm_drm_private *priv, uint32_t crtc_mask)
+{
+        int ret;
+
+        spin_lock(&priv->pending_crtcs_event.lock);
+        ret = wait_event_interruptible_locked(priv->pending_crtcs_event,
+                        !(priv->pending_crtcs & crtc_mask));
+        if (ret == 0) {
+                DBG("start: %08x", crtc_mask);
+                priv->pending_crtcs |= crtc_mask;
+        }
+        spin_unlock(&priv->pending_crtcs_event.lock);
+
+        return ret;
+}
+
+/* clear specified crtcs (no longer pending update)
+ */
+static void end_atomic(struct msm_drm_private *priv, uint32_t crtc_mask)
+{
+        spin_lock(&priv->pending_crtcs_event.lock);
+        DBG("end: %08x", crtc_mask);
+        priv->pending_crtcs &= ~crtc_mask;
+        wake_up_all_locked(&priv->pending_crtcs_event);
+        spin_unlock(&priv->pending_crtcs_event.lock);
+}
+
 static struct msm_commit *new_commit(struct drm_atomic_state *state)
 {
         struct msm_commit *c = kzalloc(sizeof(*c), GFP_KERNEL);
@@ -58,12 +89,27 @@ static void complete_commit(struct msm_commit *c)
 
         drm_atomic_helper_commit_post_planes(dev, state);
 
+        /* NOTE: _wait_for_vblanks() only waits for vblank on
+         * enabled CRTCs.  So we end up faulting when disabling
+         * due to (potentially) unref'ing the outgoing fb's
+         * before the vblank when the disable has latched.
+         *
+         * But if it did wait on disabled (or newly disabled)
+         * CRTCs, that would be racy (ie. we could have missed
+         * the irq.  We need some way to poll for pipe shut
+         * down.  Or just live with occasionally hitting the
+         * timeout in the CRTC disable path (which really should
+         * not be critical path)
+         */
+
         drm_atomic_helper_wait_for_vblanks(dev, state);
 
         drm_atomic_helper_cleanup_planes(dev, state);
 
         drm_atomic_state_free(state);
 
+        end_atomic(dev->dev_private, c->crtc_mask);
+
         kfree(c);
 }
 
@@ -97,8 +143,9 @@ static void add_fb(struct msm_commit *c, struct drm_framebuffer *fb)
 int msm_atomic_commit(struct drm_device *dev,
                 struct drm_atomic_state *state, bool async)
 {
-        struct msm_commit *c;
         int nplanes = dev->mode_config.num_total_plane;
+        int ncrtcs = dev->mode_config.num_crtc;
+        struct msm_commit *c;
         int i, ret;
 
         ret = drm_atomic_helper_prepare_planes(dev, state);
@@ -106,6 +153,18 @@ int msm_atomic_commit(struct drm_device *dev,
                 return ret;
 
         c = new_commit(state);
+        if (!c)
+                return -ENOMEM;
+
+        /*
+         * Figure out what crtcs we have:
+         */
+        for (i = 0; i < ncrtcs; i++) {
+                struct drm_crtc *crtc = state->crtcs[i];
+                if (!crtc)
+                        continue;
+                c->crtc_mask |= (1 << drm_crtc_index(crtc));
+        }
 
         /*
          * Figure out what fence to wait for:
@@ -122,6 +181,14 @@ int msm_atomic_commit(struct drm_device *dev,
         }
 
         /*
+         * Wait for pending updates on any of the same crtc's and then
+         * mark our set of crtc's as busy:
+         */
+        ret = start_atomic(dev->dev_private, c->crtc_mask);
+        if (ret)
+                return ret;
+
+        /*
          * This is the point of no return - everything below never fails except
          * when the hw goes bonghits. Which means we can commit the new state on
          * the software side now.
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index c795217e1bfc..9a61546a0b05 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -193,6 +193,7 @@ static int msm_load(struct drm_device *dev, unsigned long flags)
 
         priv->wq = alloc_ordered_workqueue("msm", 0);
         init_waitqueue_head(&priv->fence_event);
+        init_waitqueue_head(&priv->pending_crtcs_event);
 
         INIT_LIST_HEAD(&priv->inactive_list);
         INIT_LIST_HEAD(&priv->fence_cbs);
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 136303818436..b69ef2d5a26c 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -96,6 +96,10 @@ struct msm_drm_private {
         /* callbacks deferred until bo is inactive: */
         struct list_head fence_cbs;
 
+        /* crtcs pending async atomic updates: */
+        uint32_t pending_crtcs;
+        wait_queue_head_t pending_crtcs_event;
+
         /* registered MMUs: */
         unsigned int num_mmus;
         struct msm_mmu *mmus[NUM_DOMAINS];
diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
index 94d55e526b4e..1f3af13ccede 100644
--- a/drivers/gpu/drm/msm/msm_fbdev.c
+++ b/drivers/gpu/drm/msm/msm_fbdev.c
@@ -190,8 +190,7 @@ fail_unlock:
 fail:
 
         if (ret) {
-                if (fbi)
-                        framebuffer_release(fbi);
+                framebuffer_release(fbi);
                 if (fb) {
                         drm_framebuffer_unregister_private(fb);
                         drm_framebuffer_remove(fb);
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 4a6f0e49d5b5..49dea4fb55ac 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -535,8 +535,7 @@ void msm_gem_free_object(struct drm_gem_object *obj)
                         drm_free_large(msm_obj->pages);
 
         } else {
-                if (msm_obj->vaddr)
-                        vunmap(msm_obj->vaddr);
+                vunmap(msm_obj->vaddr);
                 put_pages(obj);
         }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 5d93902a91ab..f8042433752b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -876,7 +876,6 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev,
         if (ret)
                 return ret;
 
-        bo->gem.dumb = true;
         ret = drm_gem_handle_create(file_priv, &bo->gem, &args->handle);
         drm_gem_object_unreference_unlocked(&bo->gem);
         return ret;
@@ -892,14 +891,6 @@ nouveau_display_dumb_map_offset(struct drm_file *file_priv,
         gem = drm_gem_object_lookup(dev, file_priv, handle);
         if (gem) {
                 struct nouveau_bo *bo = nouveau_gem_object(gem);
-
-                /*
-                 * We don't allow dumb mmaps on objects created using another
-                 * interface.
-                 */
-                WARN_ONCE(!(gem->dumb || gem->import_attach),
-                          "Illegal dumb map of accelerated buffer.\n");
-
                 *poffset = drm_vma_node_offset_addr(&bo->bo.vma_node);
                 drm_gem_object_unreference_unlocked(gem);
                 return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 28d51a22a4bf..42c34babc2e5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -444,9 +444,6 @@ validate_list(struct nouveau_channel *chan, struct nouveau_cli *cli,
         list_for_each_entry(nvbo, list, entry) {
                 struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[nvbo->pbbo_index];
 
-                WARN_ONCE(nvbo->gem.dumb,
-                          "GPU use of dumb buffer is illegal.\n");
-
                 ret = nouveau_gem_set_domain(&nvbo->gem, b->read_domains,
                                              b->write_domains,
                                              b->valid_domains);
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 753a6def61e7..3d1cfcb96b6b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -28,6 +28,7 @@
 #include "nouveau_ttm.h"
 #include "nouveau_gem.h"
 
+#include "drm_legacy.h"
 static int
 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
 {
@@ -281,7 +282,7 @@ nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
         struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);
 
         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
-                return -EINVAL;
+                return drm_legacy_mmap(filp, vma);
 
         return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
 }
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index fe48f229043e..a46f73737994 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -394,10 +394,9 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
         return r;
 }
 
-static int radeon_mode_mmap(struct drm_file *filp,
-                            struct drm_device *dev,
-                            uint32_t handle, bool dumb,
-                            uint64_t *offset_p)
+int radeon_mode_dumb_mmap(struct drm_file *filp,
+                          struct drm_device *dev,
+                          uint32_t handle, uint64_t *offset_p)
 {
         struct drm_gem_object *gobj;
         struct radeon_bo *robj;
@@ -406,14 +405,6 @@ static int radeon_mode_mmap(struct drm_file *filp,
         if (gobj == NULL) {
                 return -ENOENT;
         }
-
-        /*
-         * We don't allow dumb mmaps on objects created using another
-         * interface.
-         */
-        WARN_ONCE(dumb && !(gobj->dumb || gobj->import_attach),
-                "Illegal dumb map of GPU buffer.\n");
-
         robj = gem_to_radeon_bo(gobj);
         if (radeon_ttm_tt_has_userptr(robj->tbo.ttm)) {
                 drm_gem_object_unreference_unlocked(gobj);
@@ -424,20 +415,12 @@ static int radeon_mode_mmap(struct drm_file *filp,
         return 0;
 }
 
-int radeon_mode_dumb_mmap(struct drm_file *filp,
-                          struct drm_device *dev,
-                          uint32_t handle, uint64_t *offset_p)
-{
-        return radeon_mode_mmap(filp, dev, handle, true, offset_p);
-}
-
 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
                           struct drm_file *filp)
 {
         struct drm_radeon_gem_mmap *args = data;
 
-        return radeon_mode_mmap(filp, dev, args->handle, false,
-                                &args->addr_ptr);
+        return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr);
 }
 
 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
@@ -763,7 +746,6 @@ int radeon_mode_dumb_create(struct drm_file *file_priv,
                 return -ENOMEM;
 
         r = drm_gem_handle_create(file_priv, gobj, &handle);
-        gobj->dumb = true;
         /* drop reference from allocate - handle holds it now */
         drm_gem_object_unreference_unlocked(gobj);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c
index 065d02068ec3..242fd8b1b221 100644
--- a/drivers/gpu/drm/radeon/radeon_kfd.c
+++ b/drivers/gpu/drm/radeon/radeon_kfd.c
@@ -28,6 +28,8 @@
 #include "cikd.h"
 #include "cik_reg.h"
 #include "radeon_kfd.h"
+#include "radeon_ucode.h"
+#include <linux/firmware.h>
 
 #define CIK_PIPE_PER_MEC        (4)
 
@@ -49,6 +51,7 @@ static uint64_t get_vmem_size(struct kgd_dev *kgd);
 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
 
 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
+static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
 
 /*
  * Register access functions
@@ -91,6 +94,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
         .hqd_load = kgd_hqd_load,
         .hqd_is_occupies = kgd_hqd_is_occupies,
         .hqd_destroy = kgd_hqd_destroy,
+        .get_fw_version = get_fw_version
 };
 
 static const struct kgd2kfd_calls *kgd2kfd;
@@ -561,3 +565,52 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
         release_queue(kgd);
         return 0;
 }
+
+static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
+{
+        struct radeon_device *rdev = (struct radeon_device *) kgd;
+        const union radeon_firmware_header *hdr;
+
+        BUG_ON(kgd == NULL || rdev->mec_fw == NULL);
+
+        switch (type) {
+        case KGD_ENGINE_PFP:
+                hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
+                break;
+
+        case KGD_ENGINE_ME:
+                hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
+                break;
+
+        case KGD_ENGINE_CE:
+                hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
+                break;
+
+        case KGD_ENGINE_MEC1:
+                hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
+                break;
+
+        case KGD_ENGINE_MEC2:
+                hdr = (const union radeon_firmware_header *)
+                                                        rdev->mec2_fw->data;
+                break;
+
+        case KGD_ENGINE_RLC:
+                hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
+                break;
+
+        case KGD_ENGINE_SDMA:
+                hdr = (const union radeon_firmware_header *)
+                                                        rdev->sdma_fw->data;
+                break;
+
+        default:
+                return 0;
+        }
+
+        if (hdr == NULL)
+                return 0;
+
+        /* Only 12 bit in use*/
+        return hdr->common.ucode_version;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 7d68223eb469..86fc56434b28 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -529,9 +529,6 @@ int radeon_bo_list_validate(struct radeon_device *rdev,
                         u32 current_domain =
                                 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 
-                        WARN_ONCE(bo->gem_base.dumb,
-                                  "GPU use of dumb buffer is illegal.\n");
-
                         /* Check if this buffer will be moved and don't move it
                          * if we have moved too many buffers for this IB already.
                          *
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 3367960286a6..978993fa3a36 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -168,7 +168,7 @@ static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
                                  const struct tegra_dc_window *window)
 {
         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
-        unsigned long value;
+        unsigned long value, flags;
         bool yuv, planar;
 
         /*
@@ -181,6 +181,8 @@ static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
         else
                 bpp = planar ? 1 : 2;
 
+        spin_lock_irqsave(&dc->lock, flags);
+
         value = WINDOW_A_SELECT << index;
         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 
@@ -273,6 +275,7 @@ static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 
                 case TEGRA_BO_TILING_MODE_BLOCK:
                         DRM_ERROR("hardware doesn't support block linear mode\n");
+                        spin_unlock_irqrestore(&dc->lock, flags);
                         return -EINVAL;
                 }
 
@@ -331,6 +334,8 @@ static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 
         tegra_dc_window_commit(dc, index);
 
+        spin_unlock_irqrestore(&dc->lock, flags);
+
         return 0;
 }
 
@@ -338,11 +343,14 @@ static int tegra_window_plane_disable(struct drm_plane *plane)
 {
         struct tegra_dc *dc = to_tegra_dc(plane->crtc);
         struct tegra_plane *p = to_tegra_plane(plane);
+        unsigned long flags;
         u32 value;
 
         if (!plane->crtc)
                 return 0;
 
+        spin_lock_irqsave(&dc->lock, flags);
+
         value = WINDOW_A_SELECT << p->index;
         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 
@@ -352,6 +360,8 @@ static int tegra_window_plane_disable(struct drm_plane *plane)
 
         tegra_dc_window_commit(dc, p->index);
 
+        spin_unlock_irqrestore(&dc->lock, flags);
+
         return 0;
 }
 
@@ -699,14 +709,16 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
         struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
         unsigned int h_offset = 0, v_offset = 0;
         struct tegra_bo_tiling tiling;
+        unsigned long value, flags;
         unsigned int format, swap;
-        unsigned long value;
         int err;
 
         err = tegra_fb_get_tiling(fb, &tiling);
         if (err < 0)
                 return err;
 
+        spin_lock_irqsave(&dc->lock, flags);
+
         tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
 
         value = fb->offsets[0] + y * fb->pitches[0] +
@@ -752,6 +764,7 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
 
                 case TEGRA_BO_TILING_MODE_BLOCK:
                         DRM_ERROR("hardware doesn't support block linear mode\n");
+                        spin_unlock_irqrestore(&dc->lock, flags);
                         return -EINVAL;
                 }
 
@@ -778,6 +791,8 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
         tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
 
+        spin_unlock_irqrestore(&dc->lock, flags);
+
         return 0;
 }
 
@@ -814,23 +829,32 @@ static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
         unsigned long flags, base;
         struct tegra_bo *bo;
 
-        if (!dc->event)
+        spin_lock_irqsave(&drm->event_lock, flags);
+
+        if (!dc->event) {
+                spin_unlock_irqrestore(&drm->event_lock, flags);
                 return;
+        }
 
         bo = tegra_fb_get_plane(crtc->primary->fb, 0);
 
+        spin_lock_irqsave(&dc->lock, flags);
+
         /* check if new start address has been latched */
+        tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
         base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 
+        spin_unlock_irqrestore(&dc->lock, flags);
+
         if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
-                spin_lock_irqsave(&drm->event_lock, flags);
-                drm_send_vblank_event(drm, dc->pipe, dc->event);
-                drm_vblank_put(drm, dc->pipe);
+                drm_crtc_send_vblank_event(crtc, dc->event);
+                drm_crtc_vblank_put(crtc);
                 dc->event = NULL;
-                spin_unlock_irqrestore(&drm->event_lock, flags);
         }
+
+        spin_unlock_irqrestore(&drm->event_lock, flags);
 }
 
 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
@@ -843,7 +867,7 @@ void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 
         if (dc->event && dc->event->base.file_priv == file) {
                 dc->event->base.destroy(&dc->event->base);
-                drm_vblank_put(drm, dc->pipe);
+                drm_crtc_vblank_put(crtc);
                 dc->event = NULL;
         }
 
@@ -853,16 +877,16 @@ void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                               struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
 {
+        unsigned int pipe = drm_crtc_index(crtc);
         struct tegra_dc *dc = to_tegra_dc(crtc);
-        struct drm_device *drm = crtc->dev;
 
         if (dc->event)
                 return -EBUSY;
 
         if (event) {
-                event->pipe = dc->pipe;
+                event->pipe = pipe;
                 dc->event = event;
-                drm_vblank_get(drm, dc->pipe);
+                drm_crtc_vblank_get(crtc);
         }
 
         tegra_dc_set_base(dc, 0, 0, fb);
@@ -1127,7 +1151,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data)
                 /*
                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
                 */
-                drm_handle_vblank(dc->base.dev, dc->pipe);
+                drm_crtc_handle_vblank(&dc->base);
                 tegra_dc_finish_page_flip(dc);
         }
 
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index e549afeece1f..d4f827593dfa 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -694,24 +694,28 @@ static const struct file_operations tegra_drm_fops = {
         .llseek = noop_llseek,
 };
 
-static struct drm_crtc *tegra_crtc_from_pipe(struct drm_device *drm, int pipe)
+static struct drm_crtc *tegra_crtc_from_pipe(struct drm_device *drm,
+                                             unsigned int pipe)
 {
         struct drm_crtc *crtc;
 
         list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) {
-                struct tegra_dc *dc = to_tegra_dc(crtc);
-
-                if (dc->pipe == pipe)
+                if (pipe == drm_crtc_index(crtc))
                         return crtc;
         }
 
         return NULL;
 }
 
-static u32 tegra_drm_get_vblank_counter(struct drm_device *dev, int crtc)
+static u32 tegra_drm_get_vblank_counter(struct drm_device *drm, int pipe)
 {
+        struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe);
+
+        if (!crtc)
+                return 0;
+
         /* TODO: implement real hardware counter using syncpoints */
-        return drm_vblank_count(dev, crtc);
+        return drm_crtc_vblank_count(crtc);
 }
 
 static int tegra_drm_enable_vblank(struct drm_device *drm, int pipe)
diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index da32086cbeaf..8777b7f75791 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -216,32 +216,58 @@ static void tegra_bo_free(struct drm_device *drm, struct tegra_bo *bo)
         }
 }
 
-static int tegra_bo_get_pages(struct drm_device *drm, struct tegra_bo *bo,
-                              size_t size)
+static int tegra_bo_get_pages(struct drm_device *drm, struct tegra_bo *bo)
 {
+        struct scatterlist *s;
+        struct sg_table *sgt;
+        unsigned int i;
+
         bo->pages = drm_gem_get_pages(&bo->gem);
         if (IS_ERR(bo->pages))
                 return PTR_ERR(bo->pages);
 
-        bo->num_pages = size >> PAGE_SHIFT;
-
-        bo->sgt = drm_prime_pages_to_sg(bo->pages, bo->num_pages);
-        if (IS_ERR(bo->sgt)) {
-                drm_gem_put_pages(&bo->gem, bo->pages, false, false);
-                return PTR_ERR(bo->sgt);
+        bo->num_pages = bo->gem.size >> PAGE_SHIFT;
+
+        sgt = drm_prime_pages_to_sg(bo->pages, bo->num_pages);
+        if (IS_ERR(sgt))
+                goto put_pages;
+
+        /*
+         * Fake up the SG table so that dma_map_sg() can be used to flush the
+         * pages associated with it. Note that this relies on the fact that
+         * the DMA API doesn't hook into IOMMU on Tegra, therefore mapping is
+         * only cache maintenance.
+         *
+         * TODO: Replace this by drm_clflash_sg() once it can be implemented
+         * without relying on symbols that are not exported.
+         */
+        for_each_sg(sgt->sgl, s, sgt->nents, i)
+                sg_dma_address(s) = sg_phys(s);
+
+        if (dma_map_sg(drm->dev, sgt->sgl, sgt->nents, DMA_TO_DEVICE) == 0) {
+                sgt = ERR_PTR(-ENOMEM);
+                goto release_sgt;
         }
 
+        bo->sgt = sgt;
+
         return 0;
+
+release_sgt:
+        sg_free_table(sgt);
+        kfree(sgt);
+put_pages:
+        drm_gem_put_pages(&bo->gem, bo->pages, false, false);
+        return PTR_ERR(sgt);
 }
 
-static int tegra_bo_alloc(struct drm_device *drm, struct tegra_bo *bo,
-                          size_t size)
+static int tegra_bo_alloc(struct drm_device *drm, struct tegra_bo *bo)
 {
         struct tegra_drm *tegra = drm->dev_private;
         int err;
 
         if (tegra->domain) {
-                err = tegra_bo_get_pages(drm, bo, size);
+                err = tegra_bo_get_pages(drm, bo);
                 if (err < 0)
                         return err;
 
@@ -251,6 +277,8 @@ static int tegra_bo_alloc(struct drm_device *drm, struct tegra_bo *bo,
                         return err;
                 }
         } else {
+                size_t size = bo->gem.size;
+
                 bo->vaddr = dma_alloc_writecombine(drm->dev, size, &bo->paddr,
                                                    GFP_KERNEL | __GFP_NOWARN);
                 if (!bo->vaddr) {
@@ -274,7 +302,7 @@ struct tegra_bo *tegra_bo_create(struct drm_device *drm, size_t size,
         if (IS_ERR(bo))
                 return bo;
 
-        err = tegra_bo_alloc(drm, bo, size);
+        err = tegra_bo_alloc(drm, bo);
         if (err < 0)
                 goto release;
 
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 91a488c7cc44..31e8308ba899 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -753,6 +753,7 @@ config I2C_SH7760
 
 config I2C_SH_MOBILE
         tristate "SuperH Mobile I2C Controller"
+        depends on HAS_DMA
         depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
         help
           If you say yes to this option, support will be included for the
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 373f6d4e4080..30059c1df2a3 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -30,12 +30,12 @@
 #define MV64XXX_I2C_BAUD_DIV_N(val)                     (val & 0x7)
 #define MV64XXX_I2C_BAUD_DIV_M(val)                     ((val & 0xf) << 3)
 
-#define MV64XXX_I2C_REG_CONTROL_ACK                     0x00000004
-#define MV64XXX_I2C_REG_CONTROL_IFLG                    0x00000008
-#define MV64XXX_I2C_REG_CONTROL_STOP                    0x00000010
-#define MV64XXX_I2C_REG_CONTROL_START                   0x00000020
-#define MV64XXX_I2C_REG_CONTROL_TWSIEN                  0x00000040
-#define MV64XXX_I2C_REG_CONTROL_INTEN                   0x00000080
+#define MV64XXX_I2C_REG_CONTROL_ACK                     BIT(2)
+#define MV64XXX_I2C_REG_CONTROL_IFLG                    BIT(3)
+#define MV64XXX_I2C_REG_CONTROL_STOP                    BIT(4)
+#define MV64XXX_I2C_REG_CONTROL_START                   BIT(5)
+#define MV64XXX_I2C_REG_CONTROL_TWSIEN                  BIT(6)
+#define MV64XXX_I2C_REG_CONTROL_INTEN                   BIT(7)
 
 /* Ctlr status values */
 #define MV64XXX_I2C_STATUS_BUS_ERR                      0x00
@@ -68,19 +68,17 @@
 #define MV64XXX_I2C_REG_BRIDGE_TIMING                   0xe0
 
 /* Bridge Control values */
-#define MV64XXX_I2C_BRIDGE_CONTROL_WR                   0x00000001
-#define MV64XXX_I2C_BRIDGE_CONTROL_RD                   0x00000002
+#define MV64XXX_I2C_BRIDGE_CONTROL_WR                   BIT(0)
+#define MV64XXX_I2C_BRIDGE_CONTROL_RD                   BIT(1)
 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT           2
-#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT             0x00001000
+#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT             BIT(12)
 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT        13
 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT        16
-#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE               0x00080000
+#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE               BIT(19)
+#define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START       BIT(20)
 
 /* Bridge Status values */
-#define MV64XXX_I2C_BRIDGE_STATUS_ERROR                 0x00000001
-#define MV64XXX_I2C_STATUS_OFFLOAD_ERROR                0xf0000001
-#define MV64XXX_I2C_STATUS_OFFLOAD_OK                   0xf0000000
-
+#define MV64XXX_I2C_BRIDGE_STATUS_ERROR                 BIT(0)
 
 /* Driver states */
 enum {
@@ -99,14 +97,12 @@ enum {
         MV64XXX_I2C_ACTION_INVALID,
         MV64XXX_I2C_ACTION_CONTINUE,
         MV64XXX_I2C_ACTION_SEND_RESTART,
-        MV64XXX_I2C_ACTION_OFFLOAD_RESTART,
         MV64XXX_I2C_ACTION_SEND_ADDR_1,
         MV64XXX_I2C_ACTION_SEND_ADDR_2,
         MV64XXX_I2C_ACTION_SEND_DATA,
         MV64XXX_I2C_ACTION_RCV_DATA,
         MV64XXX_I2C_ACTION_RCV_DATA_STOP,
         MV64XXX_I2C_ACTION_SEND_STOP,
-        MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP,
 };
 
 struct mv64xxx_i2c_regs {
@@ -193,75 +189,6 @@ mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
         }
 }
 
-static int mv64xxx_i2c_offload_msg(struct mv64xxx_i2c_data *drv_data)
-{
-        unsigned long data_reg_hi = 0;
-        unsigned long data_reg_lo = 0;
-        unsigned long ctrl_reg;
-        struct i2c_msg *msg = drv_data->msgs;
-
-        if (!drv_data->offload_enabled)
-                return -EOPNOTSUPP;
-
-        /* Only regular transactions can be offloaded */
-        if ((msg->flags & ~(I2C_M_TEN | I2C_M_RD)) != 0)
-                return -EINVAL;
-
-        /* Only 1-8 byte transfers can be offloaded */
-        if (msg->len < 1 || msg->len > 8)
-                return -EINVAL;
-
-        /* Build transaction */
-        ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
-                   (msg->addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
-
-        if ((msg->flags & I2C_M_TEN) != 0)
-                ctrl_reg |=  MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
-
-        if ((msg->flags & I2C_M_RD) == 0) {
-                u8 local_buf[8] = { 0 };
-
-                memcpy(local_buf, msg->buf, msg->len);
-                data_reg_lo = cpu_to_le32(*((u32 *)local_buf));
-                data_reg_hi = cpu_to_le32(*((u32 *)(local_buf+4)));
-
-                ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
-                    (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT;
-
-                writel(data_reg_lo,
-                        drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
-                writel(data_reg_hi,
-                        drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
-
-        } else {
-                ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
-                    (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT;
-        }
-
-        /* Execute transaction */
-        writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
-
-        return 0;
-}
-
-static void
-mv64xxx_i2c_update_offload_data(struct mv64xxx_i2c_data *drv_data)
-{
-        struct i2c_msg *msg = drv_data->msg;
-
-        if (msg->flags & I2C_M_RD) {
-                u32 data_reg_lo = readl(drv_data->reg_base +
-                                MV64XXX_I2C_REG_RX_DATA_LO);
-                u32 data_reg_hi = readl(drv_data->reg_base +
-                                MV64XXX_I2C_REG_RX_DATA_HI);
-                u8 local_buf[8] = { 0 };
-
-                *((u32 *)local_buf) = le32_to_cpu(data_reg_lo);
-                *((u32 *)(local_buf+4)) = le32_to_cpu(data_reg_hi);
-                memcpy(msg->buf, local_buf, msg->len);
-        }
-
-}
 /*
  *****************************************************************************
  *
@@ -389,16 +316,6 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
                 drv_data->rc = -ENXIO;
                 break;
 
-        case MV64XXX_I2C_STATUS_OFFLOAD_OK:
-                if (drv_data->send_stop || drv_data->aborting) {
-                        drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP;
-                        drv_data->state = MV64XXX_I2C_STATE_IDLE;
-                } else {
-                        drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_RESTART;
-                        drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
-                }
-                break;
-
         default:
                 dev_err(&drv_data->adapter.dev,
                         "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
@@ -419,25 +336,15 @@ static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
         drv_data->aborting = 0;
         drv_data->rc = 0;
 
-        /* Can we offload this msg ? */
-        if (mv64xxx_i2c_offload_msg(drv_data) < 0) {
-                /* No, switch to standard path */
-                mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
-                writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
-                        drv_data->reg_base + drv_data->reg_offsets.control);
-        }
+        mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
+        writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
+               drv_data->reg_base + drv_data->reg_offsets.control);
 }
 
 static void
 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 {
         switch(drv_data->action) {
-        case MV64XXX_I2C_ACTION_OFFLOAD_RESTART:
-                mv64xxx_i2c_update_offload_data(drv_data);
-                writel(0, drv_data->reg_base +  MV64XXX_I2C_REG_BRIDGE_CONTROL);
-                writel(0, drv_data->reg_base +
-                        MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
-                /* FALLTHRU */
         case MV64XXX_I2C_ACTION_SEND_RESTART:
                 /* We should only get here if we have further messages */
                 BUG_ON(drv_data->num_msgs == 0);
@@ -518,16 +425,71 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
                 drv_data->block = 0;
                 wake_up(&drv_data->waitq);
                 break;
+        }
+}
 
-        case MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP:
-                mv64xxx_i2c_update_offload_data(drv_data);
-                writel(0, drv_data->reg_base +  MV64XXX_I2C_REG_BRIDGE_CONTROL);
-                writel(0, drv_data->reg_base +
-                        MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
-                drv_data->block = 0;
-                wake_up(&drv_data->waitq);
-                break;
+static void
+mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
+                                 struct i2c_msg *msg)
+{
+        u32 buf[2];
+
+        buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
+        buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
+
+        memcpy(msg->buf, buf, msg->len);
+}
+
+static int
+mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
+{
+        u32 cause, status;
+
+        cause = readl(drv_data->reg_base +
+                      MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
+        if (!cause)
+                return IRQ_NONE;
+
+        status = readl(drv_data->reg_base +
+                       MV64XXX_I2C_REG_BRIDGE_STATUS);
+
+        if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
+                drv_data->rc = -EIO;
+                goto out;
+        }
+
+        drv_data->rc = 0;
+
+        /*
+         * Transaction is a one message read transaction, read data
+         * for this message.
+         */
+        if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
+                mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
+                drv_data->msgs++;
+                drv_data->num_msgs--;
+        }
+        /*
+         * Transaction is a two messages write/read transaction, read
+         * data for the second (read) message.
+         */
+        else if (drv_data->num_msgs == 2 &&
+                 !(drv_data->msgs[0].flags & I2C_M_RD) &&
+                 drv_data->msgs[1].flags & I2C_M_RD) {
+                mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
+                drv_data->msgs += 2;
+                drv_data->num_msgs -= 2;
         }
+
+out:
+        writel(0, drv_data->reg_base +  MV64XXX_I2C_REG_BRIDGE_CONTROL);
+        writel(0, drv_data->reg_base +
+               MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
+        drv_data->block = 0;
+
+        wake_up(&drv_data->waitq);
+
+        return IRQ_HANDLED;
 }
 
 static irqreturn_t
@@ -540,20 +502,9 @@ mv64xxx_i2c_intr(int irq, void *dev_id)
 
         spin_lock_irqsave(&drv_data->lock, flags);
 
-        if (drv_data->offload_enabled) {
-                while (readl(drv_data->reg_base +
-                                MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE)) {
-                        int reg_status = readl(drv_data->reg_base +
-                                        MV64XXX_I2C_REG_BRIDGE_STATUS);
-                        if (reg_status & MV64XXX_I2C_BRIDGE_STATUS_ERROR)
-                                status = MV64XXX_I2C_STATUS_OFFLOAD_ERROR;
-                        else
-                                status = MV64XXX_I2C_STATUS_OFFLOAD_OK;
-                        mv64xxx_i2c_fsm(drv_data, status);
-                        mv64xxx_i2c_do_action(drv_data);
-                        rc = IRQ_HANDLED;
-                }
-        }
+        if (drv_data->offload_enabled)
+                rc = mv64xxx_i2c_intr_offload(drv_data);
+
         while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
                                                 MV64XXX_I2C_REG_CONTROL_IFLG) {
                 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
@@ -635,6 +586,117 @@ mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
         return drv_data->rc;
 }
 
+static void
+mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
+{
+        struct i2c_msg *msg = drv_data->msgs;
+        u32 buf[2];
+
+        memcpy(buf, msg->buf, msg->len);
+
+        writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
+        writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
+}
+
+static int
+mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
+{
+        struct i2c_msg *msgs = drv_data->msgs;
+        int num = drv_data->num_msgs;
+        unsigned long ctrl_reg;
+        unsigned long flags;
+
+        spin_lock_irqsave(&drv_data->lock, flags);
+
+        /* Build transaction */
+        ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
+                (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
+
+        if (msgs[0].flags & I2C_M_TEN)
+                ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
+
+        /* Single write message transaction */
+        if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
+                size_t len = msgs[0].len - 1;
+
+                ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
+                        (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
+                mv64xxx_i2c_prepare_tx(drv_data);
+        }
+        /* Single read message transaction */
+        else if (num == 1 && msgs[0].flags & I2C_M_RD) {
+                size_t len = msgs[0].len - 1;
+
+                ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
+                        (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
+        }
+        /*
+         * Transaction with one write and one read message. This is
+         * guaranteed by the mv64xx_i2c_can_offload() checks.
+         */
+        else if (num == 2) {
+                size_t lentx = msgs[0].len - 1;
+                size_t lenrx = msgs[1].len - 1;
+
+                ctrl_reg |=
+                        MV64XXX_I2C_BRIDGE_CONTROL_RD |
+                        MV64XXX_I2C_BRIDGE_CONTROL_WR |
+                        (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
+                        (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
+                        MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
+                mv64xxx_i2c_prepare_tx(drv_data);
+        }
+
+        /* Execute transaction */
+        drv_data->block = 1;
+        writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
+        spin_unlock_irqrestore(&drv_data->lock, flags);
+
+        mv64xxx_i2c_wait_for_completion(drv_data);
+
+        return drv_data->rc;
+}
+
+static bool
+mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
+{
+        return msg->len <= 8 && msg->len >= 1;
+}
+
+static bool
+mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
+{
+        struct i2c_msg *msgs = drv_data->msgs;
+        int num = drv_data->num_msgs;
+
+        return false;
+
+        if (!drv_data->offload_enabled)
+                return false;
+
+        /*
+         * We can offload a transaction consisting of a single
+         * message, as long as the message has a length between 1 and
+         * 8 bytes.
+         */
+        if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
+                return true;
+
+        /*
+         * We can offload a transaction consisting of two messages, if
+         * the first is a write and a second is a read, and both have
+         * a length between 1 and 8 bytes.
+         */
+        if (num == 2 &&
+            mv64xxx_i2c_valid_offload_sz(msgs) &&
+            mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
+            !(msgs[0].flags & I2C_M_RD) &&
+            msgs[1].flags & I2C_M_RD)
+                return true;
+
+        return false;
+}
+
 /*
  *****************************************************************************
  *
@@ -658,7 +720,11 @@ mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
         drv_data->msgs = msgs;
         drv_data->num_msgs = num;
 
-        rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
+        if (mv64xxx_i2c_can_offload(drv_data))
+                rc = mv64xxx_i2c_offload_xfer(drv_data);
+        else
+                rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
+
         if (rc < 0)
                 ret = rc;
 
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index d7efaf44868b..440d5dbc8b5f 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -140,6 +140,7 @@ struct sh_mobile_i2c_data {
         int sr;
         bool send_stop;
 
+        struct resource *res;
         struct dma_chan *dma_tx;
         struct dma_chan *dma_rx;
         struct scatterlist sg;
@@ -539,6 +540,42 @@ static void sh_mobile_i2c_dma_callback(void *data)
         iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
 }
 
+static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
+                                enum dma_transfer_direction dir, dma_addr_t port_addr)
+{
+        struct dma_chan *chan;
+        struct dma_slave_config cfg;
+        char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
+        int ret;
+
+        chan = dma_request_slave_channel_reason(dev, chan_name);
+        if (IS_ERR(chan)) {
+                ret = PTR_ERR(chan);
+                dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
+                return chan;
+        }
+
+        memset(&cfg, 0, sizeof(cfg));
+        cfg.direction = dir;
+        if (dir == DMA_MEM_TO_DEV) {
+                cfg.dst_addr = port_addr;
+                cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+        } else {
+                cfg.src_addr = port_addr;
+                cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+        }
+
+        ret = dmaengine_slave_config(chan, &cfg);
+        if (ret) {
+                dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
+                dma_release_channel(chan);
+                return ERR_PTR(ret);
+        }
+
+        dev_dbg(dev, "got DMA channel for %s\n", chan_name);
+        return chan;
+}
+
 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
 {
         bool read = pd->msg->flags & I2C_M_RD;
@@ -548,7 +585,16 @@ static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
         dma_addr_t dma_addr;
         dma_cookie_t cookie;
 
-        if (!chan)
+        if (PTR_ERR(chan) == -EPROBE_DEFER) {
+                if (read)
+                        chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
+                                                                           pd->res->start + ICDR);
+                else
+                        chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
+                                                                           pd->res->start + ICDR);
+        }
+
+        if (IS_ERR(chan))
                 return;
 
         dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir);
@@ -747,56 +793,16 @@ static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
 
-static int sh_mobile_i2c_request_dma_chan(struct device *dev, enum dma_transfer_direction dir,
-                                          dma_addr_t port_addr, struct dma_chan **chan_ptr)
-{
-        struct dma_chan *chan;
-        struct dma_slave_config cfg;
-        char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
-        int ret;
-
-        *chan_ptr = NULL;
-
-        chan = dma_request_slave_channel_reason(dev, chan_name);
-        if (IS_ERR(chan)) {
-                ret = PTR_ERR(chan);
-                dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
-                return ret;
-        }
-
-        memset(&cfg, 0, sizeof(cfg));
-        cfg.direction = dir;
-        if (dir == DMA_MEM_TO_DEV) {
-                cfg.dst_addr = port_addr;
-                cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
-        } else {
-                cfg.src_addr = port_addr;
-                cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
-        }
-
-        ret = dmaengine_slave_config(chan, &cfg);
-        if (ret) {
-                dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
-                dma_release_channel(chan);
-                return ret;
-        }
-
-        *chan_ptr = chan;
-
-        dev_dbg(dev, "got DMA channel for %s\n", chan_name);
-        return 0;
-}
-
 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
 {
-        if (pd->dma_tx) {
+        if (!IS_ERR(pd->dma_tx)) {
                 dma_release_channel(pd->dma_tx);
-                pd->dma_tx = NULL;
+                pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
         }
 
-        if (pd->dma_rx) {
+        if (!IS_ERR(pd->dma_rx)) {
                 dma_release_channel(pd->dma_rx);
-                pd->dma_rx = NULL;
+                pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
         }
 }
 
@@ -849,6 +855,7 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
 
         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 
+        pd->res = res;
         pd->reg = devm_ioremap_resource(&dev->dev, res);
         if (IS_ERR(pd->reg))
                 return PTR_ERR(pd->reg);
@@ -889,17 +896,7 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
         /* Init DMA */
         sg_init_table(&pd->sg, 1);
         pd->dma_direction = DMA_NONE;
-        ret = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
-                                             res->start + ICDR, &pd->dma_rx);
-        if (ret == -EPROBE_DEFER)
-                return ret;
-
-        ret = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
-                                             res->start + ICDR, &pd->dma_tx);
-        if (ret == -EPROBE_DEFER) {
-                sh_mobile_i2c_release_dma(pd);
-                return ret;
-        }
+        pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 
         /* Enable Runtime PM for this device.
          *
@@ -937,8 +934,7 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
                 return ret;
         }
 
-        dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz, DMA=%c\n",
-                 adap->nr, pd->bus_speed, (pd->dma_rx || pd->dma_tx) ? 'y' : 'n');
+        dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
 
         return 0;
 }
diff --git a/drivers/infiniband/ulp/srp/ib_srp.c b/drivers/infiniband/ulp/srp/ib_srp.c
index db3c8c851af1..0747c0595a9d 100644
--- a/drivers/infiniband/ulp/srp/ib_srp.c
+++ b/drivers/infiniband/ulp/srp/ib_srp.c
@@ -2740,7 +2740,6 @@ static struct scsi_host_template srp_template = {
         .info                           = srp_target_info,
         .queuecommand                   = srp_queuecommand,
         .change_queue_depth             = srp_change_queue_depth,
-        .change_queue_type              = scsi_change_queue_type,
         .eh_abort_handler               = srp_abort,
         .eh_device_reset_handler        = srp_reset_device,
         .eh_host_reset_handler          = srp_reset_host,
diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c
index dc829682701a..eb694ddad79f 100644
--- a/drivers/infiniband/ulp/srpt/ib_srpt.c
+++ b/drivers/infiniband/ulp/srpt/ib_srpt.c
@@ -1708,17 +1708,17 @@ static int srpt_handle_cmd(struct srpt_rdma_ch *ch,
 
         switch (srp_cmd->task_attr) {
         case SRP_CMD_SIMPLE_Q:
-                cmd->sam_task_attr = MSG_SIMPLE_TAG;
+                cmd->sam_task_attr = TCM_SIMPLE_TAG;
                 break;
         case SRP_CMD_ORDERED_Q:
         default:
-                cmd->sam_task_attr = MSG_ORDERED_TAG;
+                cmd->sam_task_attr = TCM_ORDERED_TAG;
                 break;
         case SRP_CMD_HEAD_OF_Q:
-                cmd->sam_task_attr = MSG_HEAD_TAG;
+                cmd->sam_task_attr = TCM_HEAD_TAG;
                 break;
         case SRP_CMD_ACA:
-                cmd->sam_task_attr = MSG_ACA_TAG;
+                cmd->sam_task_attr = TCM_ACA_TAG;
                 break;
         }
 
@@ -1733,7 +1733,7 @@ static int srpt_handle_cmd(struct srpt_rdma_ch *ch,
                                        sizeof(srp_cmd->lun));
         rc = target_submit_cmd(cmd, ch->sess, srp_cmd->cdb,
                         &send_ioctx->sense_data[0], unpacked_lun, data_len,
-                        MSG_SIMPLE_TAG, dir, TARGET_SCF_ACK_KREF);
+                        TCM_SIMPLE_TAG, dir, TARGET_SCF_ACK_KREF);
         if (rc != 0) {
                 ret = TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE;
                 goto send_sense;
diff --git a/drivers/macintosh/Kconfig b/drivers/macintosh/Kconfig
index 3067d56b11a6..5844b80bd90e 100644
--- a/drivers/macintosh/Kconfig
+++ b/drivers/macintosh/Kconfig
@@ -204,16 +204,6 @@ config THERM_ADT746X
           iBook G4, and the ATI based aluminium PowerBooks, allowing slightly
           better fan behaviour by default, and some manual control.
 
-config THERM_PM72
-        tristate "Support for thermal management on PowerMac G5 (AGP)"
-        depends on I2C && I2C_POWERMAC && PPC_PMAC64
-        default n
-        help
-          This driver provides thermostat and fan control for the desktop
-          G5 machines.
-
-          This is deprecated, use windfarm instead.
-
 config WINDFARM
         tristate "New PowerMac thermal control infrastructure"
         depends on PPC
diff --git a/drivers/macintosh/Makefile b/drivers/macintosh/Makefile
index d2f0120bc878..383ba920085b 100644
--- a/drivers/macintosh/Makefile
+++ b/drivers/macintosh/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_ADB_IOP)		+= adb-iop.o
 obj-$(CONFIG_ADB_PMU68K)        += via-pmu68k.o
 obj-$(CONFIG_ADB_MACIO)         += macio-adb.o
 
-obj-$(CONFIG_THERM_PM72)        += therm_pm72.o
 obj-$(CONFIG_THERM_WINDTUNNEL)  += therm_windtunnel.o
 obj-$(CONFIG_THERM_ADT746X)     += therm_adt746x.o
 obj-$(CONFIG_WINDFARM)          += windfarm_core.o
diff --git a/drivers/macintosh/therm_pm72.c b/drivers/macintosh/therm_pm72.c
deleted file mode 100644
index 7ed92582d2cf..000000000000
--- a/drivers/macintosh/therm_pm72.c
+++ /dev/null
@@ -1,2278 +0,0 @@
-/*
- * Device driver for the thermostats & fan controller of  the
- * Apple G5 "PowerMac7,2" desktop machines.
- *
- * (c) Copyright IBM Corp. 2003-2004
- *
- * Maintained by: Benjamin Herrenschmidt
- *                <benh@kernel.crashing.org>
- * 
- *
- * The algorithm used is the PID control algorithm, used the same
- * way the published Darwin code does, using the same values that
- * are present in the Darwin 7.0 snapshot property lists.
- *
- * As far as the CPUs control loops are concerned, I use the
- * calibration & PID constants provided by the EEPROM,
- * I do _not_ embed any value from the property lists, as the ones
- * provided by Darwin 7.0 seem to always have an older version that
- * what I've seen on the actual computers.
- * It would be interesting to verify that though. Darwin has a
- * version code of 1.0.0d11 for all control loops it seems, while
- * so far, the machines EEPROMs contain a dataset versioned 1.0.0f
- *
- * Darwin doesn't provide source to all parts, some missing
- * bits like the AppleFCU driver or the actual scale of some
- * of the values returned by sensors had to be "guessed" some
- * way... or based on what Open Firmware does.
- *
- * I didn't yet figure out how to get the slots power consumption
- * out of the FCU, so that part has not been implemented yet and
- * the slots fan is set to a fixed 50% PWM, hoping this value is
- * safe enough ...
- *
- * Note: I have observed strange oscillations of the CPU control
- * loop on a dual G5 here. When idle, the CPU exhaust fan tend to
- * oscillates slowly (over several minutes) between the minimum
- * of 300RPMs and approx. 1000 RPMs. I don't know what is causing
- * this, it could be some incorrect constant or an error in the
- * way I ported the algorithm, or it could be just normal. I
- * don't have full understanding on the way Apple tweaked the PID
- * algorithm for the CPU control, it is definitely not a standard
- * implementation...
- *
- * TODO:  - Check MPU structure version/signature
- *        - Add things like /sbin/overtemp for non-critical
- *          overtemp conditions so userland can take some policy
- *          decisions, like slowing down CPUs
- *        - Deal with fan and i2c failures in a better way
- *        - Maybe do a generic PID based on params used for
- *          U3 and Drives ? Definitely need to factor code a bit
- *          better... also make sensor detection more robust using
- *          the device-tree to probe for them
- *        - Figure out how to get the slots consumption and set the
- *          slots fan accordingly
- *
- * History:
- *
- *  Nov. 13, 2003 : 0.5
- *      - First release
- *
- *  Nov. 14, 2003 : 0.6
- *      - Read fan speed from FCU, low level fan routines now deal
- *        with errors & check fan status, though higher level don't
- *        do much.
- *      - Move a bunch of definitions to .h file
- *
- *  Nov. 18, 2003 : 0.7
- *      - Fix build on ppc64 kernel
- *      - Move back statics definitions to .c file
- *      - Avoid calling schedule_timeout with a negative number
- *
- *  Dec. 18, 2003 : 0.8
- *      - Fix typo when reading back fan speed on 2 CPU machines
- *
- *  Mar. 11, 2004 : 0.9
- *      - Rework code accessing the ADC chips, make it more robust and
- *        closer to the chip spec. Also make sure it is configured properly,
- *        I've seen yet unexplained cases where on startup, I would have stale
- *        values in the configuration register
- *      - Switch back to use of target fan speed for PID, thus lowering
- *        pressure on i2c
- *
- *  Oct. 20, 2004 : 1.1
- *      - Add device-tree lookup for fan IDs, should detect liquid cooling
- *        pumps when present
- *      - Enable driver for PowerMac7,3 machines
- *      - Split the U3/Backside cooling on U3 & U3H versions as Darwin does
- *      - Add new CPU cooling algorithm for machines with liquid cooling
- *      - Workaround for some PowerMac7,3 with empty "fan" node in the devtree
- *      - Fix a signed/unsigned compare issue in some PID loops
- *
- *  Mar. 10, 2005 : 1.2
- *      - Add basic support for Xserve G5
- *      - Retrieve pumps min/max from EEPROM image in device-tree (broken)
- *      - Use min/max macros here or there
- *      - Latest darwin updated U3H min fan speed to 20% PWM
- *
- *  July. 06, 2006 : 1.3
- *      - Fix setting of RPM fans on Xserve G5 (they were going too fast)
- *      - Add missing slots fan control loop for Xserve G5
- *      - Lower fixed slots fan speed from 50% to 40% on desktop G5s. We
- *        still can't properly implement the control loop for these, so let's
- *        reduce the noise a little bit, it appears that 40% still gives us
- *        a pretty good air flow
- *      - Add code to "tickle" the FCU regulary so it doesn't think that
- *        we are gone while in fact, the machine just didn't need any fan
- *        speed change lately
- *
- */
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/wait.h>
-#include <linux/reboot.h>
-#include <linux/kmod.h>
-#include <linux/i2c.h>
-#include <linux/kthread.h>
-#include <linux/mutex.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-#include <asm/prom.h>
-#include <asm/machdep.h>
-#include <asm/io.h>
-#include <asm/sections.h>
-#include <asm/macio.h>
-
-#include "therm_pm72.h"
-
-#define VERSION "1.3"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(args...)    printk(args)
-#else
-#define DBG(args...)    do { } while(0)
-#endif
-
-
-/*
- * Driver statics
- */
-
-static struct platform_device *         of_dev;
-static struct i2c_adapter *             u3_0;
-static struct i2c_adapter *             u3_1;
-static struct i2c_adapter *             k2;
-static struct i2c_client *              fcu;
-static struct cpu_pid_state             processor_state[2];
-static struct basckside_pid_params      backside_params;
-static struct backside_pid_state        backside_state;
-static struct drives_pid_state          drives_state;
-static struct dimm_pid_state            dimms_state;
-static struct slots_pid_state           slots_state;
-static int                              state;
-static int                              cpu_count;
-static int                              cpu_pid_type;
-static struct task_struct               *ctrl_task;
-static struct completion                ctrl_complete;
-static int                              critical_state;
-static int                              rackmac;
-static s32                              dimm_output_clamp;
-static int                              fcu_rpm_shift;
-static int                              fcu_tickle_ticks;
-static DEFINE_MUTEX(driver_lock);
-
-/*
- * We have 3 types of CPU PID control. One is "split" old style control
- * for intake & exhaust fans, the other is "combined" control for both
- * CPUs that also deals with the pumps when present. To be "compatible"
- * with OS X at this point, we only use "COMBINED" on the machines that
- * are identified as having the pumps (though that identification is at
- * least dodgy). Ultimately, we could probably switch completely to this
- * algorithm provided we hack it to deal with the UP case
- */
-#define CPU_PID_TYPE_SPLIT      0
-#define CPU_PID_TYPE_COMBINED   1
-#define CPU_PID_TYPE_RACKMAC    2
-
-/*
- * This table describes all fans in the FCU. The "id" and "type" values
- * are defaults valid for all earlier machines. Newer machines will
- * eventually override the table content based on the device-tree
- */
-struct fcu_fan_table
-{
-        char*   loc;    /* location code */
-        int     type;   /* 0 = rpm, 1 = pwm, 2 = pump */
-        int     id;     /* id or -1 */
-};
-
-#define FCU_FAN_RPM             0
-#define FCU_FAN_PWM             1
-
-#define FCU_FAN_ABSENT_ID       -1
-
-#define FCU_FAN_COUNT           ARRAY_SIZE(fcu_fans)
-
-struct fcu_fan_table    fcu_fans[] = {
-        [BACKSIDE_FAN_PWM_INDEX] = {
-                .loc    = "BACKSIDE,SYS CTRLR FAN",
-                .type   = FCU_FAN_PWM,
-                .id     = BACKSIDE_FAN_PWM_DEFAULT_ID,
-        },
-        [DRIVES_FAN_RPM_INDEX] = {
-                .loc    = "DRIVE BAY",
-                .type   = FCU_FAN_RPM,
-                .id     = DRIVES_FAN_RPM_DEFAULT_ID,
-        },
-        [SLOTS_FAN_PWM_INDEX] = {
-                .loc    = "SLOT,PCI FAN",
-                .type   = FCU_FAN_PWM,
-                .id     = SLOTS_FAN_PWM_DEFAULT_ID,
-        },
-        [CPUA_INTAKE_FAN_RPM_INDEX] = {
-                .loc    = "CPU A INTAKE",
-                .type   = FCU_FAN_RPM,
-                .id     = CPUA_INTAKE_FAN_RPM_DEFAULT_ID,
-        },
-        [CPUA_EXHAUST_FAN_RPM_INDEX] = {
-                .loc    = "CPU A EXHAUST",
-                .type   = FCU_FAN_RPM,
-                .id     = CPUA_EXHAUST_FAN_RPM_DEFAULT_ID,
-        },
-        [CPUB_INTAKE_FAN_RPM_INDEX] = {
-                .loc    = "CPU B INTAKE",
-                .type   = FCU_FAN_RPM,
-                .id     = CPUB_INTAKE_FAN_RPM_DEFAULT_ID,
-        },
-        [CPUB_EXHAUST_FAN_RPM_INDEX] = {
-                .loc    = "CPU B EXHAUST",
-                .type   = FCU_FAN_RPM,
-                .id     = CPUB_EXHAUST_FAN_RPM_DEFAULT_ID,
-        },
-        /* pumps aren't present by default, have to be looked up in the
-         * device-tree
-         */
-        [CPUA_PUMP_RPM_INDEX] = {
-                .loc    = "CPU A PUMP",
-                .type   = FCU_FAN_RPM,          
-                .id     = FCU_FAN_ABSENT_ID,
-        },
-        [CPUB_PUMP_RPM_INDEX] = {
-                .loc    = "CPU B PUMP",
-                .type   = FCU_FAN_RPM,
-                .id     = FCU_FAN_ABSENT_ID,
-        },
-        /* Xserve fans */
-        [CPU_A1_FAN_RPM_INDEX] = {
-                .loc    = "CPU A 1",
-                .type   = FCU_FAN_RPM,
-                .id     = FCU_FAN_ABSENT_ID,
-        },
-        [CPU_A2_FAN_RPM_INDEX] = {
-                .loc    = "CPU A 2",
-                .type   = FCU_FAN_RPM,
-                .id     = FCU_FAN_ABSENT_ID,
-        },
-        [CPU_A3_FAN_RPM_INDEX] = {
-                .loc    = "CPU A 3",
-                .type   = FCU_FAN_RPM,
-                .id     = FCU_FAN_ABSENT_ID,
-        },
-        [CPU_B1_FAN_RPM_INDEX] = {
-                .loc    = "CPU B 1",
-                .type   = FCU_FAN_RPM,
-                .id     = FCU_FAN_ABSENT_ID,
-        },
-        [CPU_B2_FAN_RPM_INDEX] = {
-                .loc    = "CPU B 2",
-                .type   = FCU_FAN_RPM,
-                .id     = FCU_FAN_ABSENT_ID,
-        },
-        [CPU_B3_FAN_RPM_INDEX] = {
-                .loc    = "CPU B 3",
-                .type   = FCU_FAN_RPM,
-                .id     = FCU_FAN_ABSENT_ID,
-        },
-};
-
-static struct i2c_driver therm_pm72_driver;
-
-/*
- * Utility function to create an i2c_client structure and
- * attach it to one of u3 adapters
- */
-static struct i2c_client *attach_i2c_chip(int id, const char *name)
-{
-        struct i2c_client *clt;
-        struct i2c_adapter *adap;
-        struct i2c_board_info info;
-
-        if (id & 0x200)
-                adap = k2;
-        else if (id & 0x100)
-                adap = u3_1;
-        else
-                adap = u3_0;
-        if (adap == NULL)
-                return NULL;
-
-        memset(&info, 0, sizeof(struct i2c_board_info));
-        info.addr = (id >> 1) & 0x7f;
-        strlcpy(info.type, "therm_pm72", I2C_NAME_SIZE);
-        clt = i2c_new_device(adap, &info);
-        if (!clt) {
-                printk(KERN_ERR "therm_pm72: Failed to attach to i2c ID 0x%x\n", id);
-                return NULL;
-        }
-
-        /*
-         * Let i2c-core delete that device on driver removal.
-         * This is safe because i2c-core holds the core_lock mutex for us.
-         */
-        list_add_tail(&clt->detected, &therm_pm72_driver.clients);
-        return clt;
-}
-
-/*
- * Here are the i2c chip access wrappers
- */
-
-static void initialize_adc(struct cpu_pid_state *state)
-{
-        int rc;
-        u8 buf[2];
-
-        /* Read ADC the configuration register and cache it. We
-         * also make sure Config2 contains proper values, I've seen
-         * cases where we got stale grabage in there, thus preventing
-         * proper reading of conv. values
-         */
-
-        /* Clear Config2 */
-        buf[0] = 5;
-        buf[1] = 0;
-        i2c_master_send(state->monitor, buf, 2);
-
-        /* Read & cache Config1 */
-        buf[0] = 1;
-        rc = i2c_master_send(state->monitor, buf, 1);
-        if (rc > 0) {
-                rc = i2c_master_recv(state->monitor, buf, 1);
-                if (rc > 0) {
-                        state->adc_config = buf[0];
-                        DBG("ADC config reg: %02x\n", state->adc_config);
-                        /* Disable shutdown mode */
-                        state->adc_config &= 0xfe;
-                        buf[0] = 1;
-                        buf[1] = state->adc_config;
-                        rc = i2c_master_send(state->monitor, buf, 2);
-                }
-        }
-        if (rc <= 0)
-                printk(KERN_ERR "therm_pm72: Error reading ADC config"
-                       " register !\n");
-}
-
-static int read_smon_adc(struct cpu_pid_state *state, int chan)
-{
-        int rc, data, tries = 0;
-        u8 buf[2];
-
-        for (;;) {
-                /* Set channel */
-                buf[0] = 1;
-                buf[1] = (state->adc_config & 0x1f) | (chan << 5);
-                rc = i2c_master_send(state->monitor, buf, 2);
-                if (rc <= 0)
-                        goto error;
-                /* Wait for conversion */
-                msleep(1);
-                /* Switch to data register */
-                buf[0] = 4;
-                rc = i2c_master_send(state->monitor, buf, 1);
-                if (rc <= 0)
-                        goto error;
-                /* Read result */
-                rc = i2c_master_recv(state->monitor, buf, 2);
-                if (rc < 0)
-                        goto error;
-                data = ((u16)buf[0]) << 8 | (u16)buf[1];
-                return data >> 6;
-        error:
-                DBG("Error reading ADC, retrying...\n");
-                if (++tries > 10) {
-                        printk(KERN_ERR "therm_pm72: Error reading ADC !\n");
-                        return -1;
-                }
-                msleep(10);
-        }
-}
-
-static int read_lm87_reg(struct i2c_client * chip, int reg)
-{
-        int rc, tries = 0;
-        u8 buf;
-
-        for (;;) {
-                /* Set address */
-                buf = (u8)reg;
-                rc = i2c_master_send(chip, &buf, 1);
-                if (rc <= 0)
-                        goto error;
-                rc = i2c_master_recv(chip, &buf, 1);
-                if (rc <= 0)
-                        goto error;
-                return (int)buf;
-        error:
-                DBG("Error reading LM87, retrying...\n");
-                if (++tries > 10) {
-                        printk(KERN_ERR "therm_pm72: Error reading LM87 !\n");
-                        return -1;
-                }
-                msleep(10);
-        }
-}
-
-static int fan_read_reg(int reg, unsigned char *buf, int nb)
-{
-        int tries, nr, nw;
-
-        buf[0] = reg;
-        tries = 0;
-        for (;;) {
-                nw = i2c_master_send(fcu, buf, 1);
-                if (nw > 0 || (nw < 0 && nw != -EIO) || tries >= 100)
-                        break;
-                msleep(10);
-                ++tries;
-        }
-        if (nw <= 0) {
-                printk(KERN_ERR "Failure writing address to FCU: %d", nw);
-                return -EIO;
-        }
-        tries = 0;
-        for (;;) {
-                nr = i2c_master_recv(fcu, buf, nb);
-                if (nr > 0 || (nr < 0 && nr != -ENODEV) || tries >= 100)
-                        break;
-                msleep(10);
-                ++tries;
-        }
-        if (nr <= 0)
-                printk(KERN_ERR "Failure reading data from FCU: %d", nw);
-        return nr;
-}
-
-static int fan_write_reg(int reg, const unsigned char *ptr, int nb)
-{
-        int tries, nw;
-        unsigned char buf[16];
-
-        buf[0] = reg;
-        memcpy(buf+1, ptr, nb);
-        ++nb;
-        tries = 0;
-        for (;;) {
-                nw = i2c_master_send(fcu, buf, nb);
-                if (nw > 0 || (nw < 0 && nw != -EIO) || tries >= 100)
-                        break;
-                msleep(10);
-                ++tries;
-        }
-        if (nw < 0)
-                printk(KERN_ERR "Failure writing to FCU: %d", nw);
-        return nw;
-}
-
-static int start_fcu(void)
-{
-        unsigned char buf = 0xff;
-        int rc;
-
-        rc = fan_write_reg(0xe, &buf, 1);
-        if (rc < 0)
-                return -EIO;
-        rc = fan_write_reg(0x2e, &buf, 1);
-        if (rc < 0)
-                return -EIO;
-        rc = fan_read_reg(0, &buf, 1);
-        if (rc < 0)
-                return -EIO;
-        fcu_rpm_shift = (buf == 1) ? 2 : 3;
-        printk(KERN_DEBUG "FCU Initialized, RPM fan shift is %d\n",
-               fcu_rpm_shift);
-
-        return 0;
-}
-
-static int set_rpm_fan(int fan_index, int rpm)
-{
-        unsigned char buf[2];
-        int rc, id, min, max;
-
-        if (fcu_fans[fan_index].type != FCU_FAN_RPM)
-                return -EINVAL;
-        id = fcu_fans[fan_index].id; 
-        if (id == FCU_FAN_ABSENT_ID)
-                return -EINVAL;
-
-        min = 2400 >> fcu_rpm_shift;
-        max = 56000 >> fcu_rpm_shift;
-
-        if (rpm < min)
-                rpm = min;
-        else if (rpm > max)
-                rpm = max;
-        buf[0] = rpm >> (8 - fcu_rpm_shift);
-        buf[1] = rpm << fcu_rpm_shift;
-        rc = fan_write_reg(0x10 + (id * 2), buf, 2);
-        if (rc < 0)
-                return -EIO;
-        return 0;
-}
-
-static int get_rpm_fan(int fan_index, int programmed)
-{
-        unsigned char failure;
-        unsigned char active;
-        unsigned char buf[2];
-        int rc, id, reg_base;
-
-        if (fcu_fans[fan_index].type != FCU_FAN_RPM)
-                return -EINVAL;
-        id = fcu_fans[fan_index].id; 
-        if (id == FCU_FAN_ABSENT_ID)
-                return -EINVAL;
-
-        rc = fan_read_reg(0xb, &failure, 1);
-        if (rc != 1)
-                return -EIO;
-        if ((failure & (1 << id)) != 0)
-                return -EFAULT;
-        rc = fan_read_reg(0xd, &active, 1);
-        if (rc != 1)
-                return -EIO;
-        if ((active & (1 << id)) == 0)
-                return -ENXIO;
-
-        /* Programmed value or real current speed */
-        reg_base = programmed ? 0x10 : 0x11;
-        rc = fan_read_reg(reg_base + (id * 2), buf, 2);
-        if (rc != 2)
-                return -EIO;
-
-        return (buf[0] << (8 - fcu_rpm_shift)) | buf[1] >> fcu_rpm_shift;
-}
-
-static int set_pwm_fan(int fan_index, int pwm)
-{
-        unsigned char buf[2];
-        int rc, id;
-
-        if (fcu_fans[fan_index].type != FCU_FAN_PWM)
-                return -EINVAL;
-        id = fcu_fans[fan_index].id; 
-        if (id == FCU_FAN_ABSENT_ID)
-                return -EINVAL;
-
-        if (pwm < 10)
-                pwm = 10;
-        else if (pwm > 100)
-                pwm = 100;
-        pwm = (pwm * 2559) / 1000;
-        buf[0] = pwm;
-        rc = fan_write_reg(0x30 + (id * 2), buf, 1);
-        if (rc < 0)
-                return rc;
-        return 0;
-}
-
-static int get_pwm_fan(int fan_index)
-{
-        unsigned char failure;
-        unsigned char active;
-        unsigned char buf[2];
-        int rc, id;
-
-        if (fcu_fans[fan_index].type != FCU_FAN_PWM)
-                return -EINVAL;
-        id = fcu_fans[fan_index].id; 
-        if (id == FCU_FAN_ABSENT_ID)
-                return -EINVAL;
-
-        rc = fan_read_reg(0x2b, &failure, 1);
-        if (rc != 1)
-                return -EIO;
-        if ((failure & (1 << id)) != 0)
-                return -EFAULT;
-        rc = fan_read_reg(0x2d, &active, 1);
-        if (rc != 1)
-                return -EIO;
-        if ((active & (1 << id)) == 0)
-                return -ENXIO;
-
-        /* Programmed value or real current speed */
-        rc = fan_read_reg(0x30 + (id * 2), buf, 1);
-        if (rc != 1)
-                return -EIO;
-
-        return (buf[0] * 1000) / 2559;
-}
-
-static void tickle_fcu(void)
-{
-        int pwm;
-
-        pwm = get_pwm_fan(SLOTS_FAN_PWM_INDEX);
-
-        DBG("FCU Tickle, slots fan is: %d\n", pwm);
-        if (pwm < 0)
-                pwm = 100;
-
-        if (!rackmac) {
-                pwm = SLOTS_FAN_DEFAULT_PWM;
-        } else if (pwm < SLOTS_PID_OUTPUT_MIN)
-                pwm = SLOTS_PID_OUTPUT_MIN;
-
-        /* That is hopefully enough to make the FCU happy */
-        set_pwm_fan(SLOTS_FAN_PWM_INDEX, pwm);
-}
-
-
-/*
- * Utility routine to read the CPU calibration EEPROM data
- * from the device-tree
- */
-static int read_eeprom(int cpu, struct mpu_data *out)
-{
-        struct device_node *np;
-        char nodename[64];
-        const u8 *data;
-        int len;
-
-        /* prom.c routine for finding a node by path is a bit brain dead
-         * and requires exact @xxx unit numbers. This is a bit ugly but
-         * will work for these machines
-         */
-        sprintf(nodename, "/u3@0,f8000000/i2c@f8001000/cpuid@a%d", cpu ? 2 : 0);
-        np = of_find_node_by_path(nodename);
-        if (np == NULL) {
-                printk(KERN_ERR "therm_pm72: Failed to retrieve cpuid node from device-tree\n");
-                return -ENODEV;
-        }
-        data = of_get_property(np, "cpuid", &len);
-        if (data == NULL) {
-                printk(KERN_ERR "therm_pm72: Failed to retrieve cpuid property from device-tree\n");
-                of_node_put(np);
-                return -ENODEV;
-        }
-        memcpy(out, data, sizeof(struct mpu_data));
-        of_node_put(np);
-        
-        return 0;
-}
-
-static void fetch_cpu_pumps_minmax(void)
-{
-        struct cpu_pid_state *state0 = &processor_state[0];
-        struct cpu_pid_state *state1 = &processor_state[1];
-        u16 pump_min = 0, pump_max = 0xffff;
-        u16 tmp[4];
-
-        /* Try to fetch pumps min/max infos from eeprom */
-
-        memcpy(&tmp, &state0->mpu.processor_part_num, 8);
-        if (tmp[0] != 0xffff && tmp[1] != 0xffff) {
-                pump_min = max(pump_min, tmp[0]);
-                pump_max = min(pump_max, tmp[1]);
-        }
-        if (tmp[2] != 0xffff && tmp[3] != 0xffff) {
-                pump_min = max(pump_min, tmp[2]);
-                pump_max = min(pump_max, tmp[3]);
-        }
-
-        /* Double check the values, this _IS_ needed as the EEPROM on
-         * some dual 2.5Ghz G5s seem, at least, to have both min & max
-         * same to the same value ... (grrrr)
-         */
-        if (pump_min == pump_max || pump_min == 0 || pump_max == 0xffff) {
-                pump_min = CPU_PUMP_OUTPUT_MIN;
-                pump_max = CPU_PUMP_OUTPUT_MAX;
-        }
-
-        state0->pump_min = state1->pump_min = pump_min;
-        state0->pump_max = state1->pump_max = pump_max;
-}
-
-/* 
- * Now, unfortunately, sysfs doesn't give us a nice void * we could
- * pass around to the attribute functions, so we don't really have
- * choice but implement a bunch of them...
- *
- * That sucks a bit, we take the lock because FIX32TOPRINT evaluates
- * the input twice... I accept patches :)
- */
-#define BUILD_SHOW_FUNC_FIX(name, data)                         \
-static ssize_t show_##name(struct device *dev, struct device_attribute *attr, char *buf)        \
-{                                                               \
-        ssize_t r;                                              \
-        mutex_lock(&driver_lock);                                       \
-        r = sprintf(buf, "%d.%03d", FIX32TOPRINT(data));        \
-        mutex_unlock(&driver_lock);                                     \
-        return r;                                               \
-}
-#define BUILD_SHOW_FUNC_INT(name, data)                         \
-static ssize_t show_##name(struct device *dev, struct device_attribute *attr, char *buf)        \
-{                                                               \
-        return sprintf(buf, "%d", data);                        \
-}
-
-BUILD_SHOW_FUNC_FIX(cpu0_temperature, processor_state[0].last_temp)
-BUILD_SHOW_FUNC_FIX(cpu0_voltage, processor_state[0].voltage)
-BUILD_SHOW_FUNC_FIX(cpu0_current, processor_state[0].current_a)
-BUILD_SHOW_FUNC_INT(cpu0_exhaust_fan_rpm, processor_state[0].rpm)
-BUILD_SHOW_FUNC_INT(cpu0_intake_fan_rpm, processor_state[0].intake_rpm)
-
-BUILD_SHOW_FUNC_FIX(cpu1_temperature, processor_state[1].last_temp)
-BUILD_SHOW_FUNC_FIX(cpu1_voltage, processor_state[1].voltage)
-BUILD_SHOW_FUNC_FIX(cpu1_current, processor_state[1].current_a)
-BUILD_SHOW_FUNC_INT(cpu1_exhaust_fan_rpm, processor_state[1].rpm)
-BUILD_SHOW_FUNC_INT(cpu1_intake_fan_rpm, processor_state[1].intake_rpm)
-
-BUILD_SHOW_FUNC_FIX(backside_temperature, backside_state.last_temp)
-BUILD_SHOW_FUNC_INT(backside_fan_pwm, backside_state.pwm)
-
-BUILD_SHOW_FUNC_FIX(drives_temperature, drives_state.last_temp)
-BUILD_SHOW_FUNC_INT(drives_fan_rpm, drives_state.rpm)
-
-BUILD_SHOW_FUNC_FIX(slots_temperature, slots_state.last_temp)
-BUILD_SHOW_FUNC_INT(slots_fan_pwm, slots_state.pwm)
-
-BUILD_SHOW_FUNC_FIX(dimms_temperature, dimms_state.last_temp)
-
-static DEVICE_ATTR(cpu0_temperature,S_IRUGO,show_cpu0_temperature,NULL);
-static DEVICE_ATTR(cpu0_voltage,S_IRUGO,show_cpu0_voltage,NULL);
-static DEVICE_ATTR(cpu0_current,S_IRUGO,show_cpu0_current,NULL);
-static DEVICE_ATTR(cpu0_exhaust_fan_rpm,S_IRUGO,show_cpu0_exhaust_fan_rpm,NULL);
-static DEVICE_ATTR(cpu0_intake_fan_rpm,S_IRUGO,show_cpu0_intake_fan_rpm,NULL);
-
-static DEVICE_ATTR(cpu1_temperature,S_IRUGO,show_cpu1_temperature,NULL);
-static DEVICE_ATTR(cpu1_voltage,S_IRUGO,show_cpu1_voltage,NULL);
-static DEVICE_ATTR(cpu1_current,S_IRUGO,show_cpu1_current,NULL);
-static DEVICE_ATTR(cpu1_exhaust_fan_rpm,S_IRUGO,show_cpu1_exhaust_fan_rpm,NULL);
-static DEVICE_ATTR(cpu1_intake_fan_rpm,S_IRUGO,show_cpu1_intake_fan_rpm,NULL);
-
-static DEVICE_ATTR(backside_temperature,S_IRUGO,show_backside_temperature,NULL);
-static DEVICE_ATTR(backside_fan_pwm,S_IRUGO,show_backside_fan_pwm,NULL);
-
-static DEVICE_ATTR(drives_temperature,S_IRUGO,show_drives_temperature,NULL);
-static DEVICE_ATTR(drives_fan_rpm,S_IRUGO,show_drives_fan_rpm,NULL);
-
-static DEVICE_ATTR(slots_temperature,S_IRUGO,show_slots_temperature,NULL);
-static DEVICE_ATTR(slots_fan_pwm,S_IRUGO,show_slots_fan_pwm,NULL);
-
-static DEVICE_ATTR(dimms_temperature,S_IRUGO,show_dimms_temperature,NULL);
-
-/*
- * CPUs fans control loop
- */
-
-static int do_read_one_cpu_values(struct cpu_pid_state *state, s32 *temp, s32 *power)
-{
-        s32 ltemp, volts, amps;
-        int index, rc = 0;
-
-        /* Default (in case of error) */
-        *temp = state->cur_temp;
-        *power = state->cur_power;
-
-        if (cpu_pid_type == CPU_PID_TYPE_RACKMAC)
-                index = (state->index == 0) ?
-                        CPU_A1_FAN_RPM_INDEX : CPU_B1_FAN_RPM_INDEX;
-        else
-                index = (state->index == 0) ?
-                        CPUA_EXHAUST_FAN_RPM_INDEX : CPUB_EXHAUST_FAN_RPM_INDEX;
-
-        /* Read current fan status */
-        rc = get_rpm_fan(index, !RPM_PID_USE_ACTUAL_SPEED);
-        if (rc < 0) {
-                /* XXX What do we do now ? Nothing for now, keep old value, but
-                 * return error upstream
-                 */
-                DBG("  cpu %d, fan reading error !\n", state->index);
-        } else {
-                state->rpm = rc;
-                DBG("  cpu %d, exhaust RPM: %d\n", state->index, state->rpm);
-        }
-
-        /* Get some sensor readings and scale it */
-        ltemp = read_smon_adc(state, 1);
-        if (ltemp == -1) {
-                /* XXX What do we do now ? */
-                state->overtemp++;
-                if (rc == 0)
-                        rc = -EIO;
-                DBG("  cpu %d, temp reading error !\n", state->index);
-        } else {
-                /* Fixup temperature according to diode calibration
-                 */
-                DBG("  cpu %d, temp raw: %04x, m_diode: %04x, b_diode: %04x\n",
-                    state->index,
-                    ltemp, state->mpu.mdiode, state->mpu.bdiode);
-                *temp = ((s32)ltemp * (s32)state->mpu.mdiode + ((s32)state->mpu.bdiode << 12)) >> 2;
-                state->last_temp = *temp;
-                DBG("  temp: %d.%03d\n", FIX32TOPRINT((*temp)));
-        }
-
-        /*
-         * Read voltage & current and calculate power
-         */
-        volts = read_smon_adc(state, 3);
-        amps = read_smon_adc(state, 4);
-
-        /* Scale voltage and current raw sensor values according to fixed scales
-         * obtained in Darwin and calculate power from I and V
-         */
-        volts *= ADC_CPU_VOLTAGE_SCALE;
-        amps *= ADC_CPU_CURRENT_SCALE;
-        *power = (((u64)volts) * ((u64)amps)) >> 16;
-        state->voltage = volts;
-        state->current_a = amps;
-        state->last_power = *power;
-
-        DBG("  cpu %d, current: %d.%03d, voltage: %d.%03d, power: %d.%03d W\n",
-            state->index, FIX32TOPRINT(state->current_a),
-            FIX32TOPRINT(state->voltage), FIX32TOPRINT(*power));
-
-        return 0;
-}
-
-static void do_cpu_pid(struct cpu_pid_state *state, s32 temp, s32 power)
-{
-        s32 power_target, integral, derivative, proportional, adj_in_target, sval;
-        s64 integ_p, deriv_p, prop_p, sum; 
-        int i;
-
-        /* Calculate power target value (could be done once for all)
-         * and convert to a 16.16 fp number
-         */
-        power_target = ((u32)(state->mpu.pmaxh - state->mpu.padjmax)) << 16;
-        DBG("  power target: %d.%03d, error: %d.%03d\n",
-            FIX32TOPRINT(power_target), FIX32TOPRINT(power_target - power));
-
-        /* Store temperature and power in history array */
-        state->cur_temp = (state->cur_temp + 1) % CPU_TEMP_HISTORY_SIZE;
-        state->temp_history[state->cur_temp] = temp;
-        state->cur_power = (state->cur_power + 1) % state->count_power;
-        state->power_history[state->cur_power] = power;
-        state->error_history[state->cur_power] = power_target - power;
-        
-        /* If first loop, fill the history table */
-        if (state->first) {
-                for (i = 0; i < (state->count_power - 1); i++) {
-                        state->cur_power = (state->cur_power + 1) % state->count_power;
-                        state->power_history[state->cur_power] = power;
-                        state->error_history[state->cur_power] = power_target - power;
-                }
-                for (i = 0; i < (CPU_TEMP_HISTORY_SIZE - 1); i++) {
-                        state->cur_temp = (state->cur_temp + 1) % CPU_TEMP_HISTORY_SIZE;
-                        state->temp_history[state->cur_temp] = temp;                    
-                }
-                state->first = 0;
-        }
-
-        /* Calculate the integral term normally based on the "power" values */
-        sum = 0;
-        integral = 0;
-        for (i = 0; i < state->count_power; i++)
-                integral += state->error_history[i];
-        integral *= CPU_PID_INTERVAL;
-        DBG("  integral: %08x\n", integral);
-
-        /* Calculate the adjusted input (sense value).
-         *   G_r is 12.20
-         *   integ is 16.16
-         *   so the result is 28.36
-         *
-         * input target is mpu.ttarget, input max is mpu.tmax
-         */
-        integ_p = ((s64)state->mpu.pid_gr) * (s64)integral;
-        DBG("   integ_p: %d\n", (int)(integ_p >> 36));
-        sval = (state->mpu.tmax << 16) - ((integ_p >> 20) & 0xffffffff);
-        adj_in_target = (state->mpu.ttarget << 16);
-        if (adj_in_target > sval)
-                adj_in_target = sval;
-        DBG("   adj_in_target: %d.%03d, ttarget: %d\n", FIX32TOPRINT(adj_in_target),
-            state->mpu.ttarget);
-
-        /* Calculate the derivative term */
-        derivative = state->temp_history[state->cur_temp] -
-                state->temp_history[(state->cur_temp + CPU_TEMP_HISTORY_SIZE - 1)
-                                    % CPU_TEMP_HISTORY_SIZE];
-        derivative /= CPU_PID_INTERVAL;
-        deriv_p = ((s64)state->mpu.pid_gd) * (s64)derivative;
-        DBG("   deriv_p: %d\n", (int)(deriv_p >> 36));
-        sum += deriv_p;
-
-        /* Calculate the proportional term */
-        proportional = temp - adj_in_target;
-        prop_p = ((s64)state->mpu.pid_gp) * (s64)proportional;
-        DBG("   prop_p: %d\n", (int)(prop_p >> 36));
-        sum += prop_p;
-
-        /* Scale sum */
-        sum >>= 36;
-
-        DBG("   sum: %d\n", (int)sum);
-        state->rpm += (s32)sum;
-}
-
-static void do_monitor_cpu_combined(void)
-{
-        struct cpu_pid_state *state0 = &processor_state[0];
-        struct cpu_pid_state *state1 = &processor_state[1];
-        s32 temp0, power0, temp1, power1;
-        s32 temp_combi, power_combi;
-        int rc, intake, pump;
-
-        rc = do_read_one_cpu_values(state0, &temp0, &power0);
-        if (rc < 0) {
-                /* XXX What do we do now ? */
-        }
-        state1->overtemp = 0;
-        rc = do_read_one_cpu_values(state1, &temp1, &power1);
-        if (rc < 0) {
-                /* XXX What do we do now ? */
-        }
-        if (state1->overtemp)
-                state0->overtemp++;
-
-        temp_combi = max(temp0, temp1);
-        power_combi = max(power0, power1);
-
-        /* Check tmax, increment overtemp if we are there. At tmax+8, we go
-         * full blown immediately and try to trigger a shutdown
-         */
-        if (temp_combi >= ((state0->mpu.tmax + 8) << 16)) {
-                printk(KERN_WARNING "Warning ! Temperature way above maximum (%d) !\n",
-                       temp_combi >> 16);
-                state0->overtemp += CPU_MAX_OVERTEMP / 4;
-        } else if (temp_combi > (state0->mpu.tmax << 16)) {
-                state0->overtemp++;
-                printk(KERN_WARNING "Temperature %d above max %d. overtemp %d\n",
-                       temp_combi >> 16, state0->mpu.tmax, state0->overtemp);
-        } else {
-                if (state0->overtemp)
-                        printk(KERN_WARNING "Temperature back down to %d\n",
-                               temp_combi >> 16);
-                state0->overtemp = 0;
-        }
-        if (state0->overtemp >= CPU_MAX_OVERTEMP)
-                critical_state = 1;
-        if (state0->overtemp > 0) {
-                state0->rpm = state0->mpu.rmaxn_exhaust_fan;
-                state0->intake_rpm = intake = state0->mpu.rmaxn_intake_fan;
-                pump = state0->pump_max;
-                goto do_set_fans;
-        }
-
-        /* Do the PID */
-        do_cpu_pid(state0, temp_combi, power_combi);
-
-        /* Range check */
-        state0->rpm = max(state0->rpm, (int)state0->mpu.rminn_exhaust_fan);
-        state0->rpm = min(state0->rpm, (int)state0->mpu.rmaxn_exhaust_fan);
-
-        /* Calculate intake fan speed */
-        intake = (state0->rpm * CPU_INTAKE_SCALE) >> 16;
-        intake = max(intake, (int)state0->mpu.rminn_intake_fan);
-        intake = min(intake, (int)state0->mpu.rmaxn_intake_fan);
-        state0->intake_rpm = intake;
-
-        /* Calculate pump speed */
-        pump = (state0->rpm * state0->pump_max) /
-                state0->mpu.rmaxn_exhaust_fan;
-        pump = min(pump, state0->pump_max);
-        pump = max(pump, state0->pump_min);
-        
- do_set_fans:
-        /* We copy values from state 0 to state 1 for /sysfs */
-        state1->rpm = state0->rpm;
-        state1->intake_rpm = state0->intake_rpm;
-
-        DBG("** CPU %d RPM: %d Ex, %d, Pump: %d, In, overtemp: %d\n",
-            state1->index, (int)state1->rpm, intake, pump, state1->overtemp);
-
-        /* We should check for errors, shouldn't we ? But then, what
-         * do we do once the error occurs ? For FCU notified fan
-         * failures (-EFAULT) we probably want to notify userland
-         * some way...
-         */
-        set_rpm_fan(CPUA_INTAKE_FAN_RPM_INDEX, intake);
-        set_rpm_fan(CPUA_EXHAUST_FAN_RPM_INDEX, state0->rpm);
-        set_rpm_fan(CPUB_INTAKE_FAN_RPM_INDEX, intake);
-        set_rpm_fan(CPUB_EXHAUST_FAN_RPM_INDEX, state0->rpm);
-
-        if (fcu_fans[CPUA_PUMP_RPM_INDEX].id != FCU_FAN_ABSENT_ID)
-                set_rpm_fan(CPUA_PUMP_RPM_INDEX, pump);
-        if (fcu_fans[CPUB_PUMP_RPM_INDEX].id != FCU_FAN_ABSENT_ID)
-                set_rpm_fan(CPUB_PUMP_RPM_INDEX, pump);
-}
-
-static void do_monitor_cpu_split(struct cpu_pid_state *state)
-{
-        s32 temp, power;
-        int rc, intake;
-
-        /* Read current fan status */
-        rc = do_read_one_cpu_values(state, &temp, &power);
-        if (rc < 0) {
-                /* XXX What do we do now ? */
-        }
-
-        /* Check tmax, increment overtemp if we are there. At tmax+8, we go
-         * full blown immediately and try to trigger a shutdown
-         */
-        if (temp >= ((state->mpu.tmax + 8) << 16)) {
-                printk(KERN_WARNING "Warning ! CPU %d temperature way above maximum"
-                       " (%d) !\n",
-                       state->index, temp >> 16);
-                state->overtemp += CPU_MAX_OVERTEMP / 4;
-        } else if (temp > (state->mpu.tmax << 16)) {
-                state->overtemp++;
-                printk(KERN_WARNING "CPU %d temperature %d above max %d. overtemp %d\n",
-                       state->index, temp >> 16, state->mpu.tmax, state->overtemp);
-        } else {
-                if (state->overtemp)
-                        printk(KERN_WARNING "CPU %d temperature back down to %d\n",
-                               state->index, temp >> 16);
-                state->overtemp = 0;
-        }
-        if (state->overtemp >= CPU_MAX_OVERTEMP)
-                critical_state = 1;
-        if (state->overtemp > 0) {
-                state->rpm = state->mpu.rmaxn_exhaust_fan;
-                state->intake_rpm = intake = state->mpu.rmaxn_intake_fan;
-                goto do_set_fans;
-        }
-
-        /* Do the PID */
-        do_cpu_pid(state, temp, power);
-
-        /* Range check */
-        state->rpm = max(state->rpm, (int)state->mpu.rminn_exhaust_fan);
-        state->rpm = min(state->rpm, (int)state->mpu.rmaxn_exhaust_fan);
-
-        /* Calculate intake fan */
-        intake = (state->rpm * CPU_INTAKE_SCALE) >> 16;
-        intake = max(intake, (int)state->mpu.rminn_intake_fan);
-        intake = min(intake, (int)state->mpu.rmaxn_intake_fan);
-        state->intake_rpm = intake;
-
- do_set_fans:
-        DBG("** CPU %d RPM: %d Ex, %d In, overtemp: %d\n",
-            state->index, (int)state->rpm, intake, state->overtemp);
-
-        /* We should check for errors, shouldn't we ? But then, what
-         * do we do once the error occurs ? For FCU notified fan
-         * failures (-EFAULT) we probably want to notify userland
-         * some way...
-         */
-        if (state->index == 0) {
-                set_rpm_fan(CPUA_INTAKE_FAN_RPM_INDEX, intake);
-                set_rpm_fan(CPUA_EXHAUST_FAN_RPM_INDEX, state->rpm);
-        } else {
-                set_rpm_fan(CPUB_INTAKE_FAN_RPM_INDEX, intake);
-                set_rpm_fan(CPUB_EXHAUST_FAN_RPM_INDEX, state->rpm);
-        }
-}
-
-static void do_monitor_cpu_rack(struct cpu_pid_state *state)
-{
-        s32 temp, power, fan_min;
-        int rc;
-
-        /* Read current fan status */
-        rc = do_read_one_cpu_values(state, &temp, &power);
-        if (rc < 0) {
-                /* XXX What do we do now ? */
-        }
-
-        /* Check tmax, increment overtemp if we are there. At tmax+8, we go
-         * full blown immediately and try to trigger a shutdown
-         */
-        if (temp >= ((state->mpu.tmax + 8) << 16)) {
-                printk(KERN_WARNING "Warning ! CPU %d temperature way above maximum"
-                       " (%d) !\n",
-                       state->index, temp >> 16);
-                state->overtemp = CPU_MAX_OVERTEMP / 4;
-        } else if (temp > (state->mpu.tmax << 16)) {
-                state->overtemp++;
-                printk(KERN_WARNING "CPU %d temperature %d above max %d. overtemp %d\n",
-                       state->index, temp >> 16, state->mpu.tmax, state->overtemp);
-        } else {
-                if (state->overtemp)
-                        printk(KERN_WARNING "CPU %d temperature back down to %d\n",
-                               state->index, temp >> 16);
-                state->overtemp = 0;
-        }
-        if (state->overtemp >= CPU_MAX_OVERTEMP)
-                critical_state = 1;
-        if (state->overtemp > 0) {
-                state->rpm = state->intake_rpm = state->mpu.rmaxn_intake_fan;
-                goto do_set_fans;
-        }
-
-        /* Do the PID */
-        do_cpu_pid(state, temp, power);
-
-        /* Check clamp from dimms */
-        fan_min = dimm_output_clamp;
-        fan_min = max(fan_min, (int)state->mpu.rminn_intake_fan);
-
-        DBG(" CPU min mpu = %d, min dimm = %d\n",
-            state->mpu.rminn_intake_fan, dimm_output_clamp);
-
-        state->rpm = max(state->rpm, (int)fan_min);
-        state->rpm = min(state->rpm, (int)state->mpu.rmaxn_intake_fan);
-        state->intake_rpm = state->rpm;
-
- do_set_fans:
-        DBG("** CPU %d RPM: %d overtemp: %d\n",
-            state->index, (int)state->rpm, state->overtemp);
-
-        /* We should check for errors, shouldn't we ? But then, what
-         * do we do once the error occurs ? For FCU notified fan
-         * failures (-EFAULT) we probably want to notify userland
-         * some way...
-         */
-        if (state->index == 0) {
-                set_rpm_fan(CPU_A1_FAN_RPM_INDEX, state->rpm);
-                set_rpm_fan(CPU_A2_FAN_RPM_INDEX, state->rpm);
-                set_rpm_fan(CPU_A3_FAN_RPM_INDEX, state->rpm);
-        } else {
-                set_rpm_fan(CPU_B1_FAN_RPM_INDEX, state->rpm);
-                set_rpm_fan(CPU_B2_FAN_RPM_INDEX, state->rpm);
-                set_rpm_fan(CPU_B3_FAN_RPM_INDEX, state->rpm);
-        }
-}
-
-/*
- * Initialize the state structure for one CPU control loop
- */
-static int init_processor_state(struct cpu_pid_state *state, int index)
-{
-        int err;
-
-        state->index = index;
-        state->first = 1;
-        state->rpm = (cpu_pid_type == CPU_PID_TYPE_RACKMAC) ? 4000 : 1000;
-        state->overtemp = 0;
-        state->adc_config = 0x00;
-
-
-        if (index == 0)
-                state->monitor = attach_i2c_chip(SUPPLY_MONITOR_ID, "CPU0_monitor");
-        else if (index == 1)
-                state->monitor = attach_i2c_chip(SUPPLY_MONITORB_ID, "CPU1_monitor");
-        if (state->monitor == NULL)
-                goto fail;
-
-        if (read_eeprom(index, &state->mpu))
-                goto fail;
-
-        state->count_power = state->mpu.tguardband;
-        if (state->count_power > CPU_POWER_HISTORY_SIZE) {
-                printk(KERN_WARNING "Warning ! too many power history slots\n");
-                state->count_power = CPU_POWER_HISTORY_SIZE;
-        }
-        DBG("CPU %d Using %d power history entries\n", index, state->count_power);
-
-        if (index == 0) {
-                err = device_create_file(&of_dev->dev, &dev_attr_cpu0_temperature);
-                err |= device_create_file(&of_dev->dev, &dev_attr_cpu0_voltage);
-                err |= device_create_file(&of_dev->dev, &dev_attr_cpu0_current);
-                err |= device_create_file(&of_dev->dev, &dev_attr_cpu0_exhaust_fan_rpm);
-                err |= device_create_file(&of_dev->dev, &dev_attr_cpu0_intake_fan_rpm);
-        } else {
-                err = device_create_file(&of_dev->dev, &dev_attr_cpu1_temperature);
-                err |= device_create_file(&of_dev->dev, &dev_attr_cpu1_voltage);
-                err |= device_create_file(&of_dev->dev, &dev_attr_cpu1_current);
-                err |= device_create_file(&of_dev->dev, &dev_attr_cpu1_exhaust_fan_rpm);
-                err |= device_create_file(&of_dev->dev, &dev_attr_cpu1_intake_fan_rpm);
-        }
-        if (err)
-                printk(KERN_WARNING "Failed to create some of the attribute"
-                        "files for CPU %d\n", index);
-
-        return 0;
- fail:
-        state->monitor = NULL;
-        
-        return -ENODEV;
-}
-
-/*
- * Dispose of the state data for one CPU control loop
- */
-static void dispose_processor_state(struct cpu_pid_state *state)
-{
-        if (state->monitor == NULL)
-                return;
-
-        if (state->index == 0) {
-                device_remove_file(&of_dev->dev, &dev_attr_cpu0_temperature);
-                device_remove_file(&of_dev->dev, &dev_attr_cpu0_voltage);
-                device_remove_file(&of_dev->dev, &dev_attr_cpu0_current);
-                device_remove_file(&of_dev->dev, &dev_attr_cpu0_exhaust_fan_rpm);
-                device_remove_file(&of_dev->dev, &dev_attr_cpu0_intake_fan_rpm);
-        } else {
-                device_remove_file(&of_dev->dev, &dev_attr_cpu1_temperature);
-                device_remove_file(&of_dev->dev, &dev_attr_cpu1_voltage);
-                device_remove_file(&of_dev->dev, &dev_attr_cpu1_current);
-                device_remove_file(&of_dev->dev, &dev_attr_cpu1_exhaust_fan_rpm);
-                device_remove_file(&of_dev->dev, &dev_attr_cpu1_intake_fan_rpm);
-        }
-
-        state->monitor = NULL;
-}
-
-/*
- * Motherboard backside & U3 heatsink fan control loop
- */
-static void do_monitor_backside(struct backside_pid_state *state)
-{
-        s32 temp, integral, derivative, fan_min;
-        s64 integ_p, deriv_p, prop_p, sum; 
-        int i, rc;
-
-        if (--state->ticks != 0)
-                return;
-        state->ticks = backside_params.interval;
-
-        DBG("backside:\n");
-
-        /* Check fan status */
-        rc = get_pwm_fan(BACKSIDE_FAN_PWM_INDEX);
-        if (rc < 0) {
-                printk(KERN_WARNING "Error %d reading backside fan !\n", rc);
-                /* XXX What do we do now ? */
-        } else
-                state->pwm = rc;
-        DBG("  current pwm: %d\n", state->pwm);
-
-        /* Get some sensor readings */
-        temp = i2c_smbus_read_byte_data(state->monitor, MAX6690_EXT_TEMP) << 16;
-        state->last_temp = temp;
-        DBG("  temp: %d.%03d, target: %d.%03d\n", FIX32TOPRINT(temp),
-            FIX32TOPRINT(backside_params.input_target));
-
-        /* Store temperature and error in history array */
-        state->cur_sample = (state->cur_sample + 1) % BACKSIDE_PID_HISTORY_SIZE;
-        state->sample_history[state->cur_sample] = temp;
-        state->error_history[state->cur_sample] = temp - backside_params.input_target;
-        
-        /* If first loop, fill the history table */
-        if (state->first) {
-                for (i = 0; i < (BACKSIDE_PID_HISTORY_SIZE - 1); i++) {
-                        state->cur_sample = (state->cur_sample + 1) %
-                                BACKSIDE_PID_HISTORY_SIZE;
-                        state->sample_history[state->cur_sample] = temp;
-                        state->error_history[state->cur_sample] =
-                                temp - backside_params.input_target;
-                }
-                state->first = 0;
-        }
-
-        /* Calculate the integral term */
-        sum = 0;
-        integral = 0;
-        for (i = 0; i < BACKSIDE_PID_HISTORY_SIZE; i++)
-                integral += state->error_history[i];
-        integral *= backside_params.interval;
-        DBG("  integral: %08x\n", integral);
-        integ_p = ((s64)backside_params.G_r) * (s64)integral;
-        DBG("   integ_p: %d\n", (int)(integ_p >> 36));
-        sum += integ_p;
-
-        /* Calculate the derivative term */
-        derivative = state->error_history[state->cur_sample] -
-                state->error_history[(state->cur_sample + BACKSIDE_PID_HISTORY_SIZE - 1)
-                                    % BACKSIDE_PID_HISTORY_SIZE];
-        derivative /= backside_params.interval;
-        deriv_p = ((s64)backside_params.G_d) * (s64)derivative;
-        DBG("   deriv_p: %d\n", (int)(deriv_p >> 36));
-        sum += deriv_p;
-
-        /* Calculate the proportional term */
-        prop_p = ((s64)backside_params.G_p) * (s64)(state->error_history[state->cur_sample]);
-        DBG("   prop_p: %d\n", (int)(prop_p >> 36));
-        sum += prop_p;
-
-        /* Scale sum */
-        sum >>= 36;
-
-        DBG("   sum: %d\n", (int)sum);
-        if (backside_params.additive)
-                state->pwm += (s32)sum;
-        else
-                state->pwm = sum;
-
-        /* Check for clamp */
-        fan_min = (dimm_output_clamp * 100) / 14000;
-        fan_min = max(fan_min, backside_params.output_min);
-
-        state->pwm = max(state->pwm, fan_min);
-        state->pwm = min(state->pwm, backside_params.output_max);
-
-        DBG("** BACKSIDE PWM: %d\n", (int)state->pwm);
-        set_pwm_fan(BACKSIDE_FAN_PWM_INDEX, state->pwm);
-}
-
-/*
- * Initialize the state structure for the backside fan control loop
- */
-static int init_backside_state(struct backside_pid_state *state)
-{
-        struct device_node *u3;
-        int u3h = 1; /* conservative by default */
-        int err;
-
-        /*
-         * There are different PID params for machines with U3 and machines
-         * with U3H, pick the right ones now
-         */
-        u3 = of_find_node_by_path("/u3@0,f8000000");
-        if (u3 != NULL) {
-                const u32 *vers = of_get_property(u3, "device-rev", NULL);
-                if (vers)
-                        if (((*vers) & 0x3f) < 0x34)
-                                u3h = 0;
-                of_node_put(u3);
-        }
-
-        if (rackmac) {
-                backside_params.G_d = BACKSIDE_PID_RACK_G_d;
-                backside_params.input_target = BACKSIDE_PID_RACK_INPUT_TARGET;
-                backside_params.output_min = BACKSIDE_PID_U3H_OUTPUT_MIN;
-                backside_params.interval = BACKSIDE_PID_RACK_INTERVAL;
-                backside_params.G_p = BACKSIDE_PID_RACK_G_p;
-                backside_params.G_r = BACKSIDE_PID_G_r;
-                backside_params.output_max = BACKSIDE_PID_OUTPUT_MAX;
-                backside_params.additive = 0;
-        } else if (u3h) {
-                backside_params.G_d = BACKSIDE_PID_U3H_G_d;
-                backside_params.input_target = BACKSIDE_PID_U3H_INPUT_TARGET;
-                backside_params.output_min = BACKSIDE_PID_U3H_OUTPUT_MIN;
-                backside_params.interval = BACKSIDE_PID_INTERVAL;
-                backside_params.G_p = BACKSIDE_PID_G_p;
-                backside_params.G_r = BACKSIDE_PID_G_r;
-                backside_params.output_max = BACKSIDE_PID_OUTPUT_MAX;
-                backside_params.additive = 1;
-        } else {
-                backside_params.G_d = BACKSIDE_PID_U3_G_d;
-                backside_params.input_target = BACKSIDE_PID_U3_INPUT_TARGET;
-                backside_params.output_min = BACKSIDE_PID_U3_OUTPUT_MIN;
-                backside_params.interval = BACKSIDE_PID_INTERVAL;
-                backside_params.G_p = BACKSIDE_PID_G_p;
-                backside_params.G_r = BACKSIDE_PID_G_r;
-                backside_params.output_max = BACKSIDE_PID_OUTPUT_MAX;
-                backside_params.additive = 1;
-        }
-
-        state->ticks = 1;
-        state->first = 1;
-        state->pwm = 50;
-
-        state->monitor = attach_i2c_chip(BACKSIDE_MAX_ID, "backside_temp");
-        if (state->monitor == NULL)
-                return -ENODEV;
-
-        err = device_create_file(&of_dev->dev, &dev_attr_backside_temperature);
-        err |= device_create_file(&of_dev->dev, &dev_attr_backside_fan_pwm);
-        if (err)
-                printk(KERN_WARNING "Failed to create attribute file(s)"
-                        " for backside fan\n");
-
-        return 0;
-}
-
-/*
- * Dispose of the state data for the backside control loop
- */
-static void dispose_backside_state(struct backside_pid_state *state)
-{
-        if (state->monitor == NULL)
-                return;
-
-        device_remove_file(&of_dev->dev, &dev_attr_backside_temperature);
-        device_remove_file(&of_dev->dev, &dev_attr_backside_fan_pwm);
-
-        state->monitor = NULL;
-}
- 
-/*
- * Drives bay fan control loop
- */
-static void do_monitor_drives(struct drives_pid_state *state)
-{
-        s32 temp, integral, derivative;
-        s64 integ_p, deriv_p, prop_p, sum; 
-        int i, rc;
-
-        if (--state->ticks != 0)
-                return;
-        state->ticks = DRIVES_PID_INTERVAL;
-
-        DBG("drives:\n");
-
-        /* Check fan status */
-        rc = get_rpm_fan(DRIVES_FAN_RPM_INDEX, !RPM_PID_USE_ACTUAL_SPEED);
-        if (rc < 0) {
-                printk(KERN_WARNING "Error %d reading drives fan !\n", rc);
-                /* XXX What do we do now ? */
-        } else
-                state->rpm = rc;
-        DBG("  current rpm: %d\n", state->rpm);
-
-        /* Get some sensor readings */
-        temp = le16_to_cpu(i2c_smbus_read_word_data(state->monitor,
-                                                    DS1775_TEMP)) << 8;
-        state->last_temp = temp;
-        DBG("  temp: %d.%03d, target: %d.%03d\n", FIX32TOPRINT(temp),
-            FIX32TOPRINT(DRIVES_PID_INPUT_TARGET));
-
-        /* Store temperature and error in history array */
-        state->cur_sample = (state->cur_sample + 1) % DRIVES_PID_HISTORY_SIZE;
-        state->sample_history[state->cur_sample] = temp;
-        state->error_history[state->cur_sample] = temp - DRIVES_PID_INPUT_TARGET;
-        
-        /* If first loop, fill the history table */
-        if (state->first) {
-                for (i = 0; i < (DRIVES_PID_HISTORY_SIZE - 1); i++) {
-                        state->cur_sample = (state->cur_sample + 1) %
-                                DRIVES_PID_HISTORY_SIZE;
-                        state->sample_history[state->cur_sample] = temp;
-                        state->error_history[state->cur_sample] =
-                                temp - DRIVES_PID_INPUT_TARGET;
-                }
-                state->first = 0;
-        }
-
-        /* Calculate the integral term */
-        sum = 0;
-        integral = 0;
-        for (i = 0; i < DRIVES_PID_HISTORY_SIZE; i++)
-                integral += state->error_history[i];
-        integral *= DRIVES_PID_INTERVAL;
-        DBG("  integral: %08x\n", integral);
-        integ_p = ((s64)DRIVES_PID_G_r) * (s64)integral;
-        DBG("   integ_p: %d\n", (int)(integ_p >> 36));
-        sum += integ_p;
-
-        /* Calculate the derivative term */
-        derivative = state->error_history[state->cur_sample] -
-                state->error_history[(state->cur_sample + DRIVES_PID_HISTORY_SIZE - 1)
-                                    % DRIVES_PID_HISTORY_SIZE];
-        derivative /= DRIVES_PID_INTERVAL;
-        deriv_p = ((s64)DRIVES_PID_G_d) * (s64)derivative;
-        DBG("   deriv_p: %d\n", (int)(deriv_p >> 36));
-        sum += deriv_p;
-
-        /* Calculate the proportional term */
-        prop_p = ((s64)DRIVES_PID_G_p) * (s64)(state->error_history[state->cur_sample]);
-        DBG("   prop_p: %d\n", (int)(prop_p >> 36));
-        sum += prop_p;
-
-        /* Scale sum */
-        sum >>= 36;
-
-        DBG("   sum: %d\n", (int)sum);
-        state->rpm += (s32)sum;
-
-        state->rpm = max(state->rpm, DRIVES_PID_OUTPUT_MIN);
-        state->rpm = min(state->rpm, DRIVES_PID_OUTPUT_MAX);
-
-        DBG("** DRIVES RPM: %d\n", (int)state->rpm);
-        set_rpm_fan(DRIVES_FAN_RPM_INDEX, state->rpm);
-}
-
-/*
- * Initialize the state structure for the drives bay fan control loop
- */
-static int init_drives_state(struct drives_pid_state *state)
-{
-        int err;
-
-        state->ticks = 1;
-        state->first = 1;
-        state->rpm = 1000;
-
-        state->monitor = attach_i2c_chip(DRIVES_DALLAS_ID, "drives_temp");
-        if (state->monitor == NULL)
-                return -ENODEV;
-
-        err = device_create_file(&of_dev->dev, &dev_attr_drives_temperature);
-        err |= device_create_file(&of_dev->dev, &dev_attr_drives_fan_rpm);
-        if (err)
-                printk(KERN_WARNING "Failed to create attribute file(s)"
-                        " for drives bay fan\n");
-
-        return 0;
-}
-
-/*
- * Dispose of the state data for the drives control loop
- */
-static void dispose_drives_state(struct drives_pid_state *state)
-{
-        if (state->monitor == NULL)
-                return;
-
-        device_remove_file(&of_dev->dev, &dev_attr_drives_temperature);
-        device_remove_file(&of_dev->dev, &dev_attr_drives_fan_rpm);
-
-        state->monitor = NULL;
-}
-
-/*
- * DIMMs temp control loop
- */
-static void do_monitor_dimms(struct dimm_pid_state *state)
-{
-        s32 temp, integral, derivative, fan_min;
-        s64 integ_p, deriv_p, prop_p, sum;
-        int i;
-
-        if (--state->ticks != 0)
-                return;
-        state->ticks = DIMM_PID_INTERVAL;
-
-        DBG("DIMM:\n");
-
-        DBG("  current value: %d\n", state->output);
-
-        temp = read_lm87_reg(state->monitor, LM87_INT_TEMP);
-        if (temp < 0)
-                return;
-        temp <<= 16;
-        state->last_temp = temp;
-        DBG("  temp: %d.%03d, target: %d.%03d\n", FIX32TOPRINT(temp),
-            FIX32TOPRINT(DIMM_PID_INPUT_TARGET));
-
-        /* Store temperature and error in history array */
-        state->cur_sample = (state->cur_sample + 1) % DIMM_PID_HISTORY_SIZE;
-        state->sample_history[state->cur_sample] = temp;
-        state->error_history[state->cur_sample] = temp - DIMM_PID_INPUT_TARGET;
-
-        /* If first loop, fill the history table */
-        if (state->first) {
-                for (i = 0; i < (DIMM_PID_HISTORY_SIZE - 1); i++) {
-                        state->cur_sample = (state->cur_sample + 1) %
-                                DIMM_PID_HISTORY_SIZE;
-                        state->sample_history[state->cur_sample] = temp;
-                        state->error_history[state->cur_sample] =
-                                temp - DIMM_PID_INPUT_TARGET;
-                }
-                state->first = 0;
-        }
-
-        /* Calculate the integral term */
-        sum = 0;
-        integral = 0;
-        for (i = 0; i < DIMM_PID_HISTORY_SIZE; i++)
-                integral += state->error_history[i];
-        integral *= DIMM_PID_INTERVAL;
-        DBG("  integral: %08x\n", integral);
-        integ_p = ((s64)DIMM_PID_G_r) * (s64)integral;
-        DBG("   integ_p: %d\n", (int)(integ_p >> 36));
-        sum += integ_p;
-
-        /* Calculate the derivative term */
-        derivative = state->error_history[state->cur_sample] -
-                state->error_history[(state->cur_sample + DIMM_PID_HISTORY_SIZE - 1)
-                                    % DIMM_PID_HISTORY_SIZE];
-        derivative /= DIMM_PID_INTERVAL;
-        deriv_p = ((s64)DIMM_PID_G_d) * (s64)derivative;
-        DBG("   deriv_p: %d\n", (int)(deriv_p >> 36));
-        sum += deriv_p;
-
-        /* Calculate the proportional term */
-        prop_p = ((s64)DIMM_PID_G_p) * (s64)(state->error_history[state->cur_sample]);
-        DBG("   prop_p: %d\n", (int)(prop_p >> 36));
-        sum += prop_p;
-
-        /* Scale sum */
-        sum >>= 36;
-
-        DBG("   sum: %d\n", (int)sum);
-        state->output = (s32)sum;
-        state->output = max(state->output, DIMM_PID_OUTPUT_MIN);
-        state->output = min(state->output, DIMM_PID_OUTPUT_MAX);
-        dimm_output_clamp = state->output;
-
-        DBG("** DIMM clamp value: %d\n", (int)state->output);
-
-        /* Backside PID is only every 5 seconds, force backside fan clamping now */
-        fan_min = (dimm_output_clamp * 100) / 14000;
-        fan_min = max(fan_min, backside_params.output_min);
-        if (backside_state.pwm < fan_min) {
-                backside_state.pwm = fan_min;
-                DBG(" -> applying clamp to backside fan now: %d  !\n", fan_min);
-                set_pwm_fan(BACKSIDE_FAN_PWM_INDEX, fan_min);
-        }
-}
-
-/*
- * Initialize the state structure for the DIMM temp control loop
- */
-static int init_dimms_state(struct dimm_pid_state *state)
-{
-        state->ticks = 1;
-        state->first = 1;
-        state->output = 4000;
-
-        state->monitor = attach_i2c_chip(XSERVE_DIMMS_LM87, "dimms_temp");
-        if (state->monitor == NULL)
-                return -ENODEV;
-
-        if (device_create_file(&of_dev->dev, &dev_attr_dimms_temperature))
-                printk(KERN_WARNING "Failed to create attribute file"
-                        " for DIMM temperature\n");
-
-        return 0;
-}
-
-/*
- * Dispose of the state data for the DIMM control loop
- */
-static void dispose_dimms_state(struct dimm_pid_state *state)
-{
-        if (state->monitor == NULL)
-                return;
-
-        device_remove_file(&of_dev->dev, &dev_attr_dimms_temperature);
-
-        state->monitor = NULL;
-}
-
-/*
- * Slots fan control loop
- */
-static void do_monitor_slots(struct slots_pid_state *state)
-{
-        s32 temp, integral, derivative;
-        s64 integ_p, deriv_p, prop_p, sum;
-        int i, rc;
-
-        if (--state->ticks != 0)
-                return;
-        state->ticks = SLOTS_PID_INTERVAL;
-
-        DBG("slots:\n");
-
-        /* Check fan status */
-        rc = get_pwm_fan(SLOTS_FAN_PWM_INDEX);
-        if (rc < 0) {
-                printk(KERN_WARNING "Error %d reading slots fan !\n", rc);
-                /* XXX What do we do now ? */
-        } else
-                state->pwm = rc;
-        DBG("  current pwm: %d\n", state->pwm);
-
-        /* Get some sensor readings */
-        temp = le16_to_cpu(i2c_smbus_read_word_data(state->monitor,
-                                                    DS1775_TEMP)) << 8;
-        state->last_temp = temp;
-        DBG("  temp: %d.%03d, target: %d.%03d\n", FIX32TOPRINT(temp),
-            FIX32TOPRINT(SLOTS_PID_INPUT_TARGET));
-
-        /* Store temperature and error in history array */
-        state->cur_sample = (state->cur_sample + 1) % SLOTS_PID_HISTORY_SIZE;
-        state->sample_history[state->cur_sample] = temp;
-        state->error_history[state->cur_sample] = temp - SLOTS_PID_INPUT_TARGET;
-
-        /* If first loop, fill the history table */
-        if (state->first) {
-                for (i = 0; i < (SLOTS_PID_HISTORY_SIZE - 1); i++) {
-                        state->cur_sample = (state->cur_sample + 1) %
-                                SLOTS_PID_HISTORY_SIZE;
-                        state->sample_history[state->cur_sample] = temp;
-                        state->error_history[state->cur_sample] =
-                                temp - SLOTS_PID_INPUT_TARGET;
-                }
-                state->first = 0;
-        }
-
-        /* Calculate the integral term */
-        sum = 0;
-        integral = 0;
-        for (i = 0; i < SLOTS_PID_HISTORY_SIZE; i++)
-                integral += state->error_history[i];
-        integral *= SLOTS_PID_INTERVAL;
-        DBG("  integral: %08x\n", integral);
-        integ_p = ((s64)SLOTS_PID_G_r) * (s64)integral;
-        DBG("   integ_p: %d\n", (int)(integ_p >> 36));
-        sum += integ_p;
-
-        /* Calculate the derivative term */
-        derivative = state->error_history[state->cur_sample] -
-                state->error_history[(state->cur_sample + SLOTS_PID_HISTORY_SIZE - 1)
-                                    % SLOTS_PID_HISTORY_SIZE];
-        derivative /= SLOTS_PID_INTERVAL;
-        deriv_p = ((s64)SLOTS_PID_G_d) * (s64)derivative;
-        DBG("   deriv_p: %d\n", (int)(deriv_p >> 36));
-        sum += deriv_p;
-
-        /* Calculate the proportional term */
-        prop_p = ((s64)SLOTS_PID_G_p) * (s64)(state->error_history[state->cur_sample]);
-        DBG("   prop_p: %d\n", (int)(prop_p >> 36));
-        sum += prop_p;
-
-        /* Scale sum */
-        sum >>= 36;
-
-        DBG("   sum: %d\n", (int)sum);
-        state->pwm = (s32)sum;
-
-        state->pwm = max(state->pwm, SLOTS_PID_OUTPUT_MIN);
-        state->pwm = min(state->pwm, SLOTS_PID_OUTPUT_MAX);
-
-        DBG("** DRIVES PWM: %d\n", (int)state->pwm);
-        set_pwm_fan(SLOTS_FAN_PWM_INDEX, state->pwm);
-}
-
-/*
- * Initialize the state structure for the slots bay fan control loop
- */
-static int init_slots_state(struct slots_pid_state *state)
-{
-        int err;
-
-        state->ticks = 1;
-        state->first = 1;
-        state->pwm = 50;
-
-        state->monitor = attach_i2c_chip(XSERVE_SLOTS_LM75, "slots_temp");
-        if (state->monitor == NULL)
-                return -ENODEV;
-
-        err = device_create_file(&of_dev->dev, &dev_attr_slots_temperature);
-        err |= device_create_file(&of_dev->dev, &dev_attr_slots_fan_pwm);
-        if (err)
-                printk(KERN_WARNING "Failed to create attribute file(s)"
-                        " for slots bay fan\n");
-
-        return 0;
-}
-
-/*
- * Dispose of the state data for the slots control loop
- */
-static void dispose_slots_state(struct slots_pid_state *state)
-{
-        if (state->monitor == NULL)
-                return;
-
-        device_remove_file(&of_dev->dev, &dev_attr_slots_temperature);
-        device_remove_file(&of_dev->dev, &dev_attr_slots_fan_pwm);
-
-        state->monitor = NULL;
-}
-
-
-static int call_critical_overtemp(void)
-{
-        char *argv[] = { critical_overtemp_path, NULL };
-        static char *envp[] = { "HOME=/",
-                                "TERM=linux",
-                                "PATH=/sbin:/usr/sbin:/bin:/usr/bin",
-                                NULL };
-
-        return call_usermodehelper(critical_overtemp_path,
-                                   argv, envp, UMH_WAIT_EXEC);
-}
-
-
-/*
- * Here's the kernel thread that calls the various control loops
- */
-static int main_control_loop(void *x)
-{
-        DBG("main_control_loop started\n");
-
-        mutex_lock(&driver_lock);
-
-        if (start_fcu() < 0) {
-                printk(KERN_ERR "kfand: failed to start FCU\n");
-                mutex_unlock(&driver_lock);
-                goto out;
-        }
-
-        /* Set the PCI fan once for now on non-RackMac */
-        if (!rackmac)
-                set_pwm_fan(SLOTS_FAN_PWM_INDEX, SLOTS_FAN_DEFAULT_PWM);
-
-        /* Initialize ADCs */
-        initialize_adc(&processor_state[0]);
-        if (processor_state[1].monitor != NULL)
-                initialize_adc(&processor_state[1]);
-
-        fcu_tickle_ticks = FCU_TICKLE_TICKS;
-
-        mutex_unlock(&driver_lock);
-
-        while (state == state_attached) {
-                unsigned long elapsed, start;
-
-                start = jiffies;
-
-                mutex_lock(&driver_lock);
-
-                /* Tickle the FCU just in case */
-                if (--fcu_tickle_ticks < 0) {
-                        fcu_tickle_ticks = FCU_TICKLE_TICKS;
-                        tickle_fcu();
-                }
-
-                /* First, we always calculate the new DIMMs state on an Xserve */
-                if (rackmac)
-                        do_monitor_dimms(&dimms_state);
-
-                /* Then, the CPUs */
-                if (cpu_pid_type == CPU_PID_TYPE_COMBINED)
-                        do_monitor_cpu_combined();
-                else if (cpu_pid_type == CPU_PID_TYPE_RACKMAC) {
-                        do_monitor_cpu_rack(&processor_state[0]);
-                        if (processor_state[1].monitor != NULL)
-                                do_monitor_cpu_rack(&processor_state[1]);
-                        // better deal with UP
-                } else {
-                        do_monitor_cpu_split(&processor_state[0]);
-                        if (processor_state[1].monitor != NULL)
-                                do_monitor_cpu_split(&processor_state[1]);
-                        // better deal with UP
-                }
-                /* Then, the rest */
-                do_monitor_backside(&backside_state);
-                if (rackmac)
-                        do_monitor_slots(&slots_state);
-                else
-                        do_monitor_drives(&drives_state);
-                mutex_unlock(&driver_lock);
-
-                if (critical_state == 1) {
-                        printk(KERN_WARNING "Temperature control detected a critical condition\n");
-                        printk(KERN_WARNING "Attempting to shut down...\n");
-                        if (call_critical_overtemp()) {
-                                printk(KERN_WARNING "Can't call %s, power off now!\n",
-                                       critical_overtemp_path);
-                                machine_power_off();
-                        }
-                }
-                if (critical_state > 0)
-                        critical_state++;
-                if (critical_state > MAX_CRITICAL_STATE) {
-                        printk(KERN_WARNING "Shutdown timed out, power off now !\n");
-                        machine_power_off();
-                }
-
-                // FIXME: Deal with signals
-                elapsed = jiffies - start;
-                if (elapsed < HZ)
-                        schedule_timeout_interruptible(HZ - elapsed);
-        }
-
- out:
-        DBG("main_control_loop ended\n");
-
-        ctrl_task = 0;
-        complete_and_exit(&ctrl_complete, 0);
-}
-
-/*
- * Dispose the control loops when tearing down
- */
-static void dispose_control_loops(void)
-{
-        dispose_processor_state(&processor_state[0]);
-        dispose_processor_state(&processor_state[1]);
-        dispose_backside_state(&backside_state);
-        dispose_drives_state(&drives_state);
-        dispose_slots_state(&slots_state);
-        dispose_dimms_state(&dimms_state);
-}
-
-/*
- * Create the control loops. U3-0 i2c bus is up, so we can now
- * get to the various sensors
- */
-static int create_control_loops(void)
-{
-        struct device_node *np;
-
-        /* Count CPUs from the device-tree, we don't care how many are
-         * actually used by Linux
-         */
-        cpu_count = 0;
-        for (np = NULL; NULL != (np = of_find_node_by_type(np, "cpu"));)
-                cpu_count++;
-
-        DBG("counted %d CPUs in the device-tree\n", cpu_count);
-
-        /* Decide the type of PID algorithm to use based on the presence of
-         * the pumps, though that may not be the best way, that is good enough
-         * for now
-         */
-        if (rackmac)
-                cpu_pid_type = CPU_PID_TYPE_RACKMAC;
-        else if (of_machine_is_compatible("PowerMac7,3")
-            && (cpu_count > 1)
-            && fcu_fans[CPUA_PUMP_RPM_INDEX].id != FCU_FAN_ABSENT_ID
-            && fcu_fans[CPUB_PUMP_RPM_INDEX].id != FCU_FAN_ABSENT_ID) {
-                printk(KERN_INFO "Liquid cooling pumps detected, using new algorithm !\n");
-                cpu_pid_type = CPU_PID_TYPE_COMBINED;
-        } else
-                cpu_pid_type = CPU_PID_TYPE_SPLIT;
-
-        /* Create control loops for everything. If any fail, everything
-         * fails
-         */
-        if (init_processor_state(&processor_state[0], 0))
-                goto fail;
-        if (cpu_pid_type == CPU_PID_TYPE_COMBINED)
-                fetch_cpu_pumps_minmax();
-
-        if (cpu_count > 1 && init_processor_state(&processor_state[1], 1))
-                goto fail;
-        if (init_backside_state(&backside_state))
-                goto fail;
-        if (rackmac && init_dimms_state(&dimms_state))
-                goto fail;
-        if (rackmac && init_slots_state(&slots_state))
-                goto fail;
-        if (!rackmac && init_drives_state(&drives_state))
-                goto fail;
-
-        DBG("all control loops up !\n");
-
-        return 0;
-        
- fail:
-        DBG("failure creating control loops, disposing\n");
-
-        dispose_control_loops();
-
-        return -ENODEV;
-}
-
-/*
- * Start the control loops after everything is up, that is create
- * the thread that will make them run
- */
-static void start_control_loops(void)
-{
-        init_completion(&ctrl_complete);
-
-        ctrl_task = kthread_run(main_control_loop, NULL, "kfand");
-}
-
-/*
- * Stop the control loops when tearing down
- */
-static void stop_control_loops(void)
-{
-        if (ctrl_task)
-                wait_for_completion(&ctrl_complete);
-}
-
-/*
- * Attach to the i2c FCU after detecting U3-1 bus
- */
-static int attach_fcu(void)
-{
-        fcu = attach_i2c_chip(FAN_CTRLER_ID, "fcu");
-        if (fcu == NULL)
-                return -ENODEV;
-
-        DBG("FCU attached\n");
-
-        return 0;
-}
-
-/*
- * Detach from the i2c FCU when tearing down
- */
-static void detach_fcu(void)
-{
-        fcu = NULL;
-}
-
-/*
- * Attach to the i2c controller. We probe the various chips based
- * on the device-tree nodes and build everything for the driver to
- * run, we then kick the driver monitoring thread
- */
-static int therm_pm72_attach(struct i2c_adapter *adapter)
-{
-        mutex_lock(&driver_lock);
-
-        /* Check state */
-        if (state == state_detached)
-                state = state_attaching;
-        if (state != state_attaching) {
-                mutex_unlock(&driver_lock);
-                return 0;
-        }
-
-        /* Check if we are looking for one of these */
-        if (u3_0 == NULL && !strcmp(adapter->name, "u3 0")) {
-                u3_0 = adapter;
-                DBG("found U3-0\n");
-                if (k2 || !rackmac)
-                        if (create_control_loops())
-                                u3_0 = NULL;
-        } else if (u3_1 == NULL && !strcmp(adapter->name, "u3 1")) {
-                u3_1 = adapter;
-                DBG("found U3-1, attaching FCU\n");
-                if (attach_fcu())
-                        u3_1 = NULL;
-        } else if (k2 == NULL && !strcmp(adapter->name, "mac-io 0")) {
-                k2 = adapter;
-                DBG("Found K2\n");
-                if (u3_0 && rackmac)
-                        if (create_control_loops())
-                                k2 = NULL;
-        }
-        /* We got all we need, start control loops */
-        if (u3_0 != NULL && u3_1 != NULL && (k2 || !rackmac)) {
-                DBG("everything up, starting control loops\n");
-                state = state_attached;
-                start_control_loops();
-        }
-        mutex_unlock(&driver_lock);
-
-        return 0;
-}
-
-static int therm_pm72_probe(struct i2c_client *client,
-                            const struct i2c_device_id *id)
-{
-        /* Always succeed, the real work was done in therm_pm72_attach() */
-        return 0;
-}
-
-/*
- * Called when any of the devices which participates into thermal management
- * is going away.
- */
-static int therm_pm72_remove(struct i2c_client *client)
-{
-        struct i2c_adapter *adapter = client->adapter;
-
-        mutex_lock(&driver_lock);
-
-        if (state != state_detached)
-                state = state_detaching;
-
-        /* Stop control loops if any */
-        DBG("stopping control loops\n");
-        mutex_unlock(&driver_lock);
-        stop_control_loops();
-        mutex_lock(&driver_lock);
-
-        if (u3_0 != NULL && !strcmp(adapter->name, "u3 0")) {
-                DBG("lost U3-0, disposing control loops\n");
-                dispose_control_loops();
-                u3_0 = NULL;
-        }
-        
-        if (u3_1 != NULL && !strcmp(adapter->name, "u3 1")) {
-                DBG("lost U3-1, detaching FCU\n");
-                detach_fcu();
-                u3_1 = NULL;
-        }
-        if (u3_0 == NULL && u3_1 == NULL)
-                state = state_detached;
-
-        mutex_unlock(&driver_lock);
-
-        return 0;
-}
-
-/*
- * i2c_driver structure to attach to the host i2c controller
- */
-
-static const struct i2c_device_id therm_pm72_id[] = {
-        /*
-         * Fake device name, thermal management is done by several
-         * chips but we don't need to differentiate between them at
-         * this point.
-         */
-        { "therm_pm72", 0 },
-        { }
-};
-
-static struct i2c_driver therm_pm72_driver = {
-        .driver = {
-                .name   = "therm_pm72",
-        },
-        .attach_adapter = therm_pm72_attach,
-        .probe          = therm_pm72_probe,
-        .remove         = therm_pm72_remove,
-        .id_table       = therm_pm72_id,
-};
-
-static int fan_check_loc_match(const char *loc, int fan)
-{
-        char    tmp[64];
-        char    *c, *e;
-
-        strlcpy(tmp, fcu_fans[fan].loc, 64);
-
-        c = tmp;
-        for (;;) {
-                e = strchr(c, ',');
-                if (e)
-                        *e = 0;
-                if (strcmp(loc, c) == 0)
-                        return 1;
-                if (e == NULL)
-                        break;
-                c = e + 1;
-        }
-        return 0;
-}
-
-static void fcu_lookup_fans(struct device_node *fcu_node)
-{
-        struct device_node *np = NULL;
-        int i;
-
-        /* The table is filled by default with values that are suitable
-         * for the old machines without device-tree informations. We scan
-         * the device-tree and override those values with whatever is
-         * there
-         */
-
-        DBG("Looking up FCU controls in device-tree...\n");
-
-        while ((np = of_get_next_child(fcu_node, np)) != NULL) {
-                int type = -1;
-                const char *loc;
-                const u32 *reg;
-
-                DBG(" control: %s, type: %s\n", np->name, np->type);
-
-                /* Detect control type */
-                if (!strcmp(np->type, "fan-rpm-control") ||
-                    !strcmp(np->type, "fan-rpm"))
-                        type = FCU_FAN_RPM;
-                if (!strcmp(np->type, "fan-pwm-control") ||
-                    !strcmp(np->type, "fan-pwm"))
-                        type = FCU_FAN_PWM;
-                /* Only care about fans for now */
-                if (type == -1)
-                        continue;
-
-                /* Lookup for a matching location */
-                loc = of_get_property(np, "location", NULL);
-                reg = of_get_property(np, "reg", NULL);
-                if (loc == NULL || reg == NULL)
-                        continue;
-                DBG(" matching location: %s, reg: 0x%08x\n", loc, *reg);
-
-                for (i = 0; i < FCU_FAN_COUNT; i++) {
-                        int fan_id;
-
-                        if (!fan_check_loc_match(loc, i))
-                                continue;
-                        DBG(" location match, index: %d\n", i);
-                        fcu_fans[i].id = FCU_FAN_ABSENT_ID;
-                        if (type != fcu_fans[i].type) {
-                                printk(KERN_WARNING "therm_pm72: Fan type mismatch "
-                                       "in device-tree for %s\n", np->full_name);
-                                break;
-                        }
-                        if (type == FCU_FAN_RPM)
-                                fan_id = ((*reg) - 0x10) / 2;
-                        else
-                                fan_id = ((*reg) - 0x30) / 2;
-                        if (fan_id > 7) {
-                                printk(KERN_WARNING "therm_pm72: Can't parse "
-                                       "fan ID in device-tree for %s\n", np->full_name);
-                                break;
-                        }
-                        DBG(" fan id -> %d, type -> %d\n", fan_id, type);
-                        fcu_fans[i].id = fan_id;
-                }
-        }
-
-        /* Now dump the array */
-        printk(KERN_INFO "Detected fan controls:\n");
-        for (i = 0; i < FCU_FAN_COUNT; i++) {
-                if (fcu_fans[i].id == FCU_FAN_ABSENT_ID)
-                        continue;
-                printk(KERN_INFO "  %d: %s fan, id %d, location: %s\n", i,
-                       fcu_fans[i].type == FCU_FAN_RPM ? "RPM" : "PWM",
-                       fcu_fans[i].id, fcu_fans[i].loc);
-        }
-}
-
-static int fcu_of_probe(struct platform_device* dev)
-{
-        state = state_detached;
-        of_dev = dev;
-
-        dev_info(&dev->dev, "PowerMac G5 Thermal control driver %s\n", VERSION);
-
-        /* Lookup the fans in the device tree */
-        fcu_lookup_fans(dev->dev.of_node);
-
-        /* Add the driver */
-        return i2c_add_driver(&therm_pm72_driver);
-}
-
-static int fcu_of_remove(struct platform_device* dev)
-{
-        i2c_del_driver(&therm_pm72_driver);
-
-        return 0;
-}
-
-static const struct of_device_id fcu_match[] = 
-{
-        {
-        .type           = "fcu",
-        },
-        {},
-};
-MODULE_DEVICE_TABLE(of, fcu_match);
-
-static struct platform_driver fcu_of_platform_driver = 
-{
-        .driver = {
-                .name = "temperature",
-                .of_match_table = fcu_match,
-        },
-        .probe          = fcu_of_probe,
-        .remove         = fcu_of_remove
-};
-
-/*
- * Check machine type, attach to i2c controller
- */
-static int __init therm_pm72_init(void)
-{
-        rackmac = of_machine_is_compatible("RackMac3,1");
-
-        if (!of_machine_is_compatible("PowerMac7,2") &&
-            !of_machine_is_compatible("PowerMac7,3") &&
-            !rackmac)
-                return -ENODEV;
-
-        return platform_driver_register(&fcu_of_platform_driver);
-}
-
-static void __exit therm_pm72_exit(void)
-{
-        platform_driver_unregister(&fcu_of_platform_driver);
-}
-
-module_init(therm_pm72_init);
-module_exit(therm_pm72_exit);
-
-MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
-MODULE_DESCRIPTION("Driver for Apple's PowerMac G5 thermal control");
-MODULE_LICENSE("GPL");
-
diff --git a/drivers/macintosh/therm_pm72.h b/drivers/macintosh/therm_pm72.h
deleted file mode 100644
index df3680e2a22f..000000000000
--- a/drivers/macintosh/therm_pm72.h
+++ /dev/null
@@ -1,326 +0,0 @@
-#ifndef __THERM_PMAC_7_2_H__
-#define __THERM_PMAC_7_2_H__
-
-typedef unsigned short fu16;
-typedef int fs32;
-typedef short fs16;
-
-struct mpu_data
-{
-        u8      signature;              /* 0x00 - EEPROM sig. */
-        u8      bytes_used;             /* 0x01 - Bytes used in eeprom (160 ?) */
-        u8      size;                   /* 0x02 - EEPROM size (256 ?) */
-        u8      version;                /* 0x03 - EEPROM version */
-        u32     data_revision;          /* 0x04 - Dataset revision */
-        u8      processor_bin_code[3];  /* 0x08 - Processor BIN code */
-        u8      bin_code_expansion;     /* 0x0b - ??? (padding ?) */
-        u8      processor_num;          /* 0x0c - Number of CPUs on this MPU */
-        u8      input_mul_bus_div;      /* 0x0d - Clock input multiplier/bus divider */
-        u8      reserved1[2];           /* 0x0e - */
-        u32     input_clk_freq_high;    /* 0x10 - Input clock frequency high */
-        u8      cpu_nb_target_cycles;   /* 0x14 - ??? */
-        u8      cpu_statlat;            /* 0x15 - ??? */
-        u8      cpu_snooplat;           /* 0x16 - ??? */
-        u8      cpu_snoopacc;           /* 0x17 - ??? */
-        u8      nb_paamwin;             /* 0x18 - ??? */
-        u8      nb_statlat;             /* 0x19 - ??? */
-        u8      nb_snooplat;            /* 0x1a - ??? */
-        u8      nb_snoopwin;            /* 0x1b - ??? */
-        u8      api_bus_mode;           /* 0x1c - ??? */
-        u8      reserved2[3];           /* 0x1d - */
-        u32     input_clk_freq_low;     /* 0x20 - Input clock frequency low */
-        u8      processor_card_slot;    /* 0x24 - Processor card slot number */
-        u8      reserved3[2];           /* 0x25 - */
-        u8      padjmax;                /* 0x27 - Max power adjustment (Not in OF!) */
-        u8      ttarget;                /* 0x28 - Target temperature */
-        u8      tmax;                   /* 0x29 - Max temperature */
-        u8      pmaxh;                  /* 0x2a - Max power */
-        u8      tguardband;             /* 0x2b - Guardband temp ??? Hist. len in OSX */
-        fs32    pid_gp;                 /* 0x2c - PID proportional gain */
-        fs32    pid_gr;                 /* 0x30 - PID reset gain */
-        fs32    pid_gd;                 /* 0x34 - PID derivative gain */
-        fu16    voph;                   /* 0x38 - Vop High */
-        fu16    vopl;                   /* 0x3a - Vop Low */
-        fs16    nactual_die;            /* 0x3c - nActual Die */
-        fs16    nactual_heatsink;       /* 0x3e - nActual Heatsink */
-        fs16    nactual_system;         /* 0x40 - nActual System */
-        u16     calibration_flags;      /* 0x42 - Calibration flags */
-        fu16    mdiode;                 /* 0x44 - Diode M value (scaling factor) */
-        fs16    bdiode;                 /* 0x46 - Diode B value (offset) */
-        fs32    theta_heat_sink;        /* 0x48 - Theta heat sink */
-        u16     rminn_intake_fan;       /* 0x4c - Intake fan min RPM */
-        u16     rmaxn_intake_fan;       /* 0x4e - Intake fan max RPM */
-        u16     rminn_exhaust_fan;      /* 0x50 - Exhaust fan min RPM */
-        u16     rmaxn_exhaust_fan;      /* 0x52 - Exhaust fan max RPM */
-        u8      processor_part_num[8];  /* 0x54 - Processor part number XX pumps min/max */
-        u32     processor_lot_num;      /* 0x5c - Processor lot number */
-        u8      orig_card_sernum[0x10]; /* 0x60 - Card original serial number */
-        u8      curr_card_sernum[0x10]; /* 0x70 - Card current serial number */
-        u8      mlb_sernum[0x18];       /* 0x80 - MLB serial number */
-        u32     checksum1;              /* 0x98 - */
-        u32     checksum2;              /* 0x9c - */    
-}; /* Total size = 0xa0 */
-
-/* Display a 16.16 fixed point value */
-#define FIX32TOPRINT(f) ((f) >> 16),((((f) & 0xffff) * 1000) >> 16)
-
-/*
- * Maximum number of seconds to be in critical state (after a
- * normal shutdown attempt). If the machine isn't down after
- * this counter elapses, we force an immediate machine power
- * off.
- */
-#define MAX_CRITICAL_STATE                      30
-static char * critical_overtemp_path = "/sbin/critical_overtemp";
-
-/*
- * This option is "weird" :) Basically, if you define this to 1
- * the control loop for the RPMs fans (not PWMs) will apply the
- * correction factor obtained from the PID to the _actual_ RPM
- * speed read from the FCU.
- * If you define the below constant to 0, then it will be
- * applied to the setpoint RPM speed, that is basically the
- * speed we proviously "asked" for.
- *
- * I'm not sure which of these Apple's algorithm is supposed
- * to use
- */
-#define RPM_PID_USE_ACTUAL_SPEED                0
-
-/*
- * i2c IDs. Currently, we hard code those and assume that
- * the FCU is on U3 bus 1 while all sensors are on U3 bus
- * 0. This appear to be safe enough for this first version
- * of the driver, though I would accept any clean patch
- * doing a better use of the device-tree without turning the
- * while i2c registration mechanism into a racy mess
- *
- * Note: Xserve changed this. We have some bits on the K2 bus,
- * which I arbitrarily set to 0x200. Ultimately, we really want
- * too lookup these in the device-tree though
- */
-#define FAN_CTRLER_ID           0x15e
-#define SUPPLY_MONITOR_ID       0x58
-#define SUPPLY_MONITORB_ID      0x5a
-#define DRIVES_DALLAS_ID        0x94
-#define BACKSIDE_MAX_ID         0x98
-#define XSERVE_DIMMS_LM87       0x25a
-#define XSERVE_SLOTS_LM75       0x290
-
-/*
- * Some MAX6690, DS1775, LM87 register definitions
- */
-#define MAX6690_INT_TEMP        0
-#define MAX6690_EXT_TEMP        1
-#define DS1775_TEMP             0
-#define LM87_INT_TEMP           0x27
-
-/*
- * Scaling factors for the AD7417 ADC converters (except
- * for the CPU diode which is obtained from the EEPROM).
- * Those values are obtained from the property list of
- * the darwin driver
- */
-#define ADC_12V_CURRENT_SCALE   0x0320  /* _AD2 */
-#define ADC_CPU_VOLTAGE_SCALE   0x00a0  /* _AD3 */
-#define ADC_CPU_CURRENT_SCALE   0x1f40  /* _AD4 */
-
-/*
- * PID factors for the U3/Backside fan control loop. We have 2 sets
- * of values here, one set for U3 and one set for U3H
- */
-#define BACKSIDE_FAN_PWM_DEFAULT_ID     1
-#define BACKSIDE_FAN_PWM_INDEX          0
-#define BACKSIDE_PID_U3_G_d             0x02800000
-#define BACKSIDE_PID_U3H_G_d            0x01400000
-#define BACKSIDE_PID_RACK_G_d           0x00500000
-#define BACKSIDE_PID_G_p                0x00500000
-#define BACKSIDE_PID_RACK_G_p           0x0004cccc
-#define BACKSIDE_PID_G_r                0x00000000
-#define BACKSIDE_PID_U3_INPUT_TARGET    0x00410000
-#define BACKSIDE_PID_U3H_INPUT_TARGET   0x004b0000
-#define BACKSIDE_PID_RACK_INPUT_TARGET  0x00460000
-#define BACKSIDE_PID_INTERVAL           5
-#define BACKSIDE_PID_RACK_INTERVAL      1
-#define BACKSIDE_PID_OUTPUT_MAX         100
-#define BACKSIDE_PID_U3_OUTPUT_MIN      20
-#define BACKSIDE_PID_U3H_OUTPUT_MIN     20
-#define BACKSIDE_PID_HISTORY_SIZE       2
-
-struct basckside_pid_params
-{
-        s32                     G_d;
-        s32                     G_p;
-        s32                     G_r;
-        s32                     input_target;
-        s32                     output_min;
-        s32                     output_max;
-        s32                     interval;
-        int                     additive;
-};
-
-struct backside_pid_state
-{
-        int                     ticks;
-        struct i2c_client *     monitor;
-        s32                     sample_history[BACKSIDE_PID_HISTORY_SIZE];
-        s32                     error_history[BACKSIDE_PID_HISTORY_SIZE];
-        int                     cur_sample;
-        s32                     last_temp;
-        int                     pwm;
-        int                     first;
-};
-
-/*
- * PID factors for the Drive Bay fan control loop
- */
-#define DRIVES_FAN_RPM_DEFAULT_ID       2
-#define DRIVES_FAN_RPM_INDEX            1
-#define DRIVES_PID_G_d                  0x01e00000
-#define DRIVES_PID_G_p                  0x00500000
-#define DRIVES_PID_G_r                  0x00000000
-#define DRIVES_PID_INPUT_TARGET         0x00280000
-#define DRIVES_PID_INTERVAL             5
-#define DRIVES_PID_OUTPUT_MAX           4000
-#define DRIVES_PID_OUTPUT_MIN           300
-#define DRIVES_PID_HISTORY_SIZE         2
-
-struct drives_pid_state
-{
-        int                     ticks;
-        struct i2c_client *     monitor;
-        s32                     sample_history[BACKSIDE_PID_HISTORY_SIZE];
-        s32                     error_history[BACKSIDE_PID_HISTORY_SIZE];
-        int                     cur_sample;
-        s32                     last_temp;
-        int                     rpm;
-        int                     first;
-};
-
-#define SLOTS_FAN_PWM_DEFAULT_ID        2
-#define SLOTS_FAN_PWM_INDEX             2
-#define SLOTS_FAN_DEFAULT_PWM           40 /* Do better here ! */
-
-
-/*
- * PID factors for the Xserve DIMM control loop
- */
-#define DIMM_PID_G_d                    0
-#define DIMM_PID_G_p                    0
-#define DIMM_PID_G_r                    0x06553600
-#define DIMM_PID_INPUT_TARGET           3276800
-#define DIMM_PID_INTERVAL               1
-#define DIMM_PID_OUTPUT_MAX             14000
-#define DIMM_PID_OUTPUT_MIN             4000
-#define DIMM_PID_HISTORY_SIZE           20
-
-struct dimm_pid_state
-{
-        int                     ticks;
-        struct i2c_client *     monitor;
-        s32                     sample_history[DIMM_PID_HISTORY_SIZE];
-        s32                     error_history[DIMM_PID_HISTORY_SIZE];
-        int                     cur_sample;
-        s32                     last_temp;
-        int                     first;
-        int                     output;
-};
-
-
-/*
- * PID factors for the Xserve Slots control loop
- */
-#define SLOTS_PID_G_d                   0
-#define SLOTS_PID_G_p                   0
-#define SLOTS_PID_G_r                   0x00100000
-#define SLOTS_PID_INPUT_TARGET          3200000
-#define SLOTS_PID_INTERVAL              1
-#define SLOTS_PID_OUTPUT_MAX            100
-#define SLOTS_PID_OUTPUT_MIN            20
-#define SLOTS_PID_HISTORY_SIZE          20
-
-struct slots_pid_state
-{
-        int                     ticks;
-        struct i2c_client *     monitor;
-        s32                     sample_history[SLOTS_PID_HISTORY_SIZE];
-        s32                     error_history[SLOTS_PID_HISTORY_SIZE];
-        int                     cur_sample;
-        s32                     last_temp;
-        int                     first;
-        int                     pwm;
-};
-
-
-
-/* Desktops */
-
-#define CPUA_INTAKE_FAN_RPM_DEFAULT_ID  3
-#define CPUA_EXHAUST_FAN_RPM_DEFAULT_ID 4
-#define CPUB_INTAKE_FAN_RPM_DEFAULT_ID  5
-#define CPUB_EXHAUST_FAN_RPM_DEFAULT_ID 6
-
-#define CPUA_INTAKE_FAN_RPM_INDEX       3
-#define CPUA_EXHAUST_FAN_RPM_INDEX      4
-#define CPUB_INTAKE_FAN_RPM_INDEX       5
-#define CPUB_EXHAUST_FAN_RPM_INDEX      6
-
-#define CPU_INTAKE_SCALE                0x0000f852
-#define CPU_TEMP_HISTORY_SIZE           2
-#define CPU_POWER_HISTORY_SIZE          10
-#define CPU_PID_INTERVAL                1
-#define CPU_MAX_OVERTEMP                90
-
-#define CPUA_PUMP_RPM_INDEX             7
-#define CPUB_PUMP_RPM_INDEX             8
-#define CPU_PUMP_OUTPUT_MAX             3200
-#define CPU_PUMP_OUTPUT_MIN             1250
-
-/* Xserve */
-#define CPU_A1_FAN_RPM_INDEX            9
-#define CPU_A2_FAN_RPM_INDEX            10
-#define CPU_A3_FAN_RPM_INDEX            11
-#define CPU_B1_FAN_RPM_INDEX            12
-#define CPU_B2_FAN_RPM_INDEX            13
-#define CPU_B3_FAN_RPM_INDEX            14
-
-
-struct cpu_pid_state
-{
-        int                     index;
-        struct i2c_client *     monitor;
-        struct mpu_data         mpu;
-        int                     overtemp;
-        s32                     temp_history[CPU_TEMP_HISTORY_SIZE];
-        int                     cur_temp;
-        s32                     power_history[CPU_POWER_HISTORY_SIZE];
-        s32                     error_history[CPU_POWER_HISTORY_SIZE];
-        int                     cur_power;
-        int                     count_power;
-        int                     rpm;
-        int                     intake_rpm;
-        s32                     voltage;
-        s32                     current_a;
-        s32                     last_temp;
-        s32                     last_power;
-        int                     first;
-        u8                      adc_config;
-        s32                     pump_min;
-        s32                     pump_max;
-};
-
-/* Tickle FCU every 10 seconds */
-#define FCU_TICKLE_TICKS        10
-
-/*
- * Driver state
- */
-enum {
-        state_detached,
-        state_attaching,
-        state_attached,
-        state_detaching,
-};
-
-
-#endif /* __THERM_PMAC_7_2_H__ */
diff --git a/drivers/md/dm-thin.c b/drivers/md/dm-thin.c
index 8735543eacdb..493478989dbd 100644
--- a/drivers/md/dm-thin.c
+++ b/drivers/md/dm-thin.c
@@ -1127,6 +1127,24 @@ static void schedule_external_copy(struct thin_c *tc, dm_block_t virt_block,
                 schedule_zero(tc, virt_block, data_dest, cell, bio);
 }
 
+static void set_pool_mode(struct pool *pool, enum pool_mode new_mode);
+
+static void check_for_space(struct pool *pool)
+{
+        int r;
+        dm_block_t nr_free;
+
+        if (get_pool_mode(pool) != PM_OUT_OF_DATA_SPACE)
+                return;
+
+        r = dm_pool_get_free_block_count(pool->pmd, &nr_free);
+        if (r)
+                return;
+
+        if (nr_free)
+                set_pool_mode(pool, PM_WRITE);
+}
+
 /*
  * A non-zero return indicates read_only or fail_io mode.
  * Many callers don't care about the return value.
@@ -1141,6 +1159,8 @@ static int commit(struct pool *pool)
         r = dm_pool_commit_metadata(pool->pmd);
         if (r)
                 metadata_operation_failed(pool, "dm_pool_commit_metadata", r);
+        else
+                check_for_space(pool);
 
         return r;
 }
@@ -1159,8 +1179,6 @@ static void check_low_water_mark(struct pool *pool, dm_block_t free_blocks)
         }
 }
 
-static void set_pool_mode(struct pool *pool, enum pool_mode new_mode);
-
 static int alloc_data_block(struct thin_c *tc, dm_block_t *result)
 {
         int r;
@@ -2155,7 +2173,7 @@ static void set_pool_mode(struct pool *pool, enum pool_mode new_mode)
                 pool->process_cell = process_cell_read_only;
                 pool->process_discard_cell = process_discard_cell;
                 pool->process_prepared_mapping = process_prepared_mapping;
-                pool->process_prepared_discard = process_prepared_discard_passdown;
+                pool->process_prepared_discard = process_prepared_discard;
 
                 if (!pool->pf.error_if_no_space && no_space_timeout)
                         queue_delayed_work(pool->wq, &pool->no_space_timeout, no_space_timeout);
@@ -3814,6 +3832,8 @@ static int thin_ctr(struct dm_target *ti, unsigned argc, char **argv)
                 r = -EINVAL;
                 goto bad;
         }
+        atomic_set(&tc->refcount, 1);
+        init_completion(&tc->can_destroy);
         list_add_tail_rcu(&tc->list, &tc->pool->active_thins);
         spin_unlock_irqrestore(&tc->pool->lock, flags);
         /*
@@ -3826,9 +3846,6 @@ static int thin_ctr(struct dm_target *ti, unsigned argc, char **argv)
 
         dm_put(pool_md);
 
-        atomic_set(&tc->refcount, 1);
-        init_completion(&tc->can_destroy);
-
         return 0;
 
 bad:
diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index 4c06585bf165..b98cd9d84435 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -899,7 +899,7 @@ static void disable_write_same(struct mapped_device *md)
 
 static void clone_endio(struct bio *bio, int error)
 {
-        int r = 0;
+        int r = error;
         struct dm_target_io *tio = container_of(bio, struct dm_target_io, clone);
         struct dm_io *io = tio->io;
         struct mapped_device *md = tio->io->md;
diff --git a/drivers/scsi/53c700.c b/drivers/scsi/53c700.c
index aa915da2a5e5..82abfce1cb42 100644
--- a/drivers/scsi/53c700.c
+++ b/drivers/scsi/53c700.c
@@ -176,7 +176,6 @@ STATIC int NCR_700_slave_alloc(struct scsi_device *SDpnt);
 STATIC int NCR_700_slave_configure(struct scsi_device *SDpnt);
 STATIC void NCR_700_slave_destroy(struct scsi_device *SDpnt);
 static int NCR_700_change_queue_depth(struct scsi_device *SDpnt, int depth);
-static int NCR_700_change_queue_type(struct scsi_device *SDpnt, int depth);
 
 STATIC struct device_attribute *NCR_700_dev_attrs[];
 
@@ -326,7 +325,6 @@ NCR_700_detect(struct scsi_host_template *tpnt,
         tpnt->slave_destroy = NCR_700_slave_destroy;
         tpnt->slave_alloc = NCR_700_slave_alloc;
         tpnt->change_queue_depth = NCR_700_change_queue_depth;
-        tpnt->change_queue_type = NCR_700_change_queue_type;
         tpnt->use_blk_tags = 1;
 
         if(tpnt->name == NULL)
@@ -904,8 +902,8 @@ process_message(struct Scsi_Host *host,	struct NCR_700_Host_Parameters *hostdata
                         hostdata->tag_negotiated &= ~(1<<scmd_id(SCp));
 
                         SCp->device->tagged_supported = 0;
+                        SCp->device->simple_tags = 0;
                         scsi_change_queue_depth(SCp->device, host->cmd_per_lun);
-                        scsi_set_tag_type(SCp->device, 0);
                 } else {
                         shost_printk(KERN_WARNING, host,
                                 "(%d:%d) Unexpected REJECT Message %s\n",
@@ -1818,8 +1816,8 @@ NCR_700_queuecommand_lck(struct scsi_cmnd *SCp, void (*done)(struct scsi_cmnd *)
                 hostdata->tag_negotiated &= ~(1<<scmd_id(SCp));
         }
 
-        if((hostdata->tag_negotiated &(1<<scmd_id(SCp)))
-           && scsi_get_tag_type(SCp->device)) {
+        if ((hostdata->tag_negotiated & (1<<scmd_id(SCp))) &&
+            SCp->device->simple_tags) {
                 slot->tag = SCp->request->tag;
                 CDEBUG(KERN_DEBUG, SCp, "sending out tag %d, slot %p\n",
                        slot->tag, slot);
@@ -2082,39 +2080,6 @@ NCR_700_change_queue_depth(struct scsi_device *SDp, int depth)
         return scsi_change_queue_depth(SDp, depth);
 }
 
-static int NCR_700_change_queue_type(struct scsi_device *SDp, int tag_type)
-{
-        int change_tag = ((tag_type ==0 &&  scsi_get_tag_type(SDp) != 0)
-                          || (tag_type != 0 && scsi_get_tag_type(SDp) == 0));
-        struct NCR_700_Host_Parameters *hostdata = 
-                (struct NCR_700_Host_Parameters *)SDp->host->hostdata[0];
-
-        /* We have a global (per target) flag to track whether TCQ is
-         * enabled, so we'll be turning it off for the entire target here.
-         * our tag algorithm will fail if we mix tagged and untagged commands,
-         * so quiesce the device before doing this */
-        if (change_tag)
-                scsi_target_quiesce(SDp->sdev_target);
-
-        scsi_set_tag_type(SDp, tag_type);
-        if (!tag_type) {
-                /* shift back to the default unqueued number of commands
-                 * (the user can still raise this) */
-                scsi_change_queue_depth(SDp, SDp->host->cmd_per_lun);
-                hostdata->tag_negotiated &= ~(1 << sdev_id(SDp));
-        } else {
-                /* Here, we cleared the negotiation flag above, so this
-                 * will force the driver to renegotiate */
-                scsi_change_queue_depth(SDp, SDp->queue_depth);
-                if (change_tag)
-                        NCR_700_set_tag_neg_state(SDp, NCR_700_START_TAG_NEGOTIATION);
-        }
-        if (change_tag)
-                scsi_target_resume(SDp->sdev_target);
-
-        return tag_type;
-}
-
 static ssize_t
 NCR_700_show_active_tags(struct device *dev, struct device_attribute *attr, char *buf)
 {
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 86cf3d671eb9..9c92f415229f 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -1462,18 +1462,17 @@ config SCSI_WD719X
           SCSI controllers (based on WD33C296A chip).
 
 config SCSI_DEBUG
-        tristate "SCSI debugging host simulator"
+        tristate "SCSI debugging host and device simulator"
         depends on SCSI
         select CRC_T10DIF
         help
-          This is a host adapter simulator that can simulate multiple hosts
-          each with multiple dummy SCSI devices (disks). It defaults to one
-          host adapter with one dummy SCSI disk. Each dummy disk uses kernel
-          RAM as storage (i.e. it is a ramdisk). To save space when multiple
-          dummy disks are simulated, they share the same kernel RAM for 
-          their storage. See <http://sg.danny.cz/sg/sdebug26.html> for more
-          information. This driver is primarily of use to those testing the
-          SCSI and block subsystems. If unsure, say N.
+          This pseudo driver simulates one or more hosts (SCSI initiators),
+          each with one or more targets, each with one or more logical units.
+          Defaults to one of each, creating a small RAM disk device. Many
+          parameters found in the /sys/bus/pseudo/drivers/scsi_debug
+          directory can be tweaked at run time.
+          See <http://sg.danny.cz/sg/sdebug26.html> for more information.
+          Mainly used for testing and best as a module. If unsure, say N.
 
 config SCSI_MESH
         tristate "MESH (Power Mac internal SCSI) support"
diff --git a/drivers/scsi/advansys.c b/drivers/scsi/advansys.c
index 6719a3390ebd..2c5ce48c8f95 100644
--- a/drivers/scsi/advansys.c
+++ b/drivers/scsi/advansys.c
@@ -7921,9 +7921,9 @@ static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
          */
         if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
             (boardp->reqcnt[scp->device->id] % 255) == 0) {
-                asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
+                asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
         } else {
-                asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
+                asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
         }
 
         /* Build ASC_SCSI_Q */
@@ -8351,7 +8351,7 @@ static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
         }
         q_addr = ASC_QNO_TO_QADDR(q_no);
         if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
-                scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
+                scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
         }
         scsiq->q1.status = QS_FREE;
         AscMemWordCopyPtrToLram(iop_base,
@@ -8669,7 +8669,7 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
                 }
         }
         if (disable_syn_offset_one_fix) {
-                scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
+                scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
                 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
                                        ASC_TAG_FLAG_DISABLE_DISCONNECT);
         } else {
diff --git a/drivers/scsi/aic94xx/aic94xx_init.c b/drivers/scsi/aic94xx/aic94xx_init.c
index 14fc018436c2..02a2512b76a8 100644
--- a/drivers/scsi/aic94xx/aic94xx_init.c
+++ b/drivers/scsi/aic94xx/aic94xx_init.c
@@ -63,7 +63,6 @@ static struct scsi_host_template aic94xx_sht = {
         .scan_finished          = asd_scan_finished,
         .scan_start             = asd_scan_start,
         .change_queue_depth     = sas_change_queue_depth,
-        .change_queue_type      = sas_change_queue_type,
         .bios_param             = sas_bios_param,
         .can_queue              = 1,
         .cmd_per_lun            = 1,
diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
index e861f286b42e..98d06d151958 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
+++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
@@ -2792,7 +2792,6 @@ static struct scsi_host_template bnx2fc_shost_template = {
         .eh_host_reset_handler  = fc_eh_host_reset,
         .slave_alloc            = fc_slave_alloc,
         .change_queue_depth     = scsi_change_queue_depth,
-        .change_queue_type      = scsi_change_queue_type,
         .this_id                = -1,
         .cmd_per_lun            = 3,
         .use_clustering         = ENABLE_CLUSTERING,
diff --git a/drivers/scsi/bnx2fc/bnx2fc_io.c b/drivers/scsi/bnx2fc/bnx2fc_io.c
index 4b56858c1df2..9ecca8504f60 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_io.c
+++ b/drivers/scsi/bnx2fc/bnx2fc_io.c
@@ -1737,11 +1737,7 @@ void bnx2fc_build_fcp_cmnd(struct bnx2fc_cmd *io_req,
         fcp_cmnd->fc_pri_ta = 0;
         fcp_cmnd->fc_tm_flags = io_req->mp_req.tm_flags;
         fcp_cmnd->fc_flags = io_req->io_req_flags;
-
-        if (sc_cmd->flags & SCMD_TAGGED)
-                fcp_cmnd->fc_pri_ta = FCP_PTA_SIMPLE;
-        else
-                fcp_cmnd->fc_pri_ta = 0;
+        fcp_cmnd->fc_pri_ta = FCP_PTA_SIMPLE;
 }
 
 static void bnx2fc_parse_fcp_rsp(struct bnx2fc_cmd *io_req,
diff --git a/drivers/scsi/csiostor/csio_scsi.c b/drivers/scsi/csiostor/csio_scsi.c
index 51ea5dc5f084..3987284e0d2a 100644
--- a/drivers/scsi/csiostor/csio_scsi.c
+++ b/drivers/scsi/csiostor/csio_scsi.c
@@ -172,10 +172,7 @@ csio_scsi_fcp_cmnd(struct csio_ioreq *req, void *addr)
                 fcp_cmnd->fc_cmdref = 0;
 
                 memcpy(fcp_cmnd->fc_cdb, scmnd->cmnd, 16);
-                if (scmnd->flags & SCMD_TAGGED)
-                        fcp_cmnd->fc_pri_ta = FCP_PTA_SIMPLE;
-                else
-                        fcp_cmnd->fc_pri_ta = 0;
+                fcp_cmnd->fc_pri_ta = FCP_PTA_SIMPLE;
                 fcp_cmnd->fc_dl = cpu_to_be32(scsi_bufflen(scmnd));
 
                 if (req->nsge)
diff --git a/drivers/scsi/esas2r/esas2r_flash.c b/drivers/scsi/esas2r/esas2r_flash.c
index b7dc59fca7a6..7bd376d95ed5 100644
--- a/drivers/scsi/esas2r/esas2r_flash.c
+++ b/drivers/scsi/esas2r/esas2r_flash.c
@@ -684,9 +684,9 @@ static u16 calc_fi_checksum(struct esas2r_flash_context *fc)
  *              1)  verify the fi_version is correct
  *              2)  verify the checksum of the entire image.
  *              3)  validate the adap_typ, action and length fields.
- *              4)  valdiate each component header. check the img_type and
+ *              4)  validate each component header. check the img_type and
  *                  length fields
- *              5)  valdiate each component image.  validate signatures and
+ *              5)  validate each component image.  validate signatures and
  *                  local checksums
  */
 static bool verify_fi(struct esas2r_adapter *a,
diff --git a/drivers/scsi/esas2r/esas2r_main.c b/drivers/scsi/esas2r/esas2r_main.c
index 593ff8a63c70..7e1c21e6736b 100644
--- a/drivers/scsi/esas2r/esas2r_main.c
+++ b/drivers/scsi/esas2r/esas2r_main.c
@@ -255,7 +255,6 @@ static struct scsi_host_template driver_template = {
         .emulated                       = 0,
         .proc_name                      = ESAS2R_DRVR_NAME,
         .change_queue_depth             = scsi_change_queue_depth,
-        .change_queue_type              = scsi_change_queue_type,
         .max_sectors                    = 0xFFFF,
         .use_blk_tags                   = 1,
 };
diff --git a/drivers/scsi/fcoe/fcoe.c b/drivers/scsi/fcoe/fcoe.c
index cd00a6cdf55b..ec193a8357d7 100644
--- a/drivers/scsi/fcoe/fcoe.c
+++ b/drivers/scsi/fcoe/fcoe.c
@@ -281,7 +281,6 @@ static struct scsi_host_template fcoe_shost_template = {
         .eh_host_reset_handler = fc_eh_host_reset,
         .slave_alloc = fc_slave_alloc,
         .change_queue_depth = scsi_change_queue_depth,
-        .change_queue_type = scsi_change_queue_type,
         .this_id = -1,
         .cmd_per_lun = 3,
         .can_queue = FCOE_MAX_OUTSTANDING_COMMANDS,
diff --git a/drivers/scsi/fnic/fnic_main.c b/drivers/scsi/fnic/fnic_main.c
index 0c1f8177b5b7..8a0d4d7b3254 100644
--- a/drivers/scsi/fnic/fnic_main.c
+++ b/drivers/scsi/fnic/fnic_main.c
@@ -111,7 +111,6 @@ static struct scsi_host_template fnic_host_template = {
         .eh_host_reset_handler = fnic_host_reset,
         .slave_alloc = fnic_slave_alloc,
         .change_queue_depth = scsi_change_queue_depth,
-        .change_queue_type = scsi_change_queue_type,
         .this_id = -1,
         .cmd_per_lun = 3,
         .can_queue = FNIC_DFLT_IO_REQ,
diff --git a/drivers/scsi/ibmvscsi/ibmvfc.c b/drivers/scsi/ibmvscsi/ibmvfc.c
index f58c6d8e0264..057d27721d5b 100644
--- a/drivers/scsi/ibmvscsi/ibmvfc.c
+++ b/drivers/scsi/ibmvscsi/ibmvfc.c
@@ -1615,7 +1615,6 @@ static int ibmvfc_queuecommand_lck(struct scsi_cmnd *cmnd,
         struct fc_rport *rport = starget_to_rport(scsi_target(cmnd->device));
         struct ibmvfc_cmd *vfc_cmd;
         struct ibmvfc_event *evt;
-        u8 tag[2];
         int rc;
 
         if (unlikely((rc = fc_remote_port_chkready(rport))) ||
@@ -3089,7 +3088,6 @@ static struct scsi_host_template driver_template = {
         .target_alloc = ibmvfc_target_alloc,
         .scan_finished = ibmvfc_scan_finished,
         .change_queue_depth = ibmvfc_change_queue_depth,
-        .change_queue_type = scsi_change_queue_type,
         .cmd_per_lun = 16,
         .can_queue = IBMVFC_MAX_REQUESTS_DEFAULT,
         .this_id = -1,
diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c
index 540294389355..df4e27cd996a 100644
--- a/drivers/scsi/ipr.c
+++ b/drivers/scsi/ipr.c
@@ -1426,16 +1426,14 @@ static void ipr_handle_config_change(struct ipr_ioa_cfg *ioa_cfg,
                 if (res->sdev) {
                         res->del_from_ml = 1;
                         res->res_handle = IPR_INVALID_RES_HANDLE;
-                        if (ioa_cfg->allow_ml_add_del)
-                                schedule_work(&ioa_cfg->work_q);
+                        schedule_work(&ioa_cfg->work_q);
                 } else {
                         ipr_clear_res_target(res);
                         list_move_tail(&res->queue, &ioa_cfg->free_res_q);
                 }
         } else if (!res->sdev || res->del_from_ml) {
                 res->add_to_ml = 1;
-                if (ioa_cfg->allow_ml_add_del)
-                        schedule_work(&ioa_cfg->work_q);
+                schedule_work(&ioa_cfg->work_q);
         }
 
         ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
@@ -3273,8 +3271,7 @@ static void ipr_worker_thread(struct work_struct *work)
 restart:
         do {
                 did_work = 0;
-                if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds ||
-                    !ioa_cfg->allow_ml_add_del) {
+                if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
                         spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
                         return;
                 }
@@ -3311,6 +3308,7 @@ restart:
                 }
         }
 
+        ioa_cfg->scan_done = 1;
         spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
         kobject_uevent(&ioa_cfg->host->shost_dev.kobj, KOBJ_CHANGE);
         LEAVE;
@@ -4346,30 +4344,6 @@ static int ipr_change_queue_depth(struct scsi_device *sdev, int qdepth)
 }
 
 /**
- * ipr_change_queue_type - Change the device's queue type
- * @dsev:               scsi device struct
- * @tag_type:   type of tags to use
- *
- * Return value:
- *      actual queue type set
- **/
-static int ipr_change_queue_type(struct scsi_device *sdev, int tag_type)
-{
-        struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
-        struct ipr_resource_entry *res;
-        unsigned long lock_flags = 0;
-
-        spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
-        res = (struct ipr_resource_entry *)sdev->hostdata;
-        if (res && ipr_is_gscsi(res))
-                tag_type = scsi_change_queue_type(sdev, tag_type);
-        else
-                tag_type = 0;
-        spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
-        return tag_type;
-}
-
-/**
  * ipr_show_adapter_handle - Show the adapter's resource handle for this device
  * @dev:        device struct
  * @attr:       device attribute structure
@@ -4739,6 +4713,7 @@ static int ipr_slave_configure(struct scsi_device *sdev)
                         sdev->no_uld_attach = 1;
                 }
                 if (ipr_is_vset_device(res)) {
+                        sdev->scsi_level = SCSI_SPC_3;
                         blk_queue_rq_timeout(sdev->request_queue,
                                              IPR_VSET_RW_TIMEOUT);
                         blk_queue_max_hw_sectors(sdev->request_queue, IPR_VSET_MAX_SECTORS);
@@ -5231,6 +5206,28 @@ static int ipr_cancel_op(struct scsi_cmnd *scsi_cmd)
  * @scsi_cmd:   scsi command struct
  *
  * Return value:
+ *      0 if scan in progress / 1 if scan is complete
+ **/
+static int ipr_scan_finished(struct Scsi_Host *shost, unsigned long elapsed_time)
+{
+        unsigned long lock_flags;
+        struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
+        int rc = 0;
+
+        spin_lock_irqsave(shost->host_lock, lock_flags);
+        if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead || ioa_cfg->scan_done)
+                rc = 1;
+        if ((elapsed_time/HZ) > (ioa_cfg->transop_timeout * 2))
+                rc = 1;
+        spin_unlock_irqrestore(shost->host_lock, lock_flags);
+        return rc;
+}
+
+/**
+ * ipr_eh_host_reset - Reset the host adapter
+ * @scsi_cmd:   scsi command struct
+ *
+ * Return value:
  *      SUCCESS / FAILED
  **/
 static int ipr_eh_abort(struct scsi_cmnd *scsi_cmd)
@@ -5779,7 +5776,7 @@ static void ipr_erp_cancel_all(struct ipr_cmnd *ipr_cmd)
 
         ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
 
-        if (!scsi_get_tag_type(scsi_cmd->device)) {
+        if (!scsi_cmd->device->simple_tags) {
                 ipr_erp_request_sense(ipr_cmd);
                 return;
         }
@@ -6299,10 +6296,10 @@ static struct scsi_host_template driver_template = {
         .slave_alloc = ipr_slave_alloc,
         .slave_configure = ipr_slave_configure,
         .slave_destroy = ipr_slave_destroy,
+        .scan_finished = ipr_scan_finished,
         .target_alloc = ipr_target_alloc,
         .target_destroy = ipr_target_destroy,
         .change_queue_depth = ipr_change_queue_depth,
-        .change_queue_type = ipr_change_queue_type,
         .bios_param = ipr_biosparam,
         .can_queue = IPR_MAX_COMMANDS,
         .this_id = -1,
@@ -6841,7 +6838,7 @@ static int ipr_ioa_reset_done(struct ipr_cmnd *ipr_cmd)
         ioa_cfg->doorbell |= IPR_RUNTIME_RESET;
 
         list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
-                if (ioa_cfg->allow_ml_add_del && (res->add_to_ml || res->del_from_ml)) {
+                if (res->add_to_ml || res->del_from_ml) {
                         ipr_trace;
                         break;
                 }
@@ -6870,6 +6867,7 @@ static int ipr_ioa_reset_done(struct ipr_cmnd *ipr_cmd)
         if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds)
                 scsi_block_requests(ioa_cfg->host);
 
+        schedule_work(&ioa_cfg->work_q);
         LEAVE;
         return IPR_RC_JOB_RETURN;
 }
@@ -7610,6 +7608,19 @@ static int ipr_ioafp_page0_inquiry(struct ipr_cmnd *ipr_cmd)
         type[4] = '\0';
         ioa_cfg->type = simple_strtoul((char *)type, NULL, 16);
 
+        if (ipr_invalid_adapter(ioa_cfg)) {
+                dev_err(&ioa_cfg->pdev->dev,
+                        "Adapter not supported in this hardware configuration.\n");
+
+                if (!ipr_testmode) {
+                        ioa_cfg->reset_retries += IPR_NUM_RESET_RELOAD_RETRIES;
+                        ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
+                        list_add_tail(&ipr_cmd->queue,
+                                        &ioa_cfg->hrrq->hrrq_free_q);
+                        return IPR_RC_JOB_RETURN;
+                }
+        }
+
         ipr_cmd->job_step = ipr_ioafp_page3_inquiry;
 
         ipr_ioafp_inquiry(ipr_cmd, 1, 0,
@@ -8797,20 +8808,6 @@ static int ipr_probe_ioa_part2(struct ipr_ioa_cfg *ioa_cfg)
                 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_enable_ioa,
                                         IPR_SHUTDOWN_NONE);
         spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
-        wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
-        spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
-
-        if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
-                rc = -EIO;
-        } else if (ipr_invalid_adapter(ioa_cfg)) {
-                if (!ipr_testmode)
-                        rc = -EIO;
-
-                dev_err(&ioa_cfg->pdev->dev,
-                        "Adapter not supported in this hardware configuration.\n");
-        }
-
-        spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
 
         LEAVE;
         return rc;
@@ -9264,7 +9261,7 @@ static void ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg,
                                                * ioa_cfg->max_devs_supported)));
         }
 
-        host->max_channel = IPR_MAX_BUS_TO_SCAN;
+        host->max_channel = IPR_VSET_BUS;
         host->unique_id = host->host_no;
         host->max_cmd_len = IPR_MAX_CDB_LEN;
         host->can_queue = ioa_cfg->max_cmds;
@@ -9764,25 +9761,6 @@ out_scsi_host_put:
 }
 
 /**
- * ipr_scan_vsets - Scans for VSET devices
- * @ioa_cfg:    ioa config struct
- *
- * Description: Since the VSET resources do not follow SAM in that we can have
- * sparse LUNs with no LUN 0, we have to scan for these ourselves.
- *
- * Return value:
- *      none
- **/
-static void ipr_scan_vsets(struct ipr_ioa_cfg *ioa_cfg)
-{
-        int target, lun;
-
-        for (target = 0; target < IPR_MAX_NUM_TARGETS_PER_BUS; target++)
-                for (lun = 0; lun < IPR_MAX_NUM_VSET_LUNS_PER_TARGET; lun++)
-                        scsi_add_device(ioa_cfg->host, IPR_VSET_BUS, target, lun);
-}
-
-/**
  * ipr_initiate_ioa_bringdown - Bring down an adapter
  * @ioa_cfg:            ioa config struct
  * @shutdown_type:      shutdown type
@@ -9937,10 +9915,6 @@ static int ipr_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id)
         }
 
         scsi_scan_host(ioa_cfg->host);
-        ipr_scan_vsets(ioa_cfg);
-        scsi_add_device(ioa_cfg->host, IPR_IOA_BUS, IPR_IOA_TARGET, IPR_IOA_LUN);
-        ioa_cfg->allow_ml_add_del = 1;
-        ioa_cfg->host->max_channel = IPR_VSET_BUS;
         ioa_cfg->iopoll_weight = ioa_cfg->chip_cfg->iopoll_weight;
 
         if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h
index 9ebdebd944e7..b4f3eec51bc9 100644
--- a/drivers/scsi/ipr.h
+++ b/drivers/scsi/ipr.h
@@ -157,13 +157,11 @@
 
 #define IPR_MAX_NUM_TARGETS_PER_BUS                     256
 #define IPR_MAX_NUM_LUNS_PER_TARGET                     256
-#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET        8
 #define IPR_VSET_BUS                                    0xff
 #define IPR_IOA_BUS                                             0xff
 #define IPR_IOA_TARGET                                  0xff
 #define IPR_IOA_LUN                                             0xff
 #define IPR_MAX_NUM_BUSES                               16
-#define IPR_MAX_BUS_TO_SCAN                             IPR_MAX_NUM_BUSES
 
 #define IPR_NUM_RESET_RELOAD_RETRIES            3
 
@@ -1453,7 +1451,7 @@ struct ipr_ioa_cfg {
         u8 in_ioa_bringdown:1;
         u8 ioa_unit_checked:1;
         u8 dump_taken:1;
-        u8 allow_ml_add_del:1;
+        u8 scan_done:1;
         u8 needs_hard_reset:1;
         u8 dual_raid:1;
         u8 needs_warm_reset:1;
diff --git a/drivers/scsi/isci/init.c b/drivers/scsi/isci/init.c
index 724c6265b667..cd41b63a2f10 100644
--- a/drivers/scsi/isci/init.c
+++ b/drivers/scsi/isci/init.c
@@ -158,7 +158,6 @@ static struct scsi_host_template isci_sht = {
         .scan_finished                  = isci_host_scan_finished,
         .scan_start                     = isci_host_start,
         .change_queue_depth             = sas_change_queue_depth,
-        .change_queue_type              = sas_change_queue_type,
         .bios_param                     = sas_bios_param,
         .can_queue                      = ISCI_CAN_QUEUE_VAL,
         .cmd_per_lun                    = 1,
diff --git a/drivers/scsi/libsas/sas_scsi_host.c b/drivers/scsi/libsas/sas_scsi_host.c
index 72918d227ead..519dac4e341e 100644
--- a/drivers/scsi/libsas/sas_scsi_host.c
+++ b/drivers/scsi/libsas/sas_scsi_host.c
@@ -906,13 +906,6 @@ int sas_change_queue_depth(struct scsi_device *sdev, int depth)
         return scsi_change_queue_depth(sdev, depth);
 }
 
-int sas_change_queue_type(struct scsi_device *scsi_dev, int type)
-{
-        if (dev_is_sata(sdev_to_domain_dev(scsi_dev)))
-                return -EINVAL;
-        return scsi_change_queue_type(scsi_dev, type);
-}
-
 int sas_bios_param(struct scsi_device *scsi_dev,
                           struct block_device *bdev,
                           sector_t capacity, int *hsc)
@@ -1011,7 +1004,6 @@ EXPORT_SYMBOL_GPL(sas_queuecommand);
 EXPORT_SYMBOL_GPL(sas_target_alloc);
 EXPORT_SYMBOL_GPL(sas_slave_configure);
 EXPORT_SYMBOL_GPL(sas_change_queue_depth);
-EXPORT_SYMBOL_GPL(sas_change_queue_type);
 EXPORT_SYMBOL_GPL(sas_bios_param);
 EXPORT_SYMBOL_GPL(sas_task_abort);
 EXPORT_SYMBOL_GPL(sas_phy_reset);
diff --git a/drivers/scsi/lpfc/lpfc_scsi.c b/drivers/scsi/lpfc/lpfc_scsi.c
index fd85952b621d..4f9222eb2266 100644
--- a/drivers/scsi/lpfc/lpfc_scsi.c
+++ b/drivers/scsi/lpfc/lpfc_scsi.c
@@ -5879,7 +5879,6 @@ struct scsi_host_template lpfc_template = {
         .max_sectors            = 0xFFFF,
         .vendor_id              = LPFC_NL_VENDOR_ID,
         .change_queue_depth     = scsi_change_queue_depth,
-        .change_queue_type      = scsi_change_queue_type,
         .use_blk_tags           = 1,
         .track_queue_depth      = 1,
 };
@@ -5904,7 +5903,6 @@ struct scsi_host_template lpfc_vport_template = {
         .shost_attrs            = lpfc_vport_attrs,
         .max_sectors            = 0xFFFF,
         .change_queue_depth     = scsi_change_queue_depth,
-        .change_queue_type      = scsi_change_queue_type,
         .use_blk_tags           = 1,
         .track_queue_depth      = 1,
 };
diff --git a/drivers/scsi/mpt2sas/mpt2sas_scsih.c b/drivers/scsi/mpt2sas/mpt2sas_scsih.c
index 8431eb10bbb1..6a1c036a6f3f 100644
--- a/drivers/scsi/mpt2sas/mpt2sas_scsih.c
+++ b/drivers/scsi/mpt2sas/mpt2sas_scsih.c
@@ -7592,7 +7592,6 @@ static struct scsi_host_template scsih_driver_template = {
         .scan_finished                  = _scsih_scan_finished,
         .scan_start                     = _scsih_scan_start,
         .change_queue_depth             = _scsih_change_queue_depth,
-        .change_queue_type              = scsi_change_queue_type,
         .eh_abort_handler               = _scsih_abort,
         .eh_device_reset_handler        = _scsih_dev_reset,
         .eh_target_reset_handler        = _scsih_target_reset,
diff --git a/drivers/scsi/mpt2sas/mpt2sas_transport.c b/drivers/scsi/mpt2sas/mpt2sas_transport.c
index 0d1d06488a28..e689bf20a3ea 100644
--- a/drivers/scsi/mpt2sas/mpt2sas_transport.c
+++ b/drivers/scsi/mpt2sas/mpt2sas_transport.c
@@ -1006,12 +1006,9 @@ mpt2sas_transport_update_links(struct MPT2SAS_ADAPTER *ioc,
                     &mpt2sas_phy->remote_identify);
                 _transport_add_phy_to_an_existing_port(ioc, sas_node,
                     mpt2sas_phy, mpt2sas_phy->remote_identify.sas_address);
-        } else {
+        } else
                 memset(&mpt2sas_phy->remote_identify, 0 , sizeof(struct
                     sas_identify));
-                _transport_del_phy_from_an_existing_port(ioc, sas_node,
-                    mpt2sas_phy);
-        }
 
         if (mpt2sas_phy->phy)
                 mpt2sas_phy->phy->negotiated_linkrate =
diff --git a/drivers/scsi/mpt3sas/mpt3sas_scsih.c b/drivers/scsi/mpt3sas/mpt3sas_scsih.c
index a2b60991efd4..94261ee9e72d 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_scsih.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_scsih.c
@@ -7229,7 +7229,6 @@ static struct scsi_host_template scsih_driver_template = {
         .scan_finished                  = _scsih_scan_finished,
         .scan_start                     = _scsih_scan_start,
         .change_queue_depth             = _scsih_change_queue_depth,
-        .change_queue_type              = scsi_change_queue_type,
         .eh_abort_handler               = _scsih_abort,
         .eh_device_reset_handler        = _scsih_dev_reset,
         .eh_target_reset_handler        = _scsih_target_reset,
diff --git a/drivers/scsi/mpt3sas/mpt3sas_transport.c b/drivers/scsi/mpt3sas/mpt3sas_transport.c
index d4bafaaebea9..3637ae6c0171 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_transport.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_transport.c
@@ -1003,12 +1003,9 @@ mpt3sas_transport_update_links(struct MPT3SAS_ADAPTER *ioc,
                     &mpt3sas_phy->remote_identify);
                 _transport_add_phy_to_an_existing_port(ioc, sas_node,
                     mpt3sas_phy, mpt3sas_phy->remote_identify.sas_address);
-        } else {
+        } else
                 memset(&mpt3sas_phy->remote_identify, 0 , sizeof(struct
                     sas_identify));
-                _transport_del_phy_from_an_existing_port(ioc, sas_node,
-                    mpt3sas_phy);
-        }
 
         if (mpt3sas_phy->phy)
                 mpt3sas_phy->phy->negotiated_linkrate =
diff --git a/drivers/scsi/mvsas/mv_init.c b/drivers/scsi/mvsas/mv_init.c
index f15df3de6790..53030b0e8015 100644
--- a/drivers/scsi/mvsas/mv_init.c
+++ b/drivers/scsi/mvsas/mv_init.c
@@ -54,7 +54,6 @@ static struct scsi_host_template mvs_sht = {
         .scan_finished          = mvs_scan_finished,
         .scan_start             = mvs_scan_start,
         .change_queue_depth     = sas_change_queue_depth,
-        .change_queue_type      = sas_change_queue_type,
         .bios_param             = sas_bios_param,
         .can_queue              = 1,
         .cmd_per_lun            = 1,
diff --git a/drivers/scsi/pm8001/pm8001_init.c b/drivers/scsi/pm8001/pm8001_init.c
index 329aba0083ab..65555916d3b8 100644
--- a/drivers/scsi/pm8001/pm8001_init.c
+++ b/drivers/scsi/pm8001/pm8001_init.c
@@ -76,7 +76,6 @@ static struct scsi_host_template pm8001_sht = {
         .scan_finished          = pm8001_scan_finished,
         .scan_start             = pm8001_scan_start,
         .change_queue_depth     = sas_change_queue_depth,
-        .change_queue_type      = sas_change_queue_type,
         .bios_param             = sas_bios_param,
         .can_queue              = 1,
         .cmd_per_lun            = 1,
diff --git a/drivers/scsi/pmcraid.c b/drivers/scsi/pmcraid.c
index b1b1f66b1ab7..8c27b6a77ec4 100644
--- a/drivers/scsi/pmcraid.c
+++ b/drivers/scsi/pmcraid.c
@@ -4251,7 +4251,6 @@ static struct scsi_host_template pmcraid_host_template = {
         .slave_configure = pmcraid_slave_configure,
         .slave_destroy = pmcraid_slave_destroy,
         .change_queue_depth = pmcraid_change_queue_depth,
-        .change_queue_type  = scsi_change_queue_type,
         .can_queue = PMCRAID_MAX_IO_CMD,
         .this_id = -1,
         .sg_tablesize = PMCRAID_MAX_IOADLS,
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index a4dde7e80dbd..e59f25bff7ab 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -3237,8 +3237,6 @@ qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
         struct fc_rport *rport;
         unsigned long flags;
 
-        qla2x00_rport_del(fcport);
-
         rport_ids.node_name = wwn_to_u64(fcport->node_name);
         rport_ids.port_name = wwn_to_u64(fcport->port_name);
         rport_ids.port_id = fcport->d_id.b.domain << 16 |
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 6b4d9235368a..12ca291c1380 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -258,7 +258,6 @@ struct scsi_host_template qla2xxx_driver_template = {
         .scan_finished          = qla2xxx_scan_finished,
         .scan_start             = qla2xxx_scan_start,
         .change_queue_depth     = scsi_change_queue_depth,
-        .change_queue_type      = scsi_change_queue_type,
         .this_id                = -1,
         .cmd_per_lun            = 3,
         .use_clustering         = ENABLE_CLUSTERING,
diff --git a/drivers/scsi/qla2xxx/qla_target.c b/drivers/scsi/qla2xxx/qla_target.c
index a902fa1db7af..57418258c101 100644
--- a/drivers/scsi/qla2xxx/qla_target.c
+++ b/drivers/scsi/qla2xxx/qla_target.c
@@ -3218,25 +3218,25 @@ static inline int qlt_get_fcp_task_attr(struct scsi_qla_host *vha,
 
         switch (task_codes) {
         case ATIO_SIMPLE_QUEUE:
-                fcp_task_attr = MSG_SIMPLE_TAG;
+                fcp_task_attr = TCM_SIMPLE_TAG;
                 break;
         case ATIO_HEAD_OF_QUEUE:
-                fcp_task_attr = MSG_HEAD_TAG;
+                fcp_task_attr = TCM_HEAD_TAG;
                 break;
         case ATIO_ORDERED_QUEUE:
-                fcp_task_attr = MSG_ORDERED_TAG;
+                fcp_task_attr = TCM_ORDERED_TAG;
                 break;
         case ATIO_ACA_QUEUE:
-                fcp_task_attr = MSG_ACA_TAG;
+                fcp_task_attr = TCM_ACA_TAG;
                 break;
         case ATIO_UNTAGGED:
-                fcp_task_attr = MSG_SIMPLE_TAG;
+                fcp_task_attr = TCM_SIMPLE_TAG;
                 break;
         default:
                 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf05d,
                     "qla_target: unknown task code %x, use ORDERED instead\n",
                     task_codes);
-                fcp_task_attr = MSG_ORDERED_TAG;
+                fcp_task_attr = TCM_ORDERED_TAG;
                 break;
         }
 
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 1ad0c36375b8..e02885451425 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -739,34 +739,12 @@ int scsi_track_queue_full(struct scsi_device *sdev, int depth)
 
         if (sdev->last_queue_full_count <= 10)
                 return 0;
-        if (sdev->last_queue_full_depth < 8) {
-                /* Drop back to untagged */
-                scsi_set_tag_type(sdev, 0);
-                scsi_change_queue_depth(sdev, sdev->host->cmd_per_lun);
-                return -1;
-        }
 
         return scsi_change_queue_depth(sdev, depth);
 }
 EXPORT_SYMBOL(scsi_track_queue_full);
 
 /**
- * scsi_change_queue_type() - Change a device's queue type
- * @sdev:     The SCSI device whose queue depth is to change
- * @tag_type: Identifier for queue type
- */
-int scsi_change_queue_type(struct scsi_device *sdev, int tag_type)
-{
-        if (!sdev->tagged_supported)
-                return 0;
-
-        scsi_set_tag_type(sdev, tag_type);
-        return tag_type;
-
-}
-EXPORT_SYMBOL(scsi_change_queue_type);
-
-/**
  * scsi_vpd_inquiry - Request a device provide us with a VPD page
  * @sdev: The device to ask
  * @buffer: Where to put the result
diff --git a/drivers/scsi/scsi_debug.c b/drivers/scsi/scsi_debug.c
index aa4b6b80aade..7b8b51bc29b4 100644
--- a/drivers/scsi/scsi_debug.c
+++ b/drivers/scsi/scsi_debug.c
@@ -128,7 +128,6 @@ static const char *scsi_debug_version_date = "20141022";
 #define DEF_REMOVABLE false
 #define DEF_SCSI_LEVEL   6    /* INQUIRY, byte2 [6->SPC-4] */
 #define DEF_SECTOR_SIZE 512
-#define DEF_TAGGED_QUEUING 0 /* 0 | MSG_SIMPLE_TAG | MSG_ORDERED_TAG */
 #define DEF_UNMAP_ALIGNMENT 0
 #define DEF_UNMAP_GRANULARITY 1
 #define DEF_UNMAP_MAX_BLOCKS 0xFFFFFFFF
@@ -817,6 +816,7 @@ static int check_readiness(struct scsi_cmnd *SCpnt, int uas_only,
                                         UA_CHANGED_ASC, CAPACITY_CHANGED_ASCQ);
                         if (debug)
                                 cp = "capacity data changed";
+                        break;
                 default:
                         pr_warn("%s: unexpected unit attention code=%d\n",
                                 __func__, k);
@@ -3045,18 +3045,12 @@ resp_comp_write(struct scsi_cmnd *scp, struct sdebug_dev_info *devip)
         u8 num;
         unsigned long iflags;
         int ret;
+        int retval = 0;
 
-        lba = get_unaligned_be32(cmd + 2);
+        lba = get_unaligned_be64(cmd + 2);
         num = cmd[13];          /* 1 to a maximum of 255 logical blocks */
         if (0 == num)
                 return 0;       /* degenerate case, not an error */
-        dnum = 2 * num;
-        arr = kzalloc(dnum * lb_size, GFP_ATOMIC);
-        if (NULL == arr) {
-                mk_sense_buffer(scp, ILLEGAL_REQUEST, INSUFF_RES_ASC,
-                                INSUFF_RES_ASCQ);
-                return check_condition_result;
-        }
         if (scsi_debug_dif == SD_DIF_TYPE2_PROTECTION &&
             (cmd[1] & 0xe0)) {
                 mk_sense_invalid_opcode(scp);
@@ -3079,6 +3073,13 @@ resp_comp_write(struct scsi_cmnd *scp, struct sdebug_dev_info *devip)
                 mk_sense_buffer(scp, ILLEGAL_REQUEST, INVALID_FIELD_IN_CDB, 0);
                 return check_condition_result;
         }
+        dnum = 2 * num;
+        arr = kzalloc(dnum * lb_size, GFP_ATOMIC);
+        if (NULL == arr) {
+                mk_sense_buffer(scp, ILLEGAL_REQUEST, INSUFF_RES_ASC,
+                                INSUFF_RES_ASCQ);
+                return check_condition_result;
+        }
 
         write_lock_irqsave(&atomic_rw, iflags);
 
@@ -3089,24 +3090,24 @@ resp_comp_write(struct scsi_cmnd *scp, struct sdebug_dev_info *devip)
         ret = do_device_access(scp, 0, dnum, true);
         fake_storep = fake_storep_hold;
         if (ret == -1) {
-                write_unlock_irqrestore(&atomic_rw, iflags);
-                kfree(arr);
-                return DID_ERROR << 16;
+                retval = DID_ERROR << 16;
+                goto cleanup;
         } else if ((ret < (dnum * lb_size)) &&
                  (SCSI_DEBUG_OPT_NOISE & scsi_debug_opts))
                 sdev_printk(KERN_INFO, scp->device, "%s: compare_write: cdb "
                             "indicated=%u, IO sent=%d bytes\n", my_name,
                             dnum * lb_size, ret);
         if (!comp_write_worker(lba, num, arr)) {
-                write_unlock_irqrestore(&atomic_rw, iflags);
-                kfree(arr);
                 mk_sense_buffer(scp, MISCOMPARE, MISCOMPARE_VERIFY_ASC, 0);
-                return check_condition_result;
+                retval = check_condition_result;
+                goto cleanup;
         }
         if (scsi_debug_lbp())
                 map_region(lba, num);
+cleanup:
         write_unlock_irqrestore(&atomic_rw, iflags);
-        return 0;
+        kfree(arr);
+        return retval;
 }
 
 struct unmap_block_desc {
@@ -4438,6 +4439,7 @@ static ssize_t virtual_gb_store(struct device_driver *ddp, const char *buf,
                         struct sdebug_host_info *sdhp;
                         struct sdebug_dev_info *dp;
 
+                        spin_lock(&sdebug_host_list_lock);
                         list_for_each_entry(sdhp, &sdebug_host_list,
                                             host_list) {
                                 list_for_each_entry(dp, &sdhp->dev_info_list,
@@ -4446,6 +4448,7 @@ static ssize_t virtual_gb_store(struct device_driver *ddp, const char *buf,
                                                 dp->uas_bm);
                                 }
                         }
+                        spin_unlock(&sdebug_host_list_lock);
                 }
                 return count;
         }
@@ -4988,32 +4991,6 @@ sdebug_change_qdepth(struct scsi_device *sdev, int qdepth)
 }
 
 static int
-sdebug_change_qtype(struct scsi_device *sdev, int qtype)
-{
-        qtype = scsi_change_queue_type(sdev, qtype);
-        if (SCSI_DEBUG_OPT_Q_NOISE & scsi_debug_opts) {
-                const char *cp;
-
-                switch (qtype) {
-                case 0:
-                        cp = "untagged";
-                        break;
-                case MSG_SIMPLE_TAG:
-                        cp = "simple tags";
-                        break;
-                case MSG_ORDERED_TAG:
-                        cp = "ordered tags";
-                        break;
-                default:
-                        cp = "unknown";
-                        break;
-                }
-                sdev_printk(KERN_INFO, sdev, "%s: to %s\n", __func__, cp);
-        }
-        return qtype;
-}
-
-static int
 check_inject(struct scsi_cmnd *scp)
 {
         struct sdebug_scmd_extra_t *ep = scsi_cmd_priv(scp);
@@ -5212,7 +5189,6 @@ static struct scsi_host_template sdebug_driver_template = {
         .ioctl =                scsi_debug_ioctl,
         .queuecommand =         sdebug_queuecommand_lock_or_not,
         .change_queue_depth =   sdebug_change_qdepth,
-        .change_queue_type =    sdebug_change_qtype,
         .eh_abort_handler =     scsi_debug_abort,
         .eh_device_reset_handler = scsi_debug_device_reset,
         .eh_target_reset_handler = scsi_debug_target_reset,
diff --git a/drivers/scsi/scsi_devinfo.c b/drivers/scsi/scsi_devinfo.c
index c1d04d4d3c6c..262ab837a704 100644
--- a/drivers/scsi/scsi_devinfo.c
+++ b/drivers/scsi/scsi_devinfo.c
@@ -211,6 +211,7 @@ static struct {
         {"Medion", "Flash XL  MMC/SD", "2.6D", BLIST_FORCELUN},
         {"MegaRAID", "LD", NULL, BLIST_FORCELUN},
         {"MICROP", "4110", NULL, BLIST_NOTQ},
+        {"MSFT", "Virtual HD", NULL, BLIST_NO_RSOC},
         {"MYLEX", "DACARMRB", "*", BLIST_REPORTLUN2},
         {"nCipher", "Fastness Crypto", NULL, BLIST_FORCELUN},
         {"NAKAMICH", "MJ-4.8S", NULL, BLIST_FORCELUN | BLIST_SINGLELUN},
diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c
index 43318d556cbc..9ea95dd3e260 100644
--- a/drivers/scsi/scsi_lib.c
+++ b/drivers/scsi/scsi_lib.c
@@ -1918,7 +1918,9 @@ static int scsi_mq_prep_fn(struct request *req)
 
         if (scsi_host_get_prot(shost)) {
                 cmd->prot_sdb = (void *)sg +
-                        shost->sg_tablesize * sizeof(struct scatterlist);
+                        min_t(unsigned int,
+                              shost->sg_tablesize, SCSI_MAX_SG_SEGMENTS) *
+                        sizeof(struct scatterlist);
                 memset(cmd->prot_sdb, 0, sizeof(struct scsi_data_buffer));
 
                 cmd->prot_sdb->table.sgl =
diff --git a/drivers/scsi/scsi_sysfs.c b/drivers/scsi/scsi_sysfs.c
index 1cb64a8e18c9..1ac38e73df7e 100644
--- a/drivers/scsi/scsi_sysfs.c
+++ b/drivers/scsi/scsi_sysfs.c
@@ -738,30 +738,12 @@ store_queue_type_field(struct device *dev, struct device_attribute *attr,
                        const char *buf, size_t count)
 {
         struct scsi_device *sdev = to_scsi_device(dev);
-        struct scsi_host_template *sht = sdev->host->hostt;
-        int tag_type = 0, retval;
-        int prev_tag_type = scsi_get_tag_type(sdev);
-
-        if (!sdev->tagged_supported || !sht->change_queue_type)
-                return -EINVAL;
 
-        /*
-         * We're never issueing order tags these days, but allow the value
-         * for backwards compatibility.
-         */
-        if (strncmp(buf, "ordered", 7) == 0 ||
-            strncmp(buf, "simple", 6) == 0)
-                tag_type = MSG_SIMPLE_TAG;
-        else if (strncmp(buf, "none", 4) != 0)
+        if (!sdev->tagged_supported)
                 return -EINVAL;
-
-        if (tag_type == prev_tag_type)
-                return count;
-
-        retval = sht->change_queue_type(sdev, tag_type);
-        if (retval < 0)
-                return retval;
-
+                
+        sdev_printk(KERN_INFO, sdev,
+                    "ignoring write to deprecated queue_type attribute");
         return count;
 }
 
@@ -938,10 +920,6 @@ static umode_t scsi_sdev_attr_is_visible(struct kobject *kobj,
             !sdev->host->hostt->change_queue_depth)
                 return 0;
 
-        if (attr == &dev_attr_queue_type.attr &&
-            !sdev->host->hostt->change_queue_type)
-                return S_IRUGO;
-
         return attr->mode;
 }
 
diff --git a/drivers/scsi/scsi_transport_spi.c b/drivers/scsi/scsi_transport_spi.c
index fa2aece76cc2..31bbb0da3397 100644
--- a/drivers/scsi/scsi_transport_spi.c
+++ b/drivers/scsi/scsi_transport_spi.c
@@ -1221,7 +1221,7 @@ EXPORT_SYMBOL_GPL(spi_populate_ppr_msg);
 int spi_populate_tag_msg(unsigned char *msg, struct scsi_cmnd *cmd)
 {
         if (cmd->flags & SCMD_TAGGED) {
-                *msg++ = MSG_SIMPLE_TAG;
+                *msg++ = SIMPLE_QUEUE_TAG;
                 *msg++ = cmd->request->tag;
                 return 2;
         }
diff --git a/drivers/scsi/storvsc_drv.c b/drivers/scsi/storvsc_drv.c
index e3ba251fb6e7..4cff0ddc2c25 100644
--- a/drivers/scsi/storvsc_drv.c
+++ b/drivers/scsi/storvsc_drv.c
@@ -1688,13 +1688,12 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd)
         if (ret == -EAGAIN) {
                 /* no more space */
 
-                if (cmd_request->bounce_sgl_count) {
+                if (cmd_request->bounce_sgl_count)
                         destroy_bounce_buffer(cmd_request->bounce_sgl,
                                         cmd_request->bounce_sgl_count);
 
-                        ret = SCSI_MLQUEUE_DEVICE_BUSY;
-                        goto queue_error;
-                }
+                ret = SCSI_MLQUEUE_DEVICE_BUSY;
+                goto queue_error;
         }
 
         return 0;
diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c
index 43781c9fe521..b410499cddca 100644
--- a/drivers/spi/spi-img-spfi.c
+++ b/drivers/spi/spi-img-spfi.c
@@ -663,7 +663,7 @@ static int img_spfi_remove(struct platform_device *pdev)
         return 0;
 }
 
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
 static int img_spfi_runtime_suspend(struct device *dev)
 {
         struct spi_master *master = dev_get_drvdata(dev);
@@ -692,7 +692,7 @@ static int img_spfi_runtime_resume(struct device *dev)
 
         return 0;
 }
-#endif /* CONFIG_PM_RUNTIME */
+#endif /* CONFIG_PM */
 
 #ifdef CONFIG_PM_SLEEP
 static int img_spfi_suspend(struct device *dev)
diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c
index 0e48f8c2037d..1bbac0378bf7 100644
--- a/drivers/spi/spi-meson-spifc.c
+++ b/drivers/spi/spi-meson-spifc.c
@@ -413,7 +413,7 @@ static int meson_spifc_resume(struct device *dev)
 }
 #endif /* CONFIG_PM_SLEEP */
 
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
 static int meson_spifc_runtime_suspend(struct device *dev)
 {
         struct spi_master *master = dev_get_drvdata(dev);
@@ -431,7 +431,7 @@ static int meson_spifc_runtime_resume(struct device *dev)
 
         return clk_prepare_enable(spifc->clk);
 }
-#endif /* CONFIG_PM_RUNTIME */
+#endif /* CONFIG_PM */
 
 static const struct dev_pm_ops meson_spifc_pm_ops = {
         SET_SYSTEM_SLEEP_PM_OPS(meson_spifc_suspend, meson_spifc_resume)
diff --git a/drivers/staging/lustre/lustre/llite/namei.c b/drivers/staging/lustre/lustre/llite/namei.c
index 1bf891bd321a..4f361b77c749 100644
--- a/drivers/staging/lustre/lustre/llite/namei.c
+++ b/drivers/staging/lustre/lustre/llite/namei.c
@@ -264,7 +264,7 @@ int ll_md_blocking_ast(struct ldlm_lock *lock, struct ldlm_lock_desc *desc,
 
                 if ((bits & (MDS_INODELOCK_LOOKUP | MDS_INODELOCK_PERM)) &&
                     inode->i_sb->s_root != NULL &&
-                    is_root_inode(inode))
+                    !is_root_inode(inode))
                         ll_invalidate_aliases(inode);
 
                 iput(inode);
diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c
index f8ec32298906..55f6774f706f 100644
--- a/drivers/target/iscsi/iscsi_target.c
+++ b/drivers/target/iscsi/iscsi_target.c
@@ -944,17 +944,17 @@ int iscsit_setup_scsi_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
          */
         if ((iscsi_task_attr == ISCSI_ATTR_UNTAGGED) ||
             (iscsi_task_attr == ISCSI_ATTR_SIMPLE))
-                sam_task_attr = MSG_SIMPLE_TAG;
+                sam_task_attr = TCM_SIMPLE_TAG;
         else if (iscsi_task_attr == ISCSI_ATTR_ORDERED)
-                sam_task_attr = MSG_ORDERED_TAG;
+                sam_task_attr = TCM_ORDERED_TAG;
         else if (iscsi_task_attr == ISCSI_ATTR_HEAD_OF_QUEUE)
-                sam_task_attr = MSG_HEAD_TAG;
+                sam_task_attr = TCM_HEAD_TAG;
         else if (iscsi_task_attr == ISCSI_ATTR_ACA)
-                sam_task_attr = MSG_ACA_TAG;
+                sam_task_attr = TCM_ACA_TAG;
         else {
                 pr_debug("Unknown iSCSI Task Attribute: 0x%02x, using"
-                        " MSG_SIMPLE_TAG\n", iscsi_task_attr);
-                sam_task_attr = MSG_SIMPLE_TAG;
+                        " TCM_SIMPLE_TAG\n", iscsi_task_attr);
+                sam_task_attr = TCM_SIMPLE_TAG;
         }
 
         cmd->iscsi_opcode       = ISCSI_OP_SCSI_CMD;
@@ -1812,7 +1812,7 @@ iscsit_handle_task_mgt_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
                 transport_init_se_cmd(&cmd->se_cmd,
                                       &lio_target_fabric_configfs->tf_ops,
                                       conn->sess->se_sess, 0, DMA_NONE,
-                                      MSG_SIMPLE_TAG, cmd->sense_buffer + 2);
+                                      TCM_SIMPLE_TAG, cmd->sense_buffer + 2);
 
                 target_get_sess_cmd(conn->sess->se_sess, &cmd->se_cmd, true);
                 sess_ref = true;
diff --git a/drivers/target/loopback/tcm_loop.c b/drivers/target/loopback/tcm_loop.c
index 7172a71f9f0b..6b3c32954689 100644
--- a/drivers/target/loopback/tcm_loop.c
+++ b/drivers/target/loopback/tcm_loop.c
@@ -168,7 +168,7 @@ static void tcm_loop_submission_work(struct work_struct *work)
 
         rc = target_submit_cmd_map_sgls(se_cmd, tl_nexus->se_sess, sc->cmnd,
                         &tl_cmd->tl_sense_buf[0], tl_cmd->sc->device->lun,
-                        transfer_length, MSG_SIMPLE_TAG,
+                        transfer_length, TCM_SIMPLE_TAG,
                         sc->sc_data_direction, 0,
                         scsi_sglist(sc), scsi_sg_count(sc),
                         sgl_bidi, sgl_bidi_count,
@@ -258,7 +258,7 @@ static int tcm_loop_issue_tmr(struct tcm_loop_tpg *tl_tpg,
          * Initialize struct se_cmd descriptor from target_core_mod infrastructure
          */
         transport_init_se_cmd(se_cmd, se_tpg->se_tpg_tfo, se_sess, 0,
-                                DMA_NONE, MSG_SIMPLE_TAG,
+                                DMA_NONE, TCM_SIMPLE_TAG,
                                 &tl_cmd->tl_sense_buf[0]);
 
         rc = core_tmr_alloc_req(se_cmd, tl_tmr, tmr, GFP_KERNEL);
@@ -369,7 +369,6 @@ static struct scsi_host_template tcm_loop_driver_template = {
         .name                   = "TCM_Loopback",
         .queuecommand           = tcm_loop_queuecommand,
         .change_queue_depth     = scsi_change_queue_depth,
-        .change_queue_type      = scsi_change_queue_type,
         .eh_abort_handler = tcm_loop_abort_task,
         .eh_device_reset_handler = tcm_loop_device_reset,
         .eh_target_reset_handler = tcm_loop_target_reset,
diff --git a/drivers/target/sbp/sbp_target.c b/drivers/target/sbp/sbp_target.c
index e7e93727553c..9512af6a8114 100644
--- a/drivers/target/sbp/sbp_target.c
+++ b/drivers/target/sbp/sbp_target.c
@@ -1237,7 +1237,7 @@ static void sbp_handle_command(struct sbp_target_request *req)
 
         if (target_submit_cmd(&req->se_cmd, sess->se_sess, req->cmd_buf,
                               req->sense_buf, unpacked_lun, data_length,
-                              MSG_SIMPLE_TAG, data_dir, 0))
+                              TCM_SIMPLE_TAG, data_dir, 0))
                 goto err;
 
         return;
diff --git a/drivers/target/target_core_pscsi.c b/drivers/target/target_core_pscsi.c
index 74873e42cf7e..1045dcd7bf65 100644
--- a/drivers/target/target_core_pscsi.c
+++ b/drivers/target/target_core_pscsi.c
@@ -1095,7 +1095,7 @@ pscsi_execute_cmd(struct se_cmd *cmd)
         req->retries = PS_RETRY;
 
         blk_execute_rq_nowait(pdv->pdv_sd->request_queue, NULL, req,
-                        (cmd->sam_task_attr == MSG_HEAD_TAG),
+                        (cmd->sam_task_attr == TCM_HEAD_TAG),
                         pscsi_req_done);
 
         return 0;
diff --git a/drivers/target/target_core_sbc.c b/drivers/target/target_core_sbc.c
index 8d171ff77e75..11bea1952435 100644
--- a/drivers/target/target_core_sbc.c
+++ b/drivers/target/target_core_sbc.c
@@ -485,7 +485,7 @@ static sense_reason_t compare_and_write_callback(struct se_cmd *cmd)
         cmd->t_data_nents_orig = cmd->t_data_nents;
         cmd->t_data_nents = 1;
 
-        cmd->sam_task_attr = MSG_HEAD_TAG;
+        cmd->sam_task_attr = TCM_HEAD_TAG;
         cmd->transport_complete_callback = compare_and_write_post;
         /*
          * Now reset ->execute_cmd() to the normal sbc_execute_rw() handler
diff --git a/drivers/target/target_core_spc.c b/drivers/target/target_core_spc.c
index bc286a67af7c..1307600fe726 100644
--- a/drivers/target/target_core_spc.c
+++ b/drivers/target/target_core_spc.c
@@ -1357,7 +1357,7 @@ spc_parse_cdb(struct se_cmd *cmd, unsigned int *size)
                  * Do implicit HEAD_OF_QUEUE processing for INQUIRY.
                  * See spc4r17 section 5.3
                  */
-                cmd->sam_task_attr = MSG_HEAD_TAG;
+                cmd->sam_task_attr = TCM_HEAD_TAG;
                 cmd->execute_cmd = spc_emulate_inquiry;
                 break;
         case SECURITY_PROTOCOL_IN:
@@ -1391,7 +1391,7 @@ spc_parse_cdb(struct se_cmd *cmd, unsigned int *size)
                  * Do implicit HEAD_OF_QUEUE processing for REPORT_LUNS
                  * See spc4r17 section 5.3
                  */
-                cmd->sam_task_attr = MSG_HEAD_TAG;
+                cmd->sam_task_attr = TCM_HEAD_TAG;
                 break;
         case TEST_UNIT_READY:
                 cmd->execute_cmd = spc_emulate_testunitready;
diff --git a/drivers/target/target_core_transport.c b/drivers/target/target_core_transport.c
index be877bf6f730..0adc0f650213 100644
--- a/drivers/target/target_core_transport.c
+++ b/drivers/target/target_core_transport.c
@@ -1159,7 +1159,7 @@ transport_check_alloc_task_attr(struct se_cmd *cmd)
         if (dev->transport->transport_type == TRANSPORT_PLUGIN_PHBA_PDEV)
                 return 0;
 
-        if (cmd->sam_task_attr == MSG_ACA_TAG) {
+        if (cmd->sam_task_attr == TCM_ACA_TAG) {
                 pr_debug("SAM Task Attribute ACA"
                         " emulation is not supported\n");
                 return TCM_INVALID_CDB_FIELD;
@@ -1531,7 +1531,7 @@ int target_submit_tmr(struct se_cmd *se_cmd, struct se_session *se_sess,
         BUG_ON(!se_tpg);
 
         transport_init_se_cmd(se_cmd, se_tpg->se_tpg_tfo, se_sess,
-                              0, DMA_NONE, MSG_SIMPLE_TAG, sense);
+                              0, DMA_NONE, TCM_SIMPLE_TAG, sense);
         /*
          * FIXME: Currently expect caller to handle se_cmd->se_tmr_req
          * allocation failure.
@@ -1718,12 +1718,12 @@ static bool target_handle_task_attr(struct se_cmd *cmd)
          * to allow the passed struct se_cmd list of tasks to the front of the list.
          */
         switch (cmd->sam_task_attr) {
-        case MSG_HEAD_TAG:
+        case TCM_HEAD_TAG:
                 pr_debug("Added HEAD_OF_QUEUE for CDB: 0x%02x, "
                          "se_ordered_id: %u\n",
                          cmd->t_task_cdb[0], cmd->se_ordered_id);
                 return false;
-        case MSG_ORDERED_TAG:
+        case TCM_ORDERED_TAG:
                 atomic_inc_mb(&dev->dev_ordered_sync);
 
                 pr_debug("Added ORDERED for CDB: 0x%02x to ordered list, "
@@ -1828,7 +1828,7 @@ static void target_restart_delayed_cmds(struct se_device *dev)
 
                 __target_execute_cmd(cmd);
 
-                if (cmd->sam_task_attr == MSG_ORDERED_TAG)
+                if (cmd->sam_task_attr == TCM_ORDERED_TAG)
                         break;
         }
 }
@@ -1844,18 +1844,18 @@ static void transport_complete_task_attr(struct se_cmd *cmd)
         if (dev->transport->transport_type == TRANSPORT_PLUGIN_PHBA_PDEV)
                 return;
 
-        if (cmd->sam_task_attr == MSG_SIMPLE_TAG) {
+        if (cmd->sam_task_attr == TCM_SIMPLE_TAG) {
                 atomic_dec_mb(&dev->simple_cmds);
                 dev->dev_cur_ordered_id++;
                 pr_debug("Incremented dev->dev_cur_ordered_id: %u for"
                         " SIMPLE: %u\n", dev->dev_cur_ordered_id,
                         cmd->se_ordered_id);
-        } else if (cmd->sam_task_attr == MSG_HEAD_TAG) {
+        } else if (cmd->sam_task_attr == TCM_HEAD_TAG) {
                 dev->dev_cur_ordered_id++;
                 pr_debug("Incremented dev_cur_ordered_id: %u for"
                         " HEAD_OF_QUEUE: %u\n", dev->dev_cur_ordered_id,
                         cmd->se_ordered_id);
-        } else if (cmd->sam_task_attr == MSG_ORDERED_TAG) {
+        } else if (cmd->sam_task_attr == TCM_ORDERED_TAG) {
                 atomic_dec_mb(&dev->dev_ordered_sync);
 
                 dev->dev_cur_ordered_id++;
diff --git a/drivers/target/tcm_fc/tfc_cmd.c b/drivers/target/tcm_fc/tfc_cmd.c
index be0c0d08c56a..edcafa4490c0 100644
--- a/drivers/target/tcm_fc/tfc_cmd.c
+++ b/drivers/target/tcm_fc/tfc_cmd.c
@@ -554,17 +554,17 @@ static void ft_send_work(struct work_struct *work)
          */
         switch (fcp->fc_pri_ta & FCP_PTA_MASK) {
         case FCP_PTA_HEADQ:
-                task_attr = MSG_HEAD_TAG;
+                task_attr = TCM_HEAD_TAG;
                 break;
         case FCP_PTA_ORDERED:
-                task_attr = MSG_ORDERED_TAG;
+                task_attr = TCM_ORDERED_TAG;
                 break;
         case FCP_PTA_ACA:
-                task_attr = MSG_ACA_TAG;
+                task_attr = TCM_ACA_TAG;
                 break;
         case FCP_PTA_SIMPLE: /* Fallthrough */
         default:
-                task_attr = MSG_SIMPLE_TAG;
+                task_attr = TCM_SIMPLE_TAG;
         }
 
         fc_seq_exch(cmd->seq)->lp->tt.seq_set_resp(cmd->seq, ft_recv_seq, cmd);
diff --git a/drivers/tty/serial/8250/8250_omap.c b/drivers/tty/serial/8250/8250_omap.c
index 336602eb453e..96b69bfd773f 100644
--- a/drivers/tty/serial/8250/8250_omap.c
+++ b/drivers/tty/serial/8250/8250_omap.c
@@ -561,7 +561,7 @@ static int omap_8250_startup(struct uart_port *port)
         if (ret)
                 goto err;
 
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
         up->capabilities |= UART_CAP_RPM;
 #endif
 
@@ -997,12 +997,12 @@ static int omap8250_probe(struct platform_device *pdev)
         up.port.fifosize = 64;
         up.tx_loadsz = 64;
         up.capabilities = UART_CAP_FIFO;
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
         /*
-         * PM_RUNTIME is mostly transparent. However to do it right we need to a
+         * Runtime PM is mostly transparent. However to do it right we need to a
          * TX empty interrupt before we can put the device to auto idle. So if
-         * PM_RUNTIME is not enabled we don't add that flag and can spare that
-         * one extra interrupt in the TX path.
+         * PM is not enabled we don't add that flag and can spare that one extra
+         * interrupt in the TX path.
          */
         up.capabilities |= UART_CAP_RPM;
 #endif
@@ -1105,7 +1105,7 @@ static int omap8250_remove(struct platform_device *pdev)
         return 0;
 }
 
-#if defined(CONFIG_PM_SLEEP) || defined(CONFIG_PM_RUNTIME)
+#ifdef CONFIG_PM
 
 static inline void omap8250_enable_wakeirq(struct omap8250_priv *priv,
                                            bool enable)
@@ -1179,7 +1179,7 @@ static int omap8250_resume(struct device *dev)
 #define omap8250_complete NULL
 #endif
 
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
 static int omap8250_lost_context(struct uart_8250_port *up)
 {
         u32 val;
diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c
index 024f58475a94..3a494168661e 100644
--- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c
+++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c
@@ -1131,19 +1131,19 @@ static int usbg_submit_command(struct f_uas *fu,
 
         switch (cmd_iu->prio_attr & 0x7) {
         case UAS_HEAD_TAG:
-                cmd->prio_attr = MSG_HEAD_TAG;
+                cmd->prio_attr = TCM_HEAD_TAG;
                 break;
         case UAS_ORDERED_TAG:
-                cmd->prio_attr = MSG_ORDERED_TAG;
+                cmd->prio_attr = TCM_ORDERED_TAG;
                 break;
         case UAS_ACA:
-                cmd->prio_attr = MSG_ACA_TAG;
+                cmd->prio_attr = TCM_ACA_TAG;
                 break;
         default:
                 pr_debug_once("Unsupported prio_attr: %02x.\n",
                                 cmd_iu->prio_attr);
         case UAS_SIMPLE_TAG:
-                cmd->prio_attr = MSG_SIMPLE_TAG;
+                cmd->prio_attr = TCM_SIMPLE_TAG;
                 break;
         }
 
@@ -1240,7 +1240,7 @@ static int bot_submit_command(struct f_uas *fu,
                 goto err;
         }
 
-        cmd->prio_attr = MSG_SIMPLE_TAG;
+        cmd->prio_attr = TCM_SIMPLE_TAG;
         se_cmd = &cmd->se_cmd;
         cmd->unpacked_lun = cbw->Lun;
         cmd->is_read = cbw->Flags & US_BULK_FLAG_IN ? 1 : 0;
diff --git a/drivers/usb/host/isp1760-hcd.c b/drivers/usb/host/isp1760-hcd.c
index e752c3098f38..395649f357aa 100644
--- a/drivers/usb/host/isp1760-hcd.c
+++ b/drivers/usb/host/isp1760-hcd.c
@@ -1739,7 +1739,7 @@ static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
         int retval = 1;
         unsigned long flags;
 
-        /* if !PM_RUNTIME, root hub timers won't get shut down ... */
+        /* if !PM, root hub timers won't get shut down ... */
         if (!HC_IS_RUNNING(hcd->state))
                 return 0;
 
diff --git a/drivers/usb/host/oxu210hp-hcd.c b/drivers/usb/host/oxu210hp-hcd.c
index 75811dd5a9d7..036924e640f5 100644
--- a/drivers/usb/host/oxu210hp-hcd.c
+++ b/drivers/usb/host/oxu210hp-hcd.c
@@ -3087,7 +3087,7 @@ static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf)
         int ports, i, retval = 1;
         unsigned long flags;
 
-        /* if !PM_RUNTIME, root hub timers won't get shut down ... */
+        /* if !PM, root hub timers won't get shut down ... */
         if (!HC_IS_RUNNING(hcd->state))
                 return 0;
 
diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c
index 50610a6acf3d..e999496eda3e 100644
--- a/drivers/xen/xen-scsiback.c
+++ b/drivers/xen/xen-scsiback.c
@@ -606,7 +606,7 @@ static void scsiback_device_action(struct vscsibk_pend *pending_req,
         init_waitqueue_head(&tmr->tmr_wait);
 
         transport_init_se_cmd(se_cmd, tpg->se_tpg.se_tpg_tfo,
-                tpg->tpg_nexus->tvn_se_sess, 0, DMA_NONE, MSG_SIMPLE_TAG,
+                tpg->tpg_nexus->tvn_se_sess, 0, DMA_NONE, TCM_SIMPLE_TAG,
                 &pending_req->sense_buffer[0]);
 
         rc = core_tmr_alloc_req(se_cmd, tmr, act, GFP_KERNEL);
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 8ba35c622e22..e1b2e8b98af7 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -901,11 +901,15 @@ extern int drm_vblank_init(struct drm_device *dev, int num_crtcs);
 extern int drm_wait_vblank(struct drm_device *dev, void *data,
                            struct drm_file *filp);
 extern u32 drm_vblank_count(struct drm_device *dev, int crtc);
+extern u32 drm_crtc_vblank_count(struct drm_crtc *crtc);
 extern u32 drm_vblank_count_and_time(struct drm_device *dev, int crtc,
                                      struct timeval *vblanktime);
 extern void drm_send_vblank_event(struct drm_device *dev, int crtc,
                                      struct drm_pending_vblank_event *e);
+extern void drm_crtc_send_vblank_event(struct drm_crtc *crtc,
+                                       struct drm_pending_vblank_event *e);
 extern bool drm_handle_vblank(struct drm_device *dev, int crtc);
+extern bool drm_crtc_handle_vblank(struct drm_crtc *crtc);
 extern int drm_vblank_get(struct drm_device *dev, int crtc);
 extern void drm_vblank_put(struct drm_device *dev, int crtc);
 extern int drm_crtc_vblank_get(struct drm_crtc *crtc);
diff --git a/include/drm/drm_gem.h b/include/drm/drm_gem.h
index 780511a459c0..1e6ae1458f7a 100644
--- a/include/drm/drm_gem.h
+++ b/include/drm/drm_gem.h
@@ -119,13 +119,6 @@ struct drm_gem_object {
          * simply leave it as NULL.
          */
         struct dma_buf_attachment *import_attach;
-
-        /**
-         * dumb - created as dumb buffer
-         * Whether the gem object was created using the dumb buffer interface
-         * as such it may not be used for GPU rendering.
-         */
-        bool dumb;
 };
 
 void drm_gem_object_release(struct drm_gem_object *obj);
diff --git a/include/dt-bindings/clock/exynos4415.h b/include/dt-bindings/clock/exynos4415.h
new file mode 100644
index 000000000000..7eed55100721
--- /dev/null
+++ b/include/dt-bindings/clock/exynos4415.h
@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung Exynos4415 clock controllers.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/*
+ * Main CMU
+ */
+
+#define CLK_OSCSEL                      1
+#define CLK_FIN_PLL                     2
+#define CLK_FOUT_APLL                   3
+#define CLK_FOUT_MPLL                   4
+#define CLK_FOUT_EPLL                   5
+#define CLK_FOUT_G3D_PLL                6
+#define CLK_FOUT_ISP_PLL                7
+#define CLK_FOUT_DISP_PLL               8
+
+/* Muxes */
+#define CLK_MOUT_MPLL_USER_L            16
+#define CLK_MOUT_GDL                    17
+#define CLK_MOUT_MPLL_USER_R            18
+#define CLK_MOUT_GDR                    19
+#define CLK_MOUT_EBI                    20
+#define CLK_MOUT_ACLK_200               21
+#define CLK_MOUT_ACLK_160               22
+#define CLK_MOUT_ACLK_100               23
+#define CLK_MOUT_ACLK_266               24
+#define CLK_MOUT_G3D_PLL                25
+#define CLK_MOUT_EPLL                   26
+#define CLK_MOUT_EBI_1                  27
+#define CLK_MOUT_ISP_PLL                28
+#define CLK_MOUT_DISP_PLL               29
+#define CLK_MOUT_MPLL_USER_T            30
+#define CLK_MOUT_ACLK_400_MCUISP        31
+#define CLK_MOUT_G3D_PLLSRC             32
+#define CLK_MOUT_CSIS1                  33
+#define CLK_MOUT_CSIS0                  34
+#define CLK_MOUT_CAM1                   35
+#define CLK_MOUT_FIMC3_LCLK             36
+#define CLK_MOUT_FIMC2_LCLK             37
+#define CLK_MOUT_FIMC1_LCLK             38
+#define CLK_MOUT_FIMC0_LCLK             39
+#define CLK_MOUT_MFC                    40
+#define CLK_MOUT_MFC_1                  41
+#define CLK_MOUT_MFC_0                  42
+#define CLK_MOUT_G3D                    43
+#define CLK_MOUT_G3D_1                  44
+#define CLK_MOUT_G3D_0                  45
+#define CLK_MOUT_MIPI0                  46
+#define CLK_MOUT_FIMD0                  47
+#define CLK_MOUT_TSADC_ISP              48
+#define CLK_MOUT_UART_ISP               49
+#define CLK_MOUT_SPI1_ISP               50
+#define CLK_MOUT_SPI0_ISP               51
+#define CLK_MOUT_PWM_ISP                52
+#define CLK_MOUT_AUDIO0                 53
+#define CLK_MOUT_TSADC                  54
+#define CLK_MOUT_MMC2                   55
+#define CLK_MOUT_MMC1                   56
+#define CLK_MOUT_MMC0                   57
+#define CLK_MOUT_UART3                  58
+#define CLK_MOUT_UART2                  59
+#define CLK_MOUT_UART1                  60
+#define CLK_MOUT_UART0                  61
+#define CLK_MOUT_SPI2                   62
+#define CLK_MOUT_SPI1                   63
+#define CLK_MOUT_SPI0                   64
+#define CLK_MOUT_SPDIF                  65
+#define CLK_MOUT_AUDIO2                 66
+#define CLK_MOUT_AUDIO1                 67
+#define CLK_MOUT_MPLL_USER_C            68
+#define CLK_MOUT_HPM                    69
+#define CLK_MOUT_CORE                   70
+#define CLK_MOUT_APLL                   71
+#define CLK_MOUT_PXLASYNC_CSIS1_FIMC    72
+#define CLK_MOUT_PXLASYNC_CSIS0_FIMC    73
+#define CLK_MOUT_JPEG                   74
+#define CLK_MOUT_JPEG1                  75
+#define CLK_MOUT_JPEG0                  76
+#define CLK_MOUT_ACLK_ISP0_300          77
+#define CLK_MOUT_ACLK_ISP0_400          78
+#define CLK_MOUT_ACLK_ISP0_300_USER     79
+#define CLK_MOUT_ACLK_ISP1_300          80
+#define CLK_MOUT_ACLK_ISP1_300_USER     81
+#define CLK_MOUT_HDMI                   82
+
+/* Dividers */
+#define CLK_DIV_GPL                     90
+#define CLK_DIV_GDL                     91
+#define CLK_DIV_GPR                     92
+#define CLK_DIV_GDR                     93
+#define CLK_DIV_ACLK_400_MCUISP         94
+#define CLK_DIV_EBI                     95
+#define CLK_DIV_ACLK_200                96
+#define CLK_DIV_ACLK_160                97
+#define CLK_DIV_ACLK_100                98
+#define CLK_DIV_ACLK_266                99
+#define CLK_DIV_CSIS1                   100
+#define CLK_DIV_CSIS0                   101
+#define CLK_DIV_CAM1                    102
+#define CLK_DIV_FIMC3_LCLK              103
+#define CLK_DIV_FIMC2_LCLK              104
+#define CLK_DIV_FIMC1_LCLK              105
+#define CLK_DIV_FIMC0_LCLK              106
+#define CLK_DIV_TV_BLK                  107
+#define CLK_DIV_MFC                     108
+#define CLK_DIV_G3D                     109
+#define CLK_DIV_MIPI0_PRE               110
+#define CLK_DIV_MIPI0                   111
+#define CLK_DIV_FIMD0                   112
+#define CLK_DIV_UART_ISP                113
+#define CLK_DIV_SPI1_ISP_PRE            114
+#define CLK_DIV_SPI1_ISP                115
+#define CLK_DIV_SPI0_ISP_PRE            116
+#define CLK_DIV_SPI0_ISP                117
+#define CLK_DIV_PWM_ISP                 118
+#define CLK_DIV_PCM0                    119
+#define CLK_DIV_AUDIO0                  120
+#define CLK_DIV_TSADC_PRE               121
+#define CLK_DIV_TSADC                   122
+#define CLK_DIV_MMC1_PRE                123
+#define CLK_DIV_MMC1                    124
+#define CLK_DIV_MMC0_PRE                125
+#define CLK_DIV_MMC0                    126
+#define CLK_DIV_MMC2_PRE                127
+#define CLK_DIV_MMC2                    128
+#define CLK_DIV_UART3                   129
+#define CLK_DIV_UART2                   130
+#define CLK_DIV_UART1                   131
+#define CLK_DIV_UART0                   132
+#define CLK_DIV_SPI1_PRE                133
+#define CLK_DIV_SPI1                    134
+#define CLK_DIV_SPI0_PRE                135
+#define CLK_DIV_SPI0                    136
+#define CLK_DIV_SPI2_PRE                137
+#define CLK_DIV_SPI2                    138
+#define CLK_DIV_PCM2                    139
+#define CLK_DIV_AUDIO2                  140
+#define CLK_DIV_PCM1                    141
+#define CLK_DIV_AUDIO1                  142
+#define CLK_DIV_I2S1                    143
+#define CLK_DIV_PXLASYNC_CSIS1_FIMC     144
+#define CLK_DIV_PXLASYNC_CSIS0_FIMC     145
+#define CLK_DIV_JPEG                    146
+#define CLK_DIV_CORE2                   147
+#define CLK_DIV_APLL                    148
+#define CLK_DIV_PCLK_DBG                149
+#define CLK_DIV_ATB                     150
+#define CLK_DIV_PERIPH                  151
+#define CLK_DIV_COREM1                  152
+#define CLK_DIV_COREM0                  153
+#define CLK_DIV_CORE                    154
+#define CLK_DIV_HPM                     155
+#define CLK_DIV_COPY                    156
+
+/* Gates */
+#define CLK_ASYNC_G3D                   180
+#define CLK_ASYNC_MFCL                  181
+#define CLK_ASYNC_TVX                   182
+#define CLK_PPMULEFT                    183
+#define CLK_GPIO_LEFT                   184
+#define CLK_PPMUIMAGE                   185
+#define CLK_QEMDMA2                     186
+#define CLK_QEROTATOR                   187
+#define CLK_SMMUMDMA2                   188
+#define CLK_SMMUROTATOR                 189
+#define CLK_MDMA2                       190
+#define CLK_ROTATOR                     191
+#define CLK_ASYNC_ISPMX                 192
+#define CLK_ASYNC_MAUDIOX               193
+#define CLK_ASYNC_MFCR                  194
+#define CLK_ASYNC_FSYSD                 195
+#define CLK_ASYNC_LCD0X                 196
+#define CLK_ASYNC_CAMX                  197
+#define CLK_PPMURIGHT                   198
+#define CLK_GPIO_RIGHT                  199
+#define CLK_ANTIRBK_APBIF               200
+#define CLK_EFUSE_WRITER_APBIF          201
+#define CLK_MONOCNT                     202
+#define CLK_TZPC6                       203
+#define CLK_PROVISIONKEY1               204
+#define CLK_PROVISIONKEY0               205
+#define CLK_CMU_ISPPART                 206
+#define CLK_TMU_APBIF                   207
+#define CLK_KEYIF                       208
+#define CLK_RTC                         209
+#define CLK_WDT                         210
+#define CLK_MCT                         211
+#define CLK_SECKEY                      212
+#define CLK_HDMI_CEC                    213
+#define CLK_TZPC5                       214
+#define CLK_TZPC4                       215
+#define CLK_TZPC3                       216
+#define CLK_TZPC2                       217
+#define CLK_TZPC1                       218
+#define CLK_TZPC0                       219
+#define CLK_CMU_COREPART                220
+#define CLK_CMU_TOPPART                 221
+#define CLK_PMU_APBIF                   222
+#define CLK_SYSREG                      223
+#define CLK_CHIP_ID                     224
+#define CLK_SMMUFIMC_LITE2              225
+#define CLK_FIMC_LITE2                  226
+#define CLK_PIXELASYNCM1                227
+#define CLK_PIXELASYNCM0                228
+#define CLK_PPMUCAMIF                   229
+#define CLK_SMMUJPEG                    230
+#define CLK_SMMUFIMC3                   231
+#define CLK_SMMUFIMC2                   232
+#define CLK_SMMUFIMC1                   233
+#define CLK_SMMUFIMC0                   234
+#define CLK_JPEG                        235
+#define CLK_CSIS1                       236
+#define CLK_CSIS0                       237
+#define CLK_FIMC3                       238
+#define CLK_FIMC2                       239
+#define CLK_FIMC1                       240
+#define CLK_FIMC0                       241
+#define CLK_PPMUTV                      242
+#define CLK_SMMUTV                      243
+#define CLK_HDMI                        244
+#define CLK_MIXER                       245
+#define CLK_VP                          246
+#define CLK_PPMUMFC_R                   247
+#define CLK_PPMUMFC_L                   248
+#define CLK_SMMUMFC_R                   249
+#define CLK_SMMUMFC_L                   250
+#define CLK_MFC                         251
+#define CLK_PPMUG3D                     252
+#define CLK_G3D                         253
+#define CLK_PPMULCD0                    254
+#define CLK_SMMUFIMD0                   255
+#define CLK_DSIM0                       256
+#define CLK_SMIES                       257
+#define CLK_MIE0                        258
+#define CLK_FIMD0                       259
+#define CLK_TSADC                       260
+#define CLK_PPMUFILE                    261
+#define CLK_NFCON                       262
+#define CLK_USBDEVICE                   263
+#define CLK_USBHOST                     264
+#define CLK_SROMC                       265
+#define CLK_SDMMC2                      266
+#define CLK_SDMMC1                      267
+#define CLK_SDMMC0                      268
+#define CLK_PDMA1                       269
+#define CLK_PDMA0                       270
+#define CLK_SPDIF                       271
+#define CLK_PWM                         272
+#define CLK_PCM2                        273
+#define CLK_PCM1                        274
+#define CLK_I2S1                        275
+#define CLK_SPI2                        276
+#define CLK_SPI1                        277
+#define CLK_SPI0                        278
+#define CLK_I2CHDMI                     279
+#define CLK_I2C7                        280
+#define CLK_I2C6                        281
+#define CLK_I2C5                        282
+#define CLK_I2C4                        283
+#define CLK_I2C3                        284
+#define CLK_I2C2                        285
+#define CLK_I2C1                        286
+#define CLK_I2C0                        287
+#define CLK_UART3                       288
+#define CLK_UART2                       289
+#define CLK_UART1                       290
+#define CLK_UART0                       291
+
+/* Special clocks */
+#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC    330
+#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC    331
+#define CLK_SCLK_JPEG                   332
+#define CLK_SCLK_CSIS1                  333
+#define CLK_SCLK_CSIS0                  334
+#define CLK_SCLK_CAM1                   335
+#define CLK_SCLK_FIMC3_LCLK             336
+#define CLK_SCLK_FIMC2_LCLK             337
+#define CLK_SCLK_FIMC1_LCLK             338
+#define CLK_SCLK_FIMC0_LCLK             339
+#define CLK_SCLK_PIXEL                  340
+#define CLK_SCLK_HDMI                   341
+#define CLK_SCLK_MIXER                  342
+#define CLK_SCLK_MFC                    343
+#define CLK_SCLK_G3D                    344
+#define CLK_SCLK_MIPIDPHY4L             345
+#define CLK_SCLK_MIPI0                  346
+#define CLK_SCLK_MDNIE0                 347
+#define CLK_SCLK_FIMD0                  348
+#define CLK_SCLK_PCM0                   349
+#define CLK_SCLK_AUDIO0                 350
+#define CLK_SCLK_TSADC                  351
+#define CLK_SCLK_EBI                    352
+#define CLK_SCLK_MMC2                   353
+#define CLK_SCLK_MMC1                   354
+#define CLK_SCLK_MMC0                   355
+#define CLK_SCLK_I2S                    356
+#define CLK_SCLK_PCM2                   357
+#define CLK_SCLK_PCM1                   358
+#define CLK_SCLK_AUDIO2                 359
+#define CLK_SCLK_AUDIO1                 360
+#define CLK_SCLK_SPDIF                  361
+#define CLK_SCLK_SPI2                   362
+#define CLK_SCLK_SPI1                   363
+#define CLK_SCLK_SPI0                   364
+#define CLK_SCLK_UART3                  365
+#define CLK_SCLK_UART2                  366
+#define CLK_SCLK_UART1                  367
+#define CLK_SCLK_UART0                  368
+#define CLK_SCLK_HDMIPHY                369
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define CLK_NR_CLKS                     370
+
+/*
+ * CMU DMC
+ */
+#define CLK_DMC_FOUT_MPLL               1
+#define CLK_DMC_FOUT_BPLL               2
+
+#define CLK_DMC_MOUT_MPLL               3
+#define CLK_DMC_MOUT_BPLL               4
+#define CLK_DMC_MOUT_DPHY               5
+#define CLK_DMC_MOUT_DMC_BUS            6
+
+#define CLK_DMC_DIV_DMC                 7
+#define CLK_DMC_DIV_DPHY                8
+#define CLK_DMC_DIV_DMC_PRE             9
+#define CLK_DMC_DIV_DMCP                10
+#define CLK_DMC_DIV_DMCD                11
+#define CLK_DMC_DIV_MPLL_PRE            12
+
+/*
+ * Total number of clocks of CMU_DMC.
+ * NOTE: Must be equal to highest clock ID increased by one.
+ */
+#define NR_CLKS_DMC                     13
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
new file mode 100644
index 000000000000..8e4681b07ae7
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS                 1
+#define DOUT_SCLK_BUS0_PLL              2
+#define DOUT_SCLK_BUS1_PLL              3
+#define DOUT_SCLK_CC_PLL                4
+#define DOUT_SCLK_MFC_PLL               5
+#define DOUT_ACLK_CCORE_133             6
+#define TOPC_NR_CLK                     7
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1                1
+#define DOUT_ACLK_PERIC0                2
+#define CLK_SCLK_UART0                  3
+#define CLK_SCLK_UART1                  4
+#define CLK_SCLK_UART2                  5
+#define CLK_SCLK_UART3                  6
+#define TOP0_NR_CLK                     7
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200             1
+#define DOUT_ACLK_FSYS0_200             2
+#define DOUT_SCLK_MMC2                  3
+#define DOUT_SCLK_MMC1                  4
+#define DOUT_SCLK_MMC0                  5
+#define CLK_SCLK_MMC2                   6
+#define CLK_SCLK_MMC1                   7
+#define CLK_SCLK_MMC0                   8
+#define TOP1_NR_CLK                     9
+
+/* CCORE */
+#define PCLK_RTC                        1
+#define CCORE_NR_CLK                    2
+
+/* PERIC0 */
+#define PCLK_UART0                      1
+#define SCLK_UART0                      2
+#define PCLK_HSI2C0                     3
+#define PCLK_HSI2C1                     4
+#define PCLK_HSI2C4                     5
+#define PCLK_HSI2C5                     6
+#define PCLK_HSI2C9                     7
+#define PCLK_HSI2C10                    8
+#define PCLK_HSI2C11                    9
+#define PCLK_PWM                        10
+#define SCLK_PWM                        11
+#define PCLK_ADCIF                      12
+#define PERIC0_NR_CLK                   13
+
+/* PERIC1 */
+#define PCLK_UART1                      1
+#define PCLK_UART2                      2
+#define PCLK_UART3                      3
+#define SCLK_UART1                      4
+#define SCLK_UART2                      5
+#define SCLK_UART3                      6
+#define PCLK_HSI2C2                     7
+#define PCLK_HSI2C3                     8
+#define PCLK_HSI2C6                     9
+#define PCLK_HSI2C7                     10
+#define PCLK_HSI2C8                     11
+#define PERIC1_NR_CLK                   12
+
+/* PERIS */
+#define PCLK_CHIPID                     1
+#define SCLK_CHIPID                     2
+#define PCLK_WDT                        3
+#define PCLK_TMU                        4
+#define SCLK_TMU                        5
+#define PERIS_NR_CLK                    6
+
+/* FSYS0 */
+#define ACLK_MMC2                       1
+#define FSYS0_NR_CLK                    2
+
+/* FSYS1 */
+#define ACLK_MMC1                       1
+#define ACLK_MMC0                       2
+#define FSYS1_NR_CLK                    3
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h
new file mode 100644
index 000000000000..591f7fba89e2
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,mmp2.h
@@ -0,0 +1,74 @@
+#ifndef __DTS_MARVELL_MMP2_CLOCK_H
+#define __DTS_MARVELL_MMP2_CLOCK_H
+
+/* fixed clocks and plls */
+#define MMP2_CLK_CLK32                  1
+#define MMP2_CLK_VCTCXO                 2
+#define MMP2_CLK_PLL1                   3
+#define MMP2_CLK_PLL1_2                 8
+#define MMP2_CLK_PLL1_4                 9
+#define MMP2_CLK_PLL1_8                 10
+#define MMP2_CLK_PLL1_16                11
+#define MMP2_CLK_PLL1_3                 12
+#define MMP2_CLK_PLL1_6                 13
+#define MMP2_CLK_PLL1_12                14
+#define MMP2_CLK_PLL1_20                15
+#define MMP2_CLK_PLL2                   16
+#define MMP2_CLK_PLL2_2                 17
+#define MMP2_CLK_PLL2_4                 18
+#define MMP2_CLK_PLL2_8                 19
+#define MMP2_CLK_PLL2_16                20
+#define MMP2_CLK_PLL2_3                 21
+#define MMP2_CLK_PLL2_6                 22
+#define MMP2_CLK_PLL2_12                23
+#define MMP2_CLK_VCTCXO_2               24
+#define MMP2_CLK_VCTCXO_4               25
+#define MMP2_CLK_UART_PLL               26
+#define MMP2_CLK_USB_PLL                27
+
+/* apb periphrals */
+#define MMP2_CLK_TWSI0                  60
+#define MMP2_CLK_TWSI1                  61
+#define MMP2_CLK_TWSI2                  62
+#define MMP2_CLK_TWSI3                  63
+#define MMP2_CLK_TWSI4                  64
+#define MMP2_CLK_TWSI5                  65
+#define MMP2_CLK_GPIO                   66
+#define MMP2_CLK_KPC                    67
+#define MMP2_CLK_RTC                    68
+#define MMP2_CLK_PWM0                   69
+#define MMP2_CLK_PWM1                   70
+#define MMP2_CLK_PWM2                   71
+#define MMP2_CLK_PWM3                   72
+#define MMP2_CLK_UART0                  73
+#define MMP2_CLK_UART1                  74
+#define MMP2_CLK_UART2                  75
+#define MMP2_CLK_UART3                  76
+#define MMP2_CLK_SSP0                   77
+#define MMP2_CLK_SSP1                   78
+#define MMP2_CLK_SSP2                   79
+#define MMP2_CLK_SSP3                   80
+
+/* axi periphrals */
+#define MMP2_CLK_SDH0                   101
+#define MMP2_CLK_SDH1                   102
+#define MMP2_CLK_SDH2                   103
+#define MMP2_CLK_SDH3                   104
+#define MMP2_CLK_USB                    105
+#define MMP2_CLK_DISP0                  106
+#define MMP2_CLK_DISP0_MUX              107
+#define MMP2_CLK_DISP0_SPHY             108
+#define MMP2_CLK_DISP1                  109
+#define MMP2_CLK_DISP1_MUX              110
+#define MMP2_CLK_CCIC_ARBITER           111
+#define MMP2_CLK_CCIC0                  112
+#define MMP2_CLK_CCIC0_MIX              113
+#define MMP2_CLK_CCIC0_PHY              114
+#define MMP2_CLK_CCIC0_SPHY             115
+#define MMP2_CLK_CCIC1                  116
+#define MMP2_CLK_CCIC1_MIX              117
+#define MMP2_CLK_CCIC1_PHY              118
+#define MMP2_CLK_CCIC1_SPHY             119
+
+#define MMP2_NR_CLKS                    200
+#endif
diff --git a/include/dt-bindings/clock/marvell,pxa168.h b/include/dt-bindings/clock/marvell,pxa168.h
new file mode 100644
index 000000000000..79630b9d74b8
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,pxa168.h
@@ -0,0 +1,57 @@
+#ifndef __DTS_MARVELL_PXA168_CLOCK_H
+#define __DTS_MARVELL_PXA168_CLOCK_H
+
+/* fixed clocks and plls */
+#define PXA168_CLK_CLK32                1
+#define PXA168_CLK_VCTCXO               2
+#define PXA168_CLK_PLL1                 3
+#define PXA168_CLK_PLL1_2               8
+#define PXA168_CLK_PLL1_4               9
+#define PXA168_CLK_PLL1_8               10
+#define PXA168_CLK_PLL1_16              11
+#define PXA168_CLK_PLL1_6               12
+#define PXA168_CLK_PLL1_12              13
+#define PXA168_CLK_PLL1_24              14
+#define PXA168_CLK_PLL1_48              15
+#define PXA168_CLK_PLL1_96              16
+#define PXA168_CLK_PLL1_13              17
+#define PXA168_CLK_PLL1_13_1_5          18
+#define PXA168_CLK_PLL1_2_1_5           19
+#define PXA168_CLK_PLL1_3_16            20
+#define PXA168_CLK_UART_PLL             27
+
+/* apb periphrals */
+#define PXA168_CLK_TWSI0                60
+#define PXA168_CLK_TWSI1                61
+#define PXA168_CLK_TWSI2                62
+#define PXA168_CLK_TWSI3                63
+#define PXA168_CLK_GPIO                 64
+#define PXA168_CLK_KPC                  65
+#define PXA168_CLK_RTC                  66
+#define PXA168_CLK_PWM0                 67
+#define PXA168_CLK_PWM1                 68
+#define PXA168_CLK_PWM2                 69
+#define PXA168_CLK_PWM3                 70
+#define PXA168_CLK_UART0                71
+#define PXA168_CLK_UART1                72
+#define PXA168_CLK_UART2                73
+#define PXA168_CLK_SSP0                 74
+#define PXA168_CLK_SSP1                 75
+#define PXA168_CLK_SSP2                 76
+#define PXA168_CLK_SSP3                 77
+#define PXA168_CLK_SSP4                 78
+
+/* axi periphrals */
+#define PXA168_CLK_DFC                  100
+#define PXA168_CLK_SDH0                 101
+#define PXA168_CLK_SDH1                 102
+#define PXA168_CLK_SDH2                 103
+#define PXA168_CLK_USB                  104
+#define PXA168_CLK_SPH                  105
+#define PXA168_CLK_DISP0                106
+#define PXA168_CLK_CCIC0                107
+#define PXA168_CLK_CCIC0_PHY            108
+#define PXA168_CLK_CCIC0_SPHY           109
+
+#define PXA168_NR_CLKS                  200
+#endif
diff --git a/include/dt-bindings/clock/marvell,pxa910.h b/include/dt-bindings/clock/marvell,pxa910.h
new file mode 100644
index 000000000000..719cffb2bea2
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,pxa910.h
@@ -0,0 +1,54 @@
+#ifndef __DTS_MARVELL_PXA910_CLOCK_H
+#define __DTS_MARVELL_PXA910_CLOCK_H
+
+/* fixed clocks and plls */
+#define PXA910_CLK_CLK32                1
+#define PXA910_CLK_VCTCXO               2
+#define PXA910_CLK_PLL1                 3
+#define PXA910_CLK_PLL1_2               8
+#define PXA910_CLK_PLL1_4               9
+#define PXA910_CLK_PLL1_8               10
+#define PXA910_CLK_PLL1_16              11
+#define PXA910_CLK_PLL1_6               12
+#define PXA910_CLK_PLL1_12              13
+#define PXA910_CLK_PLL1_24              14
+#define PXA910_CLK_PLL1_48              15
+#define PXA910_CLK_PLL1_96              16
+#define PXA910_CLK_PLL1_13              17
+#define PXA910_CLK_PLL1_13_1_5          18
+#define PXA910_CLK_PLL1_2_1_5           19
+#define PXA910_CLK_PLL1_3_16            20
+#define PXA910_CLK_UART_PLL             27
+
+/* apb periphrals */
+#define PXA910_CLK_TWSI0                60
+#define PXA910_CLK_TWSI1                61
+#define PXA910_CLK_TWSI2                62
+#define PXA910_CLK_TWSI3                63
+#define PXA910_CLK_GPIO                 64
+#define PXA910_CLK_KPC                  65
+#define PXA910_CLK_RTC                  66
+#define PXA910_CLK_PWM0                 67
+#define PXA910_CLK_PWM1                 68
+#define PXA910_CLK_PWM2                 69
+#define PXA910_CLK_PWM3                 70
+#define PXA910_CLK_UART0                71
+#define PXA910_CLK_UART1                72
+#define PXA910_CLK_UART2                73
+#define PXA910_CLK_SSP0                 74
+#define PXA910_CLK_SSP1                 75
+
+/* axi periphrals */
+#define PXA910_CLK_DFC                  100
+#define PXA910_CLK_SDH0                 101
+#define PXA910_CLK_SDH1                 102
+#define PXA910_CLK_SDH2                 103
+#define PXA910_CLK_USB                  104
+#define PXA910_CLK_SPH                  105
+#define PXA910_CLK_DISP0                106
+#define PXA910_CLK_CCIC0                107
+#define PXA910_CLK_CCIC0_PHY            108
+#define PXA910_CLK_CCIC0_SPHY           109
+
+#define PXA910_NR_CLKS                  200
+#endif
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c47692..f60ce72a2b2c 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -71,6 +71,15 @@
 #define SCLK_HDMI_CEC           110
 #define SCLK_HEVC_CABAC         111
 #define SCLK_HEVC_CORE          112
+#define SCLK_I2S0_OUT           113
+#define SCLK_SDMMC_DRV          114
+#define SCLK_SDIO0_DRV          115
+#define SCLK_SDIO1_DRV          116
+#define SCLK_EMMC_DRV           117
+#define SCLK_SDMMC_SAMPLE       118
+#define SCLK_SDIO0_SAMPLE       119
+#define SCLK_SDIO1_SAMPLE       120
+#define SCLK_EMMC_SAMPLE        121
 
 #define DCLK_VOP0               190
 #define DCLK_VOP1               191
@@ -141,6 +150,10 @@
 #define PCLK_VIO2_H2P           361
 #define PCLK_CPU                362
 #define PCLK_PERI               363
+#define PCLK_DDRUPCTL0          364
+#define PCLK_PUBL0              365
+#define PCLK_DDRUPCTL1          366
+#define PCLK_PUBL1              367
 
 /* hclk gates */
 #define HCLK_GPS                448
diff --git a/include/linux/audit.h b/include/linux/audit.h
index 0c04917c2f12..af84234e1f6e 100644
--- a/include/linux/audit.h
+++ b/include/linux/audit.h
@@ -47,6 +47,7 @@ struct sk_buff;
 
 struct audit_krule {
         int                     vers_ops;
+        u32                     pflags;
         u32                     flags;
         u32                     listnr;
         u32                     action;
@@ -64,6 +65,9 @@ struct audit_krule {
         u64                     prio;
 };
 
+/* Flag to indicate legacy AUDIT_LOGINUID unset usage */
+#define AUDIT_LOGINUID_LEGACY           0x1
+
 struct audit_field {
         u32                             type;
         union {
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 2839c639f092..d936409520f8 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -176,7 +176,7 @@ struct clk_ops {
                                         unsigned long *parent_rate);
         long            (*determine_rate)(struct clk_hw *hw, unsigned long rate,
                                         unsigned long *best_parent_rate,
-                                        struct clk **best_parent_clk);
+                                        struct clk_hw **best_parent_hw);
         int             (*set_parent)(struct clk_hw *hw, u8 index);
         u8              (*get_parent)(struct clk_hw *hw);
         int             (*set_rate)(struct clk_hw *hw, unsigned long rate,
@@ -544,16 +544,14 @@ u8 __clk_get_num_parents(struct clk *clk);
 struct clk *__clk_get_parent(struct clk *clk);
 struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
 unsigned int __clk_get_enable_count(struct clk *clk);
-unsigned int __clk_get_prepare_count(struct clk *clk);
 unsigned long __clk_get_rate(struct clk *clk);
-unsigned long __clk_get_accuracy(struct clk *clk);
 unsigned long __clk_get_flags(struct clk *clk);
 bool __clk_is_prepared(struct clk *clk);
 bool __clk_is_enabled(struct clk *clk);
 struct clk *__clk_lookup(const char *name);
 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
                               unsigned long *best_parent_rate,
-                              struct clk **best_parent_p);
+                              struct clk_hw **best_parent_p);
 
 /*
  * FIXME clock api without lock protection
@@ -652,7 +650,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
 #endif  /* platform dependent I/O accessors */
 
 #ifdef CONFIG_DEBUG_FS
-struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode,
+struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
                                 void *data, const struct file_operations *fops);
 #endif
 
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 74e5341463c9..55ef529a0dbf 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -264,7 +264,7 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
                                        unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk);
+                                       struct clk_hw **best_parent_clk);
 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
                                          unsigned long parent_rate);
 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
@@ -273,7 +273,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
                                         unsigned long rate,
                                         unsigned long *best_parent_rate,
-                                        struct clk **best_parent_clk);
+                                        struct clk_hw **best_parent_clk);
 u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index d5ad7b1118fc..a1c81f80978e 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -186,6 +186,80 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
 # define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __LINE__)
 #endif
 
+#include <uapi/linux/types.h>
+
+static __always_inline void data_access_exceeds_word_size(void)
+#ifdef __compiletime_warning
+__compiletime_warning("data access exceeds word size and won't be atomic")
+#endif
+;
+
+static __always_inline void data_access_exceeds_word_size(void)
+{
+}
+
+static __always_inline void __read_once_size(volatile void *p, void *res, int size)
+{
+        switch (size) {
+        case 1: *(__u8 *)res = *(volatile __u8 *)p; break;
+        case 2: *(__u16 *)res = *(volatile __u16 *)p; break;
+        case 4: *(__u32 *)res = *(volatile __u32 *)p; break;
+#ifdef CONFIG_64BIT
+        case 8: *(__u64 *)res = *(volatile __u64 *)p; break;
+#endif
+        default:
+                barrier();
+                __builtin_memcpy((void *)res, (const void *)p, size);
+                data_access_exceeds_word_size();
+                barrier();
+        }
+}
+
+static __always_inline void __assign_once_size(volatile void *p, void *res, int size)
+{
+        switch (size) {
+        case 1: *(volatile __u8 *)p = *(__u8 *)res; break;
+        case 2: *(volatile __u16 *)p = *(__u16 *)res; break;
+        case 4: *(volatile __u32 *)p = *(__u32 *)res; break;
+#ifdef CONFIG_64BIT
+        case 8: *(volatile __u64 *)p = *(__u64 *)res; break;
+#endif
+        default:
+                barrier();
+                __builtin_memcpy((void *)p, (const void *)res, size);
+                data_access_exceeds_word_size();
+                barrier();
+        }
+}
+
+/*
+ * Prevent the compiler from merging or refetching reads or writes. The
+ * compiler is also forbidden from reordering successive instances of
+ * READ_ONCE, ASSIGN_ONCE and ACCESS_ONCE (see below), but only when the
+ * compiler is aware of some particular ordering.  One way to make the
+ * compiler aware of ordering is to put the two invocations of READ_ONCE,
+ * ASSIGN_ONCE or ACCESS_ONCE() in different C statements.
+ *
+ * In contrast to ACCESS_ONCE these two macros will also work on aggregate
+ * data types like structs or unions. If the size of the accessed data
+ * type exceeds the word size of the machine (e.g., 32 bits or 64 bits)
+ * READ_ONCE() and ASSIGN_ONCE()  will fall back to memcpy and print a
+ * compile-time warning.
+ *
+ * Their two major use cases are: (1) Mediating communication between
+ * process-level code and irq/NMI handlers, all running on the same CPU,
+ * and (2) Ensuring that the compiler does not  fold, spindle, or otherwise
+ * mutilate accesses that either do not require ordering or that interact
+ * with an explicit memory barrier or atomic instruction that provides the
+ * required ordering.
+ */
+
+#define READ_ONCE(x) \
+        ({ typeof(x) __val; __read_once_size(&x, &__val, sizeof(__val)); __val; })
+
+#define ASSIGN_ONCE(val, x) \
+        ({ typeof(x) __val; __val = val; __assign_once_size(&x, &__val, sizeof(__val)); __val; })
+
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index f1863dcd83ea..ce447f0f1bad 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -188,7 +188,7 @@ extern struct devfreq *devm_devfreq_add_device(struct device *dev,
 extern void devm_devfreq_remove_device(struct device *dev,
                                   struct devfreq *devfreq);
 
-/* Supposed to be called by PM_SLEEP/PM_RUNTIME callbacks */
+/* Supposed to be called by PM callbacks */
 extern int devfreq_suspend_device(struct devfreq *devfreq);
 extern int devfreq_resume_device(struct devfreq *devfreq);
 
diff --git a/include/scsi/libsas.h b/include/scsi/libsas.h
index 9d87a37aecad..dae99d7d2bc0 100644
--- a/include/scsi/libsas.h
+++ b/include/scsi/libsas.h
@@ -688,7 +688,6 @@ extern int sas_queuecommand(struct Scsi_Host * ,struct scsi_cmnd *);
 extern int sas_target_alloc(struct scsi_target *);
 extern int sas_slave_configure(struct scsi_device *);
 extern int sas_change_queue_depth(struct scsi_device *, int new_depth);
-extern int sas_change_queue_type(struct scsi_device *, int qt);
 extern int sas_bios_param(struct scsi_device *,
                           struct block_device *,
                           sector_t capacity, int *hsc);
diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h
index e939d2b3757a..019e66858ce6 100644
--- a/include/scsi/scsi_host.h
+++ b/include/scsi/scsi_host.h
@@ -278,19 +278,6 @@ struct scsi_host_template {
         int (* change_queue_depth)(struct scsi_device *, int);
 
         /*
-         * Fill in this function to allow the changing of tag types
-         * (this also allows the enabling/disabling of tag command
-         * queueing).  An error should only be returned if something
-         * went wrong in the driver while trying to set the tag type.
-         * If the driver doesn't support the requested tag type, then
-         * it should set the closest type it does support without
-         * returning an error.  Returns the actual tag type set.
-         *
-         * Status: OPTIONAL
-         */
-        int (* change_queue_type)(struct scsi_device *, int);
-
-        /*
          * This function determines the BIOS parameters for a given
          * harddisk.  These tend to be numbers that are made up by
          * the host adapter.  Parameters:
diff --git a/include/scsi/scsi_tcq.h b/include/scsi/scsi_tcq.h
index fe4a70299419..9708b28bd2aa 100644
--- a/include/scsi/scsi_tcq.h
+++ b/include/scsi/scsi_tcq.h
@@ -6,46 +6,10 @@
 #include <scsi/scsi_device.h>
 #include <scsi/scsi_host.h>
 
-#define MSG_SIMPLE_TAG  0x20
-#define MSG_HEAD_TAG    0x21
-#define MSG_ORDERED_TAG 0x22
-#define MSG_ACA_TAG     0x24    /* unsupported */
-
 #define SCSI_NO_TAG     (-1)    /* identify no tag in use */
 
 
 #ifdef CONFIG_BLOCK
-
-int scsi_change_queue_type(struct scsi_device *sdev, int tag_type);
-
-/**
- * scsi_get_tag_type - get the type of tag the device supports
- * @sdev:       the scsi device
- */
-static inline int scsi_get_tag_type(struct scsi_device *sdev)
-{
-        if (!sdev->tagged_supported)
-                return 0;
-        if (sdev->simple_tags)
-                return MSG_SIMPLE_TAG;
-        return 0;
-}
-
-static inline void scsi_set_tag_type(struct scsi_device *sdev, int tag)
-{
-        switch (tag) {
-        case MSG_ORDERED_TAG:
-        case MSG_SIMPLE_TAG:
-                sdev->simple_tags = 1;
-                break;
-        case 0:
-                /* fall through */
-        default:
-                sdev->simple_tags = 0;
-                break;
-        }
-}
-
 static inline struct scsi_cmnd *scsi_mq_find_tag(struct Scsi_Host *shost,
                                                  int unique_tag)
 {
diff --git a/include/target/target_core_base.h b/include/target/target_core_base.h
index 23c518a0340c..397fb635766a 100644
--- a/include/target/target_core_base.h
+++ b/include/target/target_core_base.h
@@ -476,6 +476,12 @@ struct se_dif_v1_tuple {
         __be32                  ref_tag;
 };
 
+/* for sam_task_attr */
+#define TCM_SIMPLE_TAG  0x20
+#define TCM_HEAD_TAG    0x21
+#define TCM_ORDERED_TAG 0x22
+#define TCM_ACA_TAG     0x24
+
 struct se_cmd {
         /* SAM response code being sent to initiator */
         u8                      scsi_status;
diff --git a/include/trace/events/target.h b/include/trace/events/target.h
index 45403443dd82..04c3c6efdcc2 100644
--- a/include/trace/events/target.h
+++ b/include/trace/events/target.h
@@ -109,10 +109,10 @@
 
 #define show_task_attribute_name(val)                           \
         __print_symbolic(val,                                   \
-                { MSG_SIMPLE_TAG,       "SIMPLE"        },      \
-                { MSG_HEAD_TAG,         "HEAD"          },      \
-                { MSG_ORDERED_TAG,      "ORDERED"       },      \
-                { MSG_ACA_TAG,          "ACA"           } )
+                { TCM_SIMPLE_TAG,       "SIMPLE"        },      \
+                { TCM_HEAD_TAG,         "HEAD"          },      \
+                { TCM_ORDERED_TAG,      "ORDERED"       },      \
+                { TCM_ACA_TAG,          "ACA"           } )
 
 #define show_scsi_status_name(val)                              \
         __print_symbolic(val,                                   \
diff --git a/kernel/audit.c b/kernel/audit.c
index f8f203e8018c..231b7dcb154b 100644
--- a/kernel/audit.c
+++ b/kernel/audit.c
@@ -429,7 +429,7 @@ static void kauditd_send_skb(struct sk_buff *skb)
  * This function doesn't consume an skb as might be expected since it has to
  * copy it anyways.
  */
-static void kauditd_send_multicast_skb(struct sk_buff *skb)
+static void kauditd_send_multicast_skb(struct sk_buff *skb, gfp_t gfp_mask)
 {
         struct sk_buff          *copy;
         struct audit_net        *aunet = net_generic(&init_net, audit_net_id);
@@ -448,11 +448,11 @@ static void kauditd_send_multicast_skb(struct sk_buff *skb)
          * no reason for new multicast clients to continue with this
          * non-compliance.
          */
-        copy = skb_copy(skb, GFP_KERNEL);
+        copy = skb_copy(skb, gfp_mask);
         if (!copy)
                 return;
 
-        nlmsg_multicast(sock, copy, 0, AUDIT_NLGRP_READLOG, GFP_KERNEL);
+        nlmsg_multicast(sock, copy, 0, AUDIT_NLGRP_READLOG, gfp_mask);
 }
 
 /*
@@ -1940,7 +1940,7 @@ void audit_log_end(struct audit_buffer *ab)
                 struct nlmsghdr *nlh = nlmsg_hdr(ab->skb);
 
                 nlh->nlmsg_len = ab->skb->len;
-                kauditd_send_multicast_skb(ab->skb);
+                kauditd_send_multicast_skb(ab->skb, ab->gfp_mask);
 
                 /*
                  * The original kaudit unicast socket sends up messages with
diff --git a/kernel/auditfilter.c b/kernel/auditfilter.c
index 3598e13f2a65..4f68a326d92e 100644
--- a/kernel/auditfilter.c
+++ b/kernel/auditfilter.c
@@ -442,19 +442,7 @@ static struct audit_entry *audit_data_to_entry(struct audit_rule_data *data,
                 if ((f->type == AUDIT_LOGINUID) && (f->val == AUDIT_UID_UNSET)) {
                         f->type = AUDIT_LOGINUID_SET;
                         f->val = 0;
-                }
-
-                if ((f->type == AUDIT_PID) || (f->type == AUDIT_PPID)) {
-                        struct pid *pid;
-                        rcu_read_lock();
-                        pid = find_vpid(f->val);
-                        if (!pid) {
-                                rcu_read_unlock();
-                                err = -ESRCH;
-                                goto exit_free;
-                        }
-                        f->val = pid_nr(pid);
-                        rcu_read_unlock();
+                        entry->rule.pflags |= AUDIT_LOGINUID_LEGACY;
                 }
 
                 err = audit_field_valid(entry, f);
@@ -630,6 +618,13 @@ static struct audit_rule_data *audit_krule_to_data(struct audit_krule *krule)
                         data->buflen += data->values[i] =
                                 audit_pack_string(&bufp, krule->filterkey);
                         break;
+                case AUDIT_LOGINUID_SET:
+                        if (krule->pflags & AUDIT_LOGINUID_LEGACY && !f->val) {
+                                data->fields[i] = AUDIT_LOGINUID;
+                                data->values[i] = AUDIT_UID_UNSET;
+                                break;
+                        }
+                        /* fallthrough if set */
                 default:
                         data->values[i] = f->val;
                 }
@@ -646,6 +641,7 @@ static int audit_compare_rule(struct audit_krule *a, struct audit_krule *b)
         int i;
 
         if (a->flags != b->flags ||
+            a->pflags != b->pflags ||
             a->listnr != b->listnr ||
             a->action != b->action ||
             a->field_count != b->field_count)
@@ -764,6 +760,7 @@ struct audit_entry *audit_dupe_rule(struct audit_krule *old)
         new = &entry->rule;
         new->vers_ops = old->vers_ops;
         new->flags = old->flags;
+        new->pflags = old->pflags;
         new->listnr = old->listnr;
         new->action = old->action;
         for (i = 0; i < AUDIT_BITMASK_SIZE; i++)
diff --git a/kernel/auditsc.c b/kernel/auditsc.c
index c75522a83678..37c69ab561da 100644
--- a/kernel/auditsc.c
+++ b/kernel/auditsc.c
@@ -1877,12 +1877,18 @@ void __audit_inode(struct filename *name, const struct dentry *dentry,
         }
 
 out_alloc:
-        /* unable to find the name from a previous getname(). Allocate a new
-         * anonymous entry.
-         */
-        n = audit_alloc_name(context, AUDIT_TYPE_NORMAL);
+        /* unable to find an entry with both a matching name and type */
+        n = audit_alloc_name(context, AUDIT_TYPE_UNKNOWN);
         if (!n)
                 return;
+        if (name)
+                /* since name is not NULL we know there is already a matching
+                 * name record, see audit_getname(), so there must be a type
+                 * mismatch; reuse the string path since the original name
+                 * record will keep the string valid until we free it in
+                 * audit_free_names() */
+                n->name = name;
+
 out:
         if (parent) {
                 n->name_len = n->name ? parent_len(n->name->name) : AUDIT_NAME_FULL;
diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig
index 6e7708c2c21f..48b28d387c7f 100644
--- a/kernel/power/Kconfig
+++ b/kernel/power/Kconfig
@@ -94,7 +94,7 @@ config PM_STD_PARTITION
 config PM_SLEEP
         def_bool y
         depends on SUSPEND || HIBERNATE_CALLBACKS
-        select PM_RUNTIME
+        select PM
 
 config PM_SLEEP_SMP
         def_bool y
@@ -130,23 +130,19 @@ config PM_WAKELOCKS_GC
         depends on PM_WAKELOCKS
         default y
 
-config PM_RUNTIME
-        bool "Run-time PM core functionality"
+config PM
+        bool "Device power management core functionality"
         ---help---
           Enable functionality allowing I/O devices to be put into energy-saving
-          (low power) states at run time (or autosuspended) after a specified
-          period of inactivity and woken up in response to a hardware-generated
+          (low power) states, for example after a specified period of inactivity
+          (autosuspended), and woken up in response to a hardware-generated
           wake-up event or a driver's request.
 
           Hardware support is generally required for this functionality to work
           and the bus type drivers of the buses the devices are on are
-          responsible for the actual handling of the autosuspend requests and
+          responsible for the actual handling of device suspend requests and
           wake-up events.
 
-config PM
-        def_bool y
-        depends on PM_SLEEP || PM_RUNTIME
-
 config PM_DEBUG
         bool "Power Management Debug Support"
         depends on PM
diff --git a/mm/gup.c b/mm/gup.c
index 0ca1df9075ab..a900759cc807 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -968,7 +968,7 @@ static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
 
         pudp = pud_offset(&pgd, addr);
         do {
-                pud_t pud = ACCESS_ONCE(*pudp);
+                pud_t pud = READ_ONCE(*pudp);
 
                 next = pud_addr_end(addr, end);
                 if (pud_none(pud))
diff --git a/mm/memory.c b/mm/memory.c
index d8aebc52265f..ca920d1fd314 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -2378,12 +2378,12 @@ void unmap_mapping_range(struct address_space *mapping,
                 details.last_index = ULONG_MAX;
 
 
-        i_mmap_lock_read(mapping);
+        i_mmap_lock_write(mapping);
         if (unlikely(!RB_EMPTY_ROOT(&mapping->i_mmap)))
                 unmap_mapping_range_tree(&mapping->i_mmap, &details);
         if (unlikely(!list_empty(&mapping->i_mmap_nonlinear)))
                 unmap_mapping_range_list(&mapping->i_mmap_nonlinear, &details);
-        i_mmap_unlock_read(mapping);
+        i_mmap_unlock_write(mapping);
 }
 EXPORT_SYMBOL(unmap_mapping_range);
 
@@ -3195,7 +3195,16 @@ static int handle_pte_fault(struct mm_struct *mm,
         pte_t entry;
         spinlock_t *ptl;
 
-        entry = ACCESS_ONCE(*pte);
+        /*
+         * some architectures can have larger ptes than wordsize,
+         * e.g.ppc44x-defconfig has CONFIG_PTE_64BIT=y and CONFIG_32BIT=y,
+         * so READ_ONCE or ACCESS_ONCE cannot guarantee atomic accesses.
+         * The code below just needs a consistent view for the ifs and
+         * we later double check anyway with the ptl lock held. So here
+         * a barrier will do.
+         */
+        entry = *pte;
+        barrier();
         if (!pte_present(entry)) {
                 if (pte_none(entry)) {
                         if (vma->vm_ops) {
diff --git a/mm/rmap.c b/mm/rmap.c
index 45ba250babd8..c5bc241127b2 100644
--- a/mm/rmap.c
+++ b/mm/rmap.c
@@ -583,7 +583,8 @@ pmd_t *mm_find_pmd(struct mm_struct *mm, unsigned long address)
          * without holding anon_vma lock for write.  So when looking for a
          * genuine pmde (in which to find pte), test present and !THP together.
          */
-        pmde = ACCESS_ONCE(*pmd);
+        pmde = *pmd;
+        barrier();
         if (!pmd_present(pmde) || pmd_trans_huge(pmde))
                 pmd = NULL;
 out:
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 5374b1bdf02f..edd2794569db 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -185,6 +185,18 @@ modbuiltin := -f $(srctree)/scripts/Makefile.modbuiltin obj
 # $(Q)$(MAKE) $(dtbinst)=dir
 dtbinst := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.dtbinst obj
 
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=
+# Usage:
+# $(Q)$(MAKE) $(clean)=dir
+clean := -f $(srctree)/scripts/Makefile.clean obj
+
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.headersinst obj=
+# Usage:
+# $(Q)$(MAKE) $(hdr-inst)=dir
+hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
+
 # Prefix -I with $(srctree) if it is not an absolute path.
 # skip if -I has no parameter
 addtree = $(if $(patsubst -I%,%,$(1)), \
diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean
index b1c668dc6815..1bca180db8ad 100644
--- a/scripts/Makefile.clean
+++ b/scripts/Makefile.clean
@@ -7,10 +7,7 @@ src := $(obj)
 PHONY := __clean
 __clean:
 
-# Shorthand for $(Q)$(MAKE) scripts/Makefile.clean obj=dir
-# Usage:
-# $(Q)$(MAKE) $(clean)=dir
-clean := -f $(srctree)/scripts/Makefile.clean obj
+include scripts/Kbuild.include
 
 # The filename Kbuild has precedence over Makefile
 kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
@@ -91,11 +88,6 @@ PHONY += $(subdir-ymn)
 $(subdir-ymn):
         $(Q)$(MAKE) $(clean)=$@
 
-# If quiet is set, only print short version of command
-
-cmd = @$(if $($(quiet)cmd_$(1)),echo '  $($(quiet)cmd_$(1))' &&) $(cmd_$(1))
-
-
 # Declare the contents of the .PHONY variable as phony.  We keep that
 # information in a variable se we can use it in if_changed and friends.
 
diff --git a/scripts/Makefile.headersinst b/scripts/Makefile.headersinst
index 8ccf83056a7a..1106d6ca3a38 100644
--- a/scripts/Makefile.headersinst
+++ b/scripts/Makefile.headersinst
@@ -122,7 +122,6 @@ $(check-file): scripts/headers_check.pl $(output-files) FORCE
 endif
 
 # Recursion
-hdr-inst := -rR -f $(srctree)/scripts/Makefile.headersinst obj
 .PHONY: $(subdirs)
 $(subdirs):
         $(Q)$(MAKE) $(hdr-inst)=$(obj)/$@ dst=$(_dst)/$@
diff --git a/scripts/coccinelle/misc/bugon.cocci b/scripts/coccinelle/misc/bugon.cocci
index 556456ca761c..3b7eec24fb5a 100644
--- a/scripts/coccinelle/misc/bugon.cocci
+++ b/scripts/coccinelle/misc/bugon.cocci
@@ -8,7 +8,7 @@
 // Confidence: High
 // Copyright: (C) 2014 Himangi Saraogi.  GPLv2.
 // Comments:
-// Options: --no-includes, --include-headers
+// Options: --no-includes --include-headers
 
 virtual patch
 virtual context
diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c
index a26cc5d2a9b0..72c9dba84c5d 100644
--- a/scripts/kconfig/menu.c
+++ b/scripts/kconfig/menu.c
@@ -548,7 +548,7 @@ static void get_prompt_str(struct gstr *r, struct property *prop,
 {
         int i, j;
         struct menu *submenu[8], *menu, *location = NULL;
-        struct jump_key *jump;
+        struct jump_key *jump = NULL;
 
         str_printf(r, _("Prompt: %s\n"), _(prop->text));
         menu = prop->menu->parent;
@@ -586,7 +586,7 @@ static void get_prompt_str(struct gstr *r, struct property *prop,
                 str_printf(r, _("  Location:\n"));
                 for (j = 4; --i >= 0; j += 2) {
                         menu = submenu[i];
-                        if (head && location && menu == location)
+                        if (jump && menu == location)
                                 jump->offset = strlen(r->s);
                         str_printf(r, "%*c-> %s", j, ' ',
                                    _(menu_get_prompt(menu)));
diff --git a/scripts/package/mkspec b/scripts/package/mkspec
index 13957602f7ca..d9ab94b17de0 100755
--- a/scripts/package/mkspec
+++ b/scripts/package/mkspec
@@ -117,6 +117,7 @@ echo 'mv vmlinux.bz2 $RPM_BUILD_ROOT'"/boot/vmlinux-$KERNELRELEASE.bz2"
 echo 'mv vmlinux.orig vmlinux'
 echo "%endif"
 
+if ! $PREBUILT; then
 echo 'rm -f $RPM_BUILD_ROOT'"/lib/modules/$KERNELRELEASE/{build,source}"
 echo "mkdir -p "'$RPM_BUILD_ROOT'"/usr/src/kernels/$KERNELRELEASE"
 echo "EXCLUDES=\"$RCS_TAR_IGNORE --exclude .tmp_versions --exclude=*vmlinux* --exclude=*.o --exclude=*.ko --exclude=*.cmd --exclude=Documentation --exclude=firmware --exclude .config.old --exclude .missing-syscalls.d\""
@@ -124,6 +125,7 @@ echo "tar "'$EXCLUDES'" -cf- . | (cd "'$RPM_BUILD_ROOT'"/usr/src/kernels/$KERNEL
 echo 'cd $RPM_BUILD_ROOT'"/lib/modules/$KERNELRELEASE"
 echo "ln -sf /usr/src/kernels/$KERNELRELEASE build"
 echo "ln -sf /usr/src/kernels/$KERNELRELEASE source"
+fi
 
 echo ""
 echo "%clean"
@@ -151,9 +153,11 @@ echo "%files headers"
 echo '%defattr (-, root, root)'
 echo "/usr/include"
 echo ""
+if ! $PREBUILT; then
 echo "%files devel"
 echo '%defattr (-, root, root)'
 echo "/usr/src/kernels/$KERNELRELEASE"
 echo "/lib/modules/$KERNELRELEASE/build"
 echo "/lib/modules/$KERNELRELEASE/source"
 echo ""
+fi
diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c
index 8276a743e22e..0cfc9c8c4b4e 100644
--- a/sound/pci/hda/hda_controller.c
+++ b/sound/pci/hda/hda_controller.c
@@ -1922,10 +1922,18 @@ int azx_mixer_create(struct azx *chip)
 EXPORT_SYMBOL_GPL(azx_mixer_create);
 
 
+static bool is_input_stream(struct azx *chip, unsigned char index)
+{
+        return (index >= chip->capture_index_offset &&
+                index < chip->capture_index_offset + chip->capture_streams);
+}
+
 /* initialize SD streams */
 int azx_init_stream(struct azx *chip)
 {
         int i;
+        int in_stream_tag = 0;
+        int out_stream_tag = 0;
 
         /* initialize each stream (aka device)
          * assign the starting bdl address to each stream (device)
@@ -1938,9 +1946,21 @@ int azx_init_stream(struct azx *chip)
                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
                 azx_dev->sd_int_sta_mask = 1 << i;
-                /* stream tag: must be non-zero and unique */
                 azx_dev->index = i;
-                azx_dev->stream_tag = i + 1;
+
+                /* stream tag must be unique throughout
+                 * the stream direction group,
+                 * valid values 1...15
+                 * use separate stream tag if the flag
+                 * AZX_DCAPS_SEPARATE_STREAM_TAG is used
+                 */
+                if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
+                        azx_dev->stream_tag =
+                                is_input_stream(chip, i) ?
+                                ++in_stream_tag :
+                                ++out_stream_tag;
+                else
+                        azx_dev->stream_tag = i + 1;
         }
 
         return 0;
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 2bf0b568e3de..d426a0bd6a5f 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -299,6 +299,9 @@ enum {
          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
          AZX_DCAPS_SNOOP_TYPE(SCH))
 
+#define AZX_DCAPS_INTEL_SKYLAKE \
+        (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG)
+
 /* quirks for ATI SB / AMD Hudson */
 #define AZX_DCAPS_PRESET_ATI_SB \
         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
@@ -2027,7 +2030,7 @@ static const struct pci_device_id azx_ids[] = {
           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
         /* Sunrise Point-LP */
         { PCI_DEVICE(0x8086, 0x9d70),
-          .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
+          .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
         /* Haswell */
         { PCI_DEVICE(0x8086, 0x0a0c),
           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
diff --git a/sound/pci/hda/hda_priv.h b/sound/pci/hda/hda_priv.h
index aa484fdf4338..166e3e84b963 100644
--- a/sound/pci/hda/hda_priv.h
+++ b/sound/pci/hda/hda_priv.h
@@ -171,6 +171,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 #define AZX_DCAPS_I915_POWERWELL (1 << 27)      /* HSW i915 powerwell support */
 #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28)   /* CORBRP clears itself after reset */
 #define AZX_DCAPS_NO_MSI64      (1 << 29)       /* Stick to 32-bit MSIs */
+#define AZX_DCAPS_SEPARATE_STREAM_TAG   (1 << 30) /* capture and playback use separate stream tag */
 
 enum {
         AZX_SNOOP_TYPE_NONE ,
diff --git a/sound/soc/intel/sst-haswell-pcm.c b/sound/soc/intel/sst-haswell-pcm.c
index b8a782c0d4cd..619525200705 100644
--- a/sound/soc/intel/sst-haswell-pcm.c
+++ b/sound/soc/intel/sst-haswell-pcm.c
@@ -998,7 +998,7 @@ static int hsw_pcm_dev_remove(struct platform_device *pdev)
         return 0;
 }
 
-#ifdef CONFIG_PM_RUNTIME
+#ifdef CONFIG_PM
 
 static int hsw_pcm_runtime_idle(struct device *dev)
 {
@@ -1057,7 +1057,7 @@ static int hsw_pcm_runtime_resume(struct device *dev)
 #define hsw_pcm_runtime_resume          NULL
 #endif
 
-#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_PM_RUNTIME)
+#ifdef CONFIG_PM
 
 static void hsw_pcm_complete(struct device *dev)
 {
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index f5283438ee05..1cc6e2e19982 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -671,6 +671,7 @@ static void update_memslots(struct kvm_memslots *slots,
 
         WARN_ON(mslots[i].id != id);
         if (!new->npages) {
+                WARN_ON(!mslots[i].npages);
                 new->base_gfn = 0;
                 if (mslots[i].npages)
                         slots->used_slots--;
@@ -687,12 +688,25 @@ static void update_memslots(struct kvm_memslots *slots,
                 slots->id_to_index[mslots[i].id] = i;
                 i++;
         }
-        while (i > 0 &&
-               new->base_gfn > mslots[i - 1].base_gfn) {
-                mslots[i] = mslots[i - 1];
-                slots->id_to_index[mslots[i].id] = i;
-                i--;
-        }
+
+        /*
+         * The ">=" is needed when creating a slot with base_gfn == 0,
+         * so that it moves before all those with base_gfn == npages == 0.
+         *
+         * On the other hand, if new->npages is zero, the above loop has
+         * already left i pointing to the beginning of the empty part of
+         * mslots, and the ">=" would move the hole backwards in this
+         * case---which is wrong.  So skip the loop when deleting a slot.
+         */
+        if (new->npages) {
+                while (i > 0 &&
+                       new->base_gfn >= mslots[i - 1].base_gfn) {
+                        mslots[i] = mslots[i - 1];
+                        slots->id_to_index[mslots[i].id] = i;
+                        i--;
+                }
+        } else
+                WARN_ON_ONCE(i != slots->used_slots);
 
         mslots[i] = *new;
         slots->id_to_index[mslots[i].id] = i;