Merge tag 'mips_fixes_5.0_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS fixes from Paul Burton:

 - Fix IPI handling for Lantiq SoCs, which was broken by changes made
   back in v4.12.

 - Enable OF/DT serial support in ath79_defconfig to give us working
   serial by default.

 - Fix 64b builds for the Jazz platform.

 - Set up a struct device for the BCM47xx SoC to allow BCM47xx drivers
   to perform DMA again following the major DMA mapping changes made in
   v4.19.

 - Disable MSI on Cavium Octeon systems when the pcie_disable command
   line parameter introduced in v3.3 is used, in order to avoid
   inadvetently accessing PCIe controller registers despite the command
   line.

 - Fix a build failure for Cavium Octeon kernels with kexec enabled,
   introduced in v4.20.

 - Fix a regression in the behaviour of semctl/shmctl/msgctl IPC
   syscalls for kernels including n32 support but not o32 support caused
   by some cleanup in v3.19.

* tag 'mips_fixes_5.0_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: OCTEON: fix kexec support
  mips: fix n32 compat_ipc_parse_version
  Disable MSI also when pcie-octeon.pcie_disable on
  MIPS: BCM47XX: Setup struct device for the SoC
  MIPS: jazz: fix 64bit build
  MIPS: ath79: Enable OF serial ports in the default config
  MIPS: lantiq: Use CP0_LEGACY_COMPARE_IRQ
  MIPS: lantiq: Fix IPI interrupt handling

10 files changed, 47 insertions, 79 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 787290781b8c..0d14f51d0002 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3155,6 +3155,7 @@ config MIPS32_O32
 config MIPS32_N32
         bool "Kernel support for n32 binaries"
         depends on 64BIT
+        select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
         select COMPAT
         select MIPS32_COMPAT
         select SYSVIPC_COMPAT if SYSVIPC
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 6054d49e608e..fe3773539eff 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -173,6 +173,31 @@ void __init plat_mem_setup(void)
         pm_power_off = bcm47xx_machine_halt;
 }
 
+#ifdef CONFIG_BCM47XX_BCMA
+static struct device * __init bcm47xx_setup_device(void)
+{
+        struct device *dev;
+        int err;
+
+        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+        if (!dev)
+                return NULL;
+
+        err = dev_set_name(dev, "bcm47xx_soc");
+        if (err) {
+                pr_err("Failed to set SoC device name: %d\n", err);
+                kfree(dev);
+                return NULL;
+        }
+
+        err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
+        if (err)
+                pr_err("Failed to set SoC DMA mask: %d\n", err);
+
+        return dev;
+}
+#endif
+
 /*
  * This finishes bus initialization doing things that were not possible without
  * kmalloc. Make sure to call it late enough (after mm_init).
@@ -183,6 +208,10 @@ void __init bcm47xx_bus_setup(void)
         if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {
                 int err;
 
+                bcm47xx_bus.bcma.dev = bcm47xx_setup_device();
+                if (!bcm47xx_bus.bcma.dev)
+                        panic("Failed to setup SoC device\n");
+
                 err = bcma_host_soc_init(&bcm47xx_bus.bcma);
                 if (err)
                         panic("Failed to initialize BCMA bus (err %d)", err);
@@ -235,6 +264,8 @@ static int __init bcm47xx_register_bus_complete(void)
 #endif
 #ifdef CONFIG_BCM47XX_BCMA
         case BCM47XX_BUS_TYPE_BCMA:
+                if (device_register(bcm47xx_bus.bcma.dev))
+                        pr_err("Failed to register SoC device\n");
                 bcma_bus_register(&bcm47xx_bus.bcma.bus);
                 break;
 #endif
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 2c79ab52977a..8bf43c5a7bc7 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -98,7 +98,7 @@ static void octeon_kexec_smp_down(void *ignored)
         "       sync                                            \n"
         "       synci   ($0)                                    \n");
 
-        relocated_kexec_smp_wait(NULL);
+        kexec_reboot();
 }
 #endif
 
diff --git a/arch/mips/configs/ath79_defconfig b/arch/mips/configs/ath79_defconfig
index 4e4ec779f182..6f981af67826 100644
--- a/arch/mips/configs/ath79_defconfig
+++ b/arch/mips/configs/ath79_defconfig
@@ -66,6 +66,7 @@ CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_SERIAL_8250_PCI is not set
 CONFIG_SERIAL_8250_NR_UARTS=1
 CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_AR933X=y
 CONFIG_SERIAL_AR933X_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
index c6b63a409641..6dd8ad2409dc 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
@@ -18,8 +18,6 @@
 #define INT_NUM_EXTRA_START             (INT_NUM_IM4_IRL0 + 32)
 #define INT_NUM_IM_OFFSET               (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
 
-#define MIPS_CPU_TIMER_IRQ                      7
-
 #define MAX_IM                  5
 
 #endif /* _FALCON_IRQ__ */
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
index 141076325307..0b424214a5e9 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -19,8 +19,6 @@
 
 #define LTQ_DMA_CH0_INT         (INT_NUM_IM2_IRL0)
 
-#define MIPS_CPU_TIMER_IRQ      7
-
 #define MAX_IM                  5
 
 #endif
diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c
index 6256d35dbf4d..bedb5047aff3 100644
--- a/arch/mips/jazz/jazzdma.c
+++ b/arch/mips/jazz/jazzdma.c
@@ -74,14 +74,15 @@ static int __init vdma_init(void)
                                                     get_order(VDMA_PGTBL_SIZE));
         BUG_ON(!pgtbl);
         dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
-        pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);
+        pgtbl = (VDMA_PGTBL_ENTRY *)CKSEG1ADDR((unsigned long)pgtbl);
 
         /*
          * Clear the R4030 translation table
          */
         vdma_pgtbl_init();
 
-        r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, CPHYSADDR(pgtbl));
+        r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE,
+                          CPHYSADDR((unsigned long)pgtbl));
         r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE);
         r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
 
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index f0bc3312ed11..6549499eb202 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -224,9 +224,11 @@ static struct irq_chip ltq_eiu_type = {
         .irq_set_type = ltq_eiu_settype,
 };
 
-static void ltq_hw_irqdispatch(int module)
+static void ltq_hw_irq_handler(struct irq_desc *desc)
 {
+        int module = irq_desc_get_irq(desc) - 2;
         u32 irq;
+        int hwirq;
 
         irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
         if (irq == 0)
@@ -237,7 +239,8 @@ static void ltq_hw_irqdispatch(int module)
          * other bits might be bogus
          */
         irq = __fls(irq);
-        do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
+        hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module);
+        generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq));
 
         /* if this is a EBU irq, we need to ack it or get a deadlock */
         if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
@@ -245,49 +248,6 @@ static void ltq_hw_irqdispatch(int module)
                         LTQ_EBU_PCC_ISTAT);
 }
 
-#define DEFINE_HWx_IRQDISPATCH(x)                                       \
-        static void ltq_hw ## x ## _irqdispatch(void)                   \
-        {                                                               \
-                ltq_hw_irqdispatch(x);                                  \
-        }
-DEFINE_HWx_IRQDISPATCH(0)
-DEFINE_HWx_IRQDISPATCH(1)
-DEFINE_HWx_IRQDISPATCH(2)
-DEFINE_HWx_IRQDISPATCH(3)
-DEFINE_HWx_IRQDISPATCH(4)
-
-#if MIPS_CPU_TIMER_IRQ == 7
-static void ltq_hw5_irqdispatch(void)
-{
-        do_IRQ(MIPS_CPU_TIMER_IRQ);
-}
-#else
-DEFINE_HWx_IRQDISPATCH(5)
-#endif
-
-static void ltq_hw_irq_handler(struct irq_desc *desc)
-{
-        ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
-        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
-        int irq;
-
-        if (!pending) {
-                spurious_interrupt();
-                return;
-        }
-
-        pending >>= CAUSEB_IP;
-        while (pending) {
-                irq = fls(pending) - 1;
-                do_IRQ(MIPS_CPU_IRQ_BASE + irq);
-                pending &= ~BIT(irq);
-        }
-}
-
 static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 {
         struct irq_chip *chip = &ltq_irq_type;
@@ -343,38 +303,13 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
         for (i = 0; i < MAX_IM; i++)
                 irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
 
-        if (cpu_has_vint) {
-                pr_info("Setting up vectored interrupts\n");
-                set_vi_handler(2, ltq_hw0_irqdispatch);
-                set_vi_handler(3, ltq_hw1_irqdispatch);
-                set_vi_handler(4, ltq_hw2_irqdispatch);
-                set_vi_handler(5, ltq_hw3_irqdispatch);
-                set_vi_handler(6, ltq_hw4_irqdispatch);
-                set_vi_handler(7, ltq_hw5_irqdispatch);
-        }
-
         ltq_domain = irq_domain_add_linear(node,
                 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
                 &irq_domain_ops, 0);
 
-#ifndef CONFIG_MIPS_MT_SMP
-        set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
-                IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
-#else
-        set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
-                IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
-#endif
-
         /* tell oprofile which irq to use */
         ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
 
-        /*
-         * if the timer irq is not one of the mips irqs we need to
-         * create a mapping
-         */
-        if (MIPS_CPU_TIMER_IRQ != 7)
-                irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
-
         /* the external interrupts are optional and xway only */
         eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
         if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
@@ -411,7 +346,7 @@ EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
 
 unsigned int get_c0_compare_int(void)
 {
-        return MIPS_CPU_TIMER_IRQ;
+        return CP0_LEGACY_COMPARE_IRQ;
 }
 
 static struct of_device_id __initdata of_irq_ids[] = {
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index 2a5bb849b10e..288b58b00dc8 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -369,7 +369,9 @@ int __init octeon_msi_initialize(void)
         int irq;
         struct irq_chip *msi;
 
-        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
+        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_INVALID) {
+                return 0;
+        } else if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
                 msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
                 msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
                 msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
diff --git a/include/linux/bcma/bcma_soc.h b/include/linux/bcma/bcma_soc.h
index 7cca5f859a90..f3c43519baa7 100644
--- a/include/linux/bcma/bcma_soc.h
+++ b/include/linux/bcma/bcma_soc.h
@@ -6,6 +6,7 @@
 
 struct bcma_soc {
         struct bcma_bus bus;
+        struct device *dev;
 };
 
 int __init bcma_host_soc_register(struct bcma_soc *soc);