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authorAlexander Sverdlin <alexander.sverdlin@gmail.com>2018-04-28 16:51:39 -0400
committerMark Brown <broonie@kernel.org>2018-05-01 16:55:35 -0400
commit5d302ed3cc80564fb835bed5fdba1e1250ecc9e5 (patch)
tree0510db13d0c5efae3a46bb638a39b0b257fcdc1c
parent2d534113be9a2aa532a1ae127a57e83558aed358 (diff)
ASoC: cirrus: i2s: Fix {TX|RX}LinCtrlData setup
According to "EP93xx User’s Guide", I2STXLinCtrlData and I2SRXLinCtrlData registers actually have different format. The only currently used bit (Left_Right_Justify) has different position. Fix this and simplify the whole setup taking into account the fact that both registers have zero default value. The practical effect of the above is repaired SND_SOC_DAIFMT_RIGHT_J support (currently unused). Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
-rw-r--r--sound/soc/cirrus/ep93xx-i2s.c18
1 files changed, 10 insertions, 8 deletions
diff --git a/sound/soc/cirrus/ep93xx-i2s.c b/sound/soc/cirrus/ep93xx-i2s.c
index 38c240c97041..0dc3852c4621 100644
--- a/sound/soc/cirrus/ep93xx-i2s.c
+++ b/sound/soc/cirrus/ep93xx-i2s.c
@@ -51,7 +51,9 @@
51#define EP93XX_I2S_WRDLEN_24 (1 << 0) 51#define EP93XX_I2S_WRDLEN_24 (1 << 0)
52#define EP93XX_I2S_WRDLEN_32 (2 << 0) 52#define EP93XX_I2S_WRDLEN_32 (2 << 0)
53 53
54#define EP93XX_I2S_LINCTRLDATA_R_JUST (1 << 2) /* Right justify */ 54#define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */
55
56#define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */
55 57
56#define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */ 58#define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
57#define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */ 59#define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
@@ -170,25 +172,25 @@ static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
170 unsigned int fmt) 172 unsigned int fmt)
171{ 173{
172 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai); 174 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
173 unsigned int clk_cfg, lin_ctrl; 175 unsigned int clk_cfg;
176 unsigned int txlin_ctrl = 0;
177 unsigned int rxlin_ctrl = 0;
174 178
175 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG); 179 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
176 lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
177 180
178 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 181 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
179 case SND_SOC_DAIFMT_I2S: 182 case SND_SOC_DAIFMT_I2S:
180 clk_cfg |= EP93XX_I2S_CLKCFG_REL; 183 clk_cfg |= EP93XX_I2S_CLKCFG_REL;
181 lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
182 break; 184 break;
183 185
184 case SND_SOC_DAIFMT_LEFT_J: 186 case SND_SOC_DAIFMT_LEFT_J:
185 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL; 187 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
186 lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
187 break; 188 break;
188 189
189 case SND_SOC_DAIFMT_RIGHT_J: 190 case SND_SOC_DAIFMT_RIGHT_J:
190 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL; 191 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
191 lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST; 192 rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST;
193 txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST;
192 break; 194 break;
193 195
194 default: 196 default:
@@ -237,8 +239,8 @@ static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
237 /* Write new register values */ 239 /* Write new register values */
238 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg); 240 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
239 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg); 241 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
240 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl); 242 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl);
241 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl); 243 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl);
242 return 0; 244 return 0;
243} 245}
244 246