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authorDaniel Schultz <d.schultz@phytec.de>2018-02-13 04:44:32 -0500
committerHeiko Stuebner <heiko@sntech.de>2018-02-15 04:13:09 -0500
commit5ce0bad4ccd04c8a989e94d3c89e4e796ac22e48 (patch)
tree0862d10fde72053127a72d9fcc4d22c304fcbb29
parent7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff)
ARM: dts: rockchip: Remove 1.8 GHz operation point from phycore som
Rockchip recommends to run the CPU cores only with operations points of 1.6 GHz or lower. Removed the cpu0 node with too high operation points and use the default values instead. Fixes: 903d31e34628 ("ARM: dts: rockchip: Add support for phyCORE-RK3288 SoM") Cc: stable@vger.kernel.org Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--arch/arm/boot/dts/rk3288-phycore-som.dtsi20
1 files changed, 0 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index 99cfae875e12..5eae4776ffde 100644
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -110,26 +110,6 @@
110 }; 110 };
111}; 111};
112 112
113&cpu0 {
114 cpu0-supply = <&vdd_cpu>;
115 operating-points = <
116 /* KHz uV */
117 1800000 1400000
118 1608000 1350000
119 1512000 1300000
120 1416000 1200000
121 1200000 1100000
122 1008000 1050000
123 816000 1000000
124 696000 950000
125 600000 900000
126 408000 900000
127 312000 900000
128 216000 900000
129 126000 900000
130 >;
131};
132
133&emmc { 113&emmc {
134 status = "okay"; 114 status = "okay";
135 bus-width = <8>; 115 bus-width = <8>;