Merge tag 'pinctrl-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "An almost purely driver related set of changes with no major changes
  to the framework, only one patch adding an unlocked version of the
  pinctrl_find_gpio_range_from_pin() library call.

  New drivers:
   - ST Microelectronics STM32 MCU support: this is a non-MMU low-end
     platform for IoT things (etc).
   - Microchip PIC32 MCU support: same story as for STM32.

  New subdrivers:
   - Allwinner SunXi H3 R_PIO controller support.
   - Qualcomm IPQ4019 support.
   - MediaTek MT2701 and MT7623.
   - Allwinner A64

  Non-critical fixes:
   - gpio_disable_free() for the Vybrid.
   - pinctrl single: use a separate lockdep class.

  Misc:
   - Substantial cleanups and rewrites for the Super-H PFC driver and
     subdrivers.
   - Various fixes and cleanups, especially Paul Gortmakers work to make
     nonmodular drivers nonmodular"

* tag 'pinctrl-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits)
  pinctrl: single: Use a separate lockdep class
  drivers: pinctrl: add driver for Allwinner A64 SoC
  pinctrl: Broadcom Northstar2 pinctrl device tree bindings
  pinctrl: amlogic: Make driver independent from two-domain configuration
  pinctrl: amlogic: Separate some pin functions for Meson8 / Meson8b
  pinctrl: at91: use __maybe_unused to hide pm functions
  pinctrl: sh-pfc: core: don't open code of_device_get_match_data()
  pinctrl: uniphier: rename CONFIG options and file names
  pinctrl: sunxi: make A80 explicitly non-modular
  pinctrl: stm32: make explicitly non-modular
  pinctrl: sh-pfc: make explicitly non-modular
  pinctrl: meson: make explicitly non-modular
  pinctrl: pinctrl-mt6397 driver explicitly non-modular
  pinctrl: sunxi: does not need module.h
  pinctrl: pxa2xx: export symbols
  pinctrl: sunxi: Change mux setting on PI irq pins
  pinctrl: sunxi: Remove non existing irq's
  pinctrl: imx: attach iomuxc device to gpr syscon
  pinctrl-bcm2835: Fix cut-and-paste error in "pull" parsing
  pinctrl: lpc1850-scu: document nxp,gpio-pin-interrupt
  ...

100 files changed, 17651 insertions, 3027 deletions

diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
new file mode 100644
index 000000000000..ef3752889496
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
@@ -0,0 +1,49 @@
+* Microchip PIC32 GPIO devices (PIO).
+
+Required properties:
+ - compatible: "microchip,pic32mzda-gpio"
+ - reg: Base address and length for the device.
+ - interrupts: The port interrupt shared by all pins.
+ - gpio-controller: Marks the port as GPIO controller.
+ - #gpio-cells: Two. The first cell is the pin number and
+   the second cell is used to specify the gpio polarity as defined in
+   defined in <dt-bindings/gpio/gpio.h>:
+      0 = GPIO_ACTIVE_HIGH
+      1 = GPIO_ACTIVE_LOW
+      2 = GPIO_OPEN_DRAIN
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - #interrupt-cells: Two. The first cell is the GPIO number and second cell
+   is used to specify the trigger type as defined in
+   <dt-bindings/interrupt-controller/irq.h>:
+      IRQ_TYPE_EDGE_RISING
+      IRQ_TYPE_EDGE_FALLING
+      IRQ_TYPE_EDGE_BOTH
+ - clocks: Clock specifier (see clock bindings for details).
+ - microchip,gpio-bank: Specifies which bank a controller owns.
+ - gpio-ranges: Interaction with the PINCTRL subsystem.
+
+Example:
+
+/* PORTA */
+gpio0: gpio0@1f860000 {
+        compatible = "microchip,pic32mzda-gpio";
+        reg = <0x1f860000 0x100>;
+        interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
+        #gpio-cells = <2>;
+        gpio-controller;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        clocks = <&PBCLK4>;
+        microchip,gpio-bank = <0>;
+        gpio-ranges = <&pic32_pinctrl 0 0 16>;
+};
+
+keys {
+        ...
+
+        button@sw1 {
+                label = "ESC";
+                linux,code = <1>;
+                gpios = <&gpio0 12 0>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27e1036..69617220c5d6 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -21,6 +21,8 @@ Required properties:
   "allwinner,sun9i-a80-r-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
+  "allwinner,sun8i-h3-r-pinctrl"
+  "allwinner,sun50i-a64-pinctrl"
 
 - reg: Should contain the register physical address and length for the
   pin controller.
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt
new file mode 100644
index 000000000000..e295dda4bbba
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt
@@ -0,0 +1,102 @@
+Broadcom Northstar2 IOMUX Controller
+
+The Northstar2 IOMUX controller supports group based mux configuration. There
+are some individual pins that support modifying the pinconf parameters.
+
+Required properties:
+
+- compatible:
+    Must be "brcm,ns2-pinmux"
+
+- reg:
+    Define the base and range of the I/O address space that contains the
+    Northstar2 IOMUX and pin configuration registers.
+
+Properties in sub nodes:
+
+- function:
+    The mux function to select
+
+- groups:
+    The list of groups to select with a given function
+
+- pins:
+    List of pin names to change configuration
+
+The generic properties bias-disable, bias-pull-down, bias-pull-up,
+drive-strength, slew-rate, input-enable, input-disable are supported
+for some individual pins listed at the end.
+
+For more details, refer to
+Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+For example:
+
+        pinctrl: pinctrl@6501d130 {
+                compatible = "brcm,ns2-pinmux";
+                reg = <0x6501d130 0x08>,
+                      <0x660a0028 0x04>,
+                      <0x660009b0 0x40>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&nand_sel &uart3_rx &sdio0_d4>;
+
+                /* Select nand function */
+                nand_sel: nand_sel {
+                        function = "nand";
+                        groups = "nand_grp";
+                };
+
+                /* Pull up the uart3 rx pin */
+                uart3_rx: uart3_rx {
+                        pins = "uart3_sin";
+                        bias-pull-up;
+                };
+
+                /* Set the drive strength of sdio d4 pin */
+                sdio0_d4: sdio0_d4 {
+                        pins = "sdio0_data4";
+                        drive-strength = <8>;
+                };
+        };
+
+List of supported functions and groups in Northstar2:
+
+"nand": "nand_grp"
+
+"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp",
+        "nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp",
+        "nor_addr_12_15_grp"
+
+"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp",
+        "gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp",
+        "gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp",
+        "gpio_28_29_grp", "gpio_30_31_grp"
+
+"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp",
+        "pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp"
+
+"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp"
+
+"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp",
+        "uart1_rts_cts_grp", "uart1_in_out_grp"
+
+"uart2": "uart2_rts_cts_grp"
+
+"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp"
+
+
+List of pins that support pinconf parameters:
+
+"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout",
+"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck",
+"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7",
+"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4",
+"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1",
+"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk",
+"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1",
+"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk",
+"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc",
+"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent",
+"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc",
+"usb2_overcurrent", "sata_led1", "sata_led0"
diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
new file mode 100644
index 000000000000..4b5efa51bec7
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
@@ -0,0 +1,60 @@
+* Microchip PIC32 Pin Controller
+
+Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
+../interrupt-controller/interrupts.txt for generic information regarding
+pin controller, GPIO, and interrupt bindings.
+
+PIC32 'pin configuration node' is a node of a group of pins which can be
+used for a specific device or function. This node represents configuraions of
+pins, optional function, and optional mux related configuration.
+
+Required properties for pin controller node:
+ - compatible: "microchip,pic32mada-pinctrl"
+ - reg: Address range of the pinctrl registers.
+ - clocks: Clock specifier (see clock bindings for details)
+
+Required properties for pin configuration sub-nodes:
+ - pins: List of pins to which the configuration applies.
+
+Optional properties for pin configuration sub-nodes:
+----------------------------------------------------
+ - function: Mux function for the specified pins.
+ - bias-pull-up: Enable weak pull-up.
+ - bias-pull-down: Enable weak pull-down.
+ - input-enable: Set the pin as an input.
+ - output-low: Set the pin as an output level low.
+ - output-high: Set the pin as an output level high.
+ - microchip,digital: Enable digital I/O.
+ - microchip,analog: Enable analog I/O.
+
+Example:
+
+pic32_pinctrl: pinctrl@1f801400{
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "microchip,pic32mzda-pinctrl";
+        reg = <0x1f801400 0x400>;
+        clocks = <&PBCLK1>;
+
+        pinctrl_uart2: pinctrl_uart2 {
+                uart2-tx {
+                        pins = "G9";
+                        function = "U2TX";
+                        microchip,digital;
+                        output-low;
+                };
+                uart2-rx {
+                        pins = "B0";
+                        function = "U2RX";
+                        microchip,digital;
+                        input-enable;
+                };
+        };
+};
+
+uart2: serial@1f822200 {
+        compatible = "microchip,pic32mzda-uart";
+        reg = <0x1f822200 0x50>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt
index df0309c57505..bd8b0c69fa44 100644
--- a/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt
+++ b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt
@@ -22,6 +22,10 @@ The following generic nodes are supported:
  - input-schmitt-disable
  - slew-rate
 
+NXP specific properties:
+ - nxp,gpio-pin-interrupt : Assign pin to gpio pin interrupt controller
+                            irq number 0 to 7. See example below.
+
 Not all pins support all properties so either refer to the NXP 1850/4350
 user manual or the pin table in the pinctrl-lpc18xx driver for supported
 pin properties.
@@ -54,4 +58,14 @@ pinctrl: pinctrl@40086000 {
                         bias-disable;
                 };
         };
+
+        gpio_joystick_pins: gpio-joystick-pins {
+                gpio_joystick_1_cfg {
+                        pins =  "p9_0";
+                        function = "gpio";
+                        nxp,gpio-pin-interrupt = <0>;
+                        input-enable;
+                        bias-disable;
+                };
+        };
 };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
index 9ffb0b276bb4..17631d0a9af7 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
@@ -6,6 +6,7 @@ Required properties:
 - compatible: value should be one of the following.
         "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
         "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
+        "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
         "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
         "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
         "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
new file mode 100644
index 000000000000..cfb8500dd56b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
@@ -0,0 +1,74 @@
+Qualcomm Atheros IPQ4019 TLMM block
+
+This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
+platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
+
+Required properties:
+- compatible: "qcom,ipq4019-pinctrl"
+- reg: Should be the base address and length of the TLMM block.
+- interrupts: Should be the parent IRQ of the TLMM block.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells : Should be two.
+                The first cell is the gpio pin number and the
+                second cell is used for optional parameters.
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+ pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
+
+Non-empty subnodes must specify the 'pins' property.
+Note that not all properties are valid for all pins.
+
+
+Valid values for qcom,pins are:
+  gpio0-gpio99
+    Supports mux, bias and drive-strength
+
+Valid values for qcom,function are:
+gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0
+
+Example:
+
+        tlmm: pinctrl@1000000 {
+                compatible = "qcom,ipq4019-pinctrl";
+                reg = <0x1000000 0x300000>;
+
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                interrupts = <0 208 0>;
+
+                serial_pins: serial_pinmux {
+                        mux {
+                                pins = "gpio60", "gpio61";
+                                function = "blsp_uart0";
+                                bias-disable;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 0cd701b1947f..c68b9554561f 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -22,7 +22,7 @@ Required properties for iomux controller:
   - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
                        "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
                        "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl"
-                       "rockchip,rk3368-pinctrl"
+                       "rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl"
   - rockchip,grf: phandle referencing a syscon providing the
          "general register files"
 
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
new file mode 100644
index 000000000000..7b4800cc251e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -0,0 +1,126 @@
+* STM32 GPIO and Pin Mux/Config controller
+
+STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
+controller. It controls the input/output settings on the available pins and
+also provides ability to multiplex and configure the output of various on-chip
+controllers onto these pads.
+
+Pin controller node:
+Required properies:
+ - compatible: value should be one of the following:
+   (a) "st,stm32f429-pinctrl"
+ - #address-cells: The value of this property must be 1
+ - #size-cells  : The value of this property must be 1
+ - ranges       : defines mapping between pin controller node (parent) to
+   gpio-bank node (children).
+ - pins-are-numbered: Specify the subnodes are using numbered pinmux to
+   specify pins.
+
+GPIO controller/bank node:
+Required properties:
+ - gpio-controller : Indicates this device is a GPIO controller
+ - #gpio-cells    : Should be two.
+                        The first cell is the pin number
+                        The second one is the polarity:
+                                - 0 for active high
+                                - 1 for active low
+ - reg            : The gpio address range, relative to the pinctrl range
+ - clocks         : clock that drives this bank
+ - st,bank-name   : Should be a name string for this bank as specified in
+   the datasheet
+
+Optional properties:
+ - reset:         : Reference to the reset controller
+
+Example:
+#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
+...
+
+        pin-controller {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "st,stm32f429-pinctrl";
+                ranges = <0 0x40020000 0x3000>;
+                pins-are-numbered;
+
+                gpioa: gpio@40020000 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        reg = <0x0 0x400>;
+                        resets = <&reset_ahb1 0>;
+                        st,bank-name = "GPIOA";
+                };
+                ...
+                pin-functions nodes follow...
+        };
+
+Contents of function subnode node:
+----------------------------------
+Subnode format
+A pinctrl node should contain at least one subnode representing the
+pinctrl group available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, pullups, drive, output high/low and output speed.
+
+    node {
+        pinmux = <PIN_NUMBER_PINMUX>;
+        GENERIC_PINCONFIG;
+    };
+
+Required properties:
+- pinmux: integer array, represents gpio pin number and mux setting.
+  Supported pin number and mux varies for different SoCs, and are defined in
+  dt-bindings/pinctrl/<soc>-pinfunc.h directly.
+  These defines are calculated as:
+    ((port * 16 + line) << 8) | function
+  With:
+    - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
+    - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
+    - function: The function number, can be:
+      * 0 : GPIO
+      * 1 : Alternate Function 0
+      * 2 : Alternate Function 1
+      * 3 : Alternate Function 2
+      * ...
+      * 16 : Alternate Function 15
+      * 17 : Analog
+
+Optional properties:
+- GENERIC_PINCONFIG: is the generic pinconfig options to use.
+  Available options are:
+   - bias-disable,
+   - bias-pull-down,
+   - bias-pull-up,
+   - drive-push-pull,
+   - drive-open-drain,
+   - output-low
+   - output-high
+   - slew-rate = <x>, with x being:
+       < 0 > : Low speed
+       < 1 > : Medium speed
+       < 2 > : Fast speed
+       < 3 > : High speed
+
+Example:
+
+pin-controller {
+...
+        usart1_pins_a: usart1@0 {
+                pins1 {
+                        pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
+                        bias-disable;
+                        drive-push-pull;
+                        slew-rate = <0>;
+                };
+                pins2 {
+                        pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
+                        bias-disable;
+                };
+        };
+};
+
+&usart1 {
+        pinctrl-0 = <&usart1_pins_a>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/mt2701-pinfunc.h b/arch/arm/boot/dts/mt2701-pinfunc.h
new file mode 100644
index 000000000000..e24ebc8d928e
--- /dev/null
+++ b/arch/arm/boot/dts/mt2701-pinfunc.h
@@ -0,0 +1,735 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Biao Huang <biao.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DTS_MT2701_PINFUNC_H
+#define __DTS_MT2701_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
+
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
+
+#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
+
+#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
+
+#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
+
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5)
+
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7)
+
+#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7)
+
+#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
+#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
+#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4)
+#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7)
+
+#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
+#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
+#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
+#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4)
+#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7)
+
+#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
+
+#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
+
+#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
+
+#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
+
+#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1)
+#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
+#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5)
+#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7)
+
+#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
+#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2)
+#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7)
+
+#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
+#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2)
+#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4)
+#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5)
+#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6)
+#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7)
+
+#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7)
+
+#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
+#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2)
+#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3)
+#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
+#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5)
+#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6)
+#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7)
+
+#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
+#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2)
+#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3)
+#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
+#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5)
+#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6)
+#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7)
+
+#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
+#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3)
+#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4)
+#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5)
+#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7)
+#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10)
+
+#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1)
+#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3)
+#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4)
+#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
+#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7)
+#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10)
+
+#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
+#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3)
+#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4)
+#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7)
+#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10)
+
+#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1)
+#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3)
+#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4)
+#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7)
+
+#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
+#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2)
+#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3)
+#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4)
+#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5)
+#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
+#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7)
+
+#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1)
+#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2)
+#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3)
+#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4)
+#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
+#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7)
+
+#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
+#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3)
+#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4)
+#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
+#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7)
+
+#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1)
+#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
+#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3)
+#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4)
+#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5)
+#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7)
+#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14)
+
+#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7)
+
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7)
+
+#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7)
+
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7)
+
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7)
+
+#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1)
+#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2)
+#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3)
+#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4)
+
+#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1)
+#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2)
+#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3)
+#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4)
+
+#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1)
+#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2)
+#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4)
+
+#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1)
+#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2)
+#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4)
+
+#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1)
+#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
+
+#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
+#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2)
+
+#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
+#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
+
+#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1)
+
+#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1)
+#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2)
+
+#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1)
+#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2)
+
+#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7)
+
+#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7)
+
+#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
+#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3)
+#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4)
+#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7)
+
+#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
+#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
+#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
+#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4)
+#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5)
+#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7)
+
+#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3)
+#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7)
+
+#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1)
+
+#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1)
+
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7)
+
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7)
+
+#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7)
+
+#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1)
+
+#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1)
+
+#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1)
+
+#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1)
+
+#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1)
+#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
+#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5)
+
+#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
+#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2)
+
+#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1)
+#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
+
+#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
+#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2)
+
+#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
+#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2)
+#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7)
+
+#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
+#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7)
+
+#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
+#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1)
+
+#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
+#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1)
+
+#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
+#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1)
+
+#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
+#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1)
+
+#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
+#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1)
+
+#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
+#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1)
+
+#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
+#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1)
+
+#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
+#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1)
+
+#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
+#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1)
+
+#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0)
+#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1)
+
+#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4)
+
+#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3)
+#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4)
+
+#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3)
+#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4)
+
+#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4)
+
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7)
+
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7)
+
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7)
+
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7)
+
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7)
+
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7)
+
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4)
+
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4)
+
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4)
+
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4)
+
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4)
+
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4)
+
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4)
+
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4)
+
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4)
+
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4)
+
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
+
+#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1)
+#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4)
+#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5)
+
+#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1)
+#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4)
+#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
+
+#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1)
+#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4)
+#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5)
+
+#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1)
+#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4)
+#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5)
+
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7)
+
+#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7)
+
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7)
+
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7)
+
+#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1)
+
+#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1)
+#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
+#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5)
+#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7)
+#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9)
+
+#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1)
+#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2)
+#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5)
+#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7)
+#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9)
+
+#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1)
+#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2)
+#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5)
+#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7)
+
+#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1)
+#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2)
+#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3)
+#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5)
+#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7)
+
+#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1)
+#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2)
+#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3)
+#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5)
+#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7)
+
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11)
+
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11)
+
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7)
+
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
+
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2)
+
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2)
+
+#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
+#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
+
+#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
+#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
+
+#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
+#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1)
+#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
+#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3)
+#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4)
+#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7)
+
+#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
+#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
+#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2)
+#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
+#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4)
+#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7)
+
+#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)
+#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1)
+
+#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)
+#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1)
+
+#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)
+
+#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)
+#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1)
+
+#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)
+#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1)
+
+#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9)
+
+#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9)
+#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14)
+
+#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9)
+#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14)
+
+#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9)
+#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14)
+
+#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9)
+#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14)
+
+#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9)
+#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14)
+
+#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9)
+#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14)
+
+#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9)
+
+#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9)
+
+#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9)
+
+#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9)
+
+#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9)
+
+#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
+#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
+#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7)
+
+#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
+#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
+
+#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
+#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
+#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6)
+
+#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
+#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
+#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6)
+
+#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
+#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
+#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6)
+
+#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
+#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
+#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6)
+
+#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
+#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
+
+#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
+#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
+
+#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
+#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
+
+#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
+#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
+
+#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
+#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
+
+#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
+#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
+
+#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
+#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
+
+#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
+#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1)
+#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6)
+
+#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
+#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1)
+#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6)
+
+#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
+#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
+
+#endif /* __DTS_MT2701_PINFUNC_H */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 99a4c10ed43f..fb8200b8e8ec 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -79,7 +79,7 @@ config PINCTRL_AT91PIO4
           controller available on sama5d2 SoC.
 
 config PINCTRL_AMD
-        bool "AMD GPIO pin control"
+        tristate "AMD GPIO pin control"
         depends on GPIOLIB
         select GPIOLIB_IRQCHIP
         select PINCONF
@@ -168,37 +168,6 @@ config PINCTRL_ST
         select PINCONF
         select GPIOLIB_IRQCHIP
 
-config PINCTRL_TEGRA
-        bool
-        select PINMUX
-        select PINCONF
-
-config PINCTRL_TEGRA20
-        bool
-        select PINCTRL_TEGRA
-
-config PINCTRL_TEGRA30
-        bool
-        select PINCTRL_TEGRA
-
-config PINCTRL_TEGRA114
-        bool
-        select PINCTRL_TEGRA
-
-config PINCTRL_TEGRA124
-        bool
-        select PINCTRL_TEGRA
-
-config PINCTRL_TEGRA210
-        bool
-        select PINCTRL_TEGRA
-
-config PINCTRL_TEGRA_XUSB
-        def_bool y if ARCH_TEGRA
-        select GENERIC_PHY
-        select PINCONF
-        select PINMUX
-
 config PINCTRL_TZ1090
         bool "Toumaz Xenif TZ1090 pin control driver"
         depends on SOC_TZ1090
@@ -238,6 +207,23 @@ config PINCTRL_PALMAS
           open drain configuration for the Palmas series devices like
           TPS65913, TPS80036 etc.
 
+config PINCTRL_PIC32
+        bool "Microchip PIC32 pin controller driver"
+        depends on OF
+        depends on MACH_PIC32
+        select PINMUX
+        select GENERIC_PINCONF
+        select GPIOLIB_IRQCHIP
+        select OF_GPIO
+        help
+          This is the pin controller and gpio driver for Microchip PIC32
+          microcontrollers. This option is selected automatically when specific
+          machine and arch are selected to build.
+
+config PINCTRL_PIC32MZDA
+        def_bool y if PIC32MZDA
+        select PINCTRL_PIC32
+
 config PINCTRL_ZYNQ
         bool "Pinctrl driver for Xilinx Zynq"
         depends on ARCH_ZYNQ
@@ -257,7 +243,9 @@ source "drivers/pinctrl/qcom/Kconfig"
 source "drivers/pinctrl/samsung/Kconfig"
 source "drivers/pinctrl/sh-pfc/Kconfig"
 source "drivers/pinctrl/spear/Kconfig"
+source "drivers/pinctrl/stm32/Kconfig"
 source "drivers/pinctrl/sunxi/Kconfig"
+source "drivers/pinctrl/tegra/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
 source "drivers/pinctrl/vt8500/Kconfig"
 source "drivers/pinctrl/mediatek/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index bf1b5ca5180b..e4bc1151e04f 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -18,17 +18,12 @@ obj-$(CONFIG_PINCTRL_DIGICOLOR)	+= pinctrl-digicolor.o
 obj-$(CONFIG_PINCTRL_FALCON)    += pinctrl-falcon.o
 obj-$(CONFIG_PINCTRL_MESON)     += meson/
 obj-$(CONFIG_PINCTRL_PALMAS)    += pinctrl-palmas.o
+obj-$(CONFIG_PINCTRL_PIC32)     += pinctrl-pic32.o
 obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP)  += pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_SINGLE)    += pinctrl-single.o
 obj-$(CONFIG_PINCTRL_SIRF)      += sirf/
-obj-$(CONFIG_PINCTRL_TEGRA)     += pinctrl-tegra.o
-obj-$(CONFIG_PINCTRL_TEGRA20)   += pinctrl-tegra20.o
-obj-$(CONFIG_PINCTRL_TEGRA30)   += pinctrl-tegra30.o
-obj-$(CONFIG_PINCTRL_TEGRA114)  += pinctrl-tegra114.o
-obj-$(CONFIG_PINCTRL_TEGRA124)  += pinctrl-tegra124.o
-obj-$(CONFIG_PINCTRL_TEGRA210)  += pinctrl-tegra210.o
-obj-$(CONFIG_PINCTRL_TEGRA_XUSB)        += pinctrl-tegra-xusb.o
+obj-$(CONFIG_PINCTRL_TEGRA)     += tegra/
 obj-$(CONFIG_PINCTRL_TZ1090)    += pinctrl-tz1090.o
 obj-$(CONFIG_PINCTRL_TZ1090_PDC)        += pinctrl-tz1090-pdc.o
 obj-$(CONFIG_PINCTRL_U300)      += pinctrl-u300.o
@@ -46,12 +41,13 @@ obj-y				+= freescale/
 obj-$(CONFIG_X86)               += intel/
 obj-$(CONFIG_PINCTRL_MVEBU)     += mvebu/
 obj-y                           += nomadik/
-obj-$(CONFIG_ARCH_PXA)          += pxa/
+obj-$(CONFIG_PINCTRL_PXA)       += pxa/
 obj-$(CONFIG_ARCH_QCOM)         += qcom/
 obj-$(CONFIG_PINCTRL_SAMSUNG)   += samsung/
 obj-$(CONFIG_PINCTRL_SH_PFC)    += sh-pfc/
 obj-$(CONFIG_PINCTRL_SPEAR)     += spear/
-obj-$(CONFIG_ARCH_SUNXI)        += sunxi/
+obj-$(CONFIG_PINCTRL_STM32)     += stm32/
+obj-$(CONFIG_PINCTRL_SUNXI)     += sunxi/
 obj-$(CONFIG_PINCTRL_UNIPHIER)  += uniphier/
 obj-$(CONFIG_ARCH_VT8500)       += vt8500/
-obj-$(CONFIG_ARCH_MEDIATEK)     += mediatek/
+obj-$(CONFIG_PINCTRL_MTK)       += mediatek/
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 0f5997ceb494..08b1d93da9fe 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -779,7 +779,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
                 }
                 if (num_pulls) {
                         err = of_property_read_u32_index(np, "brcm,pull",
-                                        (num_funcs > 1) ? i : 0, &pull);
+                                        (num_pulls > 1) ? i : 0, &pull);
                         if (err)
                                 goto out;
                         err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 2686a4450dfc..f67a8b7a4e18 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -481,18 +481,12 @@ int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, const char *pin_group,
 }
 EXPORT_SYMBOL_GPL(pinctrl_get_group_pins);
 
-/**
- * pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin
- * @pctldev: the pin controller device to look in
- * @pin: a controller-local number to find the range for
- */
 struct pinctrl_gpio_range *
-pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
-                                 unsigned int pin)
+pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
+                                        unsigned int pin)
 {
         struct pinctrl_gpio_range *range;
 
-        mutex_lock(&pctldev->mutex);
         /* Loop over the ranges */
         list_for_each_entry(range, &pctldev->gpio_ranges, node) {
                 /* Check if we're in the valid range */
@@ -500,15 +494,32 @@ pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
                         int a;
                         for (a = 0; a < range->npins; a++) {
                                 if (range->pins[a] == pin)
-                                        goto out;
+                                        return range;
                         }
                 } else if (pin >= range->pin_base &&
                            pin < range->pin_base + range->npins)
-                        goto out;
+                        return range;
         }
-        range = NULL;
-out:
+
+        return NULL;
+}
+EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin_nolock);
+
+/**
+ * pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin
+ * @pctldev: the pin controller device to look in
+ * @pin: a controller-local number to find the range for
+ */
+struct pinctrl_gpio_range *
+pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
+                                 unsigned int pin)
+{
+        struct pinctrl_gpio_range *range;
+
+        mutex_lock(&pctldev->mutex);
+        range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
         mutex_unlock(&pctldev->mutex);
+
         return range;
 }
 EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin);
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index b24ea846c867..ca08723b9ee1 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -182,6 +182,10 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
         return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
 }
 
+extern struct pinctrl_gpio_range *
+pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
+                                        unsigned int pin);
+
 int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
                          bool dup);
 void pinctrl_unregister_map(struct pinctrl_map const *map);
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index a5bb93987378..46210512d8ec 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -15,6 +15,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
@@ -24,6 +25,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/slab.h>
+#include <linux/regmap.h>
 
 #include "../core.h"
 #include "pinctrl-imx.h"
@@ -341,6 +343,31 @@ mux_pin:
         return 0;
 }
 
+static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
+                        struct pinctrl_gpio_range *range, unsigned offset)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+        const struct imx_pin_reg *pin_reg;
+        u32 reg;
+
+        /*
+         * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
+         * They are part of the shared mux/conf register.
+         */
+        if (!(info->flags & SHARE_MUX_CONF_REG))
+                return;
+
+        pin_reg = &info->pin_regs[offset];
+        if (pin_reg->mux_reg == -1)
+                return;
+
+        /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
+        reg = readl(ipctl->base + pin_reg->mux_reg);
+        reg &= ~0x7;
+        writel(reg, ipctl->base + pin_reg->mux_reg);
+}
+
 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
            struct pinctrl_gpio_range *range, unsigned offset, bool input)
 {
@@ -377,6 +404,7 @@ static const struct pinmux_ops imx_pmx_ops = {
         .get_function_groups = imx_pmx_get_groups,
         .set_mux = imx_pmx_set,
         .gpio_request_enable = imx_pmx_gpio_request_enable,
+        .gpio_disable_free = imx_pmx_gpio_disable_free,
         .gpio_set_direction = imx_pmx_gpio_set_direction,
 };
 
@@ -692,10 +720,12 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
 int imx_pinctrl_probe(struct platform_device *pdev,
                       struct imx_pinctrl_soc_info *info)
 {
+        struct regmap_config config = { .name = "gpr" };
         struct device_node *dev_np = pdev->dev.of_node;
         struct device_node *np;
         struct imx_pinctrl *ipctl;
         struct resource *res;
+        struct regmap *gpr;
         int ret, i;
 
         if (!info || !info->pins || !info->npins) {
@@ -704,6 +734,12 @@ int imx_pinctrl_probe(struct platform_device *pdev,
         }
         info->dev = &pdev->dev;
 
+        if (info->gpr_compatible) {
+                gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
+                if (!IS_ERR(gpr))
+                        regmap_attach_dev(&pdev->dev, gpr, &config);
+        }
+
         /* Create state holders etc for this driver */
         ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
         if (!ipctl)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 2a592f657c18..3b8bd81a39a4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -82,6 +82,7 @@ struct imx_pinctrl_soc_info {
         struct imx_pmx_func *functions;
         unsigned int nfunctions;
         unsigned int flags;
+        const char *gpr_compatible;
 };
 
 #define SHARE_MUX_CONF_REG      0x1
diff --git a/drivers/pinctrl/freescale/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c
index 51b31df96273..8acc4d960cfa 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx50.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx50.c
@@ -389,6 +389,7 @@ static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
 static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
         .pins = imx50_pinctrl_pads,
         .npins = ARRAY_SIZE(imx50_pinctrl_pads),
+        .gpr_compatible = "fsl,imx50-iomuxc-gpr",
 };
 
 static const struct of_device_id imx50_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/freescale/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c
index 7344d340013c..d39dfd6a3a44 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx53.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx53.c
@@ -452,6 +452,7 @@ static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
 static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
         .pins = imx53_pinctrl_pads,
         .npins = ARRAY_SIZE(imx53_pinctrl_pads),
+        .gpr_compatible = "fsl,imx53-iomuxc-gpr",
 };
 
 static const struct of_device_id imx53_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
index 6805c678c3b2..5a2cdb0549ce 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6dl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
@@ -458,6 +458,7 @@ static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {
 static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
         .pins = imx6dl_pinctrl_pads,
         .npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
+        .gpr_compatible = "fsl,imx6q-iomuxc-gpr",
 };
 
 static const struct of_device_id imx6dl_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c
index 4d1fcb861ac1..7d50a36b1086 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6q.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c
@@ -464,6 +464,7 @@ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
 static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
         .pins = imx6q_pinctrl_pads,
         .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
+        .gpr_compatible = "fsl,imx6q-iomuxc-gpr",
 };
 
 static const struct of_device_id imx6q_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
index 83fa5f19ae89..e27d17fdc69d 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
@@ -364,6 +364,7 @@ static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = {
 static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
         .pins = imx6sl_pinctrl_pads,
         .npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
+        .gpr_compatible = "fsl,imx6sl-iomuxc-gpr",
 };
 
 static const struct of_device_id imx6sl_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
index 0d78fe690818..117180c26c50 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
@@ -368,6 +368,7 @@ static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
 static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
         .pins = imx6sx_pinctrl_pads,
         .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
+        .gpr_compatible = "fsl,imx6sx-iomuxc-gpr",
 };
 
 static const struct of_device_id imx6sx_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
index 08e75764e7be..78627c70c6ba 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6ul.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
@@ -284,6 +284,7 @@ static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
 static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
         .pins = imx6ul_pinctrl_pads,
         .npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
+        .gpr_compatible = "fsl,imx6ul-iomuxc-gpr",
 };
 
 static struct of_device_id imx6ul_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 16dc925117de..1c89613eb4b7 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -359,6 +359,7 @@ static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
 static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
         .pins = imx7d_pinctrl_pads,
         .npins = ARRAY_SIZE(imx7d_pinctrl_pads),
+        .gpr_compatible = "fsl,imx7d-iomuxc-gpr",
 };
 
 static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index c0f5586218c4..85536b467c25 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -11,13 +11,9 @@
  */
 
 #include <linux/module.h>
-#include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/acpi.h>
-#include <linux/gpio.h>
 #include <linux/gpio/driver.h>
 #include <linux/platform_device.h>
-#include <linux/pm.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/pinconf.h>
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 02f6f92df86c..4f0bc8a103f4 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -1,6 +1,6 @@
 if ARCH_MEDIATEK || COMPILE_TEST
 
-config PINCTRL_MTK_COMMON
+config PINCTRL_MTK
         bool
         depends on OF
         select PINMUX
@@ -9,17 +9,29 @@ config PINCTRL_MTK_COMMON
         select OF_GPIO
 
 # For ARMv7 SoCs
+config PINCTRL_MT2701
+        bool "Mediatek MT2701 pin control" if COMPILE_TEST && !MACH_MT2701
+        depends on OF
+        default MACH_MT2701
+        select PINCTRL_MTK
+
+config PINCTRL_MT7623
+        bool "Mediatek MT7623 pin control" if COMPILE_TEST && !MACH_MT7623
+        depends on OF
+        default MACH_MT7623
+        select PINCTRL_MTK_COMMON
+
 config PINCTRL_MT8135
         bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
         depends on OF
         default MACH_MT8135
-        select PINCTRL_MTK_COMMON
+        select PINCTRL_MTK
 
 config PINCTRL_MT8127
         bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127
         depends on OF
         default MACH_MT8127
-        select PINCTRL_MTK_COMMON
+        select PINCTRL_MTK
 
 # For ARMv8 SoCs
 config PINCTRL_MT8173
@@ -27,13 +39,13 @@ config PINCTRL_MT8173
         depends on OF
         depends on ARM64 || COMPILE_TEST
         default ARM64 && ARCH_MEDIATEK
-        select PINCTRL_MTK_COMMON
+        select PINCTRL_MTK
 
 # For PMIC
 config PINCTRL_MT6397
         bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397
         depends on OF
         default MFD_MT6397
-        select PINCTRL_MTK_COMMON
+        select PINCTRL_MTK
 
 endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index eb923d64d387..3e3390a14716 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -1,8 +1,10 @@
 # Core
-obj-$(CONFIG_PINCTRL_MTK_COMMON)        += pinctrl-mtk-common.o
+obj-y                           += pinctrl-mtk-common.o
 
 # SoC Drivers
-obj-$(CONFIG_PINCTRL_MT8135)            += pinctrl-mt8135.o
-obj-$(CONFIG_PINCTRL_MT8127)            += pinctrl-mt8127.o
-obj-$(CONFIG_PINCTRL_MT8173)            += pinctrl-mt8173.o
-obj-$(CONFIG_PINCTRL_MT6397)            += pinctrl-mt6397.o
+obj-$(CONFIG_PINCTRL_MT2701)    += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT7623)    += pinctrl-mt7623.o
+obj-$(CONFIG_PINCTRL_MT8135)    += pinctrl-mt8135.o
+obj-$(CONFIG_PINCTRL_MT8127)    += pinctrl-mt8127.o
+obj-$(CONFIG_PINCTRL_MT8173)    += pinctrl-mt8173.o
+obj-$(CONFIG_PINCTRL_MT6397)    += pinctrl-mt6397.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
new file mode 100644
index 000000000000..8d802fa7decd
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
@@ -0,0 +1,585 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Biao Huang <biao.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt2701.h"
+
+/**
+ * struct mtk_spec_pinmux_set
+ * - For special pins' mode setting
+ * @pin: The pin number.
+ * @offset: The offset of extra setting register.
+ * @bit: The bit of extra setting register.
+ */
+struct mtk_spec_pinmux_set {
+        unsigned short pin;
+        unsigned short offset;
+        unsigned char bit;
+};
+
+#define MTK_PINMUX_SPEC(_pin, _offset, _bit)    \
+        {                                       \
+                .pin = _pin,                    \
+                .offset = _offset,              \
+                .bit = _bit,                    \
+        }
+
+static const struct mtk_drv_group_desc mt2701_drv_grp[] =  {
+        /* 0E4E8SR 4/8/12/16 */
+        MTK_DRV_GRP(4, 16, 1, 2, 4),
+        /* 0E2E4SR  2/4/6/8 */
+        MTK_DRV_GRP(2, 8, 1, 2, 2),
+        /* E8E4E2  2/4/6/8/10/12/14/16 */
+        MTK_DRV_GRP(2, 16, 0, 2, 2)
+};
+
+static const struct mtk_pin_drv_grp mt2701_pin_drv[] = {
+        MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
+        MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
+        MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
+        MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
+        MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
+        MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
+        MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
+        MTK_PIN_DRV_GRP(7, 0xf50, 4, 1),
+        MTK_PIN_DRV_GRP(8, 0xf50, 4, 1),
+        MTK_PIN_DRV_GRP(9, 0xf50, 4, 1),
+        MTK_PIN_DRV_GRP(10, 0xf50, 8, 1),
+        MTK_PIN_DRV_GRP(11, 0xf50, 8, 1),
+        MTK_PIN_DRV_GRP(12, 0xf50, 8, 1),
+        MTK_PIN_DRV_GRP(13, 0xf50, 8, 1),
+        MTK_PIN_DRV_GRP(14, 0xf50, 12, 0),
+        MTK_PIN_DRV_GRP(15, 0xf50, 12, 0),
+        MTK_PIN_DRV_GRP(16, 0xf60, 0, 0),
+        MTK_PIN_DRV_GRP(17, 0xf60, 0, 0),
+        MTK_PIN_DRV_GRP(18, 0xf60, 4, 0),
+        MTK_PIN_DRV_GRP(19, 0xf60, 4, 0),
+        MTK_PIN_DRV_GRP(20, 0xf60, 4, 0),
+        MTK_PIN_DRV_GRP(21, 0xf60, 4, 0),
+        MTK_PIN_DRV_GRP(22, 0xf60, 8, 0),
+        MTK_PIN_DRV_GRP(23, 0xf60, 8, 0),
+        MTK_PIN_DRV_GRP(24, 0xf60, 8, 0),
+        MTK_PIN_DRV_GRP(25, 0xf60, 8, 0),
+        MTK_PIN_DRV_GRP(26, 0xf60, 8, 0),
+        MTK_PIN_DRV_GRP(27, 0xf60, 12, 0),
+        MTK_PIN_DRV_GRP(28, 0xf60, 12, 0),
+        MTK_PIN_DRV_GRP(29, 0xf60, 12, 0),
+        MTK_PIN_DRV_GRP(30, 0xf60, 0, 0),
+        MTK_PIN_DRV_GRP(31, 0xf60, 0, 0),
+        MTK_PIN_DRV_GRP(32, 0xf60, 0, 0),
+        MTK_PIN_DRV_GRP(33, 0xf70, 0, 0),
+        MTK_PIN_DRV_GRP(34, 0xf70, 0, 0),
+        MTK_PIN_DRV_GRP(35, 0xf70, 0, 0),
+        MTK_PIN_DRV_GRP(36, 0xf70, 0, 0),
+        MTK_PIN_DRV_GRP(37, 0xf70, 0, 0),
+        MTK_PIN_DRV_GRP(38, 0xf70, 4, 0),
+        MTK_PIN_DRV_GRP(39, 0xf70, 8, 1),
+        MTK_PIN_DRV_GRP(40, 0xf70, 8, 1),
+        MTK_PIN_DRV_GRP(41, 0xf70, 8, 1),
+        MTK_PIN_DRV_GRP(42, 0xf70, 8, 1),
+        MTK_PIN_DRV_GRP(43, 0xf70, 12, 0),
+        MTK_PIN_DRV_GRP(44, 0xf70, 12, 0),
+        MTK_PIN_DRV_GRP(45, 0xf70, 12, 0),
+        MTK_PIN_DRV_GRP(47, 0xf80, 0, 0),
+        MTK_PIN_DRV_GRP(48, 0xf80, 0, 0),
+        MTK_PIN_DRV_GRP(49, 0xf80, 4, 0),
+        MTK_PIN_DRV_GRP(50, 0xf70, 4, 0),
+        MTK_PIN_DRV_GRP(51, 0xf70, 4, 0),
+        MTK_PIN_DRV_GRP(52, 0xf70, 4, 0),
+        MTK_PIN_DRV_GRP(53, 0xf80, 12, 0),
+        MTK_PIN_DRV_GRP(54, 0xf80, 12, 0),
+        MTK_PIN_DRV_GRP(55, 0xf80, 12, 0),
+        MTK_PIN_DRV_GRP(56, 0xf80, 12, 0),
+        MTK_PIN_DRV_GRP(60, 0xf90, 8, 1),
+        MTK_PIN_DRV_GRP(61, 0xf90, 8, 1),
+        MTK_PIN_DRV_GRP(62, 0xf90, 8, 1),
+        MTK_PIN_DRV_GRP(63, 0xf90, 12, 1),
+        MTK_PIN_DRV_GRP(64, 0xf90, 12, 1),
+        MTK_PIN_DRV_GRP(65, 0xf90, 12, 1),
+        MTK_PIN_DRV_GRP(66, 0xfa0, 0, 1),
+        MTK_PIN_DRV_GRP(67, 0xfa0, 0, 1),
+        MTK_PIN_DRV_GRP(68, 0xfa0, 0, 1),
+        MTK_PIN_DRV_GRP(69, 0xfa0, 0, 1),
+        MTK_PIN_DRV_GRP(70, 0xfa0, 0, 1),
+        MTK_PIN_DRV_GRP(71, 0xfa0, 0, 1),
+        MTK_PIN_DRV_GRP(72, 0xf80, 4, 0),
+        MTK_PIN_DRV_GRP(73, 0xf80, 4, 0),
+        MTK_PIN_DRV_GRP(74, 0xf80, 4, 0),
+        MTK_PIN_DRV_GRP(85, 0xda0, 0, 2),
+        MTK_PIN_DRV_GRP(86, 0xd90, 0, 2),
+        MTK_PIN_DRV_GRP(87, 0xdb0, 0, 2),
+        MTK_PIN_DRV_GRP(88, 0xdb0, 0, 2),
+        MTK_PIN_DRV_GRP(89, 0xdb0, 0, 2),
+        MTK_PIN_DRV_GRP(90, 0xdb0, 0, 2),
+        MTK_PIN_DRV_GRP(105, 0xd40, 0, 2),
+        MTK_PIN_DRV_GRP(106, 0xd30, 0, 2),
+        MTK_PIN_DRV_GRP(107, 0xd50, 0, 2),
+        MTK_PIN_DRV_GRP(108, 0xd50, 0, 2),
+        MTK_PIN_DRV_GRP(109, 0xd50, 0, 2),
+        MTK_PIN_DRV_GRP(110, 0xd50, 0, 2),
+        MTK_PIN_DRV_GRP(111, 0xce0, 0, 2),
+        MTK_PIN_DRV_GRP(112, 0xce0, 0, 2),
+        MTK_PIN_DRV_GRP(113, 0xce0, 0, 2),
+        MTK_PIN_DRV_GRP(114, 0xce0, 0, 2),
+        MTK_PIN_DRV_GRP(115, 0xce0, 0, 2),
+        MTK_PIN_DRV_GRP(116, 0xcd0, 0, 2),
+        MTK_PIN_DRV_GRP(117, 0xcc0, 0, 2),
+        MTK_PIN_DRV_GRP(118, 0xce0, 0, 2),
+        MTK_PIN_DRV_GRP(119, 0xce0, 0, 2),
+        MTK_PIN_DRV_GRP(120, 0xce0, 0, 2),
+        MTK_PIN_DRV_GRP(121, 0xce0, 0, 2),
+        MTK_PIN_DRV_GRP(126, 0xf80, 4, 0),
+        MTK_PIN_DRV_GRP(188, 0xf70, 4, 0),
+        MTK_PIN_DRV_GRP(189, 0xfe0, 8, 0),
+        MTK_PIN_DRV_GRP(190, 0xfe0, 8, 0),
+        MTK_PIN_DRV_GRP(191, 0xfe0, 8, 0),
+        MTK_PIN_DRV_GRP(192, 0xfe0, 8, 0),
+        MTK_PIN_DRV_GRP(193, 0xfe0, 8, 0),
+        MTK_PIN_DRV_GRP(194, 0xfe0, 12, 0),
+        MTK_PIN_DRV_GRP(195, 0xfe0, 12, 0),
+        MTK_PIN_DRV_GRP(196, 0xfe0, 12, 0),
+        MTK_PIN_DRV_GRP(197, 0xfe0, 12, 0),
+        MTK_PIN_DRV_GRP(198, 0xfe0, 12, 0),
+        MTK_PIN_DRV_GRP(199, 0xf50, 4, 1),
+        MTK_PIN_DRV_GRP(200, 0xfd0, 0, 0),
+        MTK_PIN_DRV_GRP(201, 0xfd0, 0, 0),
+        MTK_PIN_DRV_GRP(202, 0xfd0, 0, 0),
+        MTK_PIN_DRV_GRP(203, 0xfd0, 4, 0),
+        MTK_PIN_DRV_GRP(204, 0xfd0, 4, 0),
+        MTK_PIN_DRV_GRP(205, 0xfd0, 4, 0),
+        MTK_PIN_DRV_GRP(206, 0xfd0, 4, 0),
+        MTK_PIN_DRV_GRP(207, 0xfd0, 4, 0),
+        MTK_PIN_DRV_GRP(208, 0xfd0, 8, 0),
+        MTK_PIN_DRV_GRP(209, 0xfd0, 8, 0),
+        MTK_PIN_DRV_GRP(210, 0xfd0, 12, 1),
+        MTK_PIN_DRV_GRP(211, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(212, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(213, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(214, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(215, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(216, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(217, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(218, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(219, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(220, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(221, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(222, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(223, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(224, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(225, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(226, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(227, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(228, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(229, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(230, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(231, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(232, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(233, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(234, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(235, 0xff0, 0, 1),
+        MTK_PIN_DRV_GRP(236, 0xff0, 4, 0),
+        MTK_PIN_DRV_GRP(237, 0xff0, 4, 0),
+        MTK_PIN_DRV_GRP(238, 0xff0, 4, 0),
+        MTK_PIN_DRV_GRP(239, 0xff0, 4, 0),
+        MTK_PIN_DRV_GRP(240, 0xff0, 4, 0),
+        MTK_PIN_DRV_GRP(241, 0xff0, 4, 0),
+        MTK_PIN_DRV_GRP(242, 0xff0, 8, 0),
+        MTK_PIN_DRV_GRP(243, 0xff0, 8, 0),
+        MTK_PIN_DRV_GRP(248, 0xf00, 0, 0),
+        MTK_PIN_DRV_GRP(249, 0xfc0, 0, 2),
+        MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2),
+        MTK_PIN_DRV_GRP(251, 0xfc0, 0, 2),
+        MTK_PIN_DRV_GRP(252, 0xfc0, 0, 2),
+        MTK_PIN_DRV_GRP(253, 0xfc0, 0, 2),
+        MTK_PIN_DRV_GRP(254, 0xfc0, 0, 2),
+        MTK_PIN_DRV_GRP(255, 0xfc0, 0, 2),
+        MTK_PIN_DRV_GRP(256, 0xfc0, 0, 2),
+        MTK_PIN_DRV_GRP(257, 0xce0, 0, 2),
+        MTK_PIN_DRV_GRP(258, 0xcb0, 0, 2),
+        MTK_PIN_DRV_GRP(259, 0xc90, 0, 2),
+        MTK_PIN_DRV_GRP(260, 0x3a0, 0, 2),
+        MTK_PIN_DRV_GRP(261, 0xd50, 0, 2),
+        MTK_PIN_DRV_GRP(262, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(263, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(264, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(265, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(266, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(267, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(268, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(269, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(270, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(271, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(272, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(273, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(274, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(275, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(276, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(277, 0xf00, 8, 0),
+        MTK_PIN_DRV_GRP(278, 0xf70, 8, 1),
+};
+
+static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
+        MTK_PIN_PUPD_SPEC_SR(111, 0xd00, 12, 13, 14),   /* ms0 data7 */
+        MTK_PIN_PUPD_SPEC_SR(112, 0xd00, 8, 9, 10),     /* ms0 data6 */
+        MTK_PIN_PUPD_SPEC_SR(113, 0xd00, 4, 5, 6),      /* ms0 data5 */
+        MTK_PIN_PUPD_SPEC_SR(114, 0xd00, 0, 1, 2),      /* ms0 data4 */
+        MTK_PIN_PUPD_SPEC_SR(115, 0xd10, 0, 1, 2),      /* ms0 rstb */
+        MTK_PIN_PUPD_SPEC_SR(116, 0xcd0, 8, 9, 10),     /* ms0 cmd */
+        MTK_PIN_PUPD_SPEC_SR(117, 0xcc0, 8, 9, 10),     /* ms0 clk */
+        MTK_PIN_PUPD_SPEC_SR(118, 0xcf0, 12, 13, 14),   /* ms0 data3 */
+        MTK_PIN_PUPD_SPEC_SR(119, 0xcf0, 8, 9, 10),     /* ms0 data2 */
+        MTK_PIN_PUPD_SPEC_SR(120, 0xcf0, 4, 5, 6),      /* ms0 data1 */
+        MTK_PIN_PUPD_SPEC_SR(121, 0xcf0, 0, 1, 2),      /* ms0 data0 */
+
+        MTK_PIN_PUPD_SPEC_SR(105, 0xd40, 8, 9, 10),     /* ms1 cmd */
+        MTK_PIN_PUPD_SPEC_SR(106, 0xd30, 8, 9, 10),     /* ms1 clk */
+        MTK_PIN_PUPD_SPEC_SR(107, 0xd60, 0, 1, 2),      /* ms1 dat0 */
+        MTK_PIN_PUPD_SPEC_SR(108, 0xd60, 10, 9, 8),     /* ms1 dat1 */
+        MTK_PIN_PUPD_SPEC_SR(109, 0xd60, 4, 5, 6),      /* ms1 dat2 */
+        MTK_PIN_PUPD_SPEC_SR(110, 0xc60, 12, 13, 14),   /* ms1 dat3 */
+
+        MTK_PIN_PUPD_SPEC_SR(85, 0xda0, 8, 9, 10),      /* ms2 cmd */
+        MTK_PIN_PUPD_SPEC_SR(86, 0xd90, 8, 9, 10),      /* ms2 clk */
+        MTK_PIN_PUPD_SPEC_SR(87, 0xdc0, 0, 1, 2),       /* ms2 dat0 */
+        MTK_PIN_PUPD_SPEC_SR(88, 0xdc0, 10, 9, 8),      /* ms2 dat1 */
+        MTK_PIN_PUPD_SPEC_SR(89, 0xdc0, 4, 5, 6),       /* ms2 dat2 */
+        MTK_PIN_PUPD_SPEC_SR(90, 0xdc0, 12, 13, 14),    /* ms2 dat3 */
+
+        MTK_PIN_PUPD_SPEC_SR(249, 0x140, 0, 1, 2),      /* ms0e rstb */
+        MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14),   /* ms0e dat7 */
+        MTK_PIN_PUPD_SPEC_SR(251, 0x130, 8, 9, 10),     /* ms0e dat6 */
+        MTK_PIN_PUPD_SPEC_SR(252, 0x130, 4, 5, 6),      /* ms0e dat5 */
+        MTK_PIN_PUPD_SPEC_SR(253, 0x130, 0, 1, 2),      /* ms0e dat4 */
+        MTK_PIN_PUPD_SPEC_SR(254, 0xf40, 12, 13, 14),   /* ms0e dat3 */
+        MTK_PIN_PUPD_SPEC_SR(255, 0xf40, 8, 9, 10),     /* ms0e dat2 */
+        MTK_PIN_PUPD_SPEC_SR(256, 0xf40, 4, 5, 6),      /* ms0e dat1 */
+        MTK_PIN_PUPD_SPEC_SR(257, 0xf40, 0, 1, 2),      /* ms0e dat0 */
+        MTK_PIN_PUPD_SPEC_SR(258, 0xcb0, 8, 9, 10),     /* ms0e cmd */
+        MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10),     /* ms0e clk */
+        MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10),     /* ms1 ins */
+};
+
+static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
+                unsigned char align, bool isup, unsigned int r1r0)
+{
+        return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
+                ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
+}
+
+static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
+        MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
+        MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
+        MTK_PIN_IES_SMT_SPEC(10, 13, 0xb30, 3),
+        MTK_PIN_IES_SMT_SPEC(14, 15, 0xb30, 13),
+        MTK_PIN_IES_SMT_SPEC(16, 17, 0xb40, 7),
+        MTK_PIN_IES_SMT_SPEC(18, 21, 0xb40, 13),
+        MTK_PIN_IES_SMT_SPEC(22, 26, 0xb40, 13),
+        MTK_PIN_IES_SMT_SPEC(27, 29, 0xb40, 13),
+        MTK_PIN_IES_SMT_SPEC(30, 32, 0xb40, 7),
+        MTK_PIN_IES_SMT_SPEC(33, 37, 0xb40, 13),
+        MTK_PIN_IES_SMT_SPEC(38, 38, 0xb20, 13),
+        MTK_PIN_IES_SMT_SPEC(39, 42, 0xb40, 13),
+        MTK_PIN_IES_SMT_SPEC(43, 45, 0xb20, 10),
+        MTK_PIN_IES_SMT_SPEC(47, 48, 0xb20, 11),
+        MTK_PIN_IES_SMT_SPEC(49, 49, 0xb20, 12),
+        MTK_PIN_IES_SMT_SPEC(50, 52, 0xb20, 13),
+        MTK_PIN_IES_SMT_SPEC(53, 56, 0xb20, 14),
+        MTK_PIN_IES_SMT_SPEC(57, 58, 0xb20, 15),
+        MTK_PIN_IES_SMT_SPEC(59, 59, 0xb30, 10),
+        MTK_PIN_IES_SMT_SPEC(60, 62, 0xb30, 0),
+        MTK_PIN_IES_SMT_SPEC(63, 65, 0xb30, 1),
+        MTK_PIN_IES_SMT_SPEC(66, 71, 0xb30, 2),
+        MTK_PIN_IES_SMT_SPEC(72, 74, 0xb20, 12),
+        MTK_PIN_IES_SMT_SPEC(75, 76, 0xb30, 3),
+        MTK_PIN_IES_SMT_SPEC(77, 78, 0xb30, 4),
+        MTK_PIN_IES_SMT_SPEC(79, 82, 0xb30, 5),
+        MTK_PIN_IES_SMT_SPEC(83, 84, 0xb30, 2),
+        MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 4),
+        MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 4),
+        MTK_PIN_IES_SMT_SPEC(87, 90, 0xdb0, 4),
+        MTK_PIN_IES_SMT_SPEC(101, 104, 0xb30, 6),
+        MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 4),
+        MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 4),
+        MTK_PIN_IES_SMT_SPEC(107, 110, 0xd50, 4),
+        MTK_PIN_IES_SMT_SPEC(111, 115, 0xce0, 4),
+        MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 4),
+        MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 4),
+        MTK_PIN_IES_SMT_SPEC(118, 121, 0xce0, 4),
+        MTK_PIN_IES_SMT_SPEC(122, 125, 0xb30, 7),
+        MTK_PIN_IES_SMT_SPEC(126, 126, 0xb20, 12),
+        MTK_PIN_IES_SMT_SPEC(127, 142, 0xb30, 9),
+        MTK_PIN_IES_SMT_SPEC(143, 160, 0xb30, 10),
+        MTK_PIN_IES_SMT_SPEC(161, 168, 0xb30, 12),
+        MTK_PIN_IES_SMT_SPEC(169, 183, 0xb30, 10),
+        MTK_PIN_IES_SMT_SPEC(184, 186, 0xb30, 9),
+        MTK_PIN_IES_SMT_SPEC(187, 187, 0xb30, 14),
+        MTK_PIN_IES_SMT_SPEC(188, 188, 0xb20, 13),
+        MTK_PIN_IES_SMT_SPEC(189, 193, 0xb30, 15),
+        MTK_PIN_IES_SMT_SPEC(194, 198, 0xb40, 0),
+        MTK_PIN_IES_SMT_SPEC(199, 199, 0xb20, 1),
+        MTK_PIN_IES_SMT_SPEC(200, 202, 0xb40, 1),
+        MTK_PIN_IES_SMT_SPEC(203, 207, 0xb40, 2),
+        MTK_PIN_IES_SMT_SPEC(208, 209, 0xb40, 3),
+        MTK_PIN_IES_SMT_SPEC(210, 210, 0xb40, 4),
+        MTK_PIN_IES_SMT_SPEC(211, 235, 0xb40, 5),
+        MTK_PIN_IES_SMT_SPEC(236, 241, 0xb40, 6),
+        MTK_PIN_IES_SMT_SPEC(242, 243, 0xb40, 7),
+        MTK_PIN_IES_SMT_SPEC(244, 247, 0xb40, 8),
+        MTK_PIN_IES_SMT_SPEC(248, 248, 0xb40, 9),
+        MTK_PIN_IES_SMT_SPEC(249, 257, 0xfc0, 4),
+        MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 4),
+        MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4),
+        MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 4),
+        MTK_PIN_IES_SMT_SPEC(261, 261, 0xd50, 4),
+        MTK_PIN_IES_SMT_SPEC(262, 277, 0xb40, 12),
+        MTK_PIN_IES_SMT_SPEC(278, 278, 0xb40, 13),
+};
+
+static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
+        MTK_PIN_IES_SMT_SPEC(0, 6, 0xb50, 0),
+        MTK_PIN_IES_SMT_SPEC(7, 9, 0xb50, 1),
+        MTK_PIN_IES_SMT_SPEC(10, 13, 0xb60, 3),
+        MTK_PIN_IES_SMT_SPEC(14, 15, 0xb60, 13),
+        MTK_PIN_IES_SMT_SPEC(16, 17, 0xb70, 7),
+        MTK_PIN_IES_SMT_SPEC(18, 21, 0xb70, 13),
+        MTK_PIN_IES_SMT_SPEC(22, 26, 0xb70, 13),
+        MTK_PIN_IES_SMT_SPEC(27, 29, 0xb70, 13),
+        MTK_PIN_IES_SMT_SPEC(30, 32, 0xb70, 7),
+        MTK_PIN_IES_SMT_SPEC(33, 37, 0xb70, 13),
+        MTK_PIN_IES_SMT_SPEC(38, 38, 0xb50, 13),
+        MTK_PIN_IES_SMT_SPEC(39, 42, 0xb70, 13),
+        MTK_PIN_IES_SMT_SPEC(43, 45, 0xb50, 10),
+        MTK_PIN_IES_SMT_SPEC(47, 48, 0xb50, 11),
+        MTK_PIN_IES_SMT_SPEC(49, 49, 0xb50, 12),
+        MTK_PIN_IES_SMT_SPEC(50, 52, 0xb50, 13),
+        MTK_PIN_IES_SMT_SPEC(53, 56, 0xb50, 14),
+        MTK_PIN_IES_SMT_SPEC(57, 58, 0xb50, 15),
+        MTK_PIN_IES_SMT_SPEC(59, 59, 0xb60, 10),
+        MTK_PIN_IES_SMT_SPEC(60, 62, 0xb60, 0),
+        MTK_PIN_IES_SMT_SPEC(63, 65, 0xb60, 1),
+        MTK_PIN_IES_SMT_SPEC(66, 71, 0xb60, 2),
+        MTK_PIN_IES_SMT_SPEC(72, 74, 0xb50, 12),
+        MTK_PIN_IES_SMT_SPEC(75, 76, 0xb60, 3),
+        MTK_PIN_IES_SMT_SPEC(77, 78, 0xb60, 4),
+        MTK_PIN_IES_SMT_SPEC(79, 82, 0xb60, 5),
+        MTK_PIN_IES_SMT_SPEC(83, 84, 0xb60, 2),
+        MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 11),
+        MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 11),
+        MTK_PIN_IES_SMT_SPEC(87, 87, 0xdc0, 3),
+        MTK_PIN_IES_SMT_SPEC(88, 88, 0xdc0, 7),
+        MTK_PIN_IES_SMT_SPEC(89, 89, 0xdc0, 11),
+        MTK_PIN_IES_SMT_SPEC(90, 90, 0xdc0, 15),
+        MTK_PIN_IES_SMT_SPEC(101, 104, 0xb60, 6),
+        MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 11),
+        MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 11),
+        MTK_PIN_IES_SMT_SPEC(107, 107, 0xd60, 3),
+        MTK_PIN_IES_SMT_SPEC(108, 108, 0xd60, 7),
+        MTK_PIN_IES_SMT_SPEC(109, 109, 0xd60, 11),
+        MTK_PIN_IES_SMT_SPEC(110, 110, 0xd60, 15),
+        MTK_PIN_IES_SMT_SPEC(111, 111, 0xd00, 15),
+        MTK_PIN_IES_SMT_SPEC(112, 112, 0xd00, 11),
+        MTK_PIN_IES_SMT_SPEC(113, 113, 0xd00, 7),
+        MTK_PIN_IES_SMT_SPEC(114, 114, 0xd00, 3),
+        MTK_PIN_IES_SMT_SPEC(115, 115, 0xd10, 3),
+        MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 11),
+        MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 11),
+        MTK_PIN_IES_SMT_SPEC(118, 118, 0xcf0, 15),
+        MTK_PIN_IES_SMT_SPEC(119, 119, 0xcf0, 11),
+        MTK_PIN_IES_SMT_SPEC(120, 120, 0xcf0, 7),
+        MTK_PIN_IES_SMT_SPEC(121, 121, 0xcf0, 3),
+        MTK_PIN_IES_SMT_SPEC(122, 125, 0xb60, 7),
+        MTK_PIN_IES_SMT_SPEC(126, 126, 0xb50, 12),
+        MTK_PIN_IES_SMT_SPEC(127, 142, 0xb60, 9),
+        MTK_PIN_IES_SMT_SPEC(143, 160, 0xb60, 10),
+        MTK_PIN_IES_SMT_SPEC(161, 168, 0xb60, 12),
+        MTK_PIN_IES_SMT_SPEC(169, 183, 0xb60, 10),
+        MTK_PIN_IES_SMT_SPEC(184, 186, 0xb60, 9),
+        MTK_PIN_IES_SMT_SPEC(187, 187, 0xb60, 14),
+        MTK_PIN_IES_SMT_SPEC(188, 188, 0xb50, 13),
+        MTK_PIN_IES_SMT_SPEC(189, 193, 0xb60, 15),
+        MTK_PIN_IES_SMT_SPEC(194, 198, 0xb70, 0),
+        MTK_PIN_IES_SMT_SPEC(199, 199, 0xb50, 1),
+        MTK_PIN_IES_SMT_SPEC(200, 202, 0xb70, 1),
+        MTK_PIN_IES_SMT_SPEC(203, 207, 0xb70, 2),
+        MTK_PIN_IES_SMT_SPEC(208, 209, 0xb70, 3),
+        MTK_PIN_IES_SMT_SPEC(210, 210, 0xb70, 4),
+        MTK_PIN_IES_SMT_SPEC(211, 235, 0xb70, 5),
+        MTK_PIN_IES_SMT_SPEC(236, 241, 0xb70, 6),
+        MTK_PIN_IES_SMT_SPEC(242, 243, 0xb70, 7),
+        MTK_PIN_IES_SMT_SPEC(244, 247, 0xb70, 8),
+        MTK_PIN_IES_SMT_SPEC(248, 248, 0xb70, 9),
+        MTK_PIN_IES_SMT_SPEC(249, 249, 0x140, 3),
+        MTK_PIN_IES_SMT_SPEC(250, 250, 0x130, 15),
+        MTK_PIN_IES_SMT_SPEC(251, 251, 0x130, 11),
+        MTK_PIN_IES_SMT_SPEC(252, 252, 0x130, 7),
+        MTK_PIN_IES_SMT_SPEC(253, 253, 0x130, 3),
+        MTK_PIN_IES_SMT_SPEC(254, 254, 0xf40, 15),
+        MTK_PIN_IES_SMT_SPEC(255, 255, 0xf40, 11),
+        MTK_PIN_IES_SMT_SPEC(256, 256, 0xf40, 7),
+        MTK_PIN_IES_SMT_SPEC(257, 257, 0xf40, 3),
+        MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 11),
+        MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 11),
+        MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 11),
+        MTK_PIN_IES_SMT_SPEC(261, 261, 0x0b0, 3),
+        MTK_PIN_IES_SMT_SPEC(262, 277, 0xb70, 12),
+        MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
+};
+
+static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
+                unsigned char align, int value, enum pin_config_param arg)
+{
+        if (arg == PIN_CONFIG_INPUT_ENABLE)
+                return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
+                        ARRAY_SIZE(mt2701_ies_set), pin, align, value);
+        else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+                return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
+                        ARRAY_SIZE(mt2701_smt_set), pin, align, value);
+        return -EINVAL;
+}
+
+static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
+        MTK_PINMUX_SPEC(22, 0xb10, 3),
+        MTK_PINMUX_SPEC(23, 0xb10, 4),
+        MTK_PINMUX_SPEC(24, 0xb10, 5),
+        MTK_PINMUX_SPEC(29, 0xb10, 9),
+        MTK_PINMUX_SPEC(208, 0xb10, 7),
+        MTK_PINMUX_SPEC(209, 0xb10, 8),
+        MTK_PINMUX_SPEC(203, 0xf20, 0),
+        MTK_PINMUX_SPEC(204, 0xf20, 1),
+        MTK_PINMUX_SPEC(249, 0xef0, 0),
+        MTK_PINMUX_SPEC(250, 0xef0, 0),
+        MTK_PINMUX_SPEC(251, 0xef0, 0),
+        MTK_PINMUX_SPEC(252, 0xef0, 0),
+        MTK_PINMUX_SPEC(253, 0xef0, 0),
+        MTK_PINMUX_SPEC(254, 0xef0, 0),
+        MTK_PINMUX_SPEC(255, 0xef0, 0),
+        MTK_PINMUX_SPEC(256, 0xef0, 0),
+        MTK_PINMUX_SPEC(257, 0xef0, 0),
+        MTK_PINMUX_SPEC(258, 0xef0, 0),
+        MTK_PINMUX_SPEC(259, 0xef0, 0),
+        MTK_PINMUX_SPEC(260, 0xef0, 0),
+};
+
+static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin,
+                        unsigned int mode)
+{
+        unsigned int i, value, mask;
+        unsigned int info_num = ARRAY_SIZE(mt2701_spec_pinmux);
+        unsigned int spec_flag;
+
+        for (i = 0; i < info_num; i++) {
+                if (pin == mt2701_spec_pinmux[i].pin)
+                        break;
+        }
+
+        if (i == info_num)
+                return;
+
+        spec_flag = (mode >> 3);
+        mask = BIT(mt2701_spec_pinmux[i].bit);
+        if (!spec_flag)
+                value = mask;
+        else
+                value = 0;
+        regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
+}
+
+static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
+{
+        if (pin > 175)
+                *reg_addr += 0x10;
+}
+
+static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
+        .pins = mtk_pins_mt2701,
+        .npins = ARRAY_SIZE(mtk_pins_mt2701),
+        .grp_desc = mt2701_drv_grp,
+        .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
+        .pin_drv_grp = mt2701_pin_drv,
+        .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
+        .spec_pull_set = mt2701_spec_pull_set,
+        .spec_ies_smt_set = mt2701_ies_smt_set,
+        .spec_pinmux_set = mt2701_spec_pinmux_set,
+        .spec_dir_set = mt2701_spec_dir_set,
+        .dir_offset = 0x0000,
+        .pullen_offset = 0x0150,
+        .pullsel_offset = 0x0280,
+        .dout_offset = 0x0500,
+        .din_offset = 0x0630,
+        .pinmux_offset = 0x0760,
+        .type1_start = 280,
+        .type1_end = 280,
+        .port_shf = 4,
+        .port_mask = 0x1f,
+        .port_align = 4,
+        .eint_offsets = {
+                .name = "mt2701_eint",
+                .stat      = 0x000,
+                .ack       = 0x040,
+                .mask      = 0x080,
+                .mask_set  = 0x0c0,
+                .mask_clr  = 0x100,
+                .sens      = 0x140,
+                .sens_set  = 0x180,
+                .sens_clr  = 0x1c0,
+                .soft      = 0x200,
+                .soft_set  = 0x240,
+                .soft_clr  = 0x280,
+                .pol       = 0x300,
+                .pol_set   = 0x340,
+                .pol_clr   = 0x380,
+                .dom_en    = 0x400,
+                .dbnc_ctrl = 0x500,
+                .dbnc_set  = 0x600,
+                .dbnc_clr  = 0x700,
+                .port_mask = 6,
+                .ports     = 6,
+        },
+        .ap_num = 169,
+        .db_cnt = 16,
+};
+
+static int mt2701_pinctrl_probe(struct platform_device *pdev)
+{
+        return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt2701_pctrl_match[] = {
+        { .compatible = "mediatek,mt2701-pinctrl", },
+        {}
+};
+MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
+
+static struct platform_driver mtk_pinctrl_driver = {
+        .probe = mt2701_pinctrl_probe,
+        .driver = {
+                .name = "mediatek-mt2701-pinctrl",
+                .of_match_table = mt2701_pctrl_match,
+                .pm = &mtk_eint_pm_ops,
+        },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+        return platform_driver_register(&mtk_pinctrl_driver);
+}
+arch_initcall(mtk_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c
index f9751ae28e32..6eccb85c02cd 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c
@@ -12,7 +12,7 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/module.h>
+#include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
@@ -55,7 +55,6 @@ static const struct of_device_id mt6397_pctrl_match[] = {
         { .compatible = "mediatek,mt6397-pinctrl", },
         { }
 };
-MODULE_DEVICE_TABLE(of, mt6397_pctrl_match);
 
 static struct platform_driver mtk_pinctrl_driver = {
         .probe = mt6397_pinctrl_probe,
@@ -69,9 +68,4 @@ static int __init mtk_pinctrl_init(void)
 {
         return platform_driver_register(&mtk_pinctrl_driver);
 }
-
-module_init(mtk_pinctrl_init);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver");
-MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
+device_initcall(mtk_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
new file mode 100644
index 000000000000..67895f8234e3
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2016 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt7623.h"
+
+static const struct mtk_drv_group_desc mt7623_drv_grp[] =  {
+        /* 0E4E8SR 4/8/12/16 */
+        MTK_DRV_GRP(4, 16, 1, 2, 4),
+        /* 0E2E4SR  2/4/6/8 */
+        MTK_DRV_GRP(2, 8, 1, 2, 2),
+        /* E8E4E2  2/4/6/8/10/12/14/16 */
+        MTK_DRV_GRP(2, 16, 0, 2, 2)
+};
+
+#define DRV_SEL0        0xf50
+#define DRV_SEL1        0xf60
+#define DRV_SEL2        0xf70
+#define DRV_SEL3        0xf80
+#define DRV_SEL4        0xf90
+#define DRV_SEL5        0xfa0
+#define DRV_SEL6        0xfb0
+#define DRV_SEL7        0xfe0
+#define DRV_SEL8        0xfd0
+#define DRV_SEL9        0xff0
+#define DRV_SEL10       0xf00
+
+#define MSDC0_CTRL0     0xcc0
+#define MSDC0_CTRL1     0xcd0
+#define MSDC0_CTRL2     0xce0
+#define MSDC0_CTRL3     0xcf0
+#define MSDC0_CTRL4     0xd00
+#define MSDC0_CTRL5     0xd10
+#define MSDC0_CTRL6     0xd20
+#define MSDC1_CTRL0     0xd30
+#define MSDC1_CTRL1     0xd40
+#define MSDC1_CTRL2     0xd50
+#define MSDC1_CTRL3     0xd60
+#define MSDC1_CTRL4     0xd70
+#define MSDC1_CTRL5     0xd80
+#define MSDC1_CTRL6     0xd90
+
+#define IES_EN0         0xb20
+#define IES_EN1         0xb30
+#define IES_EN2         0xb40
+
+#define SMT_EN0         0xb50
+#define SMT_EN1         0xb60
+#define SMT_EN2         0xb70
+
+static const struct mtk_pin_drv_grp mt7623_pin_drv[] = {
+        MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1),
+        MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1),
+        MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1),
+        MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1),
+        MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1),
+        MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1),
+        MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1),
+        MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1),
+        MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1),
+        MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1),
+        MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1),
+        MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1),
+        MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1),
+        MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1),
+        MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0),
+        MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0),
+        MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0),
+        MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0),
+        MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0),
+        MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0),
+        MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0),
+        MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0),
+        MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0),
+        MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0),
+        MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0),
+        MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0),
+        MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0),
+        MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0),
+        MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0),
+        MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0),
+        MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0),
+        MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0),
+        MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0),
+        MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1),
+        MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1),
+        MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1),
+        MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1),
+        MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0),
+        MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0),
+        MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0),
+        MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0),
+        MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0),
+        MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0),
+        MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0),
+        MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0),
+        MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0),
+        MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0),
+        MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1),
+        MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1),
+        MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1),
+        MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1),
+        MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1),
+        MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1),
+        MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1),
+        MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1),
+        MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1),
+        MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1),
+        MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1),
+        MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1),
+        MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0),
+        MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0),
+        MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0),
+        MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1),
+        MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1),
+        MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1),
+        MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1),
+        MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1),
+        MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1),
+        MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0),
+        MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1),
+        MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0),
+        MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0),
+        MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0),
+        MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0),
+        MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0),
+        MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0),
+        MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0),
+        MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0),
+        MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0),
+        MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0),
+        MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0),
+        MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0),
+        MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0),
+        MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0),
+        MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0),
+        MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0),
+        MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0),
+        MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1),
+        MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(265, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(266, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(267, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(268, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(269, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(270, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(271, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(272, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(274, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(275, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(276, DRV_SEL10, 8, 0),
+        MTK_PIN_DRV_GRP(278, DRV_SEL2, 8, 1),
+};
+
+static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = {
+        MTK_PIN_PUPD_SPEC_SR(105, MSDC1_CTRL1, 8, 9, 10),
+        MTK_PIN_PUPD_SPEC_SR(106, MSDC1_CTRL0, 8, 9, 10),
+        MTK_PIN_PUPD_SPEC_SR(107, MSDC1_CTRL3, 0, 1, 2),
+        MTK_PIN_PUPD_SPEC_SR(108, MSDC1_CTRL3, 4, 5, 6),
+        MTK_PIN_PUPD_SPEC_SR(109, MSDC1_CTRL3, 8, 9, 10),
+        MTK_PIN_PUPD_SPEC_SR(110, MSDC1_CTRL3, 12, 13, 14),
+        MTK_PIN_PUPD_SPEC_SR(111, MSDC0_CTRL4, 12, 13, 14),
+        MTK_PIN_PUPD_SPEC_SR(112, MSDC0_CTRL4, 8, 9, 10),
+        MTK_PIN_PUPD_SPEC_SR(113, MSDC0_CTRL4, 4, 5, 6),
+        MTK_PIN_PUPD_SPEC_SR(114, MSDC0_CTRL4, 0, 1, 2),
+        MTK_PIN_PUPD_SPEC_SR(115, MSDC0_CTRL5, 0, 1, 2),
+        MTK_PIN_PUPD_SPEC_SR(116, MSDC0_CTRL1, 8, 9, 10),
+        MTK_PIN_PUPD_SPEC_SR(117, MSDC0_CTRL0, 8, 9, 10),
+        MTK_PIN_PUPD_SPEC_SR(118, MSDC0_CTRL3, 12, 13, 14),
+        MTK_PIN_PUPD_SPEC_SR(119, MSDC0_CTRL3, 8, 9, 10),
+        MTK_PIN_PUPD_SPEC_SR(120, MSDC0_CTRL3, 4, 5, 6),
+        MTK_PIN_PUPD_SPEC_SR(121, MSDC0_CTRL3, 0, 1, 2),
+};
+
+static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin,
+                unsigned char align, bool isup, unsigned int r1r0)
+{
+        return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd,
+                ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0);
+}
+
+static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = {
+        MTK_PIN_IES_SMT_SPEC(0, 6, IES_EN0, 0),
+        MTK_PIN_IES_SMT_SPEC(7, 9, IES_EN0, 1),
+        MTK_PIN_IES_SMT_SPEC(10, 13, IES_EN0, 2),
+        MTK_PIN_IES_SMT_SPEC(14, 15, IES_EN0, 3),
+        MTK_PIN_IES_SMT_SPEC(18, 21, IES_EN0, 5),
+        MTK_PIN_IES_SMT_SPEC(22, 26, IES_EN0, 6),
+        MTK_PIN_IES_SMT_SPEC(27, 29, IES_EN0, 7),
+        MTK_PIN_IES_SMT_SPEC(33, 37, IES_EN0, 8),
+        MTK_PIN_IES_SMT_SPEC(39, 42, IES_EN0, 9),
+        MTK_PIN_IES_SMT_SPEC(43, 45, IES_EN0, 10),
+        MTK_PIN_IES_SMT_SPEC(47, 48, IES_EN0, 11),
+        MTK_PIN_IES_SMT_SPEC(49, 49, IES_EN0, 12),
+        MTK_PIN_IES_SMT_SPEC(53, 56, IES_EN0, 14),
+        MTK_PIN_IES_SMT_SPEC(60, 62, IES_EN1, 0),
+        MTK_PIN_IES_SMT_SPEC(63, 65, IES_EN1, 1),
+        MTK_PIN_IES_SMT_SPEC(66, 71, IES_EN1, 2),
+        MTK_PIN_IES_SMT_SPEC(72, 74, IES_EN0, 12),
+        MTK_PIN_IES_SMT_SPEC(75, 76, IES_EN1, 3),
+        MTK_PIN_IES_SMT_SPEC(83, 84, IES_EN1, 2),
+        MTK_PIN_IES_SMT_SPEC(105, 121, MSDC1_CTRL1, 4),
+        MTK_PIN_IES_SMT_SPEC(122, 125, IES_EN1, 7),
+        MTK_PIN_IES_SMT_SPEC(126, 126, IES_EN0, 12),
+        MTK_PIN_IES_SMT_SPEC(199, 201, IES_EN0, 1),
+        MTK_PIN_IES_SMT_SPEC(203, 207, IES_EN2, 2),
+        MTK_PIN_IES_SMT_SPEC(208, 209, IES_EN2, 3),
+        MTK_PIN_IES_SMT_SPEC(236, 241, IES_EN2, 6),
+        MTK_PIN_IES_SMT_SPEC(242, 243, IES_EN2, 7),
+        MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL2, 4),
+        MTK_PIN_IES_SMT_SPEC(262, 272, IES_EN2, 12),
+        MTK_PIN_IES_SMT_SPEC(274, 276, IES_EN2, 12),
+        MTK_PIN_IES_SMT_SPEC(278, 278, IES_EN2, 13),
+};
+
+static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = {
+        MTK_PIN_IES_SMT_SPEC(0, 6, SMT_EN0, 0),
+        MTK_PIN_IES_SMT_SPEC(7, 9, SMT_EN0, 1),
+        MTK_PIN_IES_SMT_SPEC(10, 13, SMT_EN0, 2),
+        MTK_PIN_IES_SMT_SPEC(14, 15, SMT_EN0, 3),
+        MTK_PIN_IES_SMT_SPEC(18, 21, SMT_EN0, 5),
+        MTK_PIN_IES_SMT_SPEC(22, 26, SMT_EN0, 6),
+        MTK_PIN_IES_SMT_SPEC(27, 29, SMT_EN0, 7),
+        MTK_PIN_IES_SMT_SPEC(33, 37, SMT_EN0, 8),
+        MTK_PIN_IES_SMT_SPEC(39, 42, SMT_EN0, 9),
+        MTK_PIN_IES_SMT_SPEC(43, 45, SMT_EN0, 10),
+        MTK_PIN_IES_SMT_SPEC(47, 48, SMT_EN0, 11),
+        MTK_PIN_IES_SMT_SPEC(49, 49, SMT_EN0, 12),
+        MTK_PIN_IES_SMT_SPEC(53, 56, SMT_EN0, 14),
+        MTK_PIN_IES_SMT_SPEC(60, 62, SMT_EN1, 0),
+        MTK_PIN_IES_SMT_SPEC(63, 65, SMT_EN1, 1),
+        MTK_PIN_IES_SMT_SPEC(66, 71, SMT_EN1, 2),
+        MTK_PIN_IES_SMT_SPEC(72, 74, SMT_EN0, 12),
+        MTK_PIN_IES_SMT_SPEC(75, 76, SMT_EN1, 3),
+        MTK_PIN_IES_SMT_SPEC(83, 84, SMT_EN1, 2),
+        MTK_PIN_IES_SMT_SPEC(105, 106, MSDC1_CTRL1, 11),
+        MTK_PIN_IES_SMT_SPEC(107, 107, MSDC1_CTRL3, 3),
+        MTK_PIN_IES_SMT_SPEC(108, 108, MSDC1_CTRL3, 7),
+        MTK_PIN_IES_SMT_SPEC(109, 109, MSDC1_CTRL3, 11),
+        MTK_PIN_IES_SMT_SPEC(110, 111, MSDC1_CTRL3, 15),
+        MTK_PIN_IES_SMT_SPEC(112, 112, MSDC0_CTRL4, 11),
+        MTK_PIN_IES_SMT_SPEC(113, 113, MSDC0_CTRL4, 7),
+        MTK_PIN_IES_SMT_SPEC(114, 115, MSDC0_CTRL4, 3),
+        MTK_PIN_IES_SMT_SPEC(116, 117, MSDC0_CTRL1, 11),
+        MTK_PIN_IES_SMT_SPEC(118, 118, MSDC0_CTRL3, 15),
+        MTK_PIN_IES_SMT_SPEC(119, 119, MSDC0_CTRL3, 11),
+        MTK_PIN_IES_SMT_SPEC(120, 120, MSDC0_CTRL3, 7),
+        MTK_PIN_IES_SMT_SPEC(121, 121, MSDC0_CTRL3, 3),
+        MTK_PIN_IES_SMT_SPEC(122, 125, SMT_EN1, 7),
+        MTK_PIN_IES_SMT_SPEC(126, 126, SMT_EN0, 12),
+        MTK_PIN_IES_SMT_SPEC(199, 201, SMT_EN0, 1),
+        MTK_PIN_IES_SMT_SPEC(203, 207, SMT_EN2, 2),
+        MTK_PIN_IES_SMT_SPEC(208, 209, SMT_EN2, 3),
+        MTK_PIN_IES_SMT_SPEC(236, 241, SMT_EN2, 6),
+        MTK_PIN_IES_SMT_SPEC(242, 243, SMT_EN2, 7),
+        MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL6, 3),
+        MTK_PIN_IES_SMT_SPEC(262, 272, SMT_EN2, 12),
+        MTK_PIN_IES_SMT_SPEC(274, 276, SMT_EN2, 12),
+        MTK_PIN_IES_SMT_SPEC(278, 278, SMT_EN2, 13),
+};
+
+static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin,
+                unsigned char align, int value, enum pin_config_param arg)
+{
+        if (arg == PIN_CONFIG_INPUT_ENABLE)
+                return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set,
+                        ARRAY_SIZE(mt7623_ies_set), pin, align, value);
+        else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+                return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set,
+                        ARRAY_SIZE(mt7623_smt_set), pin, align, value);
+        return -EINVAL;
+}
+
+static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = {
+        .pins = mtk_pins_mt7623,
+        .npins = ARRAY_SIZE(mtk_pins_mt7623),
+        .grp_desc = mt7623_drv_grp,
+        .n_grp_cls = ARRAY_SIZE(mt7623_drv_grp),
+        .pin_drv_grp = mt7623_pin_drv,
+        .n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv),
+        .spec_pull_set = mt7623_spec_pull_set,
+        .spec_ies_smt_set = mt7623_ies_smt_set,
+        .dir_offset = 0x0000,
+        .pullen_offset = 0x0150,
+        .pullsel_offset = 0x0280,
+        .dout_offset = 0x0500,
+        .din_offset = 0x0630,
+        .pinmux_offset = 0x0760,
+        .type1_start = 280,
+        .type1_end = 280,
+        .port_shf = 4,
+        .port_mask = 0x1f,
+        .port_align = 4,
+        .eint_offsets = {
+                .name = "mt7623_eint",
+                .stat      = 0x000,
+                .ack       = 0x040,
+                .mask      = 0x080,
+                .mask_set  = 0x0c0,
+                .mask_clr  = 0x100,
+                .sens      = 0x140,
+                .sens_set  = 0x180,
+                .sens_clr  = 0x1c0,
+                .soft      = 0x200,
+                .soft_set  = 0x240,
+                .soft_clr  = 0x280,
+                .pol       = 0x300,
+                .pol_set   = 0x340,
+                .pol_clr   = 0x380,
+                .dom_en    = 0x400,
+                .dbnc_ctrl = 0x500,
+                .dbnc_set  = 0x600,
+                .dbnc_clr  = 0x700,
+                .port_mask = 6,
+                .ports     = 6,
+        },
+        .ap_num = 169,
+        .db_cnt = 16,
+};
+
+static int mt7623_pinctrl_probe(struct platform_device *pdev)
+{
+        return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt7623_pctrl_match[] = {
+        { .compatible = "mediatek,mt7623-pinctrl", },
+        {}
+};
+MODULE_DEVICE_TABLE(of, mt7623_pctrl_match);
+
+static struct platform_driver mtk_pinctrl_driver = {
+        .probe = mt7623_pinctrl_probe,
+        .driver = {
+                .name = "mediatek-mt7623-pinctrl",
+                .of_match_table = mt7623_pctrl_match,
+        },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+        return platform_driver_register(&mtk_pinctrl_driver);
+}
+
+arch_initcall(mtk_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c
index 98e0bebfdf92..d76491574841 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c
@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/module.h>
+#include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
@@ -336,7 +336,6 @@ static const struct of_device_id mt8127_pctrl_match[] = {
         { .compatible = "mediatek,mt8127-pinctrl", },
         { }
 };
-MODULE_DEVICE_TABLE(of, mt8127_pctrl_match);
 
 static struct platform_driver mtk_pinctrl_driver = {
         .probe = mt8127_pinctrl_probe,
@@ -350,9 +349,4 @@ static int __init mtk_pinctrl_init(void)
 {
         return platform_driver_register(&mtk_pinctrl_driver);
 }
-
 arch_initcall(mtk_pinctrl_init);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver");
-MODULE_AUTHOR("Yingjoe Chen <yingjoe.chen@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
index 1c153b860f36..d8c645f16f21 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
@@ -12,7 +12,7 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/module.h>
+#include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
@@ -351,7 +351,6 @@ static const struct of_device_id mt8135_pctrl_match[] = {
         },
         { }
 };
-MODULE_DEVICE_TABLE(of, mt8135_pctrl_match);
 
 static struct platform_driver mtk_pinctrl_driver = {
         .probe = mt8135_pinctrl_probe,
@@ -365,9 +364,4 @@ static int __init mtk_pinctrl_init(void)
 {
         return platform_driver_register(&mtk_pinctrl_driver);
 }
-
 arch_initcall(mtk_pinctrl_init);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
-MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
index a62514eb2129..8bfd427b9135 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
@@ -12,7 +12,7 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/module.h>
+#include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
@@ -378,7 +378,6 @@ static const struct of_device_id mt8173_pctrl_match[] = {
         },
         { }
 };
-MODULE_DEVICE_TABLE(of, mt8173_pctrl_match);
 
 static struct platform_driver mtk_pinctrl_driver = {
         .probe = mt8173_pinctrl_probe,
@@ -393,9 +392,4 @@ static int __init mtk_pinctrl_init(void)
 {
         return platform_driver_register(&mtk_pinctrl_driver);
 }
-
 arch_initcall(mtk_pinctrl_init);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
-MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index e96e86d2e745..2bbe6f7964a7 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -43,10 +43,13 @@
 
 #define MAX_GPIO_MODE_PER_REG 5
 #define GPIO_MODE_BITS        3
+#define GPIO_MODE_PREFIX "GPIO"
 
 static const char * const mtk_gpio_functions[] = {
         "func0", "func1", "func2", "func3",
         "func4", "func5", "func6", "func7",
+        "func8", "func9", "func10", "func11",
+        "func12", "func13", "func14", "func15",
 };
 
 /*
@@ -81,6 +84,9 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
         reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
         bit = BIT(offset & 0xf);
 
+        if (pctl->devdata->spec_dir_set)
+                pctl->devdata->spec_dir_set(&reg_addr, offset);
+
         if (input)
                 /* Different SoC has different alignment offset. */
                 reg_addr = CLR_ADDR(reg_addr, pctl);
@@ -677,9 +683,14 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
         unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
         struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 
+        if (pctl->devdata->spec_pinmux_set)
+                pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
+                                        pin, mode);
+
         reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
                         + pctl->devdata->pinmux_offset;
 
+        mode &= mask;
         bit = pin % MAX_GPIO_MODE_PER_REG;
         mask <<= (GPIO_MODE_BITS * bit);
         val = (mode << (GPIO_MODE_BITS * bit));
@@ -725,12 +736,48 @@ static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
         return 0;
 }
 
+static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
+                                unsigned offset)
+{
+        const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
+        const struct mtk_desc_function *func = pin->functions;
+
+        while (func && func->name) {
+                if (!strncmp(func->name, GPIO_MODE_PREFIX,
+                        sizeof(GPIO_MODE_PREFIX)-1))
+                        return func->muxval;
+                func++;
+        }
+        return -EINVAL;
+}
+
+static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
+                                    struct pinctrl_gpio_range *range,
+                                    unsigned offset)
+{
+        int muxval;
+        struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        muxval = mtk_pmx_find_gpio_mode(pctl, offset);
+
+        if (muxval < 0) {
+                dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
+                return -EINVAL;
+        }
+
+        mtk_pmx_set_mode(pctldev, offset, muxval);
+        mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
+
+        return 0;
+}
+
 static const struct pinmux_ops mtk_pmx_ops = {
         .get_functions_count    = mtk_pmx_get_funcs_cnt,
         .get_function_name      = mtk_pmx_get_func_name,
         .get_function_groups    = mtk_pmx_get_func_groups,
         .set_mux                = mtk_pmx_set_mux,
         .gpio_set_direction     = mtk_pmx_gpio_set_direction,
+        .gpio_request_enable    = mtk_pmx_gpio_request_enable,
 };
 
 static int mtk_gpio_direction_input(struct gpio_chip *chip,
@@ -756,6 +803,10 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 
         reg_addr =  mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
         bit = BIT(offset & 0xf);
+
+        if (pctl->devdata->spec_dir_set)
+                pctl->devdata->spec_dir_set(&reg_addr, offset);
+
         regmap_read(pctl->regmap1, reg_addr, &read_val);
         return !(read_val & bit);
 }
@@ -814,6 +865,10 @@ static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
 
         /* set mux to INT mode */
         mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
+        /* set gpio direction to input */
+        mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, true);
+        /* set input-enable */
+        mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, PIN_CONFIG_INPUT_ENABLE);
 
         return 0;
 }
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 55a534338931..8543bc478a1e 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -209,7 +209,14 @@ struct mtk_eint_offsets {
  * means when user set smt, input enable is set at the same time. So they
  * also need special control. If special control is success, this should
  * return 0, otherwise return non-zero value.
- *
+ * @spec_pinmux_set: In some cases, there are two pinmux functions share
+ * the same value in the same segment of pinmux control register. If user
+ * want to use one of the two functions, they need an extra bit setting to
+ * select the right one.
+ * @spec_dir_set: In very few SoCs, direction control registers are not
+ * arranged continuously, they may be cut to parts. So they need special
+ * dir setting.
+
  * @dir_offset: The direction register offset.
  * @pullen_offset: The pull-up/pull-down enable register offset.
  * @pinmux_offset: The pinmux register offset.
@@ -234,6 +241,9 @@ struct mtk_pinctrl_devdata {
                         unsigned char align, bool isup, unsigned int arg);
         int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
                         unsigned char align, int value, enum pin_config_param arg);
+        void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
+                        unsigned int mode);
+        void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
         unsigned int dir_offset;
         unsigned int ies_offset;
         unsigned int smt_offset;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
new file mode 100644
index 000000000000..f90642078c31
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
@@ -0,0 +1,2323 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Biao Huang <biao.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_MT2701_H
+#define __PINCTRL_MTK_MT2701_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt2701[] = {
+        MTK_PIN(
+                PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 148),
+                MTK_FUNCTION(0, "GPIO0"),
+                MTK_FUNCTION(1, "PWRAP_SPIDO"),
+                MTK_FUNCTION(2, "PWRAP_SPIDI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 149),
+                MTK_FUNCTION(0, "GPIO1"),
+                MTK_FUNCTION(1, "PWRAP_SPIDI"),
+                MTK_FUNCTION(2, "PWRAP_SPIDO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(2, "PWRAP_INT"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 150),
+                MTK_FUNCTION(0, "GPIO2"),
+                MTK_FUNCTION(1, "PWRAP_INT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 151),
+                MTK_FUNCTION(0, "GPIO3"),
+                MTK_FUNCTION(1, "PWRAP_SPICK_I")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 152),
+                MTK_FUNCTION(0, "GPIO4"),
+                MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 153),
+                MTK_FUNCTION(0, "GPIO5"),
+                MTK_FUNCTION(1, "PWRAP_SPICK2_I"),
+                MTK_FUNCTION(5, "ANT_SEL1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 154),
+                MTK_FUNCTION(0, "GPIO6"),
+                MTK_FUNCTION(1, "PWRAP_SPICS2_B_I"),
+                MTK_FUNCTION(5, "ANT_SEL0"),
+                MTK_FUNCTION(7, "DBG_MON_A[0]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(7, "SPI1_CSN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 155),
+                MTK_FUNCTION(0, "GPIO7"),
+                MTK_FUNCTION(1, "SPI1_CS"),
+                MTK_FUNCTION(4, "KCOL0"),
+                MTK_FUNCTION(7, "DBG_MON_B[12]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(8, "SPI1_MI"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 156),
+                MTK_FUNCTION(0, "GPIO8"),
+                MTK_FUNCTION(1, "SPI1_MI"),
+                MTK_FUNCTION(2, "SPI1_MO"),
+                MTK_FUNCTION(4, "KCOL1"),
+                MTK_FUNCTION(7, "DBG_MON_B[13]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(9, "SPI1_MO"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 157),
+                MTK_FUNCTION(0, "GPIO9"),
+                MTK_FUNCTION(1, "SPI1_MO"),
+                MTK_FUNCTION(2, "SPI1_MI"),
+                MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+                MTK_FUNCTION(4, "KCOL2"),
+                MTK_FUNCTION(7, "DBG_MON_B[14]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(10, "RTC32K_CK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 158),
+                MTK_FUNCTION(0, "GPIO10"),
+                MTK_FUNCTION(1, "RTC32K_CK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(11, "WATCHDOG"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 159),
+                MTK_FUNCTION(0, "GPIO11"),
+                MTK_FUNCTION(1, "WATCHDOG")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(12, "SRCLKENA"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 160),
+                MTK_FUNCTION(0, "GPIO12"),
+                MTK_FUNCTION(1, "SRCLKENA")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(13, "SRCLKENAI"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 161),
+                MTK_FUNCTION(0, "GPIO13"),
+                MTK_FUNCTION(1, "SRCLKENAI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(14, "URXD2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 162),
+                MTK_FUNCTION(0, "GPIO14"),
+                MTK_FUNCTION(1, "URXD2"),
+                MTK_FUNCTION(2, "UTXD2"),
+                MTK_FUNCTION(5, "SRCCLKENAI2"),
+                MTK_FUNCTION(7, "DBG_MON_B[30]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(15, "UTXD2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 163),
+                MTK_FUNCTION(0, "GPIO15"),
+                MTK_FUNCTION(1, "UTXD2"),
+                MTK_FUNCTION(2, "URXD2"),
+                MTK_FUNCTION(7, "DBG_MON_B[31]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(16, "I2S5_DATA_IN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 164),
+                MTK_FUNCTION(0, "GPIO16"),
+                MTK_FUNCTION(1, "I2S5_DATA_IN"),
+                MTK_FUNCTION(3, "PCM_RX"),
+                MTK_FUNCTION(4, "ANT_SEL4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(17, "I2S5_BCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 165),
+                MTK_FUNCTION(0, "GPIO17"),
+                MTK_FUNCTION(1, "I2S5_BCK"),
+                MTK_FUNCTION(3, "PCM_CLK0"),
+                MTK_FUNCTION(4, "ANT_SEL2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(18, "PCM_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 166),
+                MTK_FUNCTION(0, "GPIO18"),
+                MTK_FUNCTION(1, "PCM_CLK0"),
+                MTK_FUNCTION(2, "MRG_CLK"),
+                MTK_FUNCTION(4, "MM_TEST_CK"),
+                MTK_FUNCTION(5, "CONN_DSP_JCK"),
+                MTK_FUNCTION(6, "WCN_PCM_CLKO"),
+                MTK_FUNCTION(7, "DBG_MON_A[3]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(19, "PCM_SYNC"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 167),
+                MTK_FUNCTION(0, "GPIO19"),
+                MTK_FUNCTION(1, "PCM_SYNC"),
+                MTK_FUNCTION(2, "MRG_SYNC"),
+                MTK_FUNCTION(5, "CONN_DSP_JINTP"),
+                MTK_FUNCTION(6, "WCN_PCM_SYNC"),
+                MTK_FUNCTION(7, "DBG_MON_A[5]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(20, "PCM_RX"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO20"),
+                MTK_FUNCTION(1, "PCM_RX"),
+                MTK_FUNCTION(2, "MRG_RX"),
+                MTK_FUNCTION(3, "MRG_TX"),
+                MTK_FUNCTION(4, "PCM_TX"),
+                MTK_FUNCTION(5, "CONN_DSP_JDI"),
+                MTK_FUNCTION(6, "WCN_PCM_RX"),
+                MTK_FUNCTION(7, "DBG_MON_A[4]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(21, "PCM_TX"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO21"),
+                MTK_FUNCTION(1, "PCM_TX"),
+                MTK_FUNCTION(2, "MRG_TX"),
+                MTK_FUNCTION(3, "MRG_RX"),
+                MTK_FUNCTION(4, "PCM_RX"),
+                MTK_FUNCTION(5, "CONN_DSP_JMS"),
+                MTK_FUNCTION(6, "WCN_PCM_TX"),
+                MTK_FUNCTION(7, "DBG_MON_A[2]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(22, "EINT0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 0),
+                MTK_FUNCTION(0, "GPIO22"),
+                MTK_FUNCTION(1, "UCTS0"),
+                MTK_FUNCTION(3, "KCOL3"),
+                MTK_FUNCTION(4, "CONN_DSP_JDO"),
+                MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+                MTK_FUNCTION(7, "DBG_MON_A[30]"),
+                MTK_FUNCTION(10, "PCIE0_PERST_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(23, "EINT1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 1),
+                MTK_FUNCTION(0, "GPIO23"),
+                MTK_FUNCTION(1, "URTS0"),
+                MTK_FUNCTION(3, "KCOL2"),
+                MTK_FUNCTION(4, "CONN_MCU_TDO"),
+                MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+                MTK_FUNCTION(7, "DBG_MON_A[29]"),
+                MTK_FUNCTION(10, "PCIE1_PERST_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(24, "EINT2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 2),
+                MTK_FUNCTION(0, "GPIO24"),
+                MTK_FUNCTION(1, "UCTS1"),
+                MTK_FUNCTION(3, "KCOL1"),
+                MTK_FUNCTION(4, "CONN_MCU_DBGACK_N"),
+                MTK_FUNCTION(7, "DBG_MON_A[28]"),
+                MTK_FUNCTION(10, "PCIE2_PERST_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(25, "EINT3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 3),
+                MTK_FUNCTION(0, "GPIO25"),
+                MTK_FUNCTION(1, "URTS1"),
+                MTK_FUNCTION(3, "KCOL0"),
+                MTK_FUNCTION(4, "CONN_MCU_DBGI_N"),
+                MTK_FUNCTION(7, "DBG_MON_A[27]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(26, "EINT4"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 4),
+                MTK_FUNCTION(0, "GPIO26"),
+                MTK_FUNCTION(1, "UCTS3"),
+                MTK_FUNCTION(2, "DRV_VBUS_P1"),
+                MTK_FUNCTION(3, "KROW3"),
+                MTK_FUNCTION(4, "CONN_MCU_TCK0"),
+                MTK_FUNCTION(5, "CONN_MCU_AICE_JCKC"),
+                MTK_FUNCTION(6, "PCIE2_WAKE_N"),
+                MTK_FUNCTION(7, "DBG_MON_A[26]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(27, "EINT5"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 5),
+                MTK_FUNCTION(0, "GPIO27"),
+                MTK_FUNCTION(1, "URTS3"),
+                MTK_FUNCTION(2, "IDDIG_P1"),
+                MTK_FUNCTION(3, "KROW2"),
+                MTK_FUNCTION(4, "CONN_MCU_TDI"),
+                MTK_FUNCTION(6, "PCIE1_WAKE_N"),
+                MTK_FUNCTION(7, "DBG_MON_A[25]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(28, "EINT6"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 6),
+                MTK_FUNCTION(0, "GPIO28"),
+                MTK_FUNCTION(1, "DRV_VBUS"),
+                MTK_FUNCTION(3, "KROW1"),
+                MTK_FUNCTION(4, "CONN_MCU_TRST_B"),
+                MTK_FUNCTION(6, "PCIE0_WAKE_N"),
+                MTK_FUNCTION(7, "DBG_MON_A[24]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(29, "EINT7"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 7),
+                MTK_FUNCTION(0, "GPIO29"),
+                MTK_FUNCTION(1, "IDDIG"),
+                MTK_FUNCTION(2, "MSDC1_WP"),
+                MTK_FUNCTION(3, "KROW0"),
+                MTK_FUNCTION(4, "CONN_MCU_TMS"),
+                MTK_FUNCTION(5, "CONN_MCU_AICE_JMSC"),
+                MTK_FUNCTION(7, "DBG_MON_A[23]"),
+                MTK_FUNCTION(14, "PCIE2_PERST_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(30, "I2S5_LRCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 12),
+                MTK_FUNCTION(0, "GPIO30"),
+                MTK_FUNCTION(1, "I2S5_LRCK"),
+                MTK_FUNCTION(3, "PCM_SYNC"),
+                MTK_FUNCTION(4, "ANT_SEL1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(31, "I2S5_MCLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 13),
+                MTK_FUNCTION(0, "GPIO31"),
+                MTK_FUNCTION(1, "I2S5_MCLK"),
+                MTK_FUNCTION(4, "ANT_SEL0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(32, "I2S5_DATA"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 14),
+                MTK_FUNCTION(0, "GPIO32"),
+                MTK_FUNCTION(1, "I2S5_DATA"),
+                MTK_FUNCTION(2, "I2S5_DATA_BYPS"),
+                MTK_FUNCTION(3, "PCM_TX"),
+                MTK_FUNCTION(4, "ANT_SEL3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(33, "I2S1_DATA"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 15),
+                MTK_FUNCTION(0, "GPIO33"),
+                MTK_FUNCTION(1, "I2S1_DATA"),
+                MTK_FUNCTION(2, "I2S1_DATA_BYPS"),
+                MTK_FUNCTION(3, "PCM_TX"),
+                MTK_FUNCTION(4, "IMG_TEST_CK"),
+                MTK_FUNCTION(5, "G1_RXD0"),
+                MTK_FUNCTION(6, "WCN_PCM_TX"),
+                MTK_FUNCTION(7, "DBG_MON_B[8]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(34, "I2S1_DATA_IN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 16),
+                MTK_FUNCTION(0, "GPIO34"),
+                MTK_FUNCTION(1, "I2S1_DATA_IN"),
+                MTK_FUNCTION(3, "PCM_RX"),
+                MTK_FUNCTION(4, "VDEC_TEST_CK"),
+                MTK_FUNCTION(5, "G1_RXD1"),
+                MTK_FUNCTION(6, "WCN_PCM_RX"),
+                MTK_FUNCTION(7, "DBG_MON_B[7]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(35, "I2S1_BCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 17),
+                MTK_FUNCTION(0, "GPIO35"),
+                MTK_FUNCTION(1, "I2S1_BCK"),
+                MTK_FUNCTION(3, "PCM_CLK0"),
+                MTK_FUNCTION(5, "G1_RXD2"),
+                MTK_FUNCTION(6, "WCN_PCM_CLKO"),
+                MTK_FUNCTION(7, "DBG_MON_B[9]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(36, "I2S1_LRCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 18),
+                MTK_FUNCTION(0, "GPIO36"),
+                MTK_FUNCTION(1, "I2S1_LRCK"),
+                MTK_FUNCTION(3, "PCM_SYNC"),
+                MTK_FUNCTION(5, "G1_RXD3"),
+                MTK_FUNCTION(6, "WCN_PCM_SYNC"),
+                MTK_FUNCTION(7, "DBG_MON_B[10]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(37, "I2S1_MCLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 19),
+                MTK_FUNCTION(0, "GPIO37"),
+                MTK_FUNCTION(1, "I2S1_MCLK"),
+                MTK_FUNCTION(5, "G1_RXDV"),
+                MTK_FUNCTION(7, "DBG_MON_B[11]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(38, "I2S2_DATA"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 20),
+                MTK_FUNCTION(0, "GPIO38"),
+                MTK_FUNCTION(2, "I2S2_DATA_BYPS"),
+                MTK_FUNCTION(3, "PCM_TX"),
+                MTK_FUNCTION(4, "DMIC_DAT0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(39, "JTMS"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 21),
+                MTK_FUNCTION(0, "GPIO39"),
+                MTK_FUNCTION(1, "JTMS"),
+                MTK_FUNCTION(2, "CONN_MCU_TMS"),
+                MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC"),
+                MTK_FUNCTION(4, "DFD_TMS_XI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(40, "JTCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 22),
+                MTK_FUNCTION(0, "GPIO40"),
+                MTK_FUNCTION(1, "JTCK"),
+                MTK_FUNCTION(2, "CONN_MCU_TCK1"),
+                MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC"),
+                MTK_FUNCTION(4, "DFD_TCK_XI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(41, "JTDI"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 23),
+                MTK_FUNCTION(0, "GPIO41"),
+                MTK_FUNCTION(1, "JTDI"),
+                MTK_FUNCTION(2, "CONN_MCU_TDI"),
+                MTK_FUNCTION(4, "DFD_TDI_XI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(42, "JTDO"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 24),
+                MTK_FUNCTION(0, "GPIO42"),
+                MTK_FUNCTION(1, "JTDO"),
+                MTK_FUNCTION(2, "CONN_MCU_TDO"),
+                MTK_FUNCTION(4, "DFD_TDO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(43, "NCLE"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 25),
+                MTK_FUNCTION(0, "GPIO43"),
+                MTK_FUNCTION(1, "NCLE"),
+                MTK_FUNCTION(2, "EXT_XCS2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(44, "NCEB1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 26),
+                MTK_FUNCTION(0, "GPIO44"),
+                MTK_FUNCTION(1, "NCEB1"),
+                MTK_FUNCTION(2, "IDDIG")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(45, "NCEB0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 27),
+                MTK_FUNCTION(0, "GPIO45"),
+                MTK_FUNCTION(1, "NCEB0"),
+                MTK_FUNCTION(2, "DRV_VBUS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(46, "IR"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 28),
+                MTK_FUNCTION(0, "GPIO46"),
+                MTK_FUNCTION(1, "IR")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(47, "NREB"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 29),
+                MTK_FUNCTION(0, "GPIO47"),
+                MTK_FUNCTION(1, "NREB"),
+                MTK_FUNCTION(2, "IDDIG_P1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(48, "NRNB"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 30),
+                MTK_FUNCTION(0, "GPIO48"),
+                MTK_FUNCTION(1, "NRNB"),
+                MTK_FUNCTION(2, "DRV_VBUS_P1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(49, "I2S0_DATA"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 31),
+                MTK_FUNCTION(0, "GPIO49"),
+                MTK_FUNCTION(1, "I2S0_DATA"),
+                MTK_FUNCTION(2, "I2S0_DATA_BYPS"),
+                MTK_FUNCTION(3, "PCM_TX"),
+                MTK_FUNCTION(6, "WCN_I2S_DO"),
+                MTK_FUNCTION(7, "DBG_MON_B[3]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(50, "I2S2_BCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 32),
+                MTK_FUNCTION(0, "GPIO50"),
+                MTK_FUNCTION(1, "I2S2_BCK"),
+                MTK_FUNCTION(3, "PCM_CLK0"),
+                MTK_FUNCTION(4, "DMIC_SCK1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(51, "I2S2_DATA_IN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 33),
+                MTK_FUNCTION(0, "GPIO51"),
+                MTK_FUNCTION(1, "I2S2_DATA_IN"),
+                MTK_FUNCTION(3, "PCM_RX"),
+                MTK_FUNCTION(4, "DMIC_SCK0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(52, "I2S2_LRCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 34),
+                MTK_FUNCTION(0, "GPIO52"),
+                MTK_FUNCTION(1, "I2S2_LRCK"),
+                MTK_FUNCTION(3, "PCM_SYNC"),
+                MTK_FUNCTION(4, "DMIC_DAT1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(53, "SPI0_CSN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 35),
+                MTK_FUNCTION(0, "GPIO53"),
+                MTK_FUNCTION(1, "SPI0_CS"),
+                MTK_FUNCTION(3, "SPDIF"),
+                MTK_FUNCTION(4, "ADC_CK"),
+                MTK_FUNCTION(5, "PWM1"),
+                MTK_FUNCTION(7, "DBG_MON_A[7]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(54, "SPI0_CK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 36),
+                MTK_FUNCTION(0, "GPIO54"),
+                MTK_FUNCTION(1, "SPI0_CK"),
+                MTK_FUNCTION(3, "SPDIF_IN1"),
+                MTK_FUNCTION(4, "ADC_DAT_IN"),
+                MTK_FUNCTION(7, "DBG_MON_A[10]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(55, "SPI0_MI"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 37),
+                MTK_FUNCTION(0, "GPIO55"),
+                MTK_FUNCTION(1, "SPI0_MI"),
+                MTK_FUNCTION(2, "SPI0_MO"),
+                MTK_FUNCTION(3, "MSDC1_WP"),
+                MTK_FUNCTION(4, "ADC_WS"),
+                MTK_FUNCTION(5, "PWM2"),
+                MTK_FUNCTION(7, "DBG_MON_A[8]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(56, "SPI0_MO"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 38),
+                MTK_FUNCTION(0, "GPIO56"),
+                MTK_FUNCTION(1, "SPI0_MO"),
+                MTK_FUNCTION(2, "SPI0_MI"),
+                MTK_FUNCTION(3, "SPDIF_IN0"),
+                MTK_FUNCTION(7, "DBG_MON_A[9]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(57, "SDA1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 39),
+                MTK_FUNCTION(0, "GPIO57"),
+                MTK_FUNCTION(1, "SDA1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(58, "SCL1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 40),
+                MTK_FUNCTION(0, "GPIO58"),
+                MTK_FUNCTION(1, "SCL1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(59, "RAMBUF_I_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO59"),
+                MTK_FUNCTION(1, "RAMBUF_I_CLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(60, "WB_RSTB"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 41),
+                MTK_FUNCTION(0, "GPIO60"),
+                MTK_FUNCTION(1, "WB_RSTB"),
+                MTK_FUNCTION(7, "DBG_MON_A[11]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(61, "F2W_DATA"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 42),
+                MTK_FUNCTION(0, "GPIO61"),
+                MTK_FUNCTION(1, "F2W_DATA"),
+                MTK_FUNCTION(7, "DBG_MON_A[16]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(62, "F2W_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 43),
+                MTK_FUNCTION(0, "GPIO62"),
+                MTK_FUNCTION(1, "F2W_CK"),
+                MTK_FUNCTION(7, "DBG_MON_A[15]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(63, "WB_SCLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 44),
+                MTK_FUNCTION(0, "GPIO63"),
+                MTK_FUNCTION(1, "WB_SCLK"),
+                MTK_FUNCTION(7, "DBG_MON_A[13]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(64, "WB_SDATA"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 45),
+                MTK_FUNCTION(0, "GPIO64"),
+                MTK_FUNCTION(1, "WB_SDATA"),
+                MTK_FUNCTION(7, "DBG_MON_A[12]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(65, "WB_SEN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 46),
+                MTK_FUNCTION(0, "GPIO65"),
+                MTK_FUNCTION(1, "WB_SEN"),
+                MTK_FUNCTION(7, "DBG_MON_A[14]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(66, "WB_CRTL0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 47),
+                MTK_FUNCTION(0, "GPIO66"),
+                MTK_FUNCTION(1, "WB_CRTL0"),
+                MTK_FUNCTION(5, "DFD_NTRST_XI"),
+                MTK_FUNCTION(7, "DBG_MON_A[17]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(67, "WB_CRTL1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 48),
+                MTK_FUNCTION(0, "GPIO67"),
+                MTK_FUNCTION(1, "WB_CRTL1"),
+                MTK_FUNCTION(5, "DFD_TMS_XI"),
+                MTK_FUNCTION(7, "DBG_MON_A[18]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(68, "WB_CRTL2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 49),
+                MTK_FUNCTION(0, "GPIO68"),
+                MTK_FUNCTION(1, "WB_CRTL2"),
+                MTK_FUNCTION(5, "DFD_TCK_XI"),
+                MTK_FUNCTION(7, "DBG_MON_A[19]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(69, "WB_CRTL3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 50),
+                MTK_FUNCTION(0, "GPIO69"),
+                MTK_FUNCTION(1, "WB_CRTL3"),
+                MTK_FUNCTION(5, "DFD_TDI_XI"),
+                MTK_FUNCTION(7, "DBG_MON_A[20]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(70, "WB_CRTL4"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 51),
+                MTK_FUNCTION(0, "GPIO70"),
+                MTK_FUNCTION(1, "WB_CRTL4"),
+                MTK_FUNCTION(5, "DFD_TDO"),
+                MTK_FUNCTION(7, "DBG_MON_A[21]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(71, "WB_CRTL5"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 52),
+                MTK_FUNCTION(0, "GPIO71"),
+                MTK_FUNCTION(1, "WB_CRTL5"),
+                MTK_FUNCTION(7, "DBG_MON_A[22]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(72, "I2S0_DATA_IN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 53),
+                MTK_FUNCTION(0, "GPIO72"),
+                MTK_FUNCTION(1, "I2S0_DATA_IN"),
+                MTK_FUNCTION(3, "PCM_RX"),
+                MTK_FUNCTION(4, "PWM0"),
+                MTK_FUNCTION(5, "DISP_PWM"),
+                MTK_FUNCTION(6, "WCN_I2S_DI"),
+                MTK_FUNCTION(7, "DBG_MON_B[2]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(73, "I2S0_LRCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 54),
+                MTK_FUNCTION(0, "GPIO73"),
+                MTK_FUNCTION(1, "I2S0_LRCK"),
+                MTK_FUNCTION(3, "PCM_SYNC"),
+                MTK_FUNCTION(6, "WCN_I2S_LRCK"),
+                MTK_FUNCTION(7, "DBG_MON_B[5]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(74, "I2S0_BCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 55),
+                MTK_FUNCTION(0, "GPIO74"),
+                MTK_FUNCTION(1, "I2S0_BCK"),
+                MTK_FUNCTION(3, "PCM_CLK0"),
+                MTK_FUNCTION(6, "WCN_I2S_BCK"),
+                MTK_FUNCTION(7, "DBG_MON_B[4]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(75, "SDA0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 56),
+                MTK_FUNCTION(0, "GPIO75"),
+                MTK_FUNCTION(1, "SDA0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(76, "SCL0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 57),
+                MTK_FUNCTION(0, "GPIO76"),
+                MTK_FUNCTION(1, "SCL0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(77, "SDA2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 58),
+                MTK_FUNCTION(0, "GPIO77"),
+                MTK_FUNCTION(1, "SDA2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(78, "SCL2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 59),
+                MTK_FUNCTION(0, "GPIO78"),
+                MTK_FUNCTION(1, "SCL2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(79, "URXD0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 60),
+                MTK_FUNCTION(0, "GPIO79"),
+                MTK_FUNCTION(1, "URXD0"),
+                MTK_FUNCTION(2, "UTXD0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(80, "UTXD0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 61),
+                MTK_FUNCTION(0, "GPIO80"),
+                MTK_FUNCTION(1, "UTXD0"),
+                MTK_FUNCTION(2, "URXD0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(81, "URXD1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 62),
+                MTK_FUNCTION(0, "GPIO81"),
+                MTK_FUNCTION(1, "URXD1"),
+                MTK_FUNCTION(2, "UTXD1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(82, "UTXD1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 63),
+                MTK_FUNCTION(0, "GPIO82"),
+                MTK_FUNCTION(1, "UTXD1"),
+                MTK_FUNCTION(2, "URXD1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(83, "LCM_RST"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 64),
+                MTK_FUNCTION(0, "GPIO83"),
+                MTK_FUNCTION(1, "LCM_RST"),
+                MTK_FUNCTION(2, "VDAC_CK_XI"),
+                MTK_FUNCTION(7, "DBG_MON_B[1]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(84, "DSI_TE"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 65),
+                MTK_FUNCTION(0, "GPIO84"),
+                MTK_FUNCTION(1, "DSI_TE"),
+                MTK_FUNCTION(7, "DBG_MON_B[0]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(85, "MSDC2_CMD"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 66),
+                MTK_FUNCTION(0, "GPIO85"),
+                MTK_FUNCTION(1, "MSDC2_CMD"),
+                MTK_FUNCTION(2, "ANT_SEL0"),
+                MTK_FUNCTION(3, "SDA1"),
+                MTK_FUNCTION(6, "I2SOUT_BCK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(86, "MSDC2_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 67),
+                MTK_FUNCTION(0, "GPIO86"),
+                MTK_FUNCTION(1, "MSDC2_CLK"),
+                MTK_FUNCTION(2, "ANT_SEL1"),
+                MTK_FUNCTION(3, "SCL1"),
+                MTK_FUNCTION(6, "I2SOUT_LRCK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(87, "MSDC2_DAT0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 68),
+                MTK_FUNCTION(0, "GPIO87"),
+                MTK_FUNCTION(1, "MSDC2_DAT0"),
+                MTK_FUNCTION(2, "ANT_SEL2"),
+                MTK_FUNCTION(5, "UTXD0"),
+                MTK_FUNCTION(6, "I2SOUT_DATA_OUT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(88, "MSDC2_DAT1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 71),
+                MTK_FUNCTION(0, "GPIO88"),
+                MTK_FUNCTION(1, "MSDC2_DAT1"),
+                MTK_FUNCTION(2, "ANT_SEL3"),
+                MTK_FUNCTION(3, "PWM0"),
+                MTK_FUNCTION(5, "URXD0"),
+                MTK_FUNCTION(6, "PWM1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(89, "MSDC2_DAT2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 72),
+                MTK_FUNCTION(0, "GPIO89"),
+                MTK_FUNCTION(1, "MSDC2_DAT2"),
+                MTK_FUNCTION(2, "ANT_SEL4"),
+                MTK_FUNCTION(3, "SDA2"),
+                MTK_FUNCTION(5, "UTXD1"),
+                MTK_FUNCTION(6, "PWM2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(90, "MSDC2_DAT3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 73),
+                MTK_FUNCTION(0, "GPIO90"),
+                MTK_FUNCTION(1, "MSDC2_DAT3"),
+                MTK_FUNCTION(2, "ANT_SEL5"),
+                MTK_FUNCTION(3, "SCL2"),
+                MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+                MTK_FUNCTION(5, "URXD1"),
+                MTK_FUNCTION(6, "PWM3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(91, "TDN3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPI91"),
+                MTK_FUNCTION(1, "TDN3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(92, "TDP3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPI92"),
+                MTK_FUNCTION(1, "TDP3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(93, "TDN2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPI93"),
+                MTK_FUNCTION(1, "TDN2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(94, "TDP2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPI94"),
+                MTK_FUNCTION(1, "TDP2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(95, "TCN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPI95"),
+                MTK_FUNCTION(1, "TCN")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(96, "TCP"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPI96"),
+                MTK_FUNCTION(1, "TCP")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(97, "TDN1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPI97"),
+                MTK_FUNCTION(1, "TDN1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(98, "TDP1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPI98"),
+                MTK_FUNCTION(1, "TDP1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(99, "TDN0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPI99"),
+                MTK_FUNCTION(1, "TDN0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(100, "TDP0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPI100"),
+                MTK_FUNCTION(1, "TDP0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(101, "SPI2_CSN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 74),
+                MTK_FUNCTION(0, "GPIO101"),
+                MTK_FUNCTION(1, "SPI2_CS"),
+                MTK_FUNCTION(3, "SCL3"),
+                MTK_FUNCTION(4, "KROW0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(102, "SPI2_MI"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 75),
+                MTK_FUNCTION(0, "GPIO102"),
+                MTK_FUNCTION(1, "SPI2_MI"),
+                MTK_FUNCTION(2, "SPI2_MO"),
+                MTK_FUNCTION(3, "SDA3"),
+                MTK_FUNCTION(4, "KROW1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(103, "SPI2_MO"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 76),
+                MTK_FUNCTION(0, "GPIO103"),
+                MTK_FUNCTION(1, "SPI2_MO"),
+                MTK_FUNCTION(2, "SPI2_MI"),
+                MTK_FUNCTION(3, "SCL3"),
+                MTK_FUNCTION(4, "KROW2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(104, "SPI2_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 77),
+                MTK_FUNCTION(0, "GPIO104"),
+                MTK_FUNCTION(1, "SPI2_CK"),
+                MTK_FUNCTION(3, "SDA3"),
+                MTK_FUNCTION(4, "KROW3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(105, "MSDC1_CMD"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 78),
+                MTK_FUNCTION(0, "GPIO105"),
+                MTK_FUNCTION(1, "MSDC1_CMD"),
+                MTK_FUNCTION(2, "ANT_SEL0"),
+                MTK_FUNCTION(3, "SDA1"),
+                MTK_FUNCTION(6, "I2SOUT_BCK"),
+                MTK_FUNCTION(7, "DBG_MON_B[27]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(106, "MSDC1_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 79),
+                MTK_FUNCTION(0, "GPIO106"),
+                MTK_FUNCTION(1, "MSDC1_CLK"),
+                MTK_FUNCTION(2, "ANT_SEL1"),
+                MTK_FUNCTION(3, "SCL1"),
+                MTK_FUNCTION(6, "I2SOUT_LRCK"),
+                MTK_FUNCTION(7, "DBG_MON_B[28]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(107, "MSDC1_DAT0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 80),
+                MTK_FUNCTION(0, "GPIO107"),
+                MTK_FUNCTION(1, "MSDC1_DAT0"),
+                MTK_FUNCTION(2, "ANT_SEL2"),
+                MTK_FUNCTION(5, "UTXD0"),
+                MTK_FUNCTION(6, "I2SOUT_DATA_OUT"),
+                MTK_FUNCTION(7, "DBG_MON_B[26]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(108, "MSDC1_DAT1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 81),
+                MTK_FUNCTION(0, "GPIO108"),
+                MTK_FUNCTION(1, "MSDC1_DAT1"),
+                MTK_FUNCTION(2, "ANT_SEL3"),
+                MTK_FUNCTION(3, "PWM0"),
+                MTK_FUNCTION(5, "URXD0"),
+                MTK_FUNCTION(6, "PWM1"),
+                MTK_FUNCTION(7, "DBG_MON_B[25]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(109, "MSDC1_DAT2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 82),
+                MTK_FUNCTION(0, "GPIO109"),
+                MTK_FUNCTION(1, "MSDC1_DAT2"),
+                MTK_FUNCTION(2, "ANT_SEL4"),
+                MTK_FUNCTION(3, "SDA2"),
+                MTK_FUNCTION(5, "UTXD1"),
+                MTK_FUNCTION(6, "PWM2"),
+                MTK_FUNCTION(7, "DBG_MON_B[24]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(110, "MSDC1_DAT3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 83),
+                MTK_FUNCTION(0, "GPIO110"),
+                MTK_FUNCTION(1, "MSDC1_DAT3"),
+                MTK_FUNCTION(2, "ANT_SEL5"),
+                MTK_FUNCTION(3, "SCL2"),
+                MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+                MTK_FUNCTION(5, "URXD1"),
+                MTK_FUNCTION(6, "PWM3"),
+                MTK_FUNCTION(7, "DBG_MON_B[23]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(111, "MSDC0_DAT7"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 84),
+                MTK_FUNCTION(0, "GPIO111"),
+                MTK_FUNCTION(1, "MSDC0_DAT7"),
+                MTK_FUNCTION(4, "NLD7")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(112, "MSDC0_DAT6"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 85),
+                MTK_FUNCTION(0, "GPIO112"),
+                MTK_FUNCTION(1, "MSDC0_DAT6"),
+                MTK_FUNCTION(4, "NLD6")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(113, "MSDC0_DAT5"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 86),
+                MTK_FUNCTION(0, "GPIO113"),
+                MTK_FUNCTION(1, "MSDC0_DAT5"),
+                MTK_FUNCTION(4, "NLD5")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(114, "MSDC0_DAT4"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 87),
+                MTK_FUNCTION(0, "GPIO114"),
+                MTK_FUNCTION(1, "MSDC0_DAT4"),
+                MTK_FUNCTION(4, "NLD4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(115, "MSDC0_RSTB"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 88),
+                MTK_FUNCTION(0, "GPIO115"),
+                MTK_FUNCTION(1, "MSDC0_RSTB"),
+                MTK_FUNCTION(4, "NLD8")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(116, "MSDC0_CMD"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 89),
+                MTK_FUNCTION(0, "GPIO116"),
+                MTK_FUNCTION(1, "MSDC0_CMD"),
+                MTK_FUNCTION(4, "NALE")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(117, "MSDC0_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 90),
+                MTK_FUNCTION(0, "GPIO117"),
+                MTK_FUNCTION(1, "MSDC0_CLK"),
+                MTK_FUNCTION(4, "NWEB")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(118, "MSDC0_DAT3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 91),
+                MTK_FUNCTION(0, "GPIO118"),
+                MTK_FUNCTION(1, "MSDC0_DAT3"),
+                MTK_FUNCTION(4, "NLD3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(119, "MSDC0_DAT2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 92),
+                MTK_FUNCTION(0, "GPIO119"),
+                MTK_FUNCTION(1, "MSDC0_DAT2"),
+                MTK_FUNCTION(4, "NLD2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(120, "MSDC0_DAT1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 93),
+                MTK_FUNCTION(0, "GPIO120"),
+                MTK_FUNCTION(1, "MSDC0_DAT1"),
+                MTK_FUNCTION(4, "NLD1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(121, "MSDC0_DAT0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 94),
+                MTK_FUNCTION(0, "GPIO121"),
+                MTK_FUNCTION(1, "MSDC0_DAT0"),
+                MTK_FUNCTION(4, "NLD0"),
+                MTK_FUNCTION(5, "WATCHDOG")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(122, "CEC"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 95),
+                MTK_FUNCTION(0, "GPIO122"),
+                MTK_FUNCTION(1, "CEC"),
+                MTK_FUNCTION(4, "SDA2"),
+                MTK_FUNCTION(5, "URXD0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(123, "HTPLG"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 96),
+                MTK_FUNCTION(0, "GPIO123"),
+                MTK_FUNCTION(1, "HTPLG"),
+                MTK_FUNCTION(4, "SCL2"),
+                MTK_FUNCTION(5, "UTXD0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(124, "HDMISCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 97),
+                MTK_FUNCTION(0, "GPIO124"),
+                MTK_FUNCTION(1, "HDMISCK"),
+                MTK_FUNCTION(4, "SDA1"),
+                MTK_FUNCTION(5, "PWM3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(125, "HDMISD"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 98),
+                MTK_FUNCTION(0, "GPIO125"),
+                MTK_FUNCTION(1, "HDMISD"),
+                MTK_FUNCTION(4, "SCL1"),
+                MTK_FUNCTION(5, "PWM4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(126, "I2S0_MCLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 99),
+                MTK_FUNCTION(0, "GPIO126"),
+                MTK_FUNCTION(1, "I2S0_MCLK"),
+                MTK_FUNCTION(6, "WCN_I2S_MCLK"),
+                MTK_FUNCTION(7, "DBG_MON_B[6]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(127, "RAMBUF_IDATA0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO127"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(128, "RAMBUF_IDATA1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO128"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(129, "RAMBUF_IDATA2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO129"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(130, "RAMBUF_IDATA3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO130"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(131, "RAMBUF_IDATA4"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO131"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(132, "RAMBUF_IDATA5"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO132"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA5")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(133, "RAMBUF_IDATA6"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO133"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA6")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(134, "RAMBUF_IDATA7"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO134"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA7")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(135, "RAMBUF_IDATA8"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO135"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA8")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(136, "RAMBUF_IDATA9"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO136"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA9")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(137, "RAMBUF_IDATA10"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO137"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA10")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(138, "RAMBUF_IDATA11"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO138"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA11")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(139, "RAMBUF_IDATA12"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO139"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA12")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(140, "RAMBUF_IDATA13"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO140"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA13")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(141, "RAMBUF_IDATA14"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO141"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA14")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(142, "RAMBUF_IDATA15"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO142"),
+                MTK_FUNCTION(1, "RAMBUF_IDATA15")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(143, "RAMBUF_ODATA0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO143"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(144, "RAMBUF_ODATA1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO144"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(145, "RAMBUF_ODATA2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO145"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(146, "RAMBUF_ODATA3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO146"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(147, "RAMBUF_ODATA4"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO147"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(148, "RAMBUF_ODATA5"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO148"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA5")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(149, "RAMBUF_ODATA6"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO149"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA6")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(150, "RAMBUF_ODATA7"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO150"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA7")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(151, "RAMBUF_ODATA8"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO151"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA8")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(152, "RAMBUF_ODATA9"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO152"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA9")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(153, "RAMBUF_ODATA10"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO153"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA10")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(154, "RAMBUF_ODATA11"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO154"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA11")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(155, "RAMBUF_ODATA12"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO155"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA12")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(156, "RAMBUF_ODATA13"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO156"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA13")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(157, "RAMBUF_ODATA14"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO157"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA14")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(158, "RAMBUF_ODATA15"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO158"),
+                MTK_FUNCTION(1, "RAMBUF_ODATA15")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(159, "RAMBUF_BE0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO159"),
+                MTK_FUNCTION(1, "RAMBUF_BE0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(160, "RAMBUF_BE1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO160"),
+                MTK_FUNCTION(1, "RAMBUF_BE1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(161, "AP2PT_INT"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO161"),
+                MTK_FUNCTION(1, "AP2PT_INT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(162, "AP2PT_INT_CLR"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO162"),
+                MTK_FUNCTION(1, "AP2PT_INT_CLR")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(163, "PT2AP_INT"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO163"),
+                MTK_FUNCTION(1, "PT2AP_INT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(164, "PT2AP_INT_CLR"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO164"),
+                MTK_FUNCTION(1, "PT2AP_INT_CLR")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(165, "AP2UP_INT"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO165"),
+                MTK_FUNCTION(1, "AP2UP_INT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(166, "AP2UP_INT_CLR"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO166"),
+                MTK_FUNCTION(1, "AP2UP_INT_CLR")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(167, "UP2AP_INT"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO167"),
+                MTK_FUNCTION(1, "UP2AP_INT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(168, "UP2AP_INT_CLR"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO168"),
+                MTK_FUNCTION(1, "UP2AP_INT_CLR")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(169, "RAMBUF_ADDR0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO169"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(170, "RAMBUF_ADDR1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO170"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(171, "RAMBUF_ADDR2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO171"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(172, "RAMBUF_ADDR3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO172"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(173, "RAMBUF_ADDR4"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO173"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(174, "RAMBUF_ADDR5"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO174"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR5")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(175, "RAMBUF_ADDR6"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO175"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR6")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(176, "RAMBUF_ADDR7"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO176"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR7")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(177, "RAMBUF_ADDR8"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO177"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR8")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(178, "RAMBUF_ADDR9"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO178"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR9")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(179, "RAMBUF_ADDR10"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO179"),
+                MTK_FUNCTION(1, "RAMBUF_ADDR10")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(180, "RAMBUF_RW"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO180"),
+                MTK_FUNCTION(1, "RAMBUF_RW")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(181, "RAMBUF_LAST"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO181"),
+                MTK_FUNCTION(1, "RAMBUF_LAST")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(182, "RAMBUF_HP"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO182"),
+                MTK_FUNCTION(1, "RAMBUF_HP")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(183, "RAMBUF_REQ"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO183"),
+                MTK_FUNCTION(1, "RAMBUF_REQ")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(184, "RAMBUF_ALE"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO184"),
+                MTK_FUNCTION(1, "RAMBUF_ALE")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(185, "RAMBUF_DLE"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO185"),
+                MTK_FUNCTION(1, "RAMBUF_DLE")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(186, "RAMBUF_WDLE"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO186"),
+                MTK_FUNCTION(1, "RAMBUF_WDLE")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(187, "RAMBUF_O_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO187"),
+                MTK_FUNCTION(1, "RAMBUF_O_CLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(188, "I2S2_MCLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 100),
+                MTK_FUNCTION(0, "GPIO188"),
+                MTK_FUNCTION(1, "I2S2_MCLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(189, "I2S3_DATA"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 101),
+                MTK_FUNCTION(0, "GPIO189"),
+                MTK_FUNCTION(2, "I2S3_DATA_BYPS"),
+                MTK_FUNCTION(3, "PCM_TX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(190, "I2S3_DATA_IN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 102),
+                MTK_FUNCTION(0, "GPIO190"),
+                MTK_FUNCTION(1, "I2S3_DATA_IN"),
+                MTK_FUNCTION(3, "PCM_RX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(191, "I2S3_BCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 103),
+                MTK_FUNCTION(0, "GPIO191"),
+                MTK_FUNCTION(1, "I2S3_BCK"),
+                MTK_FUNCTION(3, "PCM_CLK0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(192, "I2S3_LRCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 104),
+                MTK_FUNCTION(0, "GPIO192"),
+                MTK_FUNCTION(1, "I2S3_LRCK"),
+                MTK_FUNCTION(3, "PCM_SYNC")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(193, "I2S3_MCLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 105),
+                MTK_FUNCTION(0, "GPIO193"),
+                MTK_FUNCTION(1, "I2S3_MCLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(194, "I2S4_DATA"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 106),
+                MTK_FUNCTION(0, "GPIO194"),
+                MTK_FUNCTION(1, "I2S4_DATA"),
+                MTK_FUNCTION(2, "I2S4_DATA_BYPS"),
+                MTK_FUNCTION(3, "PCM_TX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(195, "I2S4_DATA_IN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 107),
+                MTK_FUNCTION(0, "GPIO195"),
+                MTK_FUNCTION(1, "I2S4_DATA_IN"),
+                MTK_FUNCTION(3, "PCM_RX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(196, "I2S4_BCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 108),
+                MTK_FUNCTION(0, "GPIO196"),
+                MTK_FUNCTION(1, "I2S4_BCK"),
+                MTK_FUNCTION(3, "PCM_CLK0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(197, "I2S4_LRCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 109),
+                MTK_FUNCTION(0, "GPIO197"),
+                MTK_FUNCTION(1, "I2S4_LRCK"),
+                MTK_FUNCTION(3, "PCM_SYNC")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(198, "I2S4_MCLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 110),
+                MTK_FUNCTION(0, "GPIO198"),
+                MTK_FUNCTION(1, "I2S4_MCLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(199, "SPI1_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 111),
+                MTK_FUNCTION(0, "GPIO199"),
+                MTK_FUNCTION(1, "SPI1_CK"),
+                MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+                MTK_FUNCTION(4, "KCOL3"),
+                MTK_FUNCTION(7, "DBG_MON_B[15]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(200, "SPDIF_OUT"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 112),
+                MTK_FUNCTION(0, "GPIO200"),
+                MTK_FUNCTION(1, "SPDIF_OUT"),
+                MTK_FUNCTION(5, "G1_TXD3"),
+                MTK_FUNCTION(6, "URXD2"),
+                MTK_FUNCTION(7, "DBG_MON_B[16]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(201, "SPDIF_IN0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 113),
+                MTK_FUNCTION(0, "GPIO201"),
+                MTK_FUNCTION(1, "SPDIF_IN0"),
+                MTK_FUNCTION(5, "G1_TXEN"),
+                MTK_FUNCTION(6, "UTXD2"),
+                MTK_FUNCTION(7, "DBG_MON_B[17]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(202, "SPDIF_IN1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 114),
+                MTK_FUNCTION(0, "GPIO202"),
+                MTK_FUNCTION(1, "SPDIF_IN1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(203, "PWM0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 115),
+                MTK_FUNCTION(0, "GPIO203"),
+                MTK_FUNCTION(1, "PWM0"),
+                MTK_FUNCTION(2, "DISP_PWM"),
+                MTK_FUNCTION(5, "G1_TXD2"),
+                MTK_FUNCTION(7, "DBG_MON_B[18]"),
+                MTK_FUNCTION(9, "I2S2_DATA")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(204, "PWM1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 116),
+                MTK_FUNCTION(0, "GPIO204"),
+                MTK_FUNCTION(1, "PWM1"),
+                MTK_FUNCTION(2, "CLKM3"),
+                MTK_FUNCTION(5, "G1_TXD1"),
+                MTK_FUNCTION(7, "DBG_MON_B[19]"),
+                MTK_FUNCTION(9, "I2S3_DATA")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(205, "PWM2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 117),
+                MTK_FUNCTION(0, "GPIO205"),
+                MTK_FUNCTION(1, "PWM2"),
+                MTK_FUNCTION(2, "CLKM2"),
+                MTK_FUNCTION(5, "G1_TXD0"),
+                MTK_FUNCTION(7, "DBG_MON_B[20]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(206, "PWM3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 118),
+                MTK_FUNCTION(0, "GPIO206"),
+                MTK_FUNCTION(1, "PWM3"),
+                MTK_FUNCTION(2, "CLKM1"),
+                MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+                MTK_FUNCTION(5, "G1_TXC"),
+                MTK_FUNCTION(7, "DBG_MON_B[21]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(207, "PWM4"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 119),
+                MTK_FUNCTION(0, "GPIO207"),
+                MTK_FUNCTION(1, "PWM4"),
+                MTK_FUNCTION(2, "CLKM0"),
+                MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+                MTK_FUNCTION(5, "G1_RXC"),
+                MTK_FUNCTION(7, "DBG_MON_B[22]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(208, "AUD_EXT_CK1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 120),
+                MTK_FUNCTION(0, "GPIO208"),
+                MTK_FUNCTION(1, "AUD_EXT_CK1"),
+                MTK_FUNCTION(2, "PWM0"),
+                MTK_FUNCTION(4, "ANT_SEL5"),
+                MTK_FUNCTION(5, "DISP_PWM"),
+                MTK_FUNCTION(7, "DBG_MON_A[31]"),
+                MTK_FUNCTION(11, "PCIE0_PERST_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(209, "AUD_EXT_CK2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 121),
+                MTK_FUNCTION(0, "GPIO209"),
+                MTK_FUNCTION(1, "AUD_EXT_CK2"),
+                MTK_FUNCTION(2, "MSDC1_WP"),
+                MTK_FUNCTION(5, "PWM1"),
+                MTK_FUNCTION(7, "DBG_MON_A[32]"),
+                MTK_FUNCTION(11, "PCIE1_PERST_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(210, "AUD_CLOCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO210"),
+                MTK_FUNCTION(1, "AUD_CLOCK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(211, "DVP_RESET"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO211"),
+                MTK_FUNCTION(1, "DVP_RESET")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(212, "DVP_CLOCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO212"),
+                MTK_FUNCTION(1, "DVP_CLOCK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(213, "DVP_CS"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO213"),
+                MTK_FUNCTION(1, "DVP_CS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(214, "DVP_CK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO214"),
+                MTK_FUNCTION(1, "DVP_CK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(215, "DVP_DI"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO215"),
+                MTK_FUNCTION(1, "DVP_DI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(216, "DVP_DO"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO216"),
+                MTK_FUNCTION(1, "DVP_DO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(217, "AP_CS"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO217"),
+                MTK_FUNCTION(1, "AP_CS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(218, "AP_CK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO218"),
+                MTK_FUNCTION(1, "AP_CK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(219, "AP_DI"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO219"),
+                MTK_FUNCTION(1, "AP_DI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(220, "AP_DO"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO220"),
+                MTK_FUNCTION(1, "AP_DO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(221, "DVD_BCLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO221"),
+                MTK_FUNCTION(1, "DVD_BCLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(222, "T8032_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO222"),
+                MTK_FUNCTION(1, "T8032_CLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(223, "AP_BCLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO223"),
+                MTK_FUNCTION(1, "AP_BCLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(224, "HOST_CS"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO224"),
+                MTK_FUNCTION(1, "HOST_CS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(225, "HOST_CK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO225"),
+                MTK_FUNCTION(1, "HOST_CK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(226, "HOST_DO0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO226"),
+                MTK_FUNCTION(1, "HOST_DO0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(227, "HOST_DO1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO227"),
+                MTK_FUNCTION(1, "HOST_DO1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(228, "SLV_CS"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO228"),
+                MTK_FUNCTION(1, "SLV_CS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(229, "SLV_CK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO229"),
+                MTK_FUNCTION(1, "SLV_CK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(230, "SLV_DI0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO230"),
+                MTK_FUNCTION(1, "SLV_DI0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(231, "SLV_DI1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO231"),
+                MTK_FUNCTION(1, "SLV_DI1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(232, "AP2DSP_INT"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO232"),
+                MTK_FUNCTION(1, "AP2DSP_INT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(233, "AP2DSP_INT_CLR"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO233"),
+                MTK_FUNCTION(1, "AP2DSP_INT_CLR")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(234, "DSP2AP_INT"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO234"),
+                MTK_FUNCTION(1, "DSP2AP_INT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(235, "DSP2AP_INT_CLR"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO235"),
+                MTK_FUNCTION(1, "DSP2AP_INT_CLR")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(236, "EXT_SDIO3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 122),
+                MTK_FUNCTION(0, "GPIO236"),
+                MTK_FUNCTION(1, "EXT_SDIO3"),
+                MTK_FUNCTION(2, "IDDIG"),
+                MTK_FUNCTION(7, "DBG_MON_A[1]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(237, "EXT_SDIO2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 123),
+                MTK_FUNCTION(0, "GPIO237"),
+                MTK_FUNCTION(1, "EXT_SDIO2"),
+                MTK_FUNCTION(2, "DRV_VBUS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(238, "EXT_SDIO1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 124),
+                MTK_FUNCTION(0, "GPIO238"),
+                MTK_FUNCTION(1, "EXT_SDIO1"),
+                MTK_FUNCTION(2, "IDDIG_P1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(239, "EXT_SDIO0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 125),
+                MTK_FUNCTION(0, "GPIO239"),
+                MTK_FUNCTION(1, "EXT_SDIO0"),
+                MTK_FUNCTION(2, "DRV_VBUS_P1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(240, "EXT_XCS"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 126),
+                MTK_FUNCTION(0, "GPIO240"),
+                MTK_FUNCTION(1, "EXT_XCS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(241, "EXT_SCK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 127),
+                MTK_FUNCTION(0, "GPIO241"),
+                MTK_FUNCTION(1, "EXT_SCK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(242, "URTS2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 128),
+                MTK_FUNCTION(0, "GPIO242"),
+                MTK_FUNCTION(1, "URTS2"),
+                MTK_FUNCTION(2, "UTXD3"),
+                MTK_FUNCTION(3, "URXD3"),
+                MTK_FUNCTION(4, "SCL1"),
+                MTK_FUNCTION(7, "DBG_MON_B[32]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(243, "UCTS2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 129),
+                MTK_FUNCTION(0, "GPIO243"),
+                MTK_FUNCTION(1, "UCTS2"),
+                MTK_FUNCTION(2, "URXD3"),
+                MTK_FUNCTION(3, "UTXD3"),
+                MTK_FUNCTION(4, "SDA1"),
+                MTK_FUNCTION(7, "DBG_MON_A[6]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(244, "HDMI_SDA_RX"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 130),
+                MTK_FUNCTION(0, "GPIO244"),
+                MTK_FUNCTION(1, "HDMI_SDA_RX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(245, "HDMI_SCL_RX"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 131),
+                MTK_FUNCTION(0, "GPIO245"),
+                MTK_FUNCTION(1, "HDMI_SCL_RX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(246, "MHL_SENCE"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 132),
+                MTK_FUNCTION(0, "GPIO246")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(247, "HDMI_HPD_CBUS_RX"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 69),
+                MTK_FUNCTION(0, "GPIO247"),
+                MTK_FUNCTION(1, "HDMI_HPD_RX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(248, "HDMI_TESTOUTP_RX"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 133),
+                MTK_FUNCTION(0, "GPIO248"),
+                MTK_FUNCTION(1, "HDMI_TESTOUTP_RX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(249, "MSDC0E_RSTB"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 134),
+                MTK_FUNCTION(0, "GPIO249"),
+                MTK_FUNCTION(1, "MSDC0E_RSTB")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(250, "MSDC0E_DAT7"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 135),
+                MTK_FUNCTION(0, "GPIO250"),
+                MTK_FUNCTION(1, "MSDC3_DAT7"),
+                MTK_FUNCTION(6, "PCIE0_CLKREQ_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(251, "MSDC0E_DAT6"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 136),
+                MTK_FUNCTION(0, "GPIO251"),
+                MTK_FUNCTION(1, "MSDC3_DAT6"),
+                MTK_FUNCTION(6, "PCIE0_WAKE_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(252, "MSDC0E_DAT5"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 137),
+                MTK_FUNCTION(0, "GPIO252"),
+                MTK_FUNCTION(1, "MSDC3_DAT5"),
+                MTK_FUNCTION(6, "PCIE1_CLKREQ_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(253, "MSDC0E_DAT4"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 138),
+                MTK_FUNCTION(0, "GPIO253"),
+                MTK_FUNCTION(1, "MSDC3_DAT4"),
+                MTK_FUNCTION(6, "PCIE1_WAKE_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(254, "MSDC0E_DAT3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 139),
+                MTK_FUNCTION(0, "GPIO254"),
+                MTK_FUNCTION(1, "MSDC3_DAT3"),
+                MTK_FUNCTION(6, "PCIE2_CLKREQ_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(255, "MSDC0E_DAT2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 140),
+                MTK_FUNCTION(0, "GPIO255"),
+                MTK_FUNCTION(1, "MSDC3_DAT2"),
+                MTK_FUNCTION(6, "PCIE2_WAKE_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(256, "MSDC0E_DAT1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 141),
+                MTK_FUNCTION(0, "GPIO256"),
+                MTK_FUNCTION(1, "MSDC3_DAT1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(257, "MSDC0E_DAT0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 142),
+                MTK_FUNCTION(0, "GPIO257"),
+                MTK_FUNCTION(1, "MSDC3_DAT0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(258, "MSDC0E_CMD"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 143),
+                MTK_FUNCTION(0, "GPIO258"),
+                MTK_FUNCTION(1, "MSDC3_CMD")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(259, "MSDC0E_CLK"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 144),
+                MTK_FUNCTION(0, "GPIO259"),
+                MTK_FUNCTION(1, "MSDC3_CLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(260, "MSDC0E_DSL"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 145),
+                MTK_FUNCTION(0, "GPIO260"),
+                MTK_FUNCTION(1, "MSDC3_DSL")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(261, "MSDC1_INS"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 146),
+                MTK_FUNCTION(0, "GPIO261"),
+                MTK_FUNCTION(1, "MSDC1_INS"),
+                MTK_FUNCTION(7, "DBG_MON_B[29]")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(262, "G2_TXEN"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 8),
+                MTK_FUNCTION(0, "GPIO262"),
+                MTK_FUNCTION(1, "G2_TXEN")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(263, "G2_TXD3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 9),
+                MTK_FUNCTION(0, "GPIO263"),
+                MTK_FUNCTION(1, "G2_TXD3"),
+                MTK_FUNCTION(6, "ANT_SEL5")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(264, "G2_TXD2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 10),
+                MTK_FUNCTION(0, "GPIO264"),
+                MTK_FUNCTION(1, "G2_TXD2"),
+                MTK_FUNCTION(6, "ANT_SEL4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(265, "G2_TXD1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 11),
+                MTK_FUNCTION(0, "GPIO265"),
+                MTK_FUNCTION(1, "G2_TXD1"),
+                MTK_FUNCTION(6, "ANT_SEL3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(266, "G2_TXD0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO266"),
+                MTK_FUNCTION(1, "G2_TXD0"),
+                MTK_FUNCTION(6, "ANT_SEL2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(267, "G2_TXC"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO267"),
+                MTK_FUNCTION(1, "G2_TXC")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(268, "G2_RXC"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO268"),
+                MTK_FUNCTION(1, "G2_RXC")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(269, "G2_RXD0"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO269"),
+                MTK_FUNCTION(1, "G2_RXD0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(270, "G2_RXD1"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO270"),
+                MTK_FUNCTION(1, "G2_RXD1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(271, "G2_RXD2"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO271"),
+                MTK_FUNCTION(1, "G2_RXD2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(272, "G2_RXD3"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO272"),
+                MTK_FUNCTION(1, "G2_RXD3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(273, "ESW_INT"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 168),
+                MTK_FUNCTION(0, "GPIO273"),
+                MTK_FUNCTION(1, "ESW_INT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(274, "G2_RXDV"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO274"),
+                MTK_FUNCTION(1, "G2_RXDV")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(275, "MDC"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO275"),
+                MTK_FUNCTION(1, "MDC"),
+                MTK_FUNCTION(6, "ANT_SEL0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(276, "MDIO"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO276"),
+                MTK_FUNCTION(1, "MDIO"),
+                MTK_FUNCTION(6, "ANT_SEL1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(277, "ESW_RST"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO277"),
+                MTK_FUNCTION(1, "ESW_RST")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(278, "JTAG_RESET"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(0, 147),
+                MTK_FUNCTION(0, "GPIO278"),
+                MTK_FUNCTION(1, "JTAG_RESET")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(279, "USB3_RES_BOND"),
+                NULL, "mt2701",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO279"),
+                MTK_FUNCTION(1, "USB3_RES_BOND")
+        ),
+};
+
+#endif /* __PINCTRL_MTK_MT2701_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
new file mode 100644
index 000000000000..3472a76ad422
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
@@ -0,0 +1,1936 @@
+/*
+ * Copyright (c) 2016 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_MT7623_H
+#define __PINCTRL_MTK_MT7623_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt7623[] = {
+        MTK_PIN(
+                PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
+                "J20", "mt7623",
+                MTK_EINT_FUNCTION(0, 148),
+                MTK_FUNCTION(0, "GPIO0"),
+                MTK_FUNCTION(1, "PWRAP_SPIDO"),
+                MTK_FUNCTION(2, "PWRAP_SPIDI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
+                "D10", "mt7623",
+                MTK_EINT_FUNCTION(0, 149),
+                MTK_FUNCTION(0, "GPIO1"),
+                MTK_FUNCTION(1, "PWRAP_SPIDI"),
+                MTK_FUNCTION(2, "PWRAP_SPIDO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(2, "PWRAP_INT"),
+                "E11", "mt7623",
+                MTK_EINT_FUNCTION(0, 150),
+                MTK_FUNCTION(0, "GPIO2"),
+                MTK_FUNCTION(1, "PWRAP_INT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
+                "H12", "mt7623",
+                MTK_EINT_FUNCTION(0, 151),
+                MTK_FUNCTION(0, "GPIO3"),
+                MTK_FUNCTION(1, "PWRAP_SPICK_I")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
+                "E12", "mt7623",
+                MTK_EINT_FUNCTION(0, 152),
+                MTK_FUNCTION(0, "GPIO4"),
+                MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
+                "H11", "mt7623",
+                MTK_EINT_FUNCTION(0, 155),
+                MTK_FUNCTION(0, "GPIO5"),
+                MTK_FUNCTION(1, "PWRAP_SPICK2_I")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
+                "G11", "mt7623",
+                MTK_EINT_FUNCTION(0, 156),
+                MTK_FUNCTION(0, "GPIO6"),
+                MTK_FUNCTION(1, "PWRAP_SPICS2_B_I")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(7, "SPI1_CSN"),
+                "G19", "mt7623",
+                MTK_EINT_FUNCTION(0, 153),
+                MTK_FUNCTION(0, "GPIO7"),
+                MTK_FUNCTION(1, "SPI1_CS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(8, "SPI1_MI"),
+                "F19", "mt7623",
+                MTK_EINT_FUNCTION(0, 154),
+                MTK_FUNCTION(0, "GPIO8"),
+                MTK_FUNCTION(1, "SPI1_MI"),
+                MTK_FUNCTION(2, "SPI1_MO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(9, "SPI1_MO"),
+                "G20", "mt7623",
+                MTK_EINT_FUNCTION(0, 157),
+                MTK_FUNCTION(0, "GPIO9"),
+                MTK_FUNCTION(1, "SPI1_MO"),
+                MTK_FUNCTION(2, "SPI1_MI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(10, "RTC32K_CK"),
+                "A13", "mt7623",
+                MTK_EINT_FUNCTION(0, 158),
+                MTK_FUNCTION(0, "GPIO10"),
+                MTK_FUNCTION(1, "RTC32K_CK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(11, "WATCHDOG"),
+                "D14", "mt7623",
+                MTK_EINT_FUNCTION(0, 159),
+                MTK_FUNCTION(0, "GPIO11"),
+                MTK_FUNCTION(1, "WATCHDOG")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(12, "SRCLKENA"),
+                "C13", "mt7623",
+                MTK_EINT_FUNCTION(0, 169),
+                MTK_FUNCTION(0, "GPIO12"),
+                MTK_FUNCTION(1, "SRCLKENA")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(13, "SRCLKENAI"),
+                "B13", "mt7623",
+                MTK_EINT_FUNCTION(0, 161),
+                MTK_FUNCTION(0, "GPIO13"),
+                MTK_FUNCTION(1, "SRCLKENAI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(14, "GPIO14"),
+                "E18", "mt7623",
+                MTK_EINT_FUNCTION(0, 162),
+                MTK_FUNCTION(0, "GPIO14"),
+                MTK_FUNCTION(1, "URXD2"),
+                MTK_FUNCTION(2, "UTXD2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(15, "GPIO15"),
+                "E17", "mt7623",
+                MTK_EINT_FUNCTION(0, 163),
+                MTK_FUNCTION(0, "GPIO15"),
+                MTK_FUNCTION(1, "UTXD2"),
+                MTK_FUNCTION(2, "URXD2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(16, "GPIO16"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO16")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(17, "GPIO17"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO17")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(18, "PCM_CLK"),
+                "C19", "mt7623",
+                MTK_EINT_FUNCTION(0, 166),
+                MTK_FUNCTION(0, "GPIO18"),
+                MTK_FUNCTION(1, "PCM_CLK0"),
+                MTK_FUNCTION(6, "AP_PCM_CLKO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(19, "PCM_SYNC"),
+                "D19", "mt7623",
+                MTK_EINT_FUNCTION(0, 167),
+                MTK_FUNCTION(0, "GPIO19"),
+                MTK_FUNCTION(1, "PCM_SYNC"),
+                MTK_FUNCTION(6, "AP_PCM_SYNC")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(20, "PCM_RX"),
+                "D18", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO20"),
+                MTK_FUNCTION(1, "PCM_RX"),
+                MTK_FUNCTION(4, "PCM_TX"),
+                MTK_FUNCTION(6, "AP_PCM_RX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(21, "PCM_TX"),
+                "C18", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO21"),
+                MTK_FUNCTION(1, "PCM_TX"),
+                MTK_FUNCTION(4, "PCM_RX"),
+                MTK_FUNCTION(6, "AP_PCM_TX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(22, "EINT0"),
+                "H15", "mt7623",
+                MTK_EINT_FUNCTION(0, 0),
+                MTK_FUNCTION(0, "GPIO22"),
+                MTK_FUNCTION(1, "UCTS0"),
+                MTK_FUNCTION(2, "PCIE0_PERST_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(23, "EINT1"),
+                "J16", "mt7623",
+                MTK_EINT_FUNCTION(0, 1),
+                MTK_FUNCTION(0, "GPIO23"),
+                MTK_FUNCTION(1, "URTS0"),
+                MTK_FUNCTION(2, "PCIE1_PERST_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(24, "EINT2"),
+                "H16", "mt7623",
+                MTK_EINT_FUNCTION(0, 2),
+                MTK_FUNCTION(0, "GPIO24"),
+                MTK_FUNCTION(1, "UCTS1"),
+                MTK_FUNCTION(2, "PCIE2_PERST_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(25, "EINT3"),
+                "K15", "mt7623",
+                MTK_EINT_FUNCTION(0, 3),
+                MTK_FUNCTION(0, "GPIO25"),
+                MTK_FUNCTION(1, "URTS1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(26, "EINT4"),
+                "G15", "mt7623",
+                MTK_EINT_FUNCTION(0, 4),
+                MTK_FUNCTION(0, "GPIO26"),
+                MTK_FUNCTION(1, "UCTS3"),
+                MTK_FUNCTION(6, "PCIE2_WAKE_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(27, "EINT5"),
+                "F15", "mt7623",
+                MTK_EINT_FUNCTION(0, 5),
+                MTK_FUNCTION(0, "GPIO27"),
+                MTK_FUNCTION(1, "URTS3"),
+                MTK_FUNCTION(6, "PCIE1_WAKE_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(28, "EINT6"),
+                "J15", "mt7623",
+                MTK_EINT_FUNCTION(0, 6),
+                MTK_FUNCTION(0, "GPIO28"),
+                MTK_FUNCTION(1, "DRV_VBUS"),
+                MTK_FUNCTION(6, "PCIE0_WAKE_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(29, "EINT7"),
+                "E15", "mt7623",
+                MTK_EINT_FUNCTION(0, 7),
+                MTK_FUNCTION(0, "GPIO29"),
+                MTK_FUNCTION(1, "IDDIG"),
+                MTK_FUNCTION(2, "MSDC1_WP"),
+                MTK_FUNCTION(6, "PCIE2_PERST_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(30, "GPIO30"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO30")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(31, "GPIO31"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO31")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(32, "GPIO32"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO32")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(33, "I2S1_DATA"),
+                "Y18", "mt7623",
+                MTK_EINT_FUNCTION(0, 15),
+                MTK_FUNCTION(0, "GPIO33"),
+                MTK_FUNCTION(1, "I2S1_DATA"),
+                MTK_FUNCTION(3, "PCM_TX"),
+                MTK_FUNCTION(6, "AP_PCM_TX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(34, "I2S1_DATA_IN"),
+                "Y17", "mt7623",
+                MTK_EINT_FUNCTION(0, 16),
+                MTK_FUNCTION(0, "GPIO34"),
+                MTK_FUNCTION(1, "I2S1_DATA_IN"),
+                MTK_FUNCTION(3, "PCM_RX"),
+                MTK_FUNCTION(6, "AP_PCM_RX")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(35, "I2S1_BCK"),
+                "V17", "mt7623",
+                MTK_EINT_FUNCTION(0, 17),
+                MTK_FUNCTION(0, "GPIO35"),
+                MTK_FUNCTION(1, "I2S1_BCK"),
+                MTK_FUNCTION(3, "PCM_CLK0"),
+                MTK_FUNCTION(6, "AP_PCM_CLKO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(36, "I2S1_LRCK"),
+                "W17", "mt7623",
+                MTK_EINT_FUNCTION(0, 18),
+                MTK_FUNCTION(0, "GPIO36"),
+                MTK_FUNCTION(1, "I2S1_LRCK"),
+                MTK_FUNCTION(3, "PCM_SYNC"),
+                MTK_FUNCTION(6, "AP_PCM_SYNC")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(37, "I2S1_MCLK"),
+                "AA18", "mt7623",
+                MTK_EINT_FUNCTION(0, 19),
+                MTK_FUNCTION(0, "GPIO37"),
+                MTK_FUNCTION(1, "I2S1_MCLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(38, "GPIO38"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO38")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(39, "JTMS"),
+                "G21", "mt7623",
+                MTK_EINT_FUNCTION(0, 21),
+                MTK_FUNCTION(0, "GPIO39"),
+                MTK_FUNCTION(1, "JTMS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(40, "GPIO40"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO40")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(41, "JTDI"),
+                "H22", "mt7623",
+                MTK_EINT_FUNCTION(0, 23),
+                MTK_FUNCTION(0, "GPIO41"),
+                MTK_FUNCTION(1, "JTDI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(42, "JTDO"),
+                "H21", "mt7623",
+                MTK_EINT_FUNCTION(0, 24),
+                MTK_FUNCTION(0, "GPIO42"),
+                MTK_FUNCTION(1, "JTDO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(43, "NCLE"),
+                "C7", "mt7623",
+                MTK_EINT_FUNCTION(0, 25),
+                MTK_FUNCTION(0, "GPIO43"),
+                MTK_FUNCTION(1, "NCLE"),
+                MTK_FUNCTION(2, "EXT_XCS2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(44, "NCEB1"),
+                "C6", "mt7623",
+                MTK_EINT_FUNCTION(0, 26),
+                MTK_FUNCTION(0, "GPIO44"),
+                MTK_FUNCTION(1, "NCEB1"),
+                MTK_FUNCTION(2, "IDDIG")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(45, "NCEB0"),
+                "D7", "mt7623",
+                MTK_EINT_FUNCTION(0, 27),
+                MTK_FUNCTION(0, "GPIO45"),
+                MTK_FUNCTION(1, "NCEB0"),
+                MTK_FUNCTION(2, "DRV_VBUS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(46, "IR"),
+                "D15", "mt7623",
+                MTK_EINT_FUNCTION(0, 28),
+                MTK_FUNCTION(0, "GPIO46"),
+                MTK_FUNCTION(1, "IR")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(47, "NREB"),
+                "A6", "mt7623",
+                MTK_EINT_FUNCTION(0, 29),
+                MTK_FUNCTION(0, "GPIO47"),
+                MTK_FUNCTION(1, "NREB")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(48, "NRNB"),
+                "B6", "mt7623",
+                MTK_EINT_FUNCTION(0, 30),
+                MTK_FUNCTION(0, "GPIO48"),
+                MTK_FUNCTION(1, "NRNB")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(49, "I2S0_DATA"),
+                "AB18", "mt7623",
+                MTK_EINT_FUNCTION(0, 31),
+                MTK_FUNCTION(0, "GPIO49"),
+                MTK_FUNCTION(1, "I2S0_DATA"),
+                MTK_FUNCTION(3, "PCM_TX"),
+                MTK_FUNCTION(6, "AP_I2S_DO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(50, "GPIO50"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO50")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(51, "GPIO51"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO51")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(52, "GPIO52"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO52")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(53, "SPI0_CSN"),
+                "E7", "mt7623",
+                MTK_EINT_FUNCTION(0, 35),
+                MTK_FUNCTION(0, "GPIO53"),
+                MTK_FUNCTION(1, "SPI0_CS"),
+                MTK_FUNCTION(5, "PWM1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(54, "SPI0_CK"),
+                "F7", "mt7623",
+                MTK_EINT_FUNCTION(0, 36),
+                MTK_FUNCTION(0, "GPIO54"),
+                MTK_FUNCTION(1, "SPI0_CK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(55, "SPI0_MI"),
+                "E6", "mt7623",
+                MTK_EINT_FUNCTION(0, 37),
+                MTK_FUNCTION(0, "GPIO55"),
+                MTK_FUNCTION(1, "SPI0_MI"),
+                MTK_FUNCTION(2, "SPI0_MO"),
+                MTK_FUNCTION(3, "MSDC1_WP"),
+                MTK_FUNCTION(5, "PWM2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(56, "SPI0_MO"),
+                "G7", "mt7623",
+                MTK_EINT_FUNCTION(0, 38),
+                MTK_FUNCTION(0, "GPIO56"),
+                MTK_FUNCTION(1, "SPI0_MO"),
+                MTK_FUNCTION(2, "SPI0_MI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(57, "GPIO57"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO57")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(58, "GPIO58"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO58")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(59, "GPIO59"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO59")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(60, "WB_RSTB"),
+                "Y21", "mt7623",
+                MTK_EINT_FUNCTION(0, 41),
+                MTK_FUNCTION(0, "GPIO60"),
+                MTK_FUNCTION(1, "WB_RSTB")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(61, "GPIO61"),
+                "AA21", "mt7623",
+                MTK_EINT_FUNCTION(0, 42),
+                MTK_FUNCTION(0, "GPIO61"),
+                MTK_FUNCTION(1, "TEST_FD")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(62, "GPIO62"),
+                "AB22", "mt7623",
+                MTK_EINT_FUNCTION(0, 43),
+                MTK_FUNCTION(0, "GPIO62"),
+                MTK_FUNCTION(1, "TEST_FC")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(63, "WB_SCLK"),
+                "AC23", "mt7623",
+                MTK_EINT_FUNCTION(0, 44),
+                MTK_FUNCTION(0, "GPIO63"),
+                MTK_FUNCTION(1, "WB_SCLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(64, "WB_SDATA"),
+                "AB21", "mt7623",
+                MTK_EINT_FUNCTION(0, 45),
+                MTK_FUNCTION(0, "GPIO64"),
+                MTK_FUNCTION(1, "WB_SDATA")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(65, "WB_SEN"),
+                "AB24", "mt7623",
+                MTK_EINT_FUNCTION(0, 46),
+                MTK_FUNCTION(0, "GPIO65"),
+                MTK_FUNCTION(1, "WB_SEN")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(66, "WB_CRTL0"),
+                "AB20", "mt7623",
+                MTK_EINT_FUNCTION(0, 47),
+                MTK_FUNCTION(0, "GPIO66"),
+                MTK_FUNCTION(1, "WB_CRTL0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(67, "WB_CRTL1"),
+                "AC20", "mt7623",
+                MTK_EINT_FUNCTION(0, 48),
+                MTK_FUNCTION(0, "GPIO67"),
+                MTK_FUNCTION(1, "WB_CRTL1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(68, "WB_CRTL2"),
+                "AB19", "mt7623",
+                MTK_EINT_FUNCTION(0, 49),
+                MTK_FUNCTION(0, "GPIO68"),
+                MTK_FUNCTION(1, "WB_CRTL2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(69, "WB_CRTL3"),
+                "AC19", "mt7623",
+                MTK_EINT_FUNCTION(0, 50),
+                MTK_FUNCTION(0, "GPIO69"),
+                MTK_FUNCTION(1, "WB_CRTL3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(70, "WB_CRTL4"),
+                "AD19", "mt7623",
+                MTK_EINT_FUNCTION(0, 51),
+                MTK_FUNCTION(0, "GPIO70"),
+                MTK_FUNCTION(1, "WB_CRTL4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(71, "WB_CRTL5"),
+                "AE19", "mt7623",
+                MTK_EINT_FUNCTION(0, 52),
+                MTK_FUNCTION(0, "GPIO71"),
+                MTK_FUNCTION(1, "WB_CRTL5")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(72, "I2S0_DATA_IN"),
+                "AA20", "mt7623",
+                MTK_EINT_FUNCTION(0, 53),
+                MTK_FUNCTION(0, "GPIO72"),
+                MTK_FUNCTION(1, "I2S0_DATA_IN"),
+                MTK_FUNCTION(3, "PCM_RX"),
+                MTK_FUNCTION(4, "PWM0"),
+                MTK_FUNCTION(5, "DISP_PWM"),
+                MTK_FUNCTION(6, "AP_I2S_DI")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(73, "I2S0_LRCK"),
+                "Y20", "mt7623",
+                MTK_EINT_FUNCTION(0, 54),
+                MTK_FUNCTION(0, "GPIO73"),
+                MTK_FUNCTION(1, "I2S0_LRCK"),
+                MTK_FUNCTION(3, "PCM_SYNC"),
+                MTK_FUNCTION(6, "AP_I2S_LRCK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(74, "I2S0_BCK"),
+                "Y19", "mt7623",
+                MTK_EINT_FUNCTION(0, 55),
+                MTK_FUNCTION(0, "GPIO74"),
+                MTK_FUNCTION(1, "I2S0_BCK"),
+                MTK_FUNCTION(3, "PCM_CLK0"),
+                MTK_FUNCTION(6, "AP_I2S_BCK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(75, "SDA0"),
+                "K19", "mt7623",
+                MTK_EINT_FUNCTION(0, 56),
+                MTK_FUNCTION(0, "GPIO75"),
+                MTK_FUNCTION(1, "SDA0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(76, "SCL0"),
+                "K20", "mt7623",
+                MTK_EINT_FUNCTION(0, 57),
+                MTK_FUNCTION(0, "GPIO76"),
+                MTK_FUNCTION(1, "SCL0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(77, "GPIO77"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO77")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(78, "GPIO78"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO78")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(79, "GPIO79"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO79")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(80, "GPIO80"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO80")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(81, "GPIO81"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO81")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(82, "GPIO82"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO82")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(83, "LCM_RST"),
+                "V16", "mt7623",
+                MTK_EINT_FUNCTION(0, 64),
+                MTK_FUNCTION(0, "GPIO83"),
+                MTK_FUNCTION(1, "LCM_RST")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(84, "DSI_TE"),
+                "V14", "mt7623",
+                MTK_EINT_FUNCTION(0, 65),
+                MTK_FUNCTION(0, "GPIO84"),
+                MTK_FUNCTION(1, "DSI_TE")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(85, "GPIO85"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO85")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(86, "GPIO86"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO86")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(87, "GPIO87"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO87")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(88, "GPIO88"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO88")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(89, "GPIO89"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO89")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(90, "GPIO90"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO90")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(91, "GPIO91"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO91")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(92, "GPIO92"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO92")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(93, "GPIO93"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO93")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(94, "GPIO94"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO94")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(95, "MIPI_TCN"),
+                "AB14", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO95"),
+                MTK_FUNCTION(1, "TCN")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(96, "MIPI_TCP"),
+                "AC14", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO96"),
+                MTK_FUNCTION(1, "TCP")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(97, "MIPI_TDN1"),
+                "AE15", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO97"),
+                MTK_FUNCTION(1, "TDN1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(98, "MIPI_TDP1"),
+                "AD15", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO98"),
+                MTK_FUNCTION(1, "TDP1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(99, "MIPI_TDN0"),
+                "AB15", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO99"),
+                MTK_FUNCTION(1, "TDN0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(100, "MIPI_TDP0"),
+                "AC15", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO100"),
+                MTK_FUNCTION(1, "TDP0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(101, "GPIO101"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO101")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(102, "GPIO102"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO102")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(103, "GPIO103"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO103")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(104, "GPIO104"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO104")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(105, "MSDC1_CMD"),
+                "AD2", "mt7623",
+                MTK_EINT_FUNCTION(0, 78),
+                MTK_FUNCTION(0, "GPIO105"),
+                MTK_FUNCTION(1, "MSDC1_CMD"),
+                MTK_FUNCTION(3, "SDA1"),
+                MTK_FUNCTION(6, "I2SOUT_BCK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(106, "MSDC1_CLK"),
+                "AD3", "mt7623",
+                MTK_EINT_FUNCTION(0, 79),
+                MTK_FUNCTION(0, "GPIO106"),
+                MTK_FUNCTION(1, "MSDC1_CLK"),
+                MTK_FUNCTION(3, "SCL1"),
+                MTK_FUNCTION(6, "I2SOUT_LRCK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(107, "MSDC1_DAT0"),
+                "AE2", "mt7623",
+                MTK_EINT_FUNCTION(0, 80),
+                MTK_FUNCTION(0, "GPIO107"),
+                MTK_FUNCTION(1, "MSDC1_DAT0"),
+                MTK_FUNCTION(5, "UTXD0"),
+                MTK_FUNCTION(6, "I2SOUT_DATA_OUT")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(108, "MSDC1_DAT1"),
+                "AC1", "mt7623",
+                MTK_EINT_FUNCTION(0, 81),
+                MTK_FUNCTION(0, "GPIO108"),
+                MTK_FUNCTION(1, "MSDC1_DAT1"),
+                MTK_FUNCTION(3, "PWM0"),
+                MTK_FUNCTION(5, "URXD0"),
+                MTK_FUNCTION(6, "PWM1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(109, "MSDC1_DAT2"),
+                "AC3", "mt7623",
+                MTK_EINT_FUNCTION(0, 82),
+                MTK_FUNCTION(0, "GPIO109"),
+                MTK_FUNCTION(1, "MSDC1_DAT2"),
+                MTK_FUNCTION(3, "SDA2"),
+                MTK_FUNCTION(5, "UTXD1"),
+                MTK_FUNCTION(6, "PWM2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(110, "MSDC1_DAT3"),
+                "AC4", "mt7623",
+                MTK_EINT_FUNCTION(0, 83),
+                MTK_FUNCTION(0, "GPIO110"),
+                MTK_FUNCTION(1, "MSDC1_DAT3"),
+                MTK_FUNCTION(3, "SCL2"),
+                MTK_FUNCTION(5, "URXD1"),
+                MTK_FUNCTION(6, "PWM3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(111, "MSDC0_DAT7"),
+                "A2", "mt7623",
+                MTK_EINT_FUNCTION(0, 84),
+                MTK_FUNCTION(0, "GPIO111"),
+                MTK_FUNCTION(1, "MSDC0_DAT7"),
+                MTK_FUNCTION(4, "NLD7")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(112, "MSDC0_DAT6"),
+                "B3", "mt7623",
+                MTK_EINT_FUNCTION(0, 85),
+                MTK_FUNCTION(0, "GPIO112"),
+                MTK_FUNCTION(1, "MSDC0_DAT6"),
+                MTK_FUNCTION(4, "NLD6")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(113, "MSDC0_DAT5"),
+                "C4", "mt7623",
+                MTK_EINT_FUNCTION(0, 86),
+                MTK_FUNCTION(0, "GPIO113"),
+                MTK_FUNCTION(1, "MSDC0_DAT5"),
+                MTK_FUNCTION(4, "NLD5")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(114, "MSDC0_DAT4"),
+                "A4", "mt7623",
+                MTK_EINT_FUNCTION(0, 87),
+                MTK_FUNCTION(0, "GPIO114"),
+                MTK_FUNCTION(1, "MSDC0_DAT4"),
+                MTK_FUNCTION(4, "NLD4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(115, "MSDC0_RSTB"),
+                "C5", "mt7623",
+                MTK_EINT_FUNCTION(0, 88),
+                MTK_FUNCTION(0, "GPIO115"),
+                MTK_FUNCTION(1, "MSDC0_RSTB"),
+                MTK_FUNCTION(4, "NLD8")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(116, "MSDC0_CMD"),
+                "D5", "mt7623",
+                MTK_EINT_FUNCTION(0, 89),
+                MTK_FUNCTION(0, "GPIO116"),
+                MTK_FUNCTION(1, "MSDC0_CMD"),
+                MTK_FUNCTION(4, "NALE")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(117, "MSDC0_CLK"),
+                "B1", "mt7623",
+                MTK_EINT_FUNCTION(0, 90),
+                MTK_FUNCTION(0, "GPIO117"),
+                MTK_FUNCTION(1, "MSDC0_CLK"),
+                MTK_FUNCTION(4, "NWEB")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(118, "MSDC0_DAT3"),
+                "D6", "mt7623",
+                MTK_EINT_FUNCTION(0, 91),
+                MTK_FUNCTION(0, "GPIO118"),
+                MTK_FUNCTION(1, "MSDC0_DAT3"),
+                MTK_FUNCTION(4, "NLD3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(119, "MSDC0_DAT2"),
+                "B2", "mt7623",
+                MTK_EINT_FUNCTION(0, 92),
+                MTK_FUNCTION(0, "GPIO119"),
+                MTK_FUNCTION(1, "MSDC0_DAT2"),
+                MTK_FUNCTION(4, "NLD2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(120, "MSDC0_DAT1"),
+                "A3", "mt7623",
+                MTK_EINT_FUNCTION(0, 93),
+                MTK_FUNCTION(0, "GPIO120"),
+                MTK_FUNCTION(1, "MSDC0_DAT1"),
+                MTK_FUNCTION(4, "NLD1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(121, "MSDC0_DAT0"),
+                "B4", "mt7623",
+                MTK_EINT_FUNCTION(0, 94),
+                MTK_FUNCTION(0, "GPIO121"),
+                MTK_FUNCTION(1, "MSDC0_DAT0"),
+                MTK_FUNCTION(4, "NLD0"),
+                MTK_FUNCTION(5, "WATCHDOG")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(122, "GPIO122"),
+                "H17", "mt7623",
+                MTK_EINT_FUNCTION(0, 95),
+                MTK_FUNCTION(0, "GPIO122"),
+                MTK_FUNCTION(1, "TEST"),
+                MTK_FUNCTION(4, "SDA2"),
+                MTK_FUNCTION(5, "URXD0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(123, "GPIO123"),
+                "F17", "mt7623",
+                MTK_EINT_FUNCTION(0, 96),
+                MTK_FUNCTION(0, "GPIO123"),
+                MTK_FUNCTION(1, "TEST"),
+                MTK_FUNCTION(4, "SCL2"),
+                MTK_FUNCTION(5, "UTXD0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(124, "GPIO124"),
+                "H18", "mt7623",
+                MTK_EINT_FUNCTION(0, 97),
+                MTK_FUNCTION(0, "GPIO124"),
+                MTK_FUNCTION(1, "TEST"),
+                MTK_FUNCTION(4, "SDA1"),
+                MTK_FUNCTION(5, "PWM3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(125, "GPIO125"),
+                "G17", "mt7623",
+                MTK_EINT_FUNCTION(0, 98),
+                MTK_FUNCTION(0, "GPIO125"),
+                MTK_FUNCTION(1, "TEST"),
+                MTK_FUNCTION(4, "SCL1"),
+                MTK_FUNCTION(5, "PWM4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(126, "I2S0_MCLK"),
+                "AA19", "mt7623",
+                MTK_EINT_FUNCTION(0, 99),
+                MTK_FUNCTION(0, "GPIO126"),
+                MTK_FUNCTION(1, "I2S0_MCLK"),
+                MTK_FUNCTION(6, "AP_I2S_MCLK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(127, "GPIO127"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO127")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(128, "GPIO128"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO128")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(129, "GPIO129"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO129")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(130, "GPIO130"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO130")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(131, "GPIO131"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO131")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(132, "GPIO132"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO132")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(133, "GPIO133"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO133")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(134, "GPIO134"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO134")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(135, "GPIO135"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO135")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(136, "GPIO136"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO136")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(137, "GPIO137"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO137")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(138, "GPIO138"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO138")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(139, "GPIO139"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO139")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(140, "GPIO140"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO140")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(141, "GPIO141"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO141")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(142, "GPIO142"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO142")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(143, "GPIO143"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO143")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(144, "GPIO144"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO144")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(145, "GPIO145"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO145")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(146, "GPIO146"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO146")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(147, "GPIO147"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO147")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(148, "GPIO148"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO148")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(149, "GPIO149"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO149")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(150, "GPIO150"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO150")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(151, "GPIO151"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO151")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(152, "GPIO152"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO152")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(153, "GPIO153"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO153")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(154, "GPIO154"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO154")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(155, "GPIO155"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO155")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(156, "GPIO156"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO156")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(157, "GPIO157"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO157")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(158, "GPIO158"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO158")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(159, "GPIO159"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO159")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(160, "GPIO160"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO160")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(161, "GPIO161"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO161")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(162, "GPIO162"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO162")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(163, "GPIO163"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO163")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(164, "GPIO164"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO164")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(165, "GPIO165"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO165")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(166, "GPIO166"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO166")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(167, "GPIO167"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO167")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(168, "GPIO168"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO168")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(169, "GPIO169"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO169")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(170, "GPIO170"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO170")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(171, "GPIO171"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO171")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(172, "GPIO172"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO172")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(173, "GPIO173"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO173")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(174, "GPIO174"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO174")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(175, "GPIO175"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO175")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(176, "GPIO176"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO176")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(177, "GPIO177"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO177")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(178, "GPIO178"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO178")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(179, "GPIO179"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO179")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(180, "GPIO180"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO180")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(181, "GPIO181"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO181")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(182, "GPIO182"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO182")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(183, "GPIO183"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO183")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(184, "GPIO184"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO184")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(185, "GPIO185"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO185")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(186, "GPIO186"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO186")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(187, "GPIO187"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO187")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(188, "GPIO188"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO188")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(189, "GPIO189"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO189")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(190, "GPIO190"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO190")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(191, "GPIO191"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO191")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(192, "GPIO192"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO192")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(193, "GPIO193"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO193")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(194, "GPIO194"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO194")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(195, "GPIO195"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO195")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(196, "GPIO196"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO196")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(197, "GPIO197"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO197")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(198, "GPIO198"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO198")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(199, "SPI1_CK"),
+                "E19", "mt7623",
+                MTK_EINT_FUNCTION(0, 111),
+                MTK_FUNCTION(0, "GPIO199"),
+                MTK_FUNCTION(1, "SPI1_CK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(200, "URXD2"),
+                "K18", "mt7623",
+                MTK_EINT_FUNCTION(0, 112),
+                MTK_FUNCTION(0, "GPIO200"),
+                MTK_FUNCTION(6, "URXD2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(201, "UTXD2"),
+                "L18", "mt7623",
+                MTK_EINT_FUNCTION(0, 113),
+                MTK_FUNCTION(0, "GPIO201"),
+                MTK_FUNCTION(6, "UTXD2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(202, "GPIO202"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO202")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(203, "PWM0"),
+                "AA16", "mt7623",
+                MTK_EINT_FUNCTION(0, 115),
+                MTK_FUNCTION(0, "GPIO203"),
+                MTK_FUNCTION(1, "PWM0"),
+                MTK_FUNCTION(2, "DISP_PWM")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(204, "PWM1"),
+                "Y16", "mt7623",
+                MTK_EINT_FUNCTION(0, 116),
+                MTK_FUNCTION(0, "GPIO204"),
+                MTK_FUNCTION(1, "PWM1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(205, "PWM2"),
+                "AA15", "mt7623",
+                MTK_EINT_FUNCTION(0, 117),
+                MTK_FUNCTION(0, "GPIO205"),
+                MTK_FUNCTION(1, "PWM2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(206, "PWM3"),
+                "AA17", "mt7623",
+                MTK_EINT_FUNCTION(0, 118),
+                MTK_FUNCTION(0, "GPIO206"),
+                MTK_FUNCTION(1, "PWM3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(207, "PWM4"),
+                "Y15", "mt7623",
+                MTK_EINT_FUNCTION(0, 119),
+                MTK_FUNCTION(0, "GPIO207"),
+                MTK_FUNCTION(1, "PWM4")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(208, "AUD_EXT_CK1"),
+                "W14", "mt7623",
+                MTK_EINT_FUNCTION(0, 120),
+                MTK_FUNCTION(0, "GPIO208"),
+                MTK_FUNCTION(1, "AUD_EXT_CK1"),
+                MTK_FUNCTION(2, "PWM0"),
+                MTK_FUNCTION(3, "PCIE0_PERST_N"),
+                MTK_FUNCTION(5, "DISP_PWM")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(209, "AUD_EXT_CK2"),
+                "V15", "mt7623",
+                MTK_EINT_FUNCTION(0, 121),
+                MTK_FUNCTION(0, "GPIO209"),
+                MTK_FUNCTION(1, "AUD_EXT_CK2"),
+                MTK_FUNCTION(2, "MSDC1_WP"),
+                MTK_FUNCTION(3, "PCIE1_PERST_N"),
+                MTK_FUNCTION(5, "PWM1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(210, "GPIO210"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO210")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(211, "GPIO211"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO211")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(212, "GPIO212"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO212")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(213, "GPIO213"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO213")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(214, "GPIO214"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO214")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(215, "GPIO215"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO215")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(216, "GPIO216"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO216")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(217, "GPIO217"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO217")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(218, "GPIO218"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO218")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(219, "GPIO219"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO219")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(220, "GPIO220"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO220")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(221, "GPIO221"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO221")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(222, "GPIO222"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO222")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(223, "GPIO223"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO223")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(224, "GPIO224"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO224")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(225, "GPIO225"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO225")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(226, "GPIO226"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO226")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(227, "GPIO227"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO227")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(228, "GPIO228"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO228")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(229, "GPIO229"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO229")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(230, "GPIO230"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO230")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(231, "GPIO231"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO231")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(232, "GPIO232"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO232")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(233, "GPIO233"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO233")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(234, "GPIO234"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO234")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(235, "GPIO235"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO235")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(236, "EXT_SDIO3"),
+                "A8", "mt7623",
+                MTK_EINT_FUNCTION(0, 122),
+                MTK_FUNCTION(0, "GPIO236"),
+                MTK_FUNCTION(1, "EXT_SDIO3"),
+                MTK_FUNCTION(2, "IDDIG")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(237, "EXT_SDIO2"),
+                "D8", "mt7623",
+                MTK_EINT_FUNCTION(0, 123),
+                MTK_FUNCTION(0, "GPIO237"),
+                MTK_FUNCTION(1, "EXT_SDIO2"),
+                MTK_FUNCTION(2, "DRV_VBUS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(238, "EXT_SDIO1"),
+                "D9", "mt7623",
+                MTK_EINT_FUNCTION(0, 124),
+                MTK_FUNCTION(0, "GPIO238"),
+                MTK_FUNCTION(1, "EXT_SDIO1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(239, "EXT_SDIO0"),
+                "B8", "mt7623",
+                MTK_EINT_FUNCTION(0, 125),
+                MTK_FUNCTION(0, "GPIO239"),
+                MTK_FUNCTION(1, "EXT_SDIO0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(240, "EXT_XCS"),
+                "C9", "mt7623",
+                MTK_EINT_FUNCTION(0, 126),
+                MTK_FUNCTION(0, "GPIO240"),
+                MTK_FUNCTION(1, "EXT_XCS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(241, "EXT_SCK"),
+                "C8", "mt7623",
+                MTK_EINT_FUNCTION(0, 127),
+                MTK_FUNCTION(0, "GPIO241"),
+                MTK_FUNCTION(1, "EXT_SCK")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(242, "URTS2"),
+                "G18", "mt7623",
+                MTK_EINT_FUNCTION(0, 128),
+                MTK_FUNCTION(0, "GPIO242"),
+                MTK_FUNCTION(1, "URTS2"),
+                MTK_FUNCTION(2, "UTXD3"),
+                MTK_FUNCTION(3, "URXD3"),
+                MTK_FUNCTION(4, "SCL1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(243, "UCTS2"),
+                "H19", "mt7623",
+                MTK_EINT_FUNCTION(0, 129),
+                MTK_FUNCTION(0, "GPIO243"),
+                MTK_FUNCTION(1, "UCTS2"),
+                MTK_FUNCTION(2, "URXD3"),
+                MTK_FUNCTION(3, "UTXD3"),
+                MTK_FUNCTION(4, "SDA1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(244, "GPIO244"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO244")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(245, "GPIO245"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO245")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(246, "GPIO246"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO246")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(247, "GPIO247"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO247")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(248, "GPIO248"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO248")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(249, "GPIO249"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO249")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(250, "GPIO250"),
+                "A15", "mt7623",
+                MTK_EINT_FUNCTION(0, 135),
+                MTK_FUNCTION(0, "GPIO250"),
+                MTK_FUNCTION(1, "TEST_MD7"),
+                MTK_FUNCTION(6, "PCIE0_CLKREQ_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(251, "GPIO251"),
+                "B15", "mt7623",
+                MTK_EINT_FUNCTION(0, 136),
+                MTK_FUNCTION(0, "GPIO251"),
+                MTK_FUNCTION(1, "TEST_MD6"),
+                MTK_FUNCTION(6, "PCIE0_WAKE_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(252, "GPIO252"),
+                "C16", "mt7623",
+                MTK_EINT_FUNCTION(0, 137),
+                MTK_FUNCTION(0, "GPIO252"),
+                MTK_FUNCTION(1, "TEST_MD5"),
+                MTK_FUNCTION(6, "PCIE1_CLKREQ_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(253, "GPIO253"),
+                "D17", "mt7623",
+                MTK_EINT_FUNCTION(0, 138),
+                MTK_FUNCTION(0, "GPIO253"),
+                MTK_FUNCTION(1, "TEST_MD4"),
+                MTK_FUNCTION(6, "PCIE1_WAKE_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(254, "GPIO254"),
+                "D16", "mt7623",
+                MTK_EINT_FUNCTION(0, 139),
+                MTK_FUNCTION(0, "GPIO254"),
+                MTK_FUNCTION(1, "TEST_MD3"),
+                MTK_FUNCTION(6, "PCIE2_CLKREQ_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(255, "GPIO255"),
+                "C17", "mt7623",
+                MTK_EINT_FUNCTION(0, 140),
+                MTK_FUNCTION(0, "GPIO255"),
+                MTK_FUNCTION(1, "TEST_MD2"),
+                MTK_FUNCTION(6, "PCIE2_WAKE_N")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(256, "GPIO256"),
+                "B17", "mt7623",
+                MTK_EINT_FUNCTION(0, 141),
+                MTK_FUNCTION(0, "GPIO256"),
+                MTK_FUNCTION(1, "TEST_MD1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(257, "GPIO257"),
+                "C15", "mt7623",
+                MTK_EINT_FUNCTION(0, 142),
+                MTK_FUNCTION(0, "GPIO257"),
+                MTK_FUNCTION(1, "TEST_MD0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(258, "GPIO258"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO258")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(259, "GPIO259"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO259")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(260, "GPIO260"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO260")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(261, "MSDC1_INS"),
+                "AD1", "mt7623",
+                MTK_EINT_FUNCTION(0, 146),
+                MTK_FUNCTION(0, "GPIO261"),
+                MTK_FUNCTION(1, "MSDC1_INS")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(262, "G2_TXEN"),
+                "A23", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO262"),
+                MTK_FUNCTION(1, "G2_TXEN")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(263, "G2_TXD3"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO263"),
+                MTK_FUNCTION(1, "G2_TXD3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(264, "G2_TXD2"),
+                "C24", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO264"),
+                MTK_FUNCTION(1, "G2_TXD2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(265, "G2_TXD1"),
+                "B25", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO265"),
+                MTK_FUNCTION(1, "G2_TXD1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(266, "G2_TXD0"),
+                "A24", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO266"),
+                MTK_FUNCTION(1, "G2_TXD0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(267, "G2_TXCLK"),
+                "C23", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO267"),
+                MTK_FUNCTION(1, "G2_TXC")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(268, "G2_RXCLK"),
+                "B23", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO268"),
+                MTK_FUNCTION(1, "G2_RXC")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(269, "G2_RXD0"),
+                "D21", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO269"),
+                MTK_FUNCTION(1, "G2_RXD0")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(270, "G2_RXD1"),
+                "B22", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO270"),
+                MTK_FUNCTION(1, "G2_RXD1")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(271, "G2_RXD2"),
+                "A22", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO271"),
+                MTK_FUNCTION(1, "G2_RXD2")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(272, "G2_RXD3"),
+                "C22", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO272"),
+                MTK_FUNCTION(1, "G2_RXD3")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(273, "GPIO273"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO273")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(274, "G2_RXDV"),
+                "C21", "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO274"),
+                MTK_FUNCTION(1, "G2_RXDV")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(275, "G2_MDC"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO275"),
+                MTK_FUNCTION(1, "MDC")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(276, "G2_MDIO"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO276"),
+                MTK_FUNCTION(1, "MDIO")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(277, "GPIO277"),
+                NULL, "mt7623",
+                MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+                MTK_FUNCTION(0, "GPIO277")
+        ),
+        MTK_PIN(
+                PINCTRL_PIN(278, "JTAG_RESET"),
+                "H20", "mt7623",
+                MTK_EINT_FUNCTION(0, 147),
+                MTK_FUNCTION(0, "GPIO278"),
+                MTK_FUNCTION(1, "JTAG_RESET")
+        ),
+};
+
+#endif /* __PINCTRL_MTK_MT7623_H */
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index 50cab27c64d4..0bdb8fd3afd1 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -49,7 +49,6 @@
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/pinctrl/pinconf-generic.h>
@@ -104,15 +103,13 @@ static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin,
                                      struct meson_bank **bank)
 {
         struct meson_domain *d;
-        int i;
 
-        for (i = 0; i < pc->data->num_domains; i++) {
-                d = &pc->domains[i];
-                if (pin >= d->data->pin_base &&
-                    pin < d->data->pin_base + d->data->num_pins) {
-                        *domain = d;
-                        return meson_get_bank(d, pin, bank);
-                }
+        d = pc->domain;
+
+        if (pin >= d->data->pin_base &&
+            pin < d->data->pin_base + d->data->num_pins) {
+                *domain = d;
+                return meson_get_bank(d, pin, bank);
         }
 
         return -EINVAL;
@@ -204,7 +201,7 @@ static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
                 for (j = 0; j < group->num_pins; j++) {
                         if (group->pins[j] == pin) {
                                 /* We have found a group using the pin */
-                                domain = &pc->domains[group->domain];
+                                domain = pc->domain;
                                 regmap_update_bits(domain->reg_mux,
                                                    group->reg * 4,
                                                    BIT(group->bit), 0);
@@ -219,7 +216,7 @@ static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
         struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
         struct meson_pmx_func *func = &pc->data->funcs[func_num];
         struct meson_pmx_group *group = &pc->data->groups[group_num];
-        struct meson_domain *domain = &pc->domains[group->domain];
+        struct meson_domain *domain = pc->domain;
         int i, ret = 0;
 
         dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
@@ -537,76 +534,67 @@ static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
 
 static const struct of_device_id meson_pinctrl_dt_match[] = {
         {
-                .compatible = "amlogic,meson8-pinctrl",
-                .data = &meson8_pinctrl_data,
+                .compatible = "amlogic,meson8-cbus-pinctrl",
+                .data = &meson8_cbus_pinctrl_data,
+        },
+        {
+                .compatible = "amlogic,meson8b-cbus-pinctrl",
+                .data = &meson8b_cbus_pinctrl_data,
+        },
+        {
+                .compatible = "amlogic,meson8-aobus-pinctrl",
+                .data = &meson8_aobus_pinctrl_data,
         },
         {
-                .compatible = "amlogic,meson8b-pinctrl",
-                .data = &meson8b_pinctrl_data,
+                .compatible = "amlogic,meson8b-aobus-pinctrl",
+                .data = &meson8b_aobus_pinctrl_data,
         },
         { },
 };
-MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
 
 static int meson_gpiolib_register(struct meson_pinctrl *pc)
 {
         struct meson_domain *domain;
-        int i, ret;
+        int ret;
 
-        for (i = 0; i < pc->data->num_domains; i++) {
-                domain = &pc->domains[i];
-
-                domain->chip.label = domain->data->name;
-                domain->chip.parent = pc->dev;
-                domain->chip.request = meson_gpio_request;
-                domain->chip.free = meson_gpio_free;
-                domain->chip.direction_input = meson_gpio_direction_input;
-                domain->chip.direction_output = meson_gpio_direction_output;
-                domain->chip.get = meson_gpio_get;
-                domain->chip.set = meson_gpio_set;
-                domain->chip.base = domain->data->pin_base;
-                domain->chip.ngpio = domain->data->num_pins;
-                domain->chip.can_sleep = false;
-                domain->chip.of_node = domain->of_node;
-                domain->chip.of_gpio_n_cells = 2;
-
-                ret = gpiochip_add_data(&domain->chip, domain);
-                if (ret) {
-                        dev_err(pc->dev, "can't add gpio chip %s\n",
-                                domain->data->name);
-                        goto fail;
-                }
+        domain = pc->domain;
+
+        domain->chip.label = domain->data->name;
+        domain->chip.parent = pc->dev;
+        domain->chip.request = meson_gpio_request;
+        domain->chip.free = meson_gpio_free;
+        domain->chip.direction_input = meson_gpio_direction_input;
+        domain->chip.direction_output = meson_gpio_direction_output;
+        domain->chip.get = meson_gpio_get;
+        domain->chip.set = meson_gpio_set;
+        domain->chip.base = domain->data->pin_base;
+        domain->chip.ngpio = domain->data->num_pins;
+        domain->chip.can_sleep = false;
+        domain->chip.of_node = domain->of_node;
+        domain->chip.of_gpio_n_cells = 2;
+
+        ret = gpiochip_add_data(&domain->chip, domain);
+        if (ret) {
+                dev_err(pc->dev, "can't add gpio chip %s\n",
+                        domain->data->name);
+                goto fail;
+        }
 
-                ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
-                                             0, domain->data->pin_base,
-                                             domain->chip.ngpio);
-                if (ret) {
-                        dev_err(pc->dev, "can't add pin range\n");
-                        goto fail;
-                }
+        ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
+                                     0, domain->data->pin_base,
+                                     domain->chip.ngpio);
+        if (ret) {
+                dev_err(pc->dev, "can't add pin range\n");
+                goto fail;
         }
 
         return 0;
 fail:
-        for (i--; i >= 0; i--)
-                gpiochip_remove(&pc->domains[i].chip);
+        gpiochip_remove(&pc->domain->chip);
 
         return ret;
 }
 
-static struct meson_domain_data *meson_get_domain_data(struct meson_pinctrl *pc,
-                                                       struct device_node *np)
-{
-        int i;
-
-        for (i = 0; i < pc->data->num_domains; i++) {
-                if (!strcmp(np->name, pc->data->domain_data[i].name))
-                        return &pc->data->domain_data[i];
-        }
-
-        return NULL;
-}
-
 static struct regmap_config meson_regmap_config = {
         .reg_bits = 32,
         .val_bits = 32,
@@ -643,7 +631,7 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
 {
         struct device_node *np;
         struct meson_domain *domain;
-        int i = 0, num_domains = 0;
+        int num_domains = 0;
 
         for_each_child_of_node(node, np) {
                 if (!of_find_property(np, "gpio-controller", NULL))
@@ -651,29 +639,22 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
                 num_domains++;
         }
 
-        if (num_domains != pc->data->num_domains) {
+        if (num_domains != 1) {
                 dev_err(pc->dev, "wrong number of subnodes\n");
                 return -EINVAL;
         }
 
-        pc->domains = devm_kzalloc(pc->dev, num_domains *
-                                   sizeof(struct meson_domain), GFP_KERNEL);
-        if (!pc->domains)
+        pc->domain = devm_kzalloc(pc->dev, sizeof(struct meson_domain), GFP_KERNEL);
+        if (!pc->domain)
                 return -ENOMEM;
 
+        domain = pc->domain;
+        domain->data = pc->data->domain_data;
+
         for_each_child_of_node(node, np) {
                 if (!of_find_property(np, "gpio-controller", NULL))
                         continue;
 
-                domain = &pc->domains[i];
-
-                domain->data = meson_get_domain_data(pc, np);
-                if (!domain->data) {
-                        dev_err(pc->dev, "domain data not found for node %s\n",
-                                np->name);
-                        return -ENODEV;
-                }
-
                 domain->of_node = np;
 
                 domain->reg_mux = meson_map_resource(pc, np, "mux");
@@ -699,7 +680,7 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
                         return PTR_ERR(domain->reg_gpio);
                 }
 
-                i++;
+                break;
         }
 
         return 0;
@@ -718,7 +699,7 @@ static int meson_pinctrl_probe(struct platform_device *pdev)
 
         pc->dev = dev;
         match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node);
-        pc->data = (struct meson_pinctrl_data *)match->data;
+        pc->data = (struct meson_pinctrl_data *) match->data;
 
         ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node);
         if (ret)
@@ -754,8 +735,4 @@ static struct platform_driver meson_pinctrl_driver = {
                 .of_match_table = meson_pinctrl_dt_match,
         },
 };
-module_platform_driver(meson_pinctrl_driver);
-
-MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
-MODULE_DESCRIPTION("Amlogic Meson pinctrl driver");
-MODULE_LICENSE("GPL v2");
+builtin_platform_driver(meson_pinctrl_driver);
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index 0fe7d53849ce..9c93e0d494a3 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -34,7 +34,6 @@ struct meson_pmx_group {
         bool is_gpio;
         unsigned int reg;
         unsigned int bit;
-        unsigned int domain;
 };
 
 /**
@@ -144,7 +143,6 @@ struct meson_pinctrl_data {
         unsigned int num_pins;
         unsigned int num_groups;
         unsigned int num_funcs;
-        unsigned int num_domains;
 };
 
 struct meson_pinctrl {
@@ -152,7 +150,7 @@ struct meson_pinctrl {
         struct pinctrl_dev *pcdev;
         struct pinctrl_desc desc;
         struct meson_pinctrl_data *data;
-        struct meson_domain *domains;
+        struct meson_domain *domain;
 };
 
 #define PIN(x, b)       (b + x)
@@ -164,7 +162,6 @@ struct meson_pinctrl {
                 .num_pins = ARRAY_SIZE(grp ## _pins),                   \
                 .reg = r,                                               \
                 .bit = b,                                               \
-                .domain = 0,                                            \
          }
 
 #define GPIO_GROUP(gpio, b)                                             \
@@ -175,16 +172,6 @@ struct meson_pinctrl {
                 .is_gpio = true,                                        \
          }
 
-#define GROUP_AO(grp, r, b)                                             \
-        {                                                               \
-                .name = #grp,                                           \
-                .pins = grp ## _pins,                                   \
-                .num_pins = ARRAY_SIZE(grp ## _pins),                   \
-                .reg = r,                                               \
-                .bit = b,                                               \
-                .domain = 1,                                            \
-         }
-
 #define FUNCTION(fn)                                                    \
         {                                                               \
                 .name = #fn,                                            \
@@ -208,5 +195,7 @@ struct meson_pinctrl {
 
 #define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
 
-extern struct meson_pinctrl_data meson8_pinctrl_data;
-extern struct meson_pinctrl_data meson8b_pinctrl_data;
+extern struct meson_pinctrl_data meson8_cbus_pinctrl_data;
+extern struct meson_pinctrl_data meson8_aobus_pinctrl_data;
+extern struct meson_pinctrl_data meson8b_cbus_pinctrl_data;
+extern struct meson_pinctrl_data meson8b_aobus_pinctrl_data;
diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c
index 7b1cc91733ef..32de191e0807 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8.c
@@ -16,7 +16,7 @@
 
 #define AO_OFF  120
 
-static const struct pinctrl_pin_desc meson8_pins[] = {
+static const struct pinctrl_pin_desc meson8_cbus_pins[] = {
         MESON_PIN(GPIOX_0, 0),
         MESON_PIN(GPIOX_1, 0),
         MESON_PIN(GPIOX_2, 0),
@@ -137,6 +137,9 @@ static const struct pinctrl_pin_desc meson8_pins[] = {
         MESON_PIN(BOOT_16, 0),
         MESON_PIN(BOOT_17, 0),
         MESON_PIN(BOOT_18, 0),
+};
+
+static const struct pinctrl_pin_desc meson8_aobus_pins[] = {
         MESON_PIN(GPIOAO_0, AO_OFF),
         MESON_PIN(GPIOAO_1, AO_OFF),
         MESON_PIN(GPIOAO_2, AO_OFF),
@@ -379,7 +382,7 @@ static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) };
 static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
 static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
 
-static struct meson_pmx_group meson8_groups[] = {
+static struct meson_pmx_group meson8_cbus_groups[] = {
         GPIO_GROUP(GPIOX_0, 0),
         GPIO_GROUP(GPIOX_1, 0),
         GPIO_GROUP(GPIOX_2, 0),
@@ -474,22 +477,6 @@ static struct meson_pmx_group meson8_groups[] = {
         GPIO_GROUP(GPIOZ_12, 0),
         GPIO_GROUP(GPIOZ_13, 0),
         GPIO_GROUP(GPIOZ_14, 0),
-        GPIO_GROUP(GPIOAO_0, AO_OFF),
-        GPIO_GROUP(GPIOAO_1, AO_OFF),
-        GPIO_GROUP(GPIOAO_2, AO_OFF),
-        GPIO_GROUP(GPIOAO_3, AO_OFF),
-        GPIO_GROUP(GPIOAO_4, AO_OFF),
-        GPIO_GROUP(GPIOAO_5, AO_OFF),
-        GPIO_GROUP(GPIOAO_6, AO_OFF),
-        GPIO_GROUP(GPIOAO_7, AO_OFF),
-        GPIO_GROUP(GPIOAO_8, AO_OFF),
-        GPIO_GROUP(GPIOAO_9, AO_OFF),
-        GPIO_GROUP(GPIOAO_10, AO_OFF),
-        GPIO_GROUP(GPIOAO_11, AO_OFF),
-        GPIO_GROUP(GPIOAO_12, AO_OFF),
-        GPIO_GROUP(GPIOAO_13, AO_OFF),
-        GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
-        GPIO_GROUP(GPIO_TEST_N, AO_OFF),
 
         /* bank X */
         GROUP(sd_d0_a,          8,      5),
@@ -675,26 +662,45 @@ static struct meson_pmx_group meson8_groups[] = {
         GROUP(sdxc_d0_b,        2,      7),
         GROUP(sdxc_clk_b,       2,      5),
         GROUP(sdxc_cmd_b,       2,      4),
+};
+
+static struct meson_pmx_group meson8_aobus_groups[] = {
+        GPIO_GROUP(GPIOAO_0, AO_OFF),
+        GPIO_GROUP(GPIOAO_1, AO_OFF),
+        GPIO_GROUP(GPIOAO_2, AO_OFF),
+        GPIO_GROUP(GPIOAO_3, AO_OFF),
+        GPIO_GROUP(GPIOAO_4, AO_OFF),
+        GPIO_GROUP(GPIOAO_5, AO_OFF),
+        GPIO_GROUP(GPIOAO_6, AO_OFF),
+        GPIO_GROUP(GPIOAO_7, AO_OFF),
+        GPIO_GROUP(GPIOAO_8, AO_OFF),
+        GPIO_GROUP(GPIOAO_9, AO_OFF),
+        GPIO_GROUP(GPIOAO_10, AO_OFF),
+        GPIO_GROUP(GPIOAO_11, AO_OFF),
+        GPIO_GROUP(GPIOAO_12, AO_OFF),
+        GPIO_GROUP(GPIOAO_13, AO_OFF),
+        GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
+        GPIO_GROUP(GPIO_TEST_N, AO_OFF),
 
         /* bank AO */
-        GROUP_AO(uart_tx_ao_a,          0,      12),
-        GROUP_AO(uart_rx_ao_a,          0,      11),
-        GROUP_AO(uart_cts_ao_a,         0,      10),
-        GROUP_AO(uart_rts_ao_a,         0,      9),
+        GROUP(uart_tx_ao_a,             0,      12),
+        GROUP(uart_rx_ao_a,             0,      11),
+        GROUP(uart_cts_ao_a,            0,      10),
+        GROUP(uart_rts_ao_a,            0,      9),
 
-        GROUP_AO(remote_input,          0,      0),
+        GROUP(remote_input,             0,      0),
 
-        GROUP_AO(i2c_slave_sck_ao,      0,      2),
-        GROUP_AO(i2c_slave_sda_ao,      0,      1),
+        GROUP(i2c_slave_sck_ao,         0,      2),
+        GROUP(i2c_slave_sda_ao,         0,      1),
 
-        GROUP_AO(uart_tx_ao_b0,         0,      26),
-        GROUP_AO(uart_rx_ao_b0,         0,      25),
+        GROUP(uart_tx_ao_b0,            0,      26),
+        GROUP(uart_rx_ao_b0,            0,      25),
 
-        GROUP_AO(uart_tx_ao_b1,         0,      24),
-        GROUP_AO(uart_rx_ao_b1,         0,      23),
+        GROUP(uart_tx_ao_b1,            0,      24),
+        GROUP(uart_rx_ao_b1,            0,      23),
 
-        GROUP_AO(i2c_mst_sck_ao,        0,      6),
-        GROUP_AO(i2c_mst_sda_ao,        0,      5),
+        GROUP(i2c_mst_sck_ao,           0,      6),
+        GROUP(i2c_mst_sda_ao,           0,      5),
 };
 
 static const char * const gpio_groups[] = {
@@ -872,7 +878,7 @@ static const char * const i2c_mst_ao_groups[] = {
         "i2c_mst_sck_ao", "i2c_mst_sda_ao"
 };
 
-static struct meson_pmx_func meson8_functions[] = {
+static struct meson_pmx_func meson8_cbus_functions[] = {
         FUNCTION(gpio),
         FUNCTION(sd_a),
         FUNCTION(sdxc_a),
@@ -899,6 +905,9 @@ static struct meson_pmx_func meson8_functions[] = {
         FUNCTION(nor),
         FUNCTION(sd_b),
         FUNCTION(sdxc_b),
+};
+
+static struct meson_pmx_func meson8_aobus_functions[] = {
         FUNCTION(uart_ao),
         FUNCTION(remote),
         FUNCTION(i2c_slave_ao),
@@ -906,7 +915,7 @@ static struct meson_pmx_func meson8_functions[] = {
         FUNCTION(i2c_mst_ao),
 };
 
-static struct meson_bank meson8_banks[] = {
+static struct meson_bank meson8_cbus_banks[] = {
         /*   name    first             last                 pullen  pull    dir     out     in  */
         BANK("X",    PIN(GPIOX_0, 0),  PIN(GPIOX_21, 0),    4,  0,  4,  0,  0,  0,  1,  0,  2,  0),
         BANK("Y",    PIN(GPIOY_0, 0),  PIN(GPIOY_16, 0),    3,  0,  3,  0,  3,  0,  4,  0,  5,  0),
@@ -917,35 +926,43 @@ static struct meson_bank meson8_banks[] = {
         BANK("BOOT", PIN(BOOT_0, 0),   PIN(BOOT_18, 0),     2,  0,  2,  0,  9,  0, 10,  0, 11,  0),
 };
 
-static struct meson_bank meson8_ao_banks[] = {
+static struct meson_bank meson8_aobus_banks[] = {
         /*   name    first                  last                      pullen  pull    dir     out     in  */
         BANK("AO",   PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),
 };
 
-static struct meson_domain_data meson8_domain_data[] = {
-        {
-                .name           = "banks",
-                .banks          = meson8_banks,
-                .num_banks      = ARRAY_SIZE(meson8_banks),
-                .pin_base       = 0,
-                .num_pins       = 120,
-        },
-        {
-                .name           = "ao-bank",
-                .banks          = meson8_ao_banks,
-                .num_banks      = ARRAY_SIZE(meson8_ao_banks),
-                .pin_base       = 120,
-                .num_pins       = 16,
-        },
-};
-
-struct meson_pinctrl_data meson8_pinctrl_data = {
-        .pins           = meson8_pins,
-        .groups         = meson8_groups,
-        .funcs          = meson8_functions,
-        .domain_data    = meson8_domain_data,
-        .num_pins       = ARRAY_SIZE(meson8_pins),
-        .num_groups     = ARRAY_SIZE(meson8_groups),
-        .num_funcs      = ARRAY_SIZE(meson8_functions),
-        .num_domains    = ARRAY_SIZE(meson8_domain_data),
+static struct meson_domain_data meson8_cbus_domain_data = {
+        .name           = "cbus-banks",
+        .banks          = meson8_cbus_banks,
+        .num_banks      = ARRAY_SIZE(meson8_cbus_banks),
+        .pin_base       = 0,
+        .num_pins       = 120,
+};
+
+static struct meson_domain_data meson8_aobus_domain_data = {
+        .name           = "ao-bank",
+        .banks          = meson8_aobus_banks,
+        .num_banks      = ARRAY_SIZE(meson8_aobus_banks),
+        .pin_base       = 120,
+        .num_pins       = 16,
+};
+
+struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
+        .pins           = meson8_cbus_pins,
+        .groups         = meson8_cbus_groups,
+        .funcs          = meson8_cbus_functions,
+        .domain_data    = &meson8_cbus_domain_data,
+        .num_pins       = ARRAY_SIZE(meson8_cbus_pins),
+        .num_groups     = ARRAY_SIZE(meson8_cbus_groups),
+        .num_funcs      = ARRAY_SIZE(meson8_cbus_functions),
+};
+
+struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
+        .pins           = meson8_aobus_pins,
+        .groups         = meson8_aobus_groups,
+        .funcs          = meson8_aobus_functions,
+        .domain_data    = &meson8_aobus_domain_data,
+        .num_pins       = ARRAY_SIZE(meson8_aobus_pins),
+        .num_groups     = ARRAY_SIZE(meson8_aobus_groups),
+        .num_funcs      = ARRAY_SIZE(meson8_aobus_functions),
 };
diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c
index 9677807db364..a100bcf4b17f 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8b.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8b.c
@@ -17,7 +17,7 @@
 
 #define AO_OFF  130
 
-static const struct pinctrl_pin_desc meson8b_pins[] = {
+static const struct pinctrl_pin_desc meson8b_cbus_pins[] = {
         MESON_PIN(GPIOX_0, 0),
         MESON_PIN(GPIOX_1, 0),
         MESON_PIN(GPIOX_2, 0),
@@ -107,7 +107,9 @@ static const struct pinctrl_pin_desc meson8b_pins[] = {
         MESON_PIN(DIF_3_N, 0),
         MESON_PIN(DIF_4_P, 0),
         MESON_PIN(DIF_4_N, 0),
+};
 
+static const struct pinctrl_pin_desc meson8b_aobus_pins[] = {
         MESON_PIN(GPIOAO_0, AO_OFF),
         MESON_PIN(GPIOAO_1, AO_OFF),
         MESON_PIN(GPIOAO_2, AO_OFF),
@@ -346,7 +348,7 @@ static const unsigned int eth_ref_clk_pins[]	= { PIN(DIF_3_N, 0) };
 static const unsigned int eth_mdc_pins[]        = { PIN(DIF_4_P, 0) };
 static const unsigned int eth_mdio_en_pins[]    = { PIN(DIF_4_N, 0) };
 
-static struct meson_pmx_group meson8b_groups[] = {
+static struct meson_pmx_group meson8b_cbus_groups[] = {
         GPIO_GROUP(GPIOX_0, 0),
         GPIO_GROUP(GPIOX_1, 0),
         GPIO_GROUP(GPIOX_2, 0),
@@ -409,23 +411,6 @@ static struct meson_pmx_group meson8b_groups[] = {
         GPIO_GROUP(DIF_4_P, 0),
         GPIO_GROUP(DIF_4_N, 0),
 
-        GPIO_GROUP(GPIOAO_0, AO_OFF),
-        GPIO_GROUP(GPIOAO_1, AO_OFF),
-        GPIO_GROUP(GPIOAO_2, AO_OFF),
-        GPIO_GROUP(GPIOAO_3, AO_OFF),
-        GPIO_GROUP(GPIOAO_4, AO_OFF),
-        GPIO_GROUP(GPIOAO_5, AO_OFF),
-        GPIO_GROUP(GPIOAO_6, AO_OFF),
-        GPIO_GROUP(GPIOAO_7, AO_OFF),
-        GPIO_GROUP(GPIOAO_8, AO_OFF),
-        GPIO_GROUP(GPIOAO_9, AO_OFF),
-        GPIO_GROUP(GPIOAO_10, AO_OFF),
-        GPIO_GROUP(GPIOAO_11, AO_OFF),
-        GPIO_GROUP(GPIOAO_12, AO_OFF),
-        GPIO_GROUP(GPIOAO_13, AO_OFF),
-        GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
-        GPIO_GROUP(GPIO_TEST_N, AO_OFF),
-
         /* bank X */
         GROUP(sd_d0_a,          8,      5),
         GROUP(sd_d1_a,          8,      4),
@@ -572,6 +557,37 @@ static struct meson_pmx_group meson8b_groups[] = {
         GROUP(sdxc_clk_b,       2,      5),
         GROUP(sdxc_cmd_b,       2,      4),
 
+        /* bank DIF */
+        GROUP(eth_rxd1,         6,      0),
+        GROUP(eth_rxd0,         6,      1),
+        GROUP(eth_rx_dv,        6,      2),
+        GROUP(eth_rx_clk,       6,      3),
+        GROUP(eth_txd0_1,       6,      4),
+        GROUP(eth_txd1_1,       6,      5),
+        GROUP(eth_tx_en,        6,      0),
+        GROUP(eth_ref_clk,      6,      8),
+        GROUP(eth_mdc,          6,      9),
+        GROUP(eth_mdio_en,      6,      10),
+};
+
+static struct meson_pmx_group meson8b_aobus_groups[] = {
+        GPIO_GROUP(GPIOAO_0, AO_OFF),
+        GPIO_GROUP(GPIOAO_1, AO_OFF),
+        GPIO_GROUP(GPIOAO_2, AO_OFF),
+        GPIO_GROUP(GPIOAO_3, AO_OFF),
+        GPIO_GROUP(GPIOAO_4, AO_OFF),
+        GPIO_GROUP(GPIOAO_5, AO_OFF),
+        GPIO_GROUP(GPIOAO_6, AO_OFF),
+        GPIO_GROUP(GPIOAO_7, AO_OFF),
+        GPIO_GROUP(GPIOAO_8, AO_OFF),
+        GPIO_GROUP(GPIOAO_9, AO_OFF),
+        GPIO_GROUP(GPIOAO_10, AO_OFF),
+        GPIO_GROUP(GPIOAO_11, AO_OFF),
+        GPIO_GROUP(GPIOAO_12, AO_OFF),
+        GPIO_GROUP(GPIOAO_13, AO_OFF),
+        GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
+        GPIO_GROUP(GPIO_TEST_N, AO_OFF),
+
         /* bank AO */
         GROUP(uart_tx_ao_a,     0,      12),
         GROUP(uart_rx_ao_a,     0,      11),
@@ -601,18 +617,6 @@ static struct meson_pmx_group meson8b_groups[] = {
         GROUP(i2s_in_ch01,      0,      13),
         GROUP(i2s_ao_clk_in,    0,      15),
         GROUP(i2s_lr_clk_in,    0,      14),
-
-        /* bank DIF */
-        GROUP(eth_rxd1,         6,      0),
-        GROUP(eth_rxd0,         6,      1),
-        GROUP(eth_rx_dv,        6,      2),
-        GROUP(eth_rx_clk,       6,      3),
-        GROUP(eth_txd0_1,       6,      4),
-        GROUP(eth_txd1_1,       6,      5),
-        GROUP(eth_tx_en,        6,      0),
-        GROUP(eth_ref_clk,      6,      8),
-        GROUP(eth_mdc,          6,      9),
-        GROUP(eth_mdio_en,      6,      10),
 };
 
 static const char * const gpio_groups[] = {
@@ -694,7 +698,10 @@ static const char * const i2c_c_groups[] = {
 };
 
 static const char * const hdmi_groups[] = {
-        "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0",
+        "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0"
+};
+
+static const char * const hdmi_cec_groups[] = {
         "hdmi_cec_1"
 };
 
@@ -770,12 +777,20 @@ static const char * const i2c_mst_ao_groups[] = {
         "i2c_mst_sck_ao", "i2c_mst_sda_ao"
 };
 
-static const char * const clk_groups[] = {
-        "clk_24m_out", "clk_32k_in_out"
+static const char * const clk_24m_groups[] = {
+        "clk_24m_out"
 };
 
-static const char * const spdif_groups[] = {
-        "spdif_out_1", "spdif_out_0"
+static const char * const clk_32k_groups[] = {
+        "clk_32k_in_out"
+};
+
+static const char * const spdif_0_groups[] = {
+        "spdif_out_0"
+};
+
+static const char * const spdif_1_groups[] = {
+        "spdif_out_1"
 };
 
 static const char * const i2s_groups[] = {
@@ -789,7 +804,11 @@ static const char * const pwm_b_groups[] = {
 };
 
 static const char * const pwm_c_groups[] = {
-        "pwm_c0", "pwm_c1", "pwm_c2"
+        "pwm_c0", "pwm_c1"
+};
+
+static const char * const pwm_c_ao_groups[] = {
+        "pwm_c2"
 };
 
 static const char * const pwm_d_groups[] = {
@@ -814,7 +833,7 @@ static const char * const tsin_b_groups[] = {
         "tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b"
 };
 
-static struct meson_pmx_func meson8b_functions[] = {
+static struct meson_pmx_func meson8b_cbus_functions[] = {
         FUNCTION(gpio),
         FUNCTION(sd_a),
         FUNCTION(sdxc_a),
@@ -837,14 +856,7 @@ static struct meson_pmx_func meson8b_functions[] = {
         FUNCTION(nor),
         FUNCTION(sd_b),
         FUNCTION(sdxc_b),
-        FUNCTION(uart_ao),
-        FUNCTION(remote),
-        FUNCTION(i2c_slave_ao),
-        FUNCTION(uart_ao_b),
-        FUNCTION(i2c_mst_ao),
-        FUNCTION(clk),
-        FUNCTION(spdif),
-        FUNCTION(i2s),
+        FUNCTION(spdif_0),
         FUNCTION(pwm_b),
         FUNCTION(pwm_c),
         FUNCTION(pwm_d),
@@ -852,9 +864,23 @@ static struct meson_pmx_func meson8b_functions[] = {
         FUNCTION(pwm_vs),
         FUNCTION(tsin_a),
         FUNCTION(tsin_b),
+        FUNCTION(clk_24m),
+};
+
+static struct meson_pmx_func meson8b_aobus_functions[] = {
+        FUNCTION(uart_ao),
+        FUNCTION(uart_ao_b),
+        FUNCTION(i2c_slave_ao),
+        FUNCTION(i2c_mst_ao),
+        FUNCTION(i2s),
+        FUNCTION(remote),
+        FUNCTION(clk_32k),
+        FUNCTION(pwm_c_ao),
+        FUNCTION(spdif_1),
+        FUNCTION(hdmi_cec),
 };
 
-static struct meson_bank meson8b_banks[] = {
+static struct meson_bank meson8b_cbus_banks[] = {
         /*   name    first                      last                   pullen  pull    dir     out     in  */
         BANK("X",    PIN(GPIOX_0, 0),           PIN(GPIOX_21, 0),      4,  0,  4,  0,  0,  0,  1,  0,  2,  0),
         BANK("Y",    PIN(GPIOY_0, 0),           PIN(GPIOY_14, 0),      3,  0,  3,  0,  3,  0,  4,  0,  5,  0),
@@ -865,35 +891,43 @@ static struct meson_bank meson8b_banks[] = {
         BANK("DIF",  PIN(DIF_0_P, 0),           PIN(DIF_4_N, 0),       5,  8,  5,  8, 12, 12, 13, 12, 14, 12),
 };
 
-static struct meson_bank meson8b_ao_banks[] = {
+static struct meson_bank meson8b_aobus_banks[] = {
         /*   name    first                  last                      pullen  pull    dir     out     in  */
         BANK("AO",   PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),
 };
 
-static struct meson_domain_data meson8b_domain_data[] = {
-        {
-                .name           = "banks",
-                .banks          = meson8b_banks,
-                .num_banks      = ARRAY_SIZE(meson8b_banks),
-                .pin_base       = 0,
-                .num_pins       = 130,
-        },
-        {
-                .name           = "ao-bank",
-                .banks          = meson8b_ao_banks,
-                .num_banks      = ARRAY_SIZE(meson8b_ao_banks),
-                .pin_base       = 130,
-                .num_pins       = 16,
-        },
-};
-
-struct meson_pinctrl_data meson8b_pinctrl_data = {
-        .pins           = meson8b_pins,
-        .groups         = meson8b_groups,
-        .funcs          = meson8b_functions,
-        .domain_data    = meson8b_domain_data,
-        .num_pins       = ARRAY_SIZE(meson8b_pins),
-        .num_groups     = ARRAY_SIZE(meson8b_groups),
-        .num_funcs      = ARRAY_SIZE(meson8b_functions),
-        .num_domains    = ARRAY_SIZE(meson8b_domain_data),
+static struct meson_domain_data meson8b_cbus_domain_data = {
+        .name           = "cbus-banks",
+        .banks          = meson8b_cbus_banks,
+        .num_banks      = ARRAY_SIZE(meson8b_cbus_banks),
+        .pin_base       = 0,
+        .num_pins       = 130,
+};
+
+static struct meson_domain_data meson8b_aobus_domain_data = {
+        .name           = "aobus-banks",
+        .banks          = meson8b_aobus_banks,
+        .num_banks      = ARRAY_SIZE(meson8b_aobus_banks),
+        .pin_base       = 130,
+        .num_pins       = 16,
+};
+
+struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
+        .pins           = meson8b_cbus_pins,
+        .groups         = meson8b_cbus_groups,
+        .funcs          = meson8b_cbus_functions,
+        .domain_data    = &meson8b_cbus_domain_data,
+        .num_pins       = ARRAY_SIZE(meson8b_cbus_pins),
+        .num_groups     = ARRAY_SIZE(meson8b_cbus_groups),
+        .num_funcs      = ARRAY_SIZE(meson8b_cbus_functions),
+};
+
+struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
+        .pins           = meson8b_aobus_pins,
+        .groups         = meson8b_aobus_groups,
+        .funcs          = meson8b_aobus_functions,
+        .domain_data    = &meson8b_aobus_domain_data,
+        .num_pins       = ARRAY_SIZE(meson8b_aobus_pins),
+        .num_groups     = ARRAY_SIZE(meson8b_aobus_groups),
+        .num_funcs      = ARRAY_SIZE(meson8b_aobus_functions),
 };
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
index 587b222f12f3..e852048c4c04 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
@@ -287,6 +287,10 @@ static const unsigned i2c0_a_1_pins[] = { STN8815_PIN_D3, STN8815_PIN_D2 };
 /* Altfunction B */
 static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 };
 static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
+static const unsigned clcd_16_23_b_1_pins[] = { STN8815_PIN_AB6,
+        STN8815_PIN_AA6, STN8815_PIN_Y6, STN8815_PIN_Y5, STN8815_PIN_AA5,
+        STN8815_PIN_AB5, STN8815_PIN_AB4, STN8815_PIN_Y4 };
+
 
 #define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins,         \
                         .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
@@ -302,6 +306,7 @@ static const struct nmk_pingroup nmk_stn8815_groups[] = {
         STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
         STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
         STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
+        STN8815_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B),
 };
 
 /* We use this macro to define the groups applicable to a function */
@@ -314,6 +319,7 @@ STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1");
 STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
 STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
 STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1");
+STN8815_FUNC_GROUPS(clcd, "clcd_16_23_b_1");
 
 #define FUNCTION(fname)                                 \
         {                                               \
@@ -329,6 +335,7 @@ static const struct nmk_function nmk_stn8815_functions[] = {
         FUNCTION(i2c1),
         FUNCTION(i2c0),
         FUNCTION(i2cusb),
+        FUNCTION(clcd),
 };
 
 static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 657449431301..5c025f5b5048 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -753,8 +753,8 @@ static int amd_gpio_probe(struct platform_device *pdev)
 
         gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
                                                 resource_size(res));
-        if (IS_ERR(gpio_dev->base))
-                return PTR_ERR(gpio_dev->base);
+        if (!gpio_dev->base)
+                return -ENOMEM;
 
         irq_base = platform_get_irq(pdev, 0);
         if (irq_base < 0) {
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index ee69db6ae1c7..4429312e848d 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -824,7 +824,7 @@ static struct pinctrl_desc atmel_pinctrl_desc = {
         .pmxops         = &atmel_pmxops,
 };
 
-static int atmel_pctrl_suspend(struct device *dev)
+static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
         struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
@@ -844,7 +844,7 @@ static int atmel_pctrl_suspend(struct device *dev)
         return 0;
 }
 
-static int atmel_pctrl_resume(struct device *dev)
+static int __maybe_unused atmel_pctrl_resume(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
         struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index cf7788df0f95..741b39eaeb8b 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -127,7 +127,7 @@ struct u300_gpio_confdata {
 }
 
 /* Initial configuration */
-static const struct __initconst u300_gpio_confdata
+static const struct u300_gpio_confdata __initconst
 bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
         /* Port 0, pins 0-7 */
         {
diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c
index f0bebbe0682b..b1767f7e45d1 100644
--- a/drivers/pinctrl/pinctrl-lpc18xx.c
+++ b/drivers/pinctrl/pinctrl-lpc18xx.c
@@ -49,6 +49,18 @@
 
 #define LPC18XX_SCU_FUNC_PER_PIN        8
 
+/* LPC18XX SCU pin interrupt select registers */
+#define LPC18XX_SCU_PINTSEL0            0xe00
+#define LPC18XX_SCU_PINTSEL1            0xe04
+#define LPC18XX_SCU_PINTSEL_VAL_MASK    0xff
+#define LPC18XX_SCU_PINTSEL_PORT_SHIFT  5
+#define LPC18XX_SCU_IRQ_PER_PINTSEL     4
+#define LPC18XX_GPIO_PINS_PER_PORT      32
+#define LPC18XX_GPIO_PIN_INT_MAX        8
+
+#define LPC18XX_SCU_PINTSEL_VAL(val, n) \
+        ((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
+
 /* LPC18xx pin types */
 enum {
         TYPE_ND,        /* Normal-drive */
@@ -618,6 +630,25 @@ static const struct pinctrl_pin_desc lpc18xx_pins[] = {
         LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
 };
 
+/**
+ * enum lpc18xx_pin_config_param - possible pin configuration parameters
+ * @PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt
+ *      controller.
+ */
+enum lpc18xx_pin_config_param {
+        PIN_CONFIG_GPIO_PIN_INT = PIN_CONFIG_END + 1,
+};
+
+static const struct pinconf_generic_params lpc18xx_params[] = {
+        {"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
+};
+
+#ifdef CONFIG_DEBUG_FS
+static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params)] = {
+        PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
+};
+#endif
+
 static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
 {
         switch (param) {
@@ -693,7 +724,71 @@ static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg
         return 0;
 }
 
-static int lpc18xx_pconf_get_pin(enum pin_config_param param, int *arg, u32 reg,
+static int lpc18xx_pin_to_gpio(struct pinctrl_dev *pctldev, unsigned pin)
+{
+        struct pinctrl_gpio_range *range;
+
+        range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
+        if (!range)
+                return -EINVAL;
+
+        return pin - range->pin_base + range->base;
+}
+
+static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg)
+{
+        u32 reg_val;
+        int i;
+
+        reg_val = readl(addr);
+        for (i = 0; i < LPC18XX_SCU_IRQ_PER_PINTSEL; i++) {
+                if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)
+                        return 0;
+
+                reg_val >>= BITS_PER_BYTE;
+                *arg += 1;
+        }
+
+        return -EINVAL;
+}
+
+static u32 lpc18xx_gpio_to_pintsel_val(int gpio)
+{
+        unsigned int gpio_port, gpio_pin;
+
+        gpio_port = gpio / LPC18XX_GPIO_PINS_PER_PORT;
+        gpio_pin  = gpio % LPC18XX_GPIO_PINS_PER_PORT;
+
+        return gpio_pin | (gpio_port << LPC18XX_SCU_PINTSEL_PORT_SHIFT);
+}
+
+static int lpc18xx_pconf_get_gpio_pin_int(struct pinctrl_dev *pctldev,
+                                          int *arg, unsigned pin)
+{
+        struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
+        int gpio, ret;
+        u32 val;
+
+        gpio = lpc18xx_pin_to_gpio(pctldev, pin);
+        if (gpio < 0)
+                return -ENOTSUPP;
+
+        val = lpc18xx_gpio_to_pintsel_val(gpio);
+
+        /*
+         * Check if this pin has been enabled as a interrupt in any of the two
+         * PINTSEL registers. *arg indicates which interrupt number (0-7).
+         */
+        *arg = 0;
+        ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg);
+        if (ret == 0)
+                return ret;
+
+        return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg);
+}
+
+static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
+                                 int *arg, u32 reg, unsigned pin,
                                  struct lpc18xx_pin_caps *pin_cap)
 {
         switch (param) {
@@ -755,6 +850,9 @@ static int lpc18xx_pconf_get_pin(enum pin_config_param param, int *arg, u32 reg,
                 }
                 break;
 
+        case PIN_CONFIG_GPIO_PIN_INT:
+                return lpc18xx_pconf_get_gpio_pin_int(pctldev, arg, pin);
+
         default:
                 return -ENOTSUPP;
         }
@@ -794,7 +892,7 @@ static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
         else if (pin_cap->type == TYPE_USB1)
                 ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
         else
-                ret = lpc18xx_pconf_get_pin(param, &arg, reg, pin_cap);
+                ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap);
 
         if (ret < 0)
                 return ret;
@@ -883,9 +981,34 @@ static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
         return 0;
 }
 
-static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev,
-                                 enum pin_config_param param,
-                                 u16 param_val, u32 *reg,
+static int lpc18xx_pconf_set_gpio_pin_int(struct pinctrl_dev *pctldev,
+                                          u16 param_val, unsigned pin)
+{
+        struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
+        u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;
+        int gpio;
+
+        if (param_val >= LPC18XX_GPIO_PIN_INT_MAX)
+                return -EINVAL;
+
+        gpio = lpc18xx_pin_to_gpio(pctldev, pin);
+        if (gpio < 0)
+                return -ENOTSUPP;
+
+        val = lpc18xx_gpio_to_pintsel_val(gpio);
+
+        reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
+
+        reg_val = readl(scu->base + reg_offset);
+        reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);
+        reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);
+        writel(reg_val, scu->base + reg_offset);
+
+        return 0;
+}
+
+static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
+                                 u16 param_val, u32 *reg, unsigned pin,
                                  struct lpc18xx_pin_caps *pin_cap)
 {
         switch (param) {
@@ -948,6 +1071,9 @@ static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev,
                 *reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
                 break;
 
+        case PIN_CONFIG_GPIO_PIN_INT:
+                return lpc18xx_pconf_set_gpio_pin_int(pctldev, param_val, pin);
+
         default:
                 dev_err(pctldev->dev, "Property not supported\n");
                 return -ENOTSUPP;
@@ -982,7 +1108,7 @@ static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
                 else if (pin_cap->type == TYPE_USB1)
                         ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, &reg);
                 else
-                        ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, &reg, pin_cap);
+                        ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, &reg, pin, pin_cap);
 
                 if (ret)
                         return ret;
@@ -1136,6 +1262,11 @@ static struct pinctrl_desc lpc18xx_scu_desc = {
         .pctlops = &lpc18xx_pctl_ops,
         .pmxops = &lpc18xx_pmx_ops,
         .confops = &lpc18xx_pconf_ops,
+        .num_custom_params = ARRAY_SIZE(lpc18xx_params),
+        .custom_params = lpc18xx_params,
+#ifdef CONFIG_DEBUG_FS
+        .custom_conf_items = lpc18xx_conf_items,
+#endif
         .owner = THIS_MODULE,
 };
 
@@ -1170,9 +1301,8 @@ static int lpc18xx_create_group_func_map(struct device *dev,
         u16 pins[ARRAY_SIZE(lpc18xx_pins)];
         int func, ngroups, i;
 
-        for (func = 0; func < FUNC_MAX; ngroups = 0, func++) {
-
-                for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
+        for (func = 0; func < FUNC_MAX; func++) {
+                for (ngroups = 0, i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
                         if (lpc18xx_valid_pin_function(i, func))
                                 pins[ngroups++] = i;
                 }
diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c
new file mode 100644
index 000000000000..0b07d4bdab95
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-pic32.c
@@ -0,0 +1,2312 @@
+/*
+ * PIC32 pinctrl driver
+ *
+ * Joshua Henderson, <joshua.henderson@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <asm/mach-pic32/pic32.h>
+
+#include "pinctrl-utils.h"
+#include "pinctrl-pic32.h"
+
+#define PINS_PER_BANK           16
+
+#define PIC32_CNCON_EDGE        11
+#define PIC32_CNCON_ON          15
+
+#define PIN_CONFIG_MICROCHIP_DIGITAL    (PIN_CONFIG_END + 1)
+#define PIN_CONFIG_MICROCHIP_ANALOG     (PIN_CONFIG_END + 2)
+
+static const struct pinconf_generic_params pic32_mpp_bindings[] = {
+        {"microchip,digital",   PIN_CONFIG_MICROCHIP_DIGITAL,   0},
+        {"microchip,analog",    PIN_CONFIG_MICROCHIP_ANALOG,    0},
+};
+
+#define GPIO_BANK_START(bank)           ((bank) * PINS_PER_BANK)
+
+struct pic32_function {
+        const char *name;
+        const char * const *groups;
+        unsigned int ngroups;
+};
+
+struct pic32_pin_group {
+        const char *name;
+        unsigned int pin;
+        struct pic32_desc_function *functions;
+};
+
+struct pic32_desc_function {
+        const char *name;
+        u32 muxreg;
+        u32 muxval;
+};
+
+struct pic32_gpio_bank {
+        void __iomem *reg_base;
+        struct gpio_chip gpio_chip;
+        struct irq_chip irq_chip;
+        struct clk *clk;
+};
+
+struct pic32_pinctrl {
+        void __iomem *reg_base;
+        struct device *dev;
+        struct pinctrl_dev *pctldev;
+        const struct pinctrl_pin_desc *pins;
+        unsigned int npins;
+        const struct pic32_function *functions;
+        unsigned int nfunctions;
+        const struct pic32_pin_group *groups;
+        unsigned int ngroups;
+        struct pic32_gpio_bank *gpio_banks;
+        unsigned int nbanks;
+        struct clk *clk;
+};
+
+static const struct pinctrl_pin_desc pic32_pins[] = {
+        PINCTRL_PIN(0, "A0"),
+        PINCTRL_PIN(1, "A1"),
+        PINCTRL_PIN(2, "A2"),
+        PINCTRL_PIN(3, "A3"),
+        PINCTRL_PIN(4, "A4"),
+        PINCTRL_PIN(5, "A5"),
+        PINCTRL_PIN(6, "A6"),
+        PINCTRL_PIN(7, "A7"),
+        PINCTRL_PIN(8, "A8"),
+        PINCTRL_PIN(9, "A9"),
+        PINCTRL_PIN(10, "A10"),
+        PINCTRL_PIN(11, "A11"),
+        PINCTRL_PIN(12, "A12"),
+        PINCTRL_PIN(13, "A13"),
+        PINCTRL_PIN(14, "A14"),
+        PINCTRL_PIN(15, "A15"),
+        PINCTRL_PIN(16, "B0"),
+        PINCTRL_PIN(17, "B1"),
+        PINCTRL_PIN(18, "B2"),
+        PINCTRL_PIN(19, "B3"),
+        PINCTRL_PIN(20, "B4"),
+        PINCTRL_PIN(21, "B5"),
+        PINCTRL_PIN(22, "B6"),
+        PINCTRL_PIN(23, "B7"),
+        PINCTRL_PIN(24, "B8"),
+        PINCTRL_PIN(25, "B9"),
+        PINCTRL_PIN(26, "B10"),
+        PINCTRL_PIN(27, "B11"),
+        PINCTRL_PIN(28, "B12"),
+        PINCTRL_PIN(29, "B13"),
+        PINCTRL_PIN(30, "B14"),
+        PINCTRL_PIN(31, "B15"),
+        PINCTRL_PIN(33, "C1"),
+        PINCTRL_PIN(34, "C2"),
+        PINCTRL_PIN(35, "C3"),
+        PINCTRL_PIN(36, "C4"),
+        PINCTRL_PIN(44, "C12"),
+        PINCTRL_PIN(45, "C13"),
+        PINCTRL_PIN(46, "C14"),
+        PINCTRL_PIN(47, "C15"),
+        PINCTRL_PIN(48, "D0"),
+        PINCTRL_PIN(49, "D1"),
+        PINCTRL_PIN(50, "D2"),
+        PINCTRL_PIN(51, "D3"),
+        PINCTRL_PIN(52, "D4"),
+        PINCTRL_PIN(53, "D5"),
+        PINCTRL_PIN(54, "D6"),
+        PINCTRL_PIN(55, "D7"),
+        PINCTRL_PIN(57, "D9"),
+        PINCTRL_PIN(58, "D10"),
+        PINCTRL_PIN(59, "D11"),
+        PINCTRL_PIN(60, "D12"),
+        PINCTRL_PIN(61, "D13"),
+        PINCTRL_PIN(62, "D14"),
+        PINCTRL_PIN(63, "D15"),
+        PINCTRL_PIN(64, "E0"),
+        PINCTRL_PIN(65, "E1"),
+        PINCTRL_PIN(66, "E2"),
+        PINCTRL_PIN(67, "E3"),
+        PINCTRL_PIN(68, "E4"),
+        PINCTRL_PIN(69, "E5"),
+        PINCTRL_PIN(70, "E6"),
+        PINCTRL_PIN(71, "E7"),
+        PINCTRL_PIN(72, "E8"),
+        PINCTRL_PIN(73, "E9"),
+        PINCTRL_PIN(80, "F0"),
+        PINCTRL_PIN(81, "F1"),
+        PINCTRL_PIN(82, "F2"),
+        PINCTRL_PIN(83, "F3"),
+        PINCTRL_PIN(84, "F4"),
+        PINCTRL_PIN(85, "F5"),
+        PINCTRL_PIN(88, "F8"),
+        PINCTRL_PIN(92, "F12"),
+        PINCTRL_PIN(93, "F13"),
+        PINCTRL_PIN(96, "G0"),
+        PINCTRL_PIN(97, "G1"),
+        PINCTRL_PIN(102, "G6"),
+        PINCTRL_PIN(103, "G7"),
+        PINCTRL_PIN(104, "G8"),
+        PINCTRL_PIN(105, "G9"),
+        PINCTRL_PIN(108, "G12"),
+        PINCTRL_PIN(109, "G13"),
+        PINCTRL_PIN(110, "G14"),
+        PINCTRL_PIN(111, "G15"),
+        PINCTRL_PIN(112, "H0"),
+        PINCTRL_PIN(113, "H1"),
+        PINCTRL_PIN(114, "H2"),
+        PINCTRL_PIN(115, "H3"),
+        PINCTRL_PIN(116, "H4"),
+        PINCTRL_PIN(117, "H5"),
+        PINCTRL_PIN(118, "H6"),
+        PINCTRL_PIN(119, "H7"),
+        PINCTRL_PIN(120, "H8"),
+        PINCTRL_PIN(121, "H9"),
+        PINCTRL_PIN(122, "H10"),
+        PINCTRL_PIN(123, "H11"),
+        PINCTRL_PIN(124, "H12"),
+        PINCTRL_PIN(125, "H13"),
+        PINCTRL_PIN(126, "H14"),
+        PINCTRL_PIN(127, "H15"),
+        PINCTRL_PIN(128, "J0"),
+        PINCTRL_PIN(129, "J1"),
+        PINCTRL_PIN(130, "J2"),
+        PINCTRL_PIN(131, "J3"),
+        PINCTRL_PIN(132, "J4"),
+        PINCTRL_PIN(133, "J5"),
+        PINCTRL_PIN(134, "J6"),
+        PINCTRL_PIN(135, "J7"),
+        PINCTRL_PIN(136, "J8"),
+        PINCTRL_PIN(137, "J9"),
+        PINCTRL_PIN(138, "J10"),
+        PINCTRL_PIN(139, "J11"),
+        PINCTRL_PIN(140, "J12"),
+        PINCTRL_PIN(141, "J13"),
+        PINCTRL_PIN(142, "J14"),
+        PINCTRL_PIN(143, "J15"),
+        PINCTRL_PIN(144, "K0"),
+        PINCTRL_PIN(145, "K1"),
+        PINCTRL_PIN(146, "K2"),
+        PINCTRL_PIN(147, "K3"),
+        PINCTRL_PIN(148, "K4"),
+        PINCTRL_PIN(149, "K5"),
+        PINCTRL_PIN(150, "K6"),
+        PINCTRL_PIN(151, "K7"),
+};
+
+static const char * const pic32_input0_group[] = {
+        "D2", "G8", "F4", "F1", "B9", "B10", "C14", "B5",
+        "C1", "D14", "G1", "A14", "D6",
+};
+
+static const char * const pic32_input1_group[] = {
+        "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
+        "B3", "C4", "G0", "A15", "D7",
+};
+
+static const char * const pic32_input2_group[] = {
+        "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
+        "F12", "D12", "F8", "C3", "E9",
+};
+
+static const char * const pic32_input3_group[] = {
+        "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
+        "F2", "C2", "E8",
+};
+
+static const char * const pic32_output0_group[] = {
+        "D2", "G8", "F4", "D10", "F1", "B9", "B10", "C14",
+        "B5", "C1", "D14", "G1", "A14", "D6",
+};
+
+static const char * const pic32_output0_1_group[] = {
+        "D2", "G8", "F4", "D10", "F1", "B9", "B10", "C14",
+        "B5", "C1", "D14", "G1", "A14", "D6",
+        "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
+        "B3", "C4", "D15", "G0", "A15", "D7",
+};
+
+static const char *const pic32_output1_group[] = {
+        "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
+        "B3", "C4", "D15", "G0", "A15", "D7",
+};
+
+static const char *const pic32_output1_3_group[] = {
+        "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
+        "B3", "C4", "D15", "G0", "A15", "D7",
+        "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
+        "C2", "E8", "F2",
+};
+
+static const char * const pic32_output2_group[] = {
+        "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
+        "F12", "D12", "F8", "C3", "E9",
+};
+
+static const char * const pic32_output2_3_group[] = {
+        "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
+        "F12", "D12", "F8", "C3", "E9",
+        "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
+        "C2", "E8", "F2",
+};
+
+static const char * const pic32_output3_group[] = {
+        "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
+        "C2", "E8", "F2",
+};
+
+#define FUNCTION(_name, _gr)                                    \
+        {                                                       \
+                .name = #_name,                                 \
+                .groups = pic32_##_gr##_group,                  \
+                .ngroups = ARRAY_SIZE(pic32_##_gr##_group),     \
+        }
+
+static const struct pic32_function pic32_functions[] = {
+        FUNCTION(INT3, input0),
+        FUNCTION(T2CK, input0),
+        FUNCTION(T6CK, input0),
+        FUNCTION(IC3, input0),
+        FUNCTION(IC7, input0),
+        FUNCTION(U1RX, input0),
+        FUNCTION(U2CTS, input0),
+        FUNCTION(U5RX, input0),
+        FUNCTION(U6CTS, input0),
+        FUNCTION(SDI1, input0),
+        FUNCTION(SDI3, input0),
+        FUNCTION(SDI5, input0),
+        FUNCTION(SS6IN, input0),
+        FUNCTION(REFCLKI1, input0),
+        FUNCTION(INT4, input1),
+        FUNCTION(T5CK, input1),
+        FUNCTION(T7CK, input1),
+        FUNCTION(IC4, input1),
+        FUNCTION(IC8, input1),
+        FUNCTION(U3RX, input1),
+        FUNCTION(U4CTS, input1),
+        FUNCTION(SDI2, input1),
+        FUNCTION(SDI4, input1),
+        FUNCTION(C1RX, input1),
+        FUNCTION(REFCLKI4, input1),
+        FUNCTION(INT2, input2),
+        FUNCTION(T3CK, input2),
+        FUNCTION(T8CK, input2),
+        FUNCTION(IC2, input2),
+        FUNCTION(IC5, input2),
+        FUNCTION(IC9, input2),
+        FUNCTION(U1CTS, input2),
+        FUNCTION(U2RX, input2),
+        FUNCTION(U5CTS, input2),
+        FUNCTION(SS1IN, input2),
+        FUNCTION(SS3IN, input2),
+        FUNCTION(SS4IN, input2),
+        FUNCTION(SS5IN, input2),
+        FUNCTION(C2RX, input2),
+        FUNCTION(INT1, input3),
+        FUNCTION(T4CK, input3),
+        FUNCTION(T9CK, input3),
+        FUNCTION(IC1, input3),
+        FUNCTION(IC6, input3),
+        FUNCTION(U3CTS, input3),
+        FUNCTION(U4RX, input3),
+        FUNCTION(U6RX, input3),
+        FUNCTION(SS2IN, input3),
+        FUNCTION(SDI6, input3),
+        FUNCTION(OCFA, input3),
+        FUNCTION(REFCLKI3, input3),
+        FUNCTION(U3TX, output0),
+        FUNCTION(U4RTS, output0),
+        FUNCTION(SDO1, output0_1),
+        FUNCTION(SDO2, output0_1),
+        FUNCTION(SDO3, output0_1),
+        FUNCTION(SDO5, output0_1),
+        FUNCTION(SS6OUT, output0),
+        FUNCTION(OC3, output0),
+        FUNCTION(OC6, output0),
+        FUNCTION(REFCLKO4, output0),
+        FUNCTION(C2OUT, output0),
+        FUNCTION(C1TX, output0),
+        FUNCTION(U1TX, output1),
+        FUNCTION(U2RTS, output1),
+        FUNCTION(U5TX, output1),
+        FUNCTION(U6RTS, output1),
+        FUNCTION(SDO4, output1_3),
+        FUNCTION(OC4, output1),
+        FUNCTION(OC7, output1),
+        FUNCTION(REFCLKO1, output1),
+        FUNCTION(U3RTS, output2),
+        FUNCTION(U4TX, output2),
+        FUNCTION(U6TX, output2_3),
+        FUNCTION(SS1OUT, output2),
+        FUNCTION(SS3OUT, output2),
+        FUNCTION(SS4OUT, output2),
+        FUNCTION(SS5OUT, output2),
+        FUNCTION(SDO6, output2_3),
+        FUNCTION(OC5, output2),
+        FUNCTION(OC8, output2),
+        FUNCTION(C1OUT, output2),
+        FUNCTION(REFCLKO3, output2),
+        FUNCTION(U1RTS, output3),
+        FUNCTION(U2TX, output3),
+        FUNCTION(U5RTS, output3),
+        FUNCTION(SS2OUT, output3),
+        FUNCTION(OC2, output3),
+        FUNCTION(OC1, output3),
+        FUNCTION(OC9, output3),
+        FUNCTION(C2TX, output3),
+};
+
+#define PIC32_PINCTRL_GROUP(_pin, _name, ...)                           \
+        {                                                               \
+                .name = #_name,                                         \
+                .pin = _pin,                                            \
+                .functions = (struct pic32_desc_function[]){            \
+                        __VA_ARGS__, { } },                             \
+        }
+
+#define PIC32_PINCTRL_FUNCTION(_name, _muxreg, _muxval) \
+        {                                               \
+                .name = #_name,                         \
+                .muxreg = _muxreg,                      \
+                .muxval = _muxval,                      \
+        }
+
+static const struct pic32_pin_group pic32_groups[] = {
+        PIC32_PINCTRL_GROUP(14, A14,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 13),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 13),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 13),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 13),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 13),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 13),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 13),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 13),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 13),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 13),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 13),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 13),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 13),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 13),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPA14R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPA14R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPA14R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPA14R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPA14R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPA14R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPA14R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPA14R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPA14R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPA14R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPA14R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPA14R, 15)),
+        PIC32_PINCTRL_GROUP(15, A15,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 13),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 13),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 13),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 13),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 13),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 13),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 13),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 13),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 13),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 13),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 13),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPA15R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPA15R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPA15R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPA15R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPA15R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPA15R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPA15R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPA15R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPA15R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPA15R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPA15R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPA15R, 15)),
+        PIC32_PINCTRL_GROUP(16, B0,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 5),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 5),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 5),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 5),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 5),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 5),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 5),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 5),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 5),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 5),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 5),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 5),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 5),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPB0R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPB0R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPB0R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPB0R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPB0R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPB0R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPB0R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPB0R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPB0R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPB0R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPB0R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB0R, 15)),
+        PIC32_PINCTRL_GROUP(17, B1,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 5),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 5),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 5),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 5),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 5),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 5),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 5),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 5),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 5),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 5),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPB1R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPB1R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPB1R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPB1R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPB1R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPB1R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPB1R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPB1R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPB1R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPB1R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPB1R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPB1R, 15)),
+        PIC32_PINCTRL_GROUP(18, B2,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 7),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 7),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 7),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 7),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 7),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 7),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 7),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 7),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 7),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 7),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 7),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 7),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPB2R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPB2R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPB2R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPB2R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPB2R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPB2R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPB2R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPB2R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPB2R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPB2R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPB2R, 15)),
+        PIC32_PINCTRL_GROUP(19, B3,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 8),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 8),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 8),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 8),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 8),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 8),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 8),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 8),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 8),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 8),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPB3R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPB3R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPB3R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPB3R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPB3R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPB3R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPB3R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPB3R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPB3R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPB3R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPB3R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPB3R, 15)),
+        PIC32_PINCTRL_GROUP(21, B5,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 8),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 8),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 8),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 8),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 8),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 8),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 8),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 8),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 8),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 8),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 8),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPB5R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPB5R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPB5R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPB5R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPB5R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPB5R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPB5R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPB5R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPB5R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB5R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPB5R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPB5R, 15)),
+        PIC32_PINCTRL_GROUP(22, B6,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 4),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 4),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 4),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 4),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 4),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 4),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 4),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 4),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 4),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 4),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 4),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPB6R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPB6R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPB6R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPB6R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPB6R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPB6R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPB6R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPB6R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPB6R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPB6R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPB6R, 15)),
+        PIC32_PINCTRL_GROUP(23, B7,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 7),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 7),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 7),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 7),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 7),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 7),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 7),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 7),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 7),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 7),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 7),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 7),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 7),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPB7R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPB7R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPB7R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPB7R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPB7R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPB7R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPB7R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPB7R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPB7R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPB7R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPB7R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB7R, 15)),
+        PIC32_PINCTRL_GROUP(24, B8,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 2),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 2),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 2),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 2),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 2),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 2),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 2),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 2),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 2),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 2),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 2),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 2),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 2),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 2),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPB8R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPB8R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPB8R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPB8R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPB8R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPB8R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPB8R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPB8R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPB8R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPB8R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPB8R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB8R, 15)),
+        PIC32_PINCTRL_GROUP(25, B9,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 5),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 5),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 5),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 5),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 5),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 5),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 5),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 5),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 5),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 5),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 5),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPB9R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPB9R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPB9R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPB9R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPB9R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPB9R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPB9R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPB9R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPB9R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB9R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPB9R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPB9R, 15)),
+        PIC32_PINCTRL_GROUP(26, B10,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 6),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 6),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 6),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 6),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 6),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 6),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 6),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 6),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 6),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 6),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 6),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 6),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPB10R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPB10R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPB10R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPB10R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPB10R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPB10R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPB10R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPB10R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPB10R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB10R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPB10R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPB10R, 15)),
+        PIC32_PINCTRL_GROUP(30, B14,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 2),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 2),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 2),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 2),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 2),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 2),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 2),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 2),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 2),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 2),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 2),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 2),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPB14R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPB14R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPB14R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPB14R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPB14R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPB14R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPB14R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPB14R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPB14R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPB14R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPB14R, 15)),
+        PIC32_PINCTRL_GROUP(31, B15,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 3),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 3),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 3),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 3),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 3),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 3),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 3),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 3),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 3),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 3),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 3),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 3),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 3),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 3),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPB15R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPB15R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPB15R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPB15R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPB15R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPB15R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPB15R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPB15R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPB15R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPB15R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPB15R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB15R, 15)),
+        PIC32_PINCTRL_GROUP(33, C1,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 10),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 10),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 10),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 10),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 10),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 10),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 10),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 10),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 10),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 10),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 10),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 10),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 10),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 10),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPC1R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPC1R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPC1R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPC1R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPC1R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPC1R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPC1R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPC1R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPC1R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPC1R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPC1R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPC1R, 15)),
+        PIC32_PINCTRL_GROUP(34, C2,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 12),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 12),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 12),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 12),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 12),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 12),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 12),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 12),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 12),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 12),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 12),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPC2R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPC2R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPC2R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPC2R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPC2R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPC2R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPC2R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPC2R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPC2R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPC2R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPC2R, 15)),
+        PIC32_PINCTRL_GROUP(35, C3,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 12),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 12),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 12),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 12),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 12),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 12),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 12),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 12),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 12),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 12),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 12),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 12),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 12),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 12),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPC3R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPC3R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPC3R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPC3R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPC3R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPC3R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPC3R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPC3R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPC3R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPC3R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPC3R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPC3R, 15)),
+        PIC32_PINCTRL_GROUP(36, C4,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 10),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 10),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 10),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 10),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 10),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 10),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 10),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 10),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 10),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 10),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 10),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPC4R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPC4R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPC4R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPC4R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPC4R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPC4R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPC4R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPC4R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPC4R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPC4R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPC4R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPC4R, 15)),
+        PIC32_PINCTRL_GROUP(45, C13,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 7),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 7),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 7),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 7),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 7),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 7),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 7),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 7),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 7),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 7),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPC13R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPC13R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPC13R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPC13R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPC13R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPC13R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPC13R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPC13R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPC13R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPC13R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPC13R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPC13R, 15)),
+        PIC32_PINCTRL_GROUP(46, C14,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 7),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 7),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 7),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 7),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 7),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 7),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 7),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 7),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 7),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 7),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 7),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPC14R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPC14R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPC14R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPC14R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPC14R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPC14R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPC14R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPC14R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPC14R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPC14R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPC14R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPC14R, 15)),
+        PIC32_PINCTRL_GROUP(48, D0,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 3),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 3),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 3),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 3),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 3),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 3),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 3),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 3),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 3),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 3),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 3),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPD0R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPD0R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPD0R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPD0R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPD0R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPD0R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPD0R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPD0R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPD0R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPD0R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPD0R, 15)),
+        PIC32_PINCTRL_GROUP(50, D2,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 0),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 0),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 0),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 0),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 0),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 0),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 0),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 0),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 0),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 0),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 0),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 0),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 0),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 0),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPD2R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPD2R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPD2R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPD2R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPD2R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPD2R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPD2R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPD2R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPD2R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD2R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPD2R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPD2R, 15)),
+        PIC32_PINCTRL_GROUP(51, D3,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 0),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 0),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 0),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 0),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 0),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 0),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 0),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 0),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 0),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 0),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 0),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPD3R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPD3R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPD3R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPD3R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPD3R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPD3R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPD3R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPD3R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPD3R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPD3R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPD3R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD3R, 15)),
+        PIC32_PINCTRL_GROUP(52, D4,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 4),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 4),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 4),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 4),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 4),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 4),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 4),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 4),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 4),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 4),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 4),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 4),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 4),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPD4R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPD4R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPD4R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPD4R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPD4R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPD4R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPD4R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPD4R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPD4R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPD4R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPD4R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD4R, 15)),
+        PIC32_PINCTRL_GROUP(53, D5,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 6),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 6),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 6),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 6),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 6),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 6),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 6),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 6),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 6),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 6),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 6),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 6),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPD5R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPD5R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPD5R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPD5R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPD5R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPD5R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPD5R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPD5R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPD5R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPD5R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPD5R, 15)),
+        PIC32_PINCTRL_GROUP(54, D6,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 14),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 14),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 14),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 14),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 14),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 14),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 14),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 14),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 14),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 14),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 14),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 14),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 14),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPD6R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPD6R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPD6R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPD6R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPD6R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPD6R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPD6R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPD6R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPD6R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD6R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPD6R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPD6R, 15)),
+        PIC32_PINCTRL_GROUP(55, D7,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 14),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 14),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 14),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 14),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 14),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 14),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 14),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 14),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 14),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPD7R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPD7R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPD7R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPD7R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPD7R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPD7R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPD7R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPD7R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPD7R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPD7R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPD7R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD7R, 15)),
+        PIC32_PINCTRL_GROUP(57, D9,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 0),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 0),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 0),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 0),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 0),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 0),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 0),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 0),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 0),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 0),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 0),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 0),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 0),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 0),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPD9R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPD9R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPD9R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPD9R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPD9R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPD9R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPD9R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPD9R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPD9R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPD9R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPD9R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD9R, 15)),
+        PIC32_PINCTRL_GROUP(58, D10,
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPD10R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPD10R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPD10R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPD10R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPD10R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPD10R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPD10R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPD10R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPD10R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD10R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPD10R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPD10R, 15)),
+        PIC32_PINCTRL_GROUP(59, D11,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 3),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 3),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 3),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 3),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 3),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 3),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 3),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 3),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 3),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 3),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 3),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPD11R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPD11R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPD11R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPD11R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPD11R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPD11R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPD11R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPD11R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPD11R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPD11R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPD11R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD11R, 15)),
+        PIC32_PINCTRL_GROUP(60, D12,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 10),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 10),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 10),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 10),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 10),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 10),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 10),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 10),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 10),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 10),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 10),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 10),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 10),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 10),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPD12R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPD12R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPD12R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPD12R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPD12R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPD12R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPD12R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPD12R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPD12R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPD12R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPD12R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD12R, 15)),
+        PIC32_PINCTRL_GROUP(62, D14,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 11),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 11),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 11),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 11),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 11),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 11),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 11),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 11),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 11),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 11),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 11),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 11),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 11),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 11),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPD14R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPD14R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPD14R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPD14R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPD14R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPD14R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPD14R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPD14R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPD14R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD14R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPD14R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPD14R, 15)),
+        PIC32_PINCTRL_GROUP(63, D15,
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPD15R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPD15R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPD15R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPD15R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPD15R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPD15R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPD15R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPD15R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPD15R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPD15R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPD15R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD15R, 15)),
+        PIC32_PINCTRL_GROUP(67, E3,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 6),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 6),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 6),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 6),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 6),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 6),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 6),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 6),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 6),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 6),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 6),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 6),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 6),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 6),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPE3R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPE3R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPE3R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPE3R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPE3R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPE3R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPE3R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPE3R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPE3R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPE3R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPE3R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPE3R, 15)),
+        PIC32_PINCTRL_GROUP(69, E5,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 6),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 6),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 6),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 6),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 6),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 6),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 6),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 6),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 6),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 6),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPE5R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPE5R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPE5R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPE5R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPE5R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPE5R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPE5R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPE5R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPE5R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPE5R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPE5R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPE5R, 15)),
+        PIC32_PINCTRL_GROUP(72, E8,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 13),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 13),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 13),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 13),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 13),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 13),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 13),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 13),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 13),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 13),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 13),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 13),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPE8R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPE8R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPE8R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPE8R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPE8R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPE8R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPE8R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPE8R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPE8R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPE8R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPE8R, 15)),
+        PIC32_PINCTRL_GROUP(73, E9,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 13),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 13),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 13),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 13),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 13),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 13),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 13),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 13),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 13),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 13),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 13),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 13),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 13),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 13),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPE9R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPE9R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPE9R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPE9R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPE9R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPE9R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPE9R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPE9R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPE9R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPE9R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPE9R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPE9R, 15)),
+        PIC32_PINCTRL_GROUP(80, F0,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 4),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 4),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 4),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 4),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 4),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 4),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 4),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 4),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 4),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 4),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPF0R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPF0R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPF0R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPF0R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPF0R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPF0R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPF0R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPF0R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPF0R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPF0R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPF0R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPF0R, 15)),
+        PIC32_PINCTRL_GROUP(81, F1,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 4),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 4),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 4),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 4),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 4),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 4),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 4),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 4),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 4),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 4),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 4),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPF1R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPF1R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPF1R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPF1R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPF1R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPF1R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPF1R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPF1R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPF1R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPF1R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPF1R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPF1R, 15)),
+        PIC32_PINCTRL_GROUP(82, F2,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 11),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 11),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 11),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 11),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 11),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 11),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 11),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 11),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 11),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 11),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 11),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 11),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPF2R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPF2R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPF2R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPF2R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPF2R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPF2R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPF2R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPF2R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPF2R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPF2R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPF2R, 15)),
+        PIC32_PINCTRL_GROUP(83, F3,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 8),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 8),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 8),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 8),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 8),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 8),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 8),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 8),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 8),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 8),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 8),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 8),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPF3R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPF3R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPF3R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPF3R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPF3R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPF3R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPF3R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPF3R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPF3R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPF3R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPF3R, 15)),
+        PIC32_PINCTRL_GROUP(84, F4,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 2),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 2),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 2),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 2),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 2),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 2),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 2),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 2),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 2),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 2),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 2),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPF4R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPF4R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPF4R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPF4R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPF4R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPF4R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPF4R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPF4R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPF4R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPF4R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPF4R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPF4R, 15)),
+        PIC32_PINCTRL_GROUP(85, F5,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 2),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 2),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 2),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 2),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 2),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 2),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 2),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 2),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 2),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 2),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPF5R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPF5R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPF5R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPF5R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPF5R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPF5R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPF5R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPF5R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPF5R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPF5R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPF5R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPF5R, 15)),
+        PIC32_PINCTRL_GROUP(88, F8,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 11),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 11),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 11),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 11),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 11),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 11),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 11),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 11),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 11),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 11),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 11),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 11),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 11),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 11),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPF8R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPF8R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPF8R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPF8R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPF8R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPF8R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPF8R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPF8R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPF8R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPF8R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPF8R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPF8R, 15)),
+        PIC32_PINCTRL_GROUP(92, F12,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 9),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 9),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 9),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 9),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 9),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 9),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 9),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 9),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 9),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 9),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 9),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 9),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 9),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 9),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPF12R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPF12R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPF12R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPF12R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPF12R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPF12R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPF12R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPF12R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPF12R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPF12R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPF12R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPF12R, 15)),
+        PIC32_PINCTRL_GROUP(93, F13,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 9),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 9),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 9),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 9),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 9),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 9),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 9),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 9),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 9),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 9),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 9),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 9),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPF13R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPF13R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPF13R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPF13R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPF13R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPF13R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPF13R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPF13R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPF13R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPF13R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPF13R, 15)),
+        PIC32_PINCTRL_GROUP(96, G0,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 12),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 12),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 12),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 12),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 12),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 12),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 12),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 12),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 12),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPG0R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPG0R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPG0R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPG0R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPG0R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPG0R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPG0R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPG0R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPG0R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPG0R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPG0R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPG0R, 15)),
+        PIC32_PINCTRL_GROUP(97, G1,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 12),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 12),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 12),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 12),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 12),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 12),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 12),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 12),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 12),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 12),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 12),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 12),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 12),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPG1R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPG1R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPG1R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPG1R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPG1R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPG1R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPG1R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPG1R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPG1R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPG1R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPG1R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPG1R, 15)),
+        PIC32_PINCTRL_GROUP(102, G6,
+                        PIC32_PINCTRL_FUNCTION(INT2, INT2R, 1),
+                        PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 1),
+                        PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 1),
+                        PIC32_PINCTRL_FUNCTION(IC2, IC2R, 1),
+                        PIC32_PINCTRL_FUNCTION(IC5, IC5R, 1),
+                        PIC32_PINCTRL_FUNCTION(IC9, IC9R, 1),
+                        PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 1),
+                        PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 1),
+                        PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 1),
+                        PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 1),
+                        PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 1),
+                        PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 1),
+                        PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 1),
+                        PIC32_PINCTRL_FUNCTION(U3RTS, RPG6R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4TX, RPG6R, 2),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPG6R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS1OUT, RPG6R, 5),
+                        PIC32_PINCTRL_FUNCTION(SS3OUT, RPG6R, 7),
+                        PIC32_PINCTRL_FUNCTION(SS4OUT, RPG6R, 8),
+                        PIC32_PINCTRL_FUNCTION(SS5OUT, RPG6R, 9),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPG6R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC5, RPG6R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC8, RPG6R, 12),
+                        PIC32_PINCTRL_FUNCTION(C1OUT, RPG6R, 14),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO3, RPG6R, 15)),
+        PIC32_PINCTRL_GROUP(103, G7,
+                        PIC32_PINCTRL_FUNCTION(INT4, INT4R, 1),
+                        PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 1),
+                        PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 1),
+                        PIC32_PINCTRL_FUNCTION(IC4, IC4R, 1),
+                        PIC32_PINCTRL_FUNCTION(IC8, IC8R, 1),
+                        PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 1),
+                        PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 1),
+                        PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 1),
+                        PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 1),
+                        PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 1),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 1),
+                        PIC32_PINCTRL_FUNCTION(U1TX, RPG7R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2RTS, RPG7R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5TX, RPG7R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6RTS, RPG7R, 4),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPG7R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPG7R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPG7R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPG7R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPG7R, 9),
+                        PIC32_PINCTRL_FUNCTION(OC4, RPG7R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC7, RPG7R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO1, RPG7R, 15)),
+        PIC32_PINCTRL_GROUP(104, G8,
+                        PIC32_PINCTRL_FUNCTION(INT3, INT3R, 1),
+                        PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 1),
+                        PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 1),
+                        PIC32_PINCTRL_FUNCTION(IC3, IC3R, 1),
+                        PIC32_PINCTRL_FUNCTION(IC7, IC7R, 1),
+                        PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 1),
+                        PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 1),
+                        PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 1),
+                        PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 1),
+                        PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 1),
+                        PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 1),
+                        PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 1),
+                        PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 1),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 1),
+                        PIC32_PINCTRL_FUNCTION(U3TX, RPG8R, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RTS, RPG8R, 2),
+                        PIC32_PINCTRL_FUNCTION(SDO1, RPG8R, 5),
+                        PIC32_PINCTRL_FUNCTION(SDO2, RPG8R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO3, RPG8R, 7),
+                        PIC32_PINCTRL_FUNCTION(SDO5, RPG8R, 9),
+                        PIC32_PINCTRL_FUNCTION(SS6OUT, RPG8R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC3, RPG8R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC6, RPG8R, 12),
+                        PIC32_PINCTRL_FUNCTION(REFCLKO4, RPG8R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2OUT, RPG8R, 14),
+                        PIC32_PINCTRL_FUNCTION(C1TX, RPG8R, 15)),
+        PIC32_PINCTRL_GROUP(105, G9,
+                        PIC32_PINCTRL_FUNCTION(INT1, INT1R, 1),
+                        PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 1),
+                        PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 1),
+                        PIC32_PINCTRL_FUNCTION(IC1, IC1R, 1),
+                        PIC32_PINCTRL_FUNCTION(IC6, IC6R, 1),
+                        PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 1),
+                        PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 1),
+                        PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 1),
+                        PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 1),
+                        PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 1),
+                        PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 1),
+                        PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 1),
+                        PIC32_PINCTRL_FUNCTION(U1RTS, RPG9R, 1),
+                        PIC32_PINCTRL_FUNCTION(U2TX, RPG9R, 2),
+                        PIC32_PINCTRL_FUNCTION(U5RTS, RPG9R, 3),
+                        PIC32_PINCTRL_FUNCTION(U6TX, RPG9R, 4),
+                        PIC32_PINCTRL_FUNCTION(SS2OUT, RPG9R, 6),
+                        PIC32_PINCTRL_FUNCTION(SDO4, RPG9R, 8),
+                        PIC32_PINCTRL_FUNCTION(SDO6, RPG9R, 10),
+                        PIC32_PINCTRL_FUNCTION(OC2, RPG9R, 11),
+                        PIC32_PINCTRL_FUNCTION(OC1, RPG9R, 12),
+                        PIC32_PINCTRL_FUNCTION(OC9, RPG9R, 13),
+                        PIC32_PINCTRL_FUNCTION(C2TX, RPG9R, 15)),
+};
+
+static inline struct pic32_gpio_bank *irqd_to_bank(struct irq_data *d)
+{
+        return gpiochip_get_data(irq_data_get_irq_chip_data(d));
+}
+
+static inline struct pic32_gpio_bank *pctl_to_bank(struct pic32_pinctrl *pctl,
+                                                unsigned pin)
+{
+        return &pctl->gpio_banks[pin / PINS_PER_BANK];
+}
+
+static int pic32_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+        struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        return pctl->ngroups;
+}
+
+static const char *pic32_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+                                                    unsigned group)
+{
+        struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        return pctl->groups[group].name;
+}
+
+static int pic32_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+                                            unsigned group,
+                                            const unsigned **pins,
+                                            unsigned *num_pins)
+{
+        struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        *pins = &pctl->groups[group].pin;
+        *num_pins = 1;
+
+        return 0;
+}
+
+static const struct pinctrl_ops pic32_pinctrl_ops = {
+        .get_groups_count = pic32_pinctrl_get_groups_count,
+        .get_group_name = pic32_pinctrl_get_group_name,
+        .get_group_pins = pic32_pinctrl_get_group_pins,
+        .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+        .dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int pic32_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
+{
+        struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        return pctl->nfunctions;
+}
+
+static const char *
+pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
+{
+        struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        return pctl->functions[func].name;
+}
+
+static int pic32_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
+                                                unsigned func,
+                                                const char * const **groups,
+                                                unsigned * const num_groups)
+{
+        struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        *groups = pctl->functions[func].groups;
+        *num_groups = pctl->functions[func].ngroups;
+
+        return 0;
+}
+
+static int pic32_pinmux_enable(struct pinctrl_dev *pctldev,
+                                   unsigned func, unsigned group)
+{
+        struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct pic32_pin_group *pg = &pctl->groups[group];
+        const struct pic32_function *pf = &pctl->functions[func];
+        const char *fname = pf->name;
+        struct pic32_desc_function *functions = pg->functions;
+
+        while (functions->name) {
+                if (!strcmp(functions->name, fname)) {
+                        dev_dbg(pctl->dev,
+                                "setting function %s reg 0x%x = %d\n",
+                                fname, functions->muxreg, functions->muxval);
+
+                        writel(functions->muxval, pctl->reg_base + functions->muxreg);
+
+                        return 0;
+                }
+
+                functions++;
+        }
+
+        dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
+
+        return -EINVAL;
+}
+
+static int pic32_gpio_request_enable(struct pinctrl_dev *pctldev,
+                                     struct pinctrl_gpio_range *range,
+                                     unsigned offset)
+{
+        struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc);
+        u32 mask = BIT(offset - bank->gpio_chip.base);
+
+        dev_dbg(pctl->dev, "requesting gpio %d in bank %d with mask 0x%x\n",
+                offset, bank->gpio_chip.base, mask);
+
+        writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG));
+
+        return 0;
+}
+
+static int pic32_gpio_direction_input(struct gpio_chip *chip,
+                                          unsigned offset)
+{
+        struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
+        u32 mask = BIT(offset);
+
+        writel(mask, bank->reg_base + PIC32_SET(TRIS_REG));
+
+        return 0;
+}
+
+static int pic32_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
+
+        return !!(readl(bank->reg_base + PORT_REG) & BIT(offset));
+}
+
+static void pic32_gpio_set(struct gpio_chip *chip, unsigned offset,
+                               int value)
+{
+        struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
+        u32 mask = BIT(offset);
+
+        if (value)
+                writel(mask, bank->reg_base + PIC32_SET(PORT_REG));
+        else
+                writel(mask, bank->reg_base + PIC32_CLR(PORT_REG));
+}
+
+static int pic32_gpio_direction_output(struct gpio_chip *chip,
+                                           unsigned offset, int value)
+{
+        struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
+        u32 mask = BIT(offset);
+
+        pic32_gpio_set(chip, offset, value);
+        writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG));
+
+        return 0;
+}
+
+static int pic32_gpio_set_direction(struct pinctrl_dev *pctldev,
+                                              struct pinctrl_gpio_range *range,
+                                              unsigned offset, bool input)
+{
+        struct gpio_chip *chip = range->gc;
+
+        if (input)
+                pic32_gpio_direction_input(chip, offset);
+        else
+                pic32_gpio_direction_output(chip, offset, 0);
+
+        return 0;
+}
+
+static const struct pinmux_ops pic32_pinmux_ops = {
+        .get_functions_count = pic32_pinmux_get_functions_count,
+        .get_function_name = pic32_pinmux_get_function_name,
+        .get_function_groups = pic32_pinmux_get_function_groups,
+        .set_mux = pic32_pinmux_enable,
+        .gpio_request_enable = pic32_gpio_request_enable,
+        .gpio_set_direction = pic32_gpio_set_direction,
+};
+
+static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
+                                 unsigned long *config)
+{
+        struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
+        unsigned param = pinconf_to_config_param(*config);
+        u32 mask = BIT(pin - bank->gpio_chip.base);
+        u32 arg;
+
+        switch (param) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+                arg = !!(readl(bank->reg_base + CNPU_REG) & mask);
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                arg = !!(readl(bank->reg_base + CNPD_REG) & mask);
+                break;
+        case PIN_CONFIG_MICROCHIP_DIGITAL:
+                arg = !(readl(bank->reg_base + ANSEL_REG) & mask);
+                break;
+        case PIN_CONFIG_MICROCHIP_ANALOG:
+                arg = !!(readl(bank->reg_base + ANSEL_REG) & mask);
+                break;
+        case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+                arg = !!(readl(bank->reg_base + ODCU_REG) & mask);
+                break;
+        case PIN_CONFIG_INPUT_ENABLE:
+                arg = !!(readl(bank->reg_base + TRIS_REG) & mask);
+                break;
+        case PIN_CONFIG_OUTPUT:
+                arg = !(readl(bank->reg_base + TRIS_REG) & mask);
+                break;
+        default:
+                dev_err(pctl->dev, "Property %u not supported\n", param);
+                return -ENOTSUPP;
+        }
+
+        *config = pinconf_to_config_packed(param, arg);
+
+        return 0;
+}
+
+static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
+                                 unsigned long *configs, unsigned num_configs)
+{
+        struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
+        unsigned param;
+        u32 arg;
+        unsigned int i;
+        u32 offset = pin - bank->gpio_chip.base;
+        u32 mask = BIT(offset);
+
+        dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
+                pin, bank->gpio_chip.base, mask);
+
+        for (i = 0; i < num_configs; i++) {
+                param = pinconf_to_config_param(configs[i]);
+                arg = pinconf_to_config_argument(configs[i]);
+
+                switch (param) {
+                case PIN_CONFIG_BIAS_PULL_UP:
+                        dev_dbg(pctl->dev, "   pullup\n");
+                        writel(mask, bank->reg_base +PIC32_SET(CNPU_REG));
+                        break;
+                case PIN_CONFIG_BIAS_PULL_DOWN:
+                        dev_dbg(pctl->dev, "   pulldown\n");
+                        writel(mask, bank->reg_base + PIC32_SET(CNPD_REG));
+                        break;
+                case PIN_CONFIG_MICROCHIP_DIGITAL:
+                        dev_dbg(pctl->dev, "   digital\n");
+                        writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG));
+                        break;
+                case PIN_CONFIG_MICROCHIP_ANALOG:
+                        dev_dbg(pctl->dev, "   analog\n");
+                        writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG));
+                        break;
+                case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+                        dev_dbg(pctl->dev, "   opendrain\n");
+                        writel(mask, bank->reg_base + PIC32_SET(ODCU_REG));
+                        break;
+                case PIN_CONFIG_INPUT_ENABLE:
+                        pic32_gpio_direction_input(&bank->gpio_chip, offset);
+                        break;
+                case PIN_CONFIG_OUTPUT:
+                        pic32_gpio_direction_output(&bank->gpio_chip,
+                                                    offset, arg);
+                        break;
+                default:
+                        dev_err(pctl->dev, "Property %u not supported\n",
+                                param);
+                        return -ENOTSUPP;
+                }
+        }
+
+        return 0;
+}
+
+static const struct pinconf_ops pic32_pinconf_ops = {
+        .pin_config_get = pic32_pinconf_get,
+        .pin_config_set = pic32_pinconf_set,
+        .is_generic = true,
+};
+
+static struct pinctrl_desc pic32_pinctrl_desc = {
+        .name = "pic32-pinctrl",
+        .pctlops = &pic32_pinctrl_ops,
+        .pmxops = &pic32_pinmux_ops,
+        .confops = &pic32_pinconf_ops,
+        .owner = THIS_MODULE,
+};
+
+static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
+{
+        struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
+
+        return !!(readl(bank->reg_base + TRIS_REG) & BIT(offset));
+}
+
+static void pic32_gpio_irq_ack(struct irq_data *data)
+{
+        struct pic32_gpio_bank *bank = irqd_to_bank(data);
+
+        writel(0, bank->reg_base + CNF_REG);
+}
+
+static void pic32_gpio_irq_mask(struct irq_data *data)
+{
+        struct pic32_gpio_bank *bank = irqd_to_bank(data);
+
+        writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG));
+}
+
+static void pic32_gpio_irq_unmask(struct irq_data *data)
+{
+        struct pic32_gpio_bank *bank = irqd_to_bank(data);
+
+        writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG));
+}
+
+static unsigned int pic32_gpio_irq_startup(struct irq_data *data)
+{
+        struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
+
+        pic32_gpio_direction_input(chip, data->hwirq);
+        pic32_gpio_irq_unmask(data);
+
+        return 0;
+}
+
+static int pic32_gpio_irq_set_type(struct irq_data *data, unsigned int type)
+{
+        struct pic32_gpio_bank *bank = irqd_to_bank(data);
+        u32 mask = BIT(data->hwirq);
+
+        switch (type & IRQ_TYPE_SENSE_MASK) {
+        case IRQ_TYPE_EDGE_RISING:
+                /* enable RISE */
+                writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));
+                /* disable FALL */
+                writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG));
+                /* enable EDGE */
+                writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                /* disable RISE */
+                writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG));
+                /* enable FALL */
+                writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));
+                /* enable EDGE */
+                writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                /* enable RISE */
+                writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));
+                /* enable FALL */
+                writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));
+                /* enable EDGE */
+                writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        irq_set_handler_locked(data, handle_edge_irq);
+
+        return 0;
+}
+
+static u32 pic32_gpio_get_pending(struct gpio_chip *gc, unsigned long status)
+{
+        struct pic32_gpio_bank *bank = gpiochip_get_data(gc);
+        u32 pending = 0;
+        u32 cnen_rise, cnne_fall;
+        u32 pin;
+
+        cnen_rise = readl(bank->reg_base + CNEN_REG);
+        cnne_fall = readl(bank->reg_base + CNNE_REG);
+
+        for_each_set_bit(pin, &status, BITS_PER_LONG) {
+                u32 mask = BIT(pin);
+
+                if ((mask & cnen_rise) || (mask && cnne_fall))
+                        pending |= mask;
+        }
+
+        return pending;
+}
+
+static void pic32_gpio_irq_handler(struct irq_desc *desc)
+{
+        struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+        struct pic32_gpio_bank *bank = gpiochip_get_data(gc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        unsigned long pending;
+        unsigned int pin;
+        u32 stat;
+
+        chained_irq_enter(chip, desc);
+
+        stat = readl(bank->reg_base + CNF_REG);
+        pending = pic32_gpio_get_pending(gc, stat);
+
+        for_each_set_bit(pin, &pending, BITS_PER_LONG)
+                generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
+
+        chained_irq_exit(chip, desc);
+}
+
+#define GPIO_BANK(_bank, _npins)                                        \
+        {                                                               \
+                .gpio_chip = {                                          \
+                        .label = "GPIO" #_bank,                         \
+                        .request = gpiochip_generic_request,            \
+                        .free = gpiochip_generic_free,                  \
+                        .get_direction = pic32_gpio_get_direction,      \
+                        .direction_input = pic32_gpio_direction_input,  \
+                        .direction_output = pic32_gpio_direction_output, \
+                        .get = pic32_gpio_get,                          \
+                        .set = pic32_gpio_set,                          \
+                        .ngpio = _npins,                                \
+                        .base = GPIO_BANK_START(_bank),                 \
+                        .owner = THIS_MODULE,                           \
+                        .can_sleep = 0,                                 \
+                },                                                      \
+                .irq_chip = {                                           \
+                        .name = "GPIO" #_bank,                          \
+                        .irq_startup = pic32_gpio_irq_startup,  \
+                        .irq_ack = pic32_gpio_irq_ack,          \
+                        .irq_mask = pic32_gpio_irq_mask,                \
+                        .irq_unmask = pic32_gpio_irq_unmask,            \
+                        .irq_set_type = pic32_gpio_irq_set_type,        \
+                },                                                      \
+        }
+
+static struct pic32_gpio_bank pic32_gpio_banks[] = {
+        GPIO_BANK(0, PINS_PER_BANK),
+        GPIO_BANK(1, PINS_PER_BANK),
+        GPIO_BANK(2, PINS_PER_BANK),
+        GPIO_BANK(3, PINS_PER_BANK),
+        GPIO_BANK(4, PINS_PER_BANK),
+        GPIO_BANK(5, PINS_PER_BANK),
+        GPIO_BANK(6, PINS_PER_BANK),
+        GPIO_BANK(7, PINS_PER_BANK),
+        GPIO_BANK(8, PINS_PER_BANK),
+        GPIO_BANK(9, PINS_PER_BANK),
+};
+
+static int pic32_pinctrl_probe(struct platform_device *pdev)
+{
+        struct pic32_pinctrl *pctl;
+        struct resource *res;
+        int ret;
+
+        pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
+        if (!pctl)
+                return -ENOMEM;
+        pctl->dev = &pdev->dev;
+        dev_set_drvdata(&pdev->dev, pctl);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        pctl->reg_base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(pctl->reg_base))
+                return PTR_ERR(pctl->reg_base);
+
+        pctl->clk = devm_clk_get(&pdev->dev, NULL);
+        if (IS_ERR(pctl->clk)) {
+                ret = PTR_ERR(pctl->clk);
+                dev_err(&pdev->dev, "clk get failed\n");
+                return ret;
+        }
+
+        ret = clk_prepare_enable(pctl->clk);
+        if (ret) {
+                dev_err(&pdev->dev, "clk enable failed\n");
+                return ret;
+        }
+
+        pctl->pins = pic32_pins;
+        pctl->npins = ARRAY_SIZE(pic32_pins);
+        pctl->functions = pic32_functions;
+        pctl->nfunctions = ARRAY_SIZE(pic32_functions);
+        pctl->groups = pic32_groups;
+        pctl->ngroups = ARRAY_SIZE(pic32_groups);
+        pctl->gpio_banks = pic32_gpio_banks;
+        pctl->nbanks = ARRAY_SIZE(pic32_gpio_banks);
+
+        pic32_pinctrl_desc.pins = pctl->pins;
+        pic32_pinctrl_desc.npins = pctl->npins;
+        pic32_pinctrl_desc.custom_params = pic32_mpp_bindings;
+        pic32_pinctrl_desc.num_custom_params = ARRAY_SIZE(pic32_mpp_bindings);
+
+        pctl->pctldev = pinctrl_register(&pic32_pinctrl_desc, &pdev->dev, pctl);
+        if (IS_ERR(pctl->pctldev)) {
+                dev_err(&pdev->dev, "Failed to register pinctrl device\n");
+                return PTR_ERR(pctl->pctldev);
+        }
+
+        return 0;
+}
+
+static int pic32_gpio_probe(struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct pic32_gpio_bank *bank;
+        u32 id;
+        int irq, ret;
+        struct resource *res;
+
+        if (of_property_read_u32(np, "microchip,gpio-bank", &id)) {
+                dev_err(&pdev->dev, "microchip,gpio-bank property not found\n");
+                return -EINVAL;
+        }
+
+        if (id >= ARRAY_SIZE(pic32_gpio_banks)) {
+                dev_err(&pdev->dev, "invalid microchip,gpio-bank property\n");
+                return -EINVAL;
+        }
+
+        bank = &pic32_gpio_banks[id];
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        bank->reg_base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(bank->reg_base))
+                return PTR_ERR(bank->reg_base);
+
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0) {
+                dev_err(&pdev->dev, "irq get failed\n");
+                return irq;
+        }
+
+        bank->clk = devm_clk_get(&pdev->dev, NULL);
+        if (IS_ERR(bank->clk)) {
+                ret = PTR_ERR(bank->clk);
+                dev_err(&pdev->dev, "clk get failed\n");
+                return ret;
+        }
+
+        ret = clk_prepare_enable(bank->clk);
+        if (ret) {
+                dev_err(&pdev->dev, "clk enable failed\n");
+                return ret;
+        }
+
+        bank->gpio_chip.parent = &pdev->dev;
+        bank->gpio_chip.of_node = np;
+        ret = gpiochip_add_data(&bank->gpio_chip, bank);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
+                        id, ret);
+                return ret;
+        }
+
+        ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
+                                0, handle_level_irq, IRQ_TYPE_NONE);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n",
+                        id, ret);
+                gpiochip_remove(&bank->gpio_chip);
+                return ret;
+        }
+
+        gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
+                                     irq, pic32_gpio_irq_handler);
+
+        return 0;
+}
+
+static const struct of_device_id pic32_pinctrl_of_match[] = {
+        { .compatible = "microchip,pic32mzda-pinctrl", },
+        { },
+};
+
+static struct platform_driver pic32_pinctrl_driver = {
+        .driver = {
+                .name = "pic32-pinctrl",
+                .of_match_table = pic32_pinctrl_of_match,
+                .suppress_bind_attrs = true,
+        },
+        .probe = pic32_pinctrl_probe,
+};
+
+static const struct of_device_id pic32_gpio_of_match[] = {
+        { .compatible = "microchip,pic32mzda-gpio", },
+        { },
+};
+
+static struct platform_driver pic32_gpio_driver = {
+        .driver = {
+                .name = "pic32-gpio",
+                .of_match_table = pic32_gpio_of_match,
+                .suppress_bind_attrs = true,
+        },
+        .probe = pic32_gpio_probe,
+};
+
+static int __init pic32_gpio_register(void)
+{
+        return platform_driver_register(&pic32_gpio_driver);
+}
+arch_initcall(pic32_gpio_register);
+
+static int __init pic32_pinctrl_register(void)
+{
+        return platform_driver_register(&pic32_pinctrl_driver);
+}
+arch_initcall(pic32_pinctrl_register);
diff --git a/drivers/pinctrl/pinctrl-pic32.h b/drivers/pinctrl/pinctrl-pic32.h
new file mode 100644
index 000000000000..12826267dc96
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-pic32.h
@@ -0,0 +1,141 @@
+/*
+ * PIC32 pinctrl driver
+ *
+ * Joshua Henderson, <joshua.henderson@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+#ifndef PINCTRL_PINCTRL_PIC32_H
+#define PINCTRL_PINCTRL_PIC32_H
+
+/* PORT Registers */
+#define ANSEL_REG       0x00
+#define TRIS_REG        0x10
+#define PORT_REG        0x20
+#define LAT_REG         0x30
+#define ODCU_REG        0x40
+#define CNPU_REG        0x50
+#define CNPD_REG        0x60
+#define CNCON_REG       0x70
+#define CNEN_REG        0x80
+#define CNSTAT_REG      0x90
+#define CNNE_REG        0xA0
+#define CNF_REG         0xB0
+
+/* Input PPS Registers */
+#define INT1R 0x04
+#define INT2R 0x08
+#define INT3R 0x0C
+#define INT4R 0x10
+#define T2CKR 0x18
+#define T3CKR 0x1C
+#define T4CKR 0x20
+#define T5CKR 0x24
+#define T6CKR 0x28
+#define T7CKR 0x2C
+#define T8CKR 0x30
+#define T9CKR 0x34
+#define IC1R 0x38
+#define IC2R 0x3C
+#define IC3R 0x40
+#define IC4R 0x44
+#define IC5R 0x48
+#define IC6R 0x4C
+#define IC7R 0x50
+#define IC8R 0x54
+#define IC9R 0x58
+#define OCFAR 0x60
+#define U1RXR 0x68
+#define U1CTSR 0x6C
+#define U2RXR 0x70
+#define U2CTSR 0x74
+#define U3RXR 0x78
+#define U3CTSR 0x7C
+#define U4RXR 0x80
+#define U4CTSR 0x84
+#define U5RXR 0x88
+#define U5CTSR 0x8C
+#define U6RXR 0x90
+#define U6CTSR 0x94
+#define SDI1R 0x9C
+#define SS1INR 0xA0
+#define SDI2R 0xA8
+#define SS2INR 0xAC
+#define SDI3R 0xB4
+#define SS3INR 0xB8
+#define SDI4R 0xC0
+#define SS4INR 0xC4
+#define SDI5R 0xCC
+#define SS5INR 0xD0
+#define SDI6R 0xD8
+#define SS6INR 0xDC
+#define C1RXR 0xE0
+#define C2RXR 0xE4
+#define REFCLKI1R 0xE8
+#define REFCLKI3R 0xF0
+#define REFCLKI4R 0xF4
+
+/* Output PPS Registers */
+#define RPA14R 0x138
+#define RPA15R 0x13C
+#define RPB0R 0x140
+#define RPB1R 0x144
+#define RPB2R 0x148
+#define RPB3R 0x14C
+#define RPB5R 0x154
+#define RPB6R 0x158
+#define RPB7R 0x15C
+#define RPB8R 0x160
+#define RPB9R 0x164
+#define RPB10R 0x168
+#define RPB14R 0x178
+#define RPB15R 0x17C
+#define RPC1R 0x184
+#define RPC2R 0x188
+#define RPC3R 0x18C
+#define RPC4R 0x190
+#define RPC13R 0x1B4
+#define RPC14R 0x1B8
+#define RPD0R 0x1C0
+#define RPD1R 0x1C4
+#define RPD2R 0x1C8
+#define RPD3R 0x1CC
+#define RPD4R 0x1D0
+#define RPD5R 0x1D4
+#define RPD6R 0x1D8
+#define RPD7R 0x1DC
+#define RPD9R 0x1E4
+#define RPD10R 0x1E8
+#define RPD11R 0x1EC
+#define RPD12R 0x1F0
+#define RPD14R 0x1F8
+#define RPD15R 0x1FC
+#define RPE3R 0x20C
+#define RPE5R 0x214
+#define RPE8R 0x220
+#define RPE9R 0x224
+#define RPF0R 0x240
+#define RPF1R 0x244
+#define RPF2R 0x248
+#define RPF3R 0x24C
+#define RPF4R 0x250
+#define RPF5R 0x254
+#define RPF8R 0x260
+#define RPF12R 0x270
+#define RPF13R 0x274
+#define RPG0R 0x280
+#define RPG1R 0x284
+#define RPG6R 0x298
+#define RPG7R 0x29C
+#define RPG8R 0x2A0
+#define RPG9R 0x2A4
+
+#endif  /* PINCTRL_PINCTRL_PIC32_H */
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 183545a068ad..bf032b9b4c57 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -64,6 +64,7 @@ enum rockchip_pinctrl_type {
         RK3188,
         RK3288,
         RK3368,
+        RK3399,
 };
 
 /**
@@ -86,6 +87,31 @@ struct rockchip_iomux {
 };
 
 /**
+ * enum type index corresponding to rockchip_perpin_drv_list arrays index.
+ */
+enum rockchip_pin_drv_type {
+        DRV_TYPE_IO_DEFAULT = 0,
+        DRV_TYPE_IO_1V8_OR_3V0,
+        DRV_TYPE_IO_1V8_ONLY,
+        DRV_TYPE_IO_1V8_3V0_AUTO,
+        DRV_TYPE_IO_3V3_ONLY,
+        DRV_TYPE_MAX
+};
+
+/**
+ * @drv_type: drive strength variant using rockchip_perpin_drv_type
+ * @offset: if initialized to -1 it will be autocalculated, by specifying
+ *          an initial offset value the relevant source offset can be reset
+ *          to a new value for autocalculating the following drive strength
+ *          registers. if used chips own cal_drv func instead to calculate
+ *          registers offset, the variant could be ignored.
+ */
+struct rockchip_drv {
+        enum rockchip_pin_drv_type      drv_type;
+        int                             offset;
+};
+
+/**
  * @reg_base: register base of the gpio bank
  * @reg_pull: optional separate register for additional pull settings
  * @clk: clock of the gpio bank
@@ -96,6 +122,7 @@ struct rockchip_iomux {
  * @name: name of the bank
  * @bank_num: number of the bank, to account for holes
  * @iomux: array describing the 4 iomux sources of the bank
+ * @drv: array describing the 4 drive strength sources of the bank
  * @valid: are all necessary informations present
  * @of_node: dt node of this bank
  * @drvdata: common pinctrl basedata
@@ -115,6 +142,7 @@ struct rockchip_pin_bank {
         char                            *name;
         u8                              bank_num;
         struct rockchip_iomux           iomux[4];
+        struct rockchip_drv             drv[4];
         bool                            valid;
         struct device_node              *of_node;
         struct rockchip_pinctrl         *drvdata;
@@ -151,6 +179,47 @@ struct rockchip_pin_bank {
                 },                                                      \
         }
 
+#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
+        {                                                               \
+                .bank_num       = id,                                   \
+                .nr_pins        = pins,                                 \
+                .name           = label,                                \
+                .iomux          = {                                     \
+                        { .offset = -1 },                               \
+                        { .offset = -1 },                               \
+                        { .offset = -1 },                               \
+                        { .offset = -1 },                               \
+                },                                                      \
+                .drv            = {                                     \
+                        { .drv_type = type0, .offset = -1 },            \
+                        { .drv_type = type1, .offset = -1 },            \
+                        { .drv_type = type2, .offset = -1 },            \
+                        { .drv_type = type3, .offset = -1 },            \
+                },                                                      \
+        }
+
+#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
+                                        iom2, iom3, drv0, drv1, drv2,   \
+                                        drv3, offset0, offset1,         \
+                                        offset2, offset3)               \
+        {                                                               \
+                .bank_num       = id,                                   \
+                .nr_pins        = pins,                                 \
+                .name           = label,                                \
+                .iomux          = {                                     \
+                        { .type = iom0, .offset = -1 },                 \
+                        { .type = iom1, .offset = -1 },                 \
+                        { .type = iom2, .offset = -1 },                 \
+                        { .type = iom3, .offset = -1 },                 \
+                },                                                      \
+                .drv            = {                                     \
+                        { .drv_type = drv0, .offset = offset0 },        \
+                        { .drv_type = drv1, .offset = offset1 },        \
+                        { .drv_type = drv2, .offset = offset2 },        \
+                        { .drv_type = drv3, .offset = offset3 },        \
+                },                                                      \
+        }
+
 /**
  */
 struct rockchip_pin_ctrl {
@@ -161,6 +230,9 @@ struct rockchip_pin_ctrl {
         enum rockchip_pinctrl_type      type;
         int                             grf_mux_offset;
         int                             pmu_mux_offset;
+        int                             grf_drv_offset;
+        int                             pmu_drv_offset;
+
         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
                                     int pin_num, struct regmap **regmap,
                                     int *reg, u8 *bit);
@@ -705,7 +777,68 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
         }
 }
 
-static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 };
+#define RK3399_PULL_GRF_OFFSET          0xe040
+#define RK3399_PULL_PMU_OFFSET          0x40
+#define RK3399_DRV_3BITS_PER_PIN        3
+
+static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+                                         int pin_num, struct regmap **regmap,
+                                         int *reg, u8 *bit)
+{
+        struct rockchip_pinctrl *info = bank->drvdata;
+
+        /* The bank0:16 and bank1:32 pins are located in PMU */
+        if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
+                *regmap = info->regmap_pmu;
+                *reg = RK3399_PULL_PMU_OFFSET;
+
+                *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+
+                *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+                *bit = pin_num % RK3188_PULL_PINS_PER_REG;
+                *bit *= RK3188_PULL_BITS_PER_PIN;
+        } else {
+                *regmap = info->regmap_base;
+                *reg = RK3399_PULL_GRF_OFFSET;
+
+                /* correct the offset, as we're starting with the 3rd bank */
+                *reg -= 0x20;
+                *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+                *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+                *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
+                *bit *= RK3188_PULL_BITS_PER_PIN;
+        }
+}
+
+static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+                                        int pin_num, struct regmap **regmap,
+                                        int *reg, u8 *bit)
+{
+        struct rockchip_pinctrl *info = bank->drvdata;
+        int drv_num = (pin_num / 8);
+
+        /*  The bank0:16 and bank1:32 pins are located in PMU */
+        if ((bank->bank_num == 0) || (bank->bank_num == 1))
+                *regmap = info->regmap_pmu;
+        else
+                *regmap = info->regmap_base;
+
+        *reg = bank->drv[drv_num].offset;
+        if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
+            (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
+                *bit = (pin_num % 8) * 3;
+        else
+                *bit = (pin_num % 8) * 2;
+}
+
+static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
+        { 2, 4, 8, 12, -1, -1, -1, -1 },
+        { 3, 6, 9, 12, -1, -1, -1, -1 },
+        { 5, 10, 15, 20, -1, -1, -1, -1 },
+        { 4, 6, 8, 10, 12, 14, 16, 18 },
+        { 4, 7, 10, 13, 16, 19, 22, 26 }
+};
 
 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
                                      int pin_num)
@@ -714,19 +847,74 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
         struct rockchip_pin_ctrl *ctrl = info->ctrl;
         struct regmap *regmap;
         int reg, ret;
-        u32 data;
+        u32 data, temp, rmask_bits;
         u8 bit;
+        int drv_type = bank->drv[pin_num / 8].drv_type;
 
         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 
+        switch (drv_type) {
+        case DRV_TYPE_IO_1V8_3V0_AUTO:
+        case DRV_TYPE_IO_3V3_ONLY:
+                rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+                switch (bit) {
+                case 0 ... 12:
+                        /* regular case, nothing to do */
+                        break;
+                case 15:
+                        /*
+                         * drive-strength offset is special, as it is
+                         * spread over 2 registers
+                         */
+                        ret = regmap_read(regmap, reg, &data);
+                        if (ret)
+                                return ret;
+
+                        ret = regmap_read(regmap, reg + 0x4, &temp);
+                        if (ret)
+                                return ret;
+
+                        /*
+                         * the bit data[15] contains bit 0 of the value
+                         * while temp[1:0] contains bits 2 and 1
+                         */
+                        data >>= 15;
+                        temp &= 0x3;
+                        temp <<= 1;
+                        data |= temp;
+
+                        return rockchip_perpin_drv_list[drv_type][data];
+                case 18 ... 21:
+                        /* setting fully enclosed in the second register */
+                        reg += 4;
+                        bit -= 16;
+                        break;
+                default:
+                        dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
+                                bit, drv_type);
+                        return -EINVAL;
+                }
+
+                break;
+        case DRV_TYPE_IO_DEFAULT:
+        case DRV_TYPE_IO_1V8_OR_3V0:
+        case DRV_TYPE_IO_1V8_ONLY:
+                rmask_bits = RK3288_DRV_BITS_PER_PIN;
+                break;
+        default:
+                dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
+                        drv_type);
+                return -EINVAL;
+        }
+
         ret = regmap_read(regmap, reg, &data);
         if (ret)
                 return ret;
 
         data >>= bit;
-        data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
+        data &= (1 << rmask_bits) - 1;
 
-        return rockchip_perpin_drv_list[data];
+        return rockchip_perpin_drv_list[drv_type][data];
 }
 
 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
@@ -737,16 +925,23 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
         struct regmap *regmap;
         unsigned long flags;
         int reg, ret, i;
-        u32 data, rmask;
+        u32 data, rmask, rmask_bits, temp;
         u8 bit;
+        int drv_type = bank->drv[pin_num / 8].drv_type;
+
+        dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
+                bank->bank_num, pin_num, strength);
 
         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 
         ret = -EINVAL;
-        for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) {
-                if (rockchip_perpin_drv_list[i] == strength) {
+        for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
+                if (rockchip_perpin_drv_list[drv_type][i] == strength) {
                         ret = i;
                         break;
+                } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
+                        ret = rockchip_perpin_drv_list[drv_type][i];
+                        break;
                 }
         }
 
@@ -758,8 +953,64 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 
         spin_lock_irqsave(&bank->slock, flags);
 
+        switch (drv_type) {
+        case DRV_TYPE_IO_1V8_3V0_AUTO:
+        case DRV_TYPE_IO_3V3_ONLY:
+                rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+                switch (bit) {
+                case 0 ... 12:
+                        /* regular case, nothing to do */
+                        break;
+                case 15:
+                        /*
+                         * drive-strength offset is special, as it is spread
+                         * over 2 registers, the bit data[15] contains bit 0
+                         * of the value while temp[1:0] contains bits 2 and 1
+                         */
+                        data = (ret & 0x1) << 15;
+                        temp = (ret >> 0x1) & 0x3;
+
+                        rmask = BIT(15) | BIT(31);
+                        data |= BIT(31);
+                        ret = regmap_update_bits(regmap, reg, rmask, data);
+                        if (ret) {
+                                spin_unlock_irqrestore(&bank->slock, flags);
+                                return ret;
+                        }
+
+                        rmask = 0x3 | (0x3 << 16);
+                        temp |= (0x3 << 16);
+                        reg += 0x4;
+                        ret = regmap_update_bits(regmap, reg, rmask, temp);
+
+                        spin_unlock_irqrestore(&bank->slock, flags);
+                        return ret;
+                case 18 ... 21:
+                        /* setting fully enclosed in the second register */
+                        reg += 4;
+                        bit -= 16;
+                        break;
+                default:
+                        spin_unlock_irqrestore(&bank->slock, flags);
+                        dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
+                                bit, drv_type);
+                        return -EINVAL;
+                }
+                break;
+        case DRV_TYPE_IO_DEFAULT:
+        case DRV_TYPE_IO_1V8_OR_3V0:
+        case DRV_TYPE_IO_1V8_ONLY:
+                rmask_bits = RK3288_DRV_BITS_PER_PIN;
+                break;
+        default:
+                spin_unlock_irqrestore(&bank->slock, flags);
+                dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
+                        drv_type);
+                return -EINVAL;
+        }
+
         /* enable the write to the equivalent lower bits */
-        data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+        data = ((1 << rmask_bits) - 1) << (bit + 16);
         rmask = data | (data >> 16);
         data |= (ret << bit);
 
@@ -796,6 +1047,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
         case RK3188:
         case RK3288:
         case RK3368:
+        case RK3399:
                 data >>= bit;
                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 
@@ -852,6 +1104,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
         case RK3188:
         case RK3288:
         case RK3368:
+        case RK3399:
                 spin_lock_irqsave(&bank->slock, flags);
 
                 /* enable the write to the equivalent lower bits */
@@ -1032,6 +1285,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
         case RK3188:
         case RK3288:
         case RK3368:
+        case RK3399:
                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
         }
 
@@ -1892,7 +2146,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
         struct device_node *np;
         struct rockchip_pin_ctrl *ctrl;
         struct rockchip_pin_bank *bank;
-        int grf_offs, pmu_offs, i, j;
+        int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
 
         match = of_match_node(rockchip_pinctrl_dt_match, node);
         ctrl = (struct rockchip_pin_ctrl *)match->data;
@@ -1916,6 +2170,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
 
         grf_offs = ctrl->grf_mux_offset;
         pmu_offs = ctrl->pmu_mux_offset;
+        drv_pmu_offs = ctrl->pmu_drv_offset;
+        drv_grf_offs = ctrl->grf_drv_offset;
         bank = ctrl->pin_banks;
         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
                 int bank_pins = 0;
@@ -1925,27 +2181,39 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
                 bank->pin_base = ctrl->nr_pins;
                 ctrl->nr_pins += bank->nr_pins;
 
-                /* calculate iomux offsets */
+                /* calculate iomux and drv offsets */
                 for (j = 0; j < 4; j++) {
                         struct rockchip_iomux *iom = &bank->iomux[j];
+                        struct rockchip_drv *drv = &bank->drv[j];
                         int inc;
 
                         if (bank_pins >= bank->nr_pins)
                                 break;
 
-                        /* preset offset value, set new start value */
+                        /* preset iomux offset value, set new start value */
                         if (iom->offset >= 0) {
                                 if (iom->type & IOMUX_SOURCE_PMU)
                                         pmu_offs = iom->offset;
                                 else
                                         grf_offs = iom->offset;
-                        } else { /* set current offset */
+                        } else { /* set current iomux offset */
                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
                                                         pmu_offs : grf_offs;
                         }
 
-                        dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
-                                 i, j, iom->offset);
+                        /* preset drv offset value, set new start value */
+                        if (drv->offset >= 0) {
+                                if (iom->type & IOMUX_SOURCE_PMU)
+                                        drv_pmu_offs = drv->offset;
+                                else
+                                        drv_grf_offs = drv->offset;
+                        } else { /* set current drv offset */
+                                drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+                                                drv_pmu_offs : drv_grf_offs;
+                        }
+
+                        dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
+                                i, j, iom->offset, drv->offset);
 
                         /*
                          * Increase offset according to iomux width.
@@ -1957,6 +2225,21 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
                         else
                                 grf_offs += inc;
 
+                        /*
+                         * Increase offset according to drv width.
+                         * 3bit drive-strenth'es are spread over two registers.
+                         */
+                        if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
+                            (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
+                                inc = 8;
+                        else
+                                inc = 4;
+
+                        if (iom->type & IOMUX_SOURCE_PMU)
+                                drv_pmu_offs += inc;
+                        else
+                                drv_grf_offs += inc;
+
                         bank_pins += 8;
                 }
         }
@@ -2257,6 +2540,62 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
 };
 
+static struct rockchip_pin_bank rk3399_pin_banks[] = {
+        PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_SOURCE_PMU,
+                                        IOMUX_SOURCE_PMU,
+                                        IOMUX_SOURCE_PMU,
+                                        IOMUX_SOURCE_PMU,
+                                        DRV_TYPE_IO_1V8_ONLY,
+                                        DRV_TYPE_IO_1V8_ONLY,
+                                        DRV_TYPE_IO_DEFAULT,
+                                        DRV_TYPE_IO_DEFAULT,
+                                        0x0,
+                                        0x8,
+                                        -1,
+                                        -1
+                                        ),
+        PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
+                                        IOMUX_SOURCE_PMU,
+                                        IOMUX_SOURCE_PMU,
+                                        IOMUX_SOURCE_PMU,
+                                        DRV_TYPE_IO_1V8_OR_3V0,
+                                        DRV_TYPE_IO_1V8_OR_3V0,
+                                        DRV_TYPE_IO_1V8_OR_3V0,
+                                        DRV_TYPE_IO_1V8_OR_3V0,
+                                        0x20,
+                                        0x28,
+                                        0x30,
+                                        0x38
+                                        ),
+        PIN_BANK_DRV_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
+                           DRV_TYPE_IO_1V8_OR_3V0,
+                           DRV_TYPE_IO_1V8_ONLY,
+                           DRV_TYPE_IO_1V8_ONLY
+                           ),
+        PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
+                           DRV_TYPE_IO_3V3_ONLY,
+                           DRV_TYPE_IO_3V3_ONLY,
+                           DRV_TYPE_IO_1V8_OR_3V0
+                           ),
+        PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
+                           DRV_TYPE_IO_1V8_3V0_AUTO,
+                           DRV_TYPE_IO_1V8_OR_3V0,
+                           DRV_TYPE_IO_1V8_OR_3V0
+                           ),
+};
+
+static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
+                .pin_banks              = rk3399_pin_banks,
+                .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
+                .label                  = "RK3399-GPIO",
+                .type                   = RK3399,
+                .grf_mux_offset         = 0xe000,
+                .pmu_mux_offset         = 0x0,
+                .grf_drv_offset         = 0xe100,
+                .pmu_drv_offset         = 0x80,
+                .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
+                .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
+};
 
 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
         { .compatible = "rockchip,rk2928-pinctrl",
@@ -2275,6 +2614,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
                 .data = (void *)&rk3288_pin_ctrl },
         { .compatible = "rockchip,rk3368-pinctrl",
                 .data = (void *)&rk3368_pin_ctrl },
+        { .compatible = "rockchip,rk3399-pinctrl",
+                .data = (void *)&rk3399_pin_ctrl },
         {},
 };
 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index d24e5f1d1525..fb126d56ad40 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -255,6 +255,13 @@ static enum pin_config_param pcs_bias[] = {
 };
 
 /*
+ * This lock class tells lockdep that irqchip core that this single
+ * pinctrl can be in a different category than its parents, so it won't
+ * report false recursion.
+ */
+static struct lock_class_key pcs_lock_class;
+
+/*
  * REVISIT: Reads and writes could eventually use regmap or something
  * generic. But at least on omaps, some mux registers are performance
  * critical as they may need to be remuxed every time before and after
@@ -1713,6 +1720,7 @@ static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
         irq_set_chip_data(irq, pcs_soc);
         irq_set_chip_and_handler(irq, &pcs->chip,
                                  handle_level_irq);
+        irq_set_lockdep_class(irq, &pcs_lock_class);
         irq_set_noprobe(irq);
 
         return 0;
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index fac844a85cb4..cab66c64149f 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -985,6 +985,7 @@ static struct pinmux_ops st_pmxops = {
         .get_function_groups    = st_pmx_get_groups,
         .set_mux                = st_pmx_set_mux,
         .gpio_set_direction     = st_pmx_set_gpio_direction,
+        .strict                 = true,
 };
 
 /* Pinconf  */
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index d57b5eca7b98..76f1abd71e31 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -590,7 +590,7 @@ static const char * const usb1_groups[] = {"usb1_0_grp"};
 static const char * const mdio0_groups[] = {"mdio0_0_grp"};
 static const char * const mdio1_groups[] = {"mdio1_0_grp"};
 static const char * const qspi0_groups[] = {"qspi0_0_grp"};
-static const char * const qspi1_groups[] = {"qspi0_1_grp"};
+static const char * const qspi1_groups[] = {"qspi1_0_grp"};
 static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
 static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
 static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c
index 216f227c6009..f553313bc2ef 100644
--- a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c
+++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c
@@ -426,7 +426,7 @@ int pxa2xx_pinctrl_init(struct platform_device *pdev,
 
         return 0;
 }
-EXPORT_SYMBOL(pxa2xx_pinctrl_init);
+EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_init);
 
 int pxa2xx_pinctrl_exit(struct platform_device *pdev)
 {
@@ -435,3 +435,4 @@ int pxa2xx_pinctrl_exit(struct platform_device *pdev)
         pinctrl_unregister(pctl->pctl_dev);
         return 0;
 }
+EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_exit);
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index eeac8cba8a21..67bc70dcda64 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -23,6 +23,14 @@ config PINCTRL_APQ8084
           This is the pinctrl, pinmux, pinconf and gpiolib driver for the
           Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
 
+config PINCTRL_IPQ4019
+        tristate "Qualcomm IPQ4019 pin controller driver"
+        depends on GPIOLIB && OF
+        select PINCTRL_MSM
+        help
+          This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+          Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
+
 config PINCTRL_IPQ8064
         tristate "Qualcomm IPQ8064 pin controller driver"
         depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index dfb50a9fe04a..c964a2c4b90a 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -2,6 +2,7 @@
 obj-$(CONFIG_PINCTRL_MSM)       += pinctrl-msm.o
 obj-$(CONFIG_PINCTRL_APQ8064)   += pinctrl-apq8064.o
 obj-$(CONFIG_PINCTRL_APQ8084)   += pinctrl-apq8084.o
+obj-$(CONFIG_PINCTRL_IPQ4019)   += pinctrl-ipq4019.o
 obj-$(CONFIG_PINCTRL_IPQ8064)   += pinctrl-ipq8064.o
 obj-$(CONFIG_PINCTRL_MSM8660)   += pinctrl-msm8660.o
 obj-$(CONFIG_PINCTRL_MSM8960)   += pinctrl-msm8960.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
new file mode 100644
index 000000000000..b5d81ced6ce6
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+static const struct pinctrl_pin_desc ipq4019_pins[] = {
+        PINCTRL_PIN(0, "GPIO_0"),
+        PINCTRL_PIN(1, "GPIO_1"),
+        PINCTRL_PIN(2, "GPIO_2"),
+        PINCTRL_PIN(3, "GPIO_3"),
+        PINCTRL_PIN(4, "GPIO_4"),
+        PINCTRL_PIN(5, "GPIO_5"),
+        PINCTRL_PIN(6, "GPIO_6"),
+        PINCTRL_PIN(7, "GPIO_7"),
+        PINCTRL_PIN(8, "GPIO_8"),
+        PINCTRL_PIN(9, "GPIO_9"),
+        PINCTRL_PIN(10, "GPIO_10"),
+        PINCTRL_PIN(11, "GPIO_11"),
+        PINCTRL_PIN(12, "GPIO_12"),
+        PINCTRL_PIN(13, "GPIO_13"),
+        PINCTRL_PIN(14, "GPIO_14"),
+        PINCTRL_PIN(15, "GPIO_15"),
+        PINCTRL_PIN(16, "GPIO_16"),
+        PINCTRL_PIN(17, "GPIO_17"),
+        PINCTRL_PIN(18, "GPIO_18"),
+        PINCTRL_PIN(19, "GPIO_19"),
+        PINCTRL_PIN(20, "GPIO_20"),
+        PINCTRL_PIN(21, "GPIO_21"),
+        PINCTRL_PIN(22, "GPIO_22"),
+        PINCTRL_PIN(23, "GPIO_23"),
+        PINCTRL_PIN(24, "GPIO_24"),
+        PINCTRL_PIN(25, "GPIO_25"),
+        PINCTRL_PIN(26, "GPIO_26"),
+        PINCTRL_PIN(27, "GPIO_27"),
+        PINCTRL_PIN(28, "GPIO_28"),
+        PINCTRL_PIN(29, "GPIO_29"),
+        PINCTRL_PIN(30, "GPIO_30"),
+        PINCTRL_PIN(31, "GPIO_31"),
+        PINCTRL_PIN(32, "GPIO_32"),
+        PINCTRL_PIN(33, "GPIO_33"),
+        PINCTRL_PIN(34, "GPIO_34"),
+        PINCTRL_PIN(35, "GPIO_35"),
+        PINCTRL_PIN(36, "GPIO_36"),
+        PINCTRL_PIN(37, "GPIO_37"),
+        PINCTRL_PIN(38, "GPIO_38"),
+        PINCTRL_PIN(39, "GPIO_39"),
+        PINCTRL_PIN(40, "GPIO_40"),
+        PINCTRL_PIN(41, "GPIO_41"),
+        PINCTRL_PIN(42, "GPIO_42"),
+        PINCTRL_PIN(43, "GPIO_43"),
+        PINCTRL_PIN(44, "GPIO_44"),
+        PINCTRL_PIN(45, "GPIO_45"),
+        PINCTRL_PIN(46, "GPIO_46"),
+        PINCTRL_PIN(47, "GPIO_47"),
+        PINCTRL_PIN(48, "GPIO_48"),
+        PINCTRL_PIN(49, "GPIO_49"),
+        PINCTRL_PIN(50, "GPIO_50"),
+        PINCTRL_PIN(51, "GPIO_51"),
+        PINCTRL_PIN(52, "GPIO_52"),
+        PINCTRL_PIN(53, "GPIO_53"),
+        PINCTRL_PIN(54, "GPIO_54"),
+        PINCTRL_PIN(55, "GPIO_55"),
+        PINCTRL_PIN(56, "GPIO_56"),
+        PINCTRL_PIN(57, "GPIO_57"),
+        PINCTRL_PIN(58, "GPIO_58"),
+        PINCTRL_PIN(59, "GPIO_59"),
+        PINCTRL_PIN(60, "GPIO_60"),
+        PINCTRL_PIN(61, "GPIO_61"),
+        PINCTRL_PIN(62, "GPIO_62"),
+        PINCTRL_PIN(63, "GPIO_63"),
+        PINCTRL_PIN(64, "GPIO_64"),
+        PINCTRL_PIN(65, "GPIO_65"),
+        PINCTRL_PIN(66, "GPIO_66"),
+        PINCTRL_PIN(67, "GPIO_67"),
+        PINCTRL_PIN(68, "GPIO_68"),
+        PINCTRL_PIN(69, "GPIO_69"),
+        PINCTRL_PIN(70, "GPIO_70"),
+        PINCTRL_PIN(71, "GPIO_71"),
+        PINCTRL_PIN(72, "GPIO_72"),
+        PINCTRL_PIN(73, "GPIO_73"),
+        PINCTRL_PIN(74, "GPIO_74"),
+        PINCTRL_PIN(75, "GPIO_75"),
+        PINCTRL_PIN(76, "GPIO_76"),
+        PINCTRL_PIN(77, "GPIO_77"),
+        PINCTRL_PIN(78, "GPIO_78"),
+        PINCTRL_PIN(79, "GPIO_79"),
+        PINCTRL_PIN(80, "GPIO_80"),
+        PINCTRL_PIN(81, "GPIO_81"),
+        PINCTRL_PIN(82, "GPIO_82"),
+        PINCTRL_PIN(83, "GPIO_83"),
+        PINCTRL_PIN(84, "GPIO_84"),
+        PINCTRL_PIN(85, "GPIO_85"),
+        PINCTRL_PIN(86, "GPIO_86"),
+        PINCTRL_PIN(87, "GPIO_87"),
+        PINCTRL_PIN(88, "GPIO_88"),
+        PINCTRL_PIN(89, "GPIO_89"),
+        PINCTRL_PIN(90, "GPIO_90"),
+        PINCTRL_PIN(91, "GPIO_91"),
+        PINCTRL_PIN(92, "GPIO_92"),
+        PINCTRL_PIN(93, "GPIO_93"),
+        PINCTRL_PIN(94, "GPIO_94"),
+        PINCTRL_PIN(95, "GPIO_95"),
+        PINCTRL_PIN(96, "GPIO_96"),
+        PINCTRL_PIN(97, "GPIO_97"),
+        PINCTRL_PIN(98, "GPIO_98"),
+        PINCTRL_PIN(99, "GPIO_99"),
+};
+
+#define DECLARE_QCA_GPIO_PINS(pin) \
+        static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_QCA_GPIO_PINS(0);
+DECLARE_QCA_GPIO_PINS(1);
+DECLARE_QCA_GPIO_PINS(2);
+DECLARE_QCA_GPIO_PINS(3);
+DECLARE_QCA_GPIO_PINS(4);
+DECLARE_QCA_GPIO_PINS(5);
+DECLARE_QCA_GPIO_PINS(6);
+DECLARE_QCA_GPIO_PINS(7);
+DECLARE_QCA_GPIO_PINS(8);
+DECLARE_QCA_GPIO_PINS(9);
+DECLARE_QCA_GPIO_PINS(10);
+DECLARE_QCA_GPIO_PINS(11);
+DECLARE_QCA_GPIO_PINS(12);
+DECLARE_QCA_GPIO_PINS(13);
+DECLARE_QCA_GPIO_PINS(14);
+DECLARE_QCA_GPIO_PINS(15);
+DECLARE_QCA_GPIO_PINS(16);
+DECLARE_QCA_GPIO_PINS(17);
+DECLARE_QCA_GPIO_PINS(18);
+DECLARE_QCA_GPIO_PINS(19);
+DECLARE_QCA_GPIO_PINS(20);
+DECLARE_QCA_GPIO_PINS(21);
+DECLARE_QCA_GPIO_PINS(22);
+DECLARE_QCA_GPIO_PINS(23);
+DECLARE_QCA_GPIO_PINS(24);
+DECLARE_QCA_GPIO_PINS(25);
+DECLARE_QCA_GPIO_PINS(26);
+DECLARE_QCA_GPIO_PINS(27);
+DECLARE_QCA_GPIO_PINS(28);
+DECLARE_QCA_GPIO_PINS(29);
+DECLARE_QCA_GPIO_PINS(30);
+DECLARE_QCA_GPIO_PINS(31);
+DECLARE_QCA_GPIO_PINS(32);
+DECLARE_QCA_GPIO_PINS(33);
+DECLARE_QCA_GPIO_PINS(34);
+DECLARE_QCA_GPIO_PINS(35);
+DECLARE_QCA_GPIO_PINS(36);
+DECLARE_QCA_GPIO_PINS(37);
+DECLARE_QCA_GPIO_PINS(38);
+DECLARE_QCA_GPIO_PINS(39);
+DECLARE_QCA_GPIO_PINS(40);
+DECLARE_QCA_GPIO_PINS(41);
+DECLARE_QCA_GPIO_PINS(42);
+DECLARE_QCA_GPIO_PINS(43);
+DECLARE_QCA_GPIO_PINS(44);
+DECLARE_QCA_GPIO_PINS(45);
+DECLARE_QCA_GPIO_PINS(46);
+DECLARE_QCA_GPIO_PINS(47);
+DECLARE_QCA_GPIO_PINS(48);
+DECLARE_QCA_GPIO_PINS(49);
+DECLARE_QCA_GPIO_PINS(50);
+DECLARE_QCA_GPIO_PINS(51);
+DECLARE_QCA_GPIO_PINS(52);
+DECLARE_QCA_GPIO_PINS(53);
+DECLARE_QCA_GPIO_PINS(54);
+DECLARE_QCA_GPIO_PINS(55);
+DECLARE_QCA_GPIO_PINS(56);
+DECLARE_QCA_GPIO_PINS(57);
+DECLARE_QCA_GPIO_PINS(58);
+DECLARE_QCA_GPIO_PINS(59);
+DECLARE_QCA_GPIO_PINS(60);
+DECLARE_QCA_GPIO_PINS(61);
+DECLARE_QCA_GPIO_PINS(62);
+DECLARE_QCA_GPIO_PINS(63);
+DECLARE_QCA_GPIO_PINS(64);
+DECLARE_QCA_GPIO_PINS(65);
+DECLARE_QCA_GPIO_PINS(66);
+DECLARE_QCA_GPIO_PINS(67);
+DECLARE_QCA_GPIO_PINS(68);
+DECLARE_QCA_GPIO_PINS(69);
+DECLARE_QCA_GPIO_PINS(70);
+DECLARE_QCA_GPIO_PINS(71);
+DECLARE_QCA_GPIO_PINS(72);
+DECLARE_QCA_GPIO_PINS(73);
+DECLARE_QCA_GPIO_PINS(74);
+DECLARE_QCA_GPIO_PINS(75);
+DECLARE_QCA_GPIO_PINS(76);
+DECLARE_QCA_GPIO_PINS(77);
+DECLARE_QCA_GPIO_PINS(78);
+DECLARE_QCA_GPIO_PINS(79);
+DECLARE_QCA_GPIO_PINS(80);
+DECLARE_QCA_GPIO_PINS(81);
+DECLARE_QCA_GPIO_PINS(82);
+DECLARE_QCA_GPIO_PINS(83);
+DECLARE_QCA_GPIO_PINS(84);
+DECLARE_QCA_GPIO_PINS(85);
+DECLARE_QCA_GPIO_PINS(86);
+DECLARE_QCA_GPIO_PINS(87);
+DECLARE_QCA_GPIO_PINS(88);
+DECLARE_QCA_GPIO_PINS(89);
+DECLARE_QCA_GPIO_PINS(90);
+DECLARE_QCA_GPIO_PINS(91);
+DECLARE_QCA_GPIO_PINS(92);
+DECLARE_QCA_GPIO_PINS(93);
+DECLARE_QCA_GPIO_PINS(94);
+DECLARE_QCA_GPIO_PINS(95);
+DECLARE_QCA_GPIO_PINS(96);
+DECLARE_QCA_GPIO_PINS(97);
+DECLARE_QCA_GPIO_PINS(98);
+DECLARE_QCA_GPIO_PINS(99);
+
+#define FUNCTION(fname)                                 \
+        [qca_mux_##fname] = {                           \
+                .name = #fname,                         \
+                .groups = fname##_groups,               \
+                .ngroups = ARRAY_SIZE(fname##_groups),  \
+        }
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \
+        {                                               \
+                .name = "gpio" #id,                     \
+                .pins = gpio##id##_pins,                \
+                .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
+                .funcs = (int[]){                       \
+                        qca_mux_NA, /* gpio mode */     \
+                        qca_mux_##f1,                   \
+                        qca_mux_##f2,                   \
+                        qca_mux_##f3,                   \
+                        qca_mux_##f4,                   \
+                        qca_mux_##f5,                   \
+                        qca_mux_##f6,                   \
+                        qca_mux_##f7,                   \
+                        qca_mux_##f8,                   \
+                        qca_mux_##f9,                   \
+                        qca_mux_##f10,                  \
+                        qca_mux_##f11,                  \
+                        qca_mux_##f12,                  \
+                        qca_mux_##f13,                  \
+                        qca_mux_##f14                   \
+                },                                      \
+                .nfuncs = 15,                           \
+                .ctl_reg = 0x1000 + 0x10 * id,          \
+                .io_reg = 0x1004 + 0x10 * id,           \
+                .intr_cfg_reg = 0x1008 + 0x10 * id,     \
+                .intr_status_reg = 0x100c + 0x10 * id,  \
+                .intr_target_reg = 0x400 + 0x4 * id,    \
+                .mux_bit = 2,                   \
+                .pull_bit = 0,                  \
+                .drv_bit = 6,                   \
+                .oe_bit = 9,                    \
+                .in_bit = 0,                    \
+                .out_bit = 1,                   \
+                .intr_enable_bit = 0,           \
+                .intr_status_bit = 0,           \
+                .intr_target_bit = 5,           \
+                .intr_raw_status_bit = 4,       \
+                .intr_polarity_bit = 1,         \
+                .intr_detection_bit = 2,        \
+                .intr_detection_width = 2,      \
+        }
+
+
+enum ipq4019_functions {
+        qca_mux_gpio,
+        qca_mux_blsp_uart1,
+        qca_mux_blsp_i2c0,
+        qca_mux_blsp_i2c1,
+        qca_mux_blsp_uart0,
+        qca_mux_blsp_spi1,
+        qca_mux_blsp_spi0,
+        qca_mux_NA,
+};
+
+static const char * const gpio_groups[] = {
+        "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+        "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+        "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+        "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+        "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+        "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+        "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+        "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+        "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+        "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+        "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+        "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+        "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+        "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+        "gpio99",
+};
+
+static const char * const blsp_uart1_groups[] = {
+        "gpio8", "gpio9", "gpio10", "gpio11",
+};
+static const char * const blsp_i2c0_groups[] = {
+        "gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59",
+};
+static const char * const blsp_spi0_groups[] = {
+        "gpio12", "gpio13", "gpio14", "gpio15", "gpio45",
+        "gpio54", "gpio55", "gpio56", "gpio57",
+};
+static const char * const blsp_i2c1_groups[] = {
+        "gpio12", "gpio13", "gpio34", "gpio35",
+};
+static const char * const blsp_uart0_groups[] = {
+        "gpio16", "gpio17", "gpio60", "gpio61",
+};
+static const char * const blsp_spi1_groups[] = {
+        "gpio44", "gpio45", "gpio46", "gpio47",
+};
+
+static const struct msm_function ipq4019_functions[] = {
+        FUNCTION(gpio),
+        FUNCTION(blsp_uart1),
+        FUNCTION(blsp_i2c0),
+        FUNCTION(blsp_i2c1),
+        FUNCTION(blsp_uart0),
+        FUNCTION(blsp_spi1),
+        FUNCTION(blsp_spi0),
+};
+
+static const struct msm_pingroup ipq4019_groups[] = {
+        PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+        PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+};
+
+static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
+        .pins = ipq4019_pins,
+        .npins = ARRAY_SIZE(ipq4019_pins),
+        .functions = ipq4019_functions,
+        .nfunctions = ARRAY_SIZE(ipq4019_functions),
+        .groups = ipq4019_groups,
+        .ngroups = ARRAY_SIZE(ipq4019_groups),
+        .ngpios = 70,
+};
+
+static int ipq4019_pinctrl_probe(struct platform_device *pdev)
+{
+        return msm_pinctrl_probe(pdev, &ipq4019_pinctrl);
+}
+
+static const struct of_device_id ipq4019_pinctrl_of_match[] = {
+        { .compatible = "qcom,ipq4019-pinctrl", },
+        { },
+};
+
+static struct platform_driver ipq4019_pinctrl_driver = {
+        .driver = {
+                .name = "ipq4019-pinctrl",
+                .of_match_table = ipq4019_pinctrl_of_match,
+        },
+        .probe = ipq4019_pinctrl_probe,
+        .remove = msm_pinctrl_remove,
+};
+
+static int __init ipq4019_pinctrl_init(void)
+{
+        return platform_driver_register(&ipq4019_pinctrl_driver);
+}
+arch_initcall(ipq4019_pinctrl_init);
+
+static void __exit ipq4019_pinctrl_exit(void)
+{
+        platform_driver_unregister(&ipq4019_pinctrl_driver);
+}
+module_exit(ipq4019_pinctrl_exit);
+
+MODULE_DESCRIPTION("Qualcomm ipq4019 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
index 2f18323571a6..2a3e5490a483 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
@@ -117,6 +117,7 @@
  * @output_enabled: Set to true if MPP output logic is enabled.
  * @input_enabled: Set to true if MPP input buffer logic is enabled.
  * @paired: Pin operates in paired mode
+ * @has_pullup: Pin has support to configure pullup
  * @num_sources: Number of power-sources supported by this MPP.
  * @power_source: Current power-source used.
  * @amux_input: Set the source for analog input.
@@ -134,6 +135,7 @@ struct pmic_mpp_pad {
         bool            output_enabled;
         bool            input_enabled;
         bool            paired;
+        bool            has_pullup;
         unsigned int    num_sources;
         unsigned int    power_source;
         unsigned int    amux_input;
@@ -477,11 +479,14 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
         if (ret < 0)
                 return ret;
 
-        val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
+        if (pad->has_pullup) {
+                val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
 
-        ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, val);
-        if (ret < 0)
-                return ret;
+                ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL,
+                                     val);
+                if (ret < 0)
+                        return ret;
+        }
 
         val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK;
 
@@ -534,7 +539,8 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
                 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
                 seq_printf(s, " vin-%d", pad->power_source);
                 seq_printf(s, " %d", pad->aout_level);
-                seq_printf(s, " %-8s", biases[pad->pullup]);
+                if (pad->has_pullup)
+                        seq_printf(s, " %-8s", biases[pad->pullup]);
                 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
                 if (pad->dtest)
                         seq_printf(s, " dtest%d", pad->dtest);
@@ -748,12 +754,16 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state,
         pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT;
         pad->power_source &= PMIC_MPP_REG_VIN_MASK;
 
-        val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
-        if (val < 0)
-                return val;
+        if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT &&
+            subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) {
+                val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
+                if (val < 0)
+                        return val;
 
-        pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
-        pad->pullup &= PMIC_MPP_REG_PULL_MASK;
+                pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
+                pad->pullup &= PMIC_MPP_REG_PULL_MASK;
+                pad->has_pullup = true;
+        }
 
         val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL);
         if (val < 0)
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 35d6e95fa21f..415dd8023063 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -2,10 +2,9 @@
 # Renesas SH and SH Mobile PINCTRL drivers
 #
 
-if ARCH_SHMOBILE || SUPERH
+if ARCH_RENESAS || SUPERH
 
 config PINCTRL_SH_PFC
-        select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
         select PINMUX
         select PINCONF
         select GENERIC_PINCONF
@@ -13,12 +12,12 @@ config PINCTRL_SH_PFC
         help
           This enables pin control drivers for SH and SH Mobile platforms
 
-config GPIO_SH_PFC
-        bool "SuperH PFC GPIO support"
-        depends on PINCTRL_SH_PFC && GPIOLIB
+config PINCTRL_SH_PFC_GPIO
+        select GPIOLIB
+        select PINCTRL_SH_PFC
+        bool
         help
-          This enables support for GPIOs within the SoC's pin function
-          controller.
+          This enables pin control and GPIO drivers for SH/SH Mobile platforms
 
 config PINCTRL_PFC_EMEV2
         def_bool y
@@ -28,12 +27,12 @@ config PINCTRL_PFC_EMEV2
 config PINCTRL_PFC_R8A73A4
         def_bool y
         depends on ARCH_R8A73A4
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_R8A7740
         def_bool y
         depends on ARCH_R8A7740
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_R8A7778
         def_bool y
@@ -73,79 +72,66 @@ config PINCTRL_PFC_R8A7795
 config PINCTRL_PFC_SH7203
         def_bool y
         depends on CPU_SUBTYPE_SH7203
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SH7264
         def_bool y
         depends on CPU_SUBTYPE_SH7264
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SH7269
         def_bool y
         depends on CPU_SUBTYPE_SH7269
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SH73A0
         def_bool y
         depends on ARCH_SH73A0
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
         select REGULATOR
 
 config PINCTRL_PFC_SH7720
         def_bool y
         depends on CPU_SUBTYPE_SH7720
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SH7722
         def_bool y
         depends on CPU_SUBTYPE_SH7722
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SH7723
         def_bool y
         depends on CPU_SUBTYPE_SH7723
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SH7724
         def_bool y
         depends on CPU_SUBTYPE_SH7724
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SH7734
         def_bool y
         depends on CPU_SUBTYPE_SH7734
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SH7757
         def_bool y
         depends on CPU_SUBTYPE_SH7757
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SH7785
         def_bool y
         depends on CPU_SUBTYPE_SH7785
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SH7786
         def_bool y
         depends on CPU_SUBTYPE_SH7786
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
+        select PINCTRL_SH_PFC_GPIO
 
 config PINCTRL_PFC_SHX3
         def_bool y
         depends on CPU_SUBTYPE_SHX3
-        depends on GPIOLIB
-        select PINCTRL_SH_PFC
-
+        select PINCTRL_SH_PFC_GPIO
 endif
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 173305fa3811..8a2c8710fc93 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -1,8 +1,5 @@
-sh-pfc-objs                     = core.o pinctrl.o
-ifeq ($(CONFIG_GPIO_SH_PFC),y)
-sh-pfc-objs                     += gpio.o
-endif
-obj-$(CONFIG_PINCTRL_SH_PFC)    += sh-pfc.o
+obj-$(CONFIG_PINCTRL_SH_PFC)    += core.o pinctrl.o
+obj-$(CONFIG_PINCTRL_SH_PFC_GPIO)       += gpio.o
 obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
 obj-$(CONFIG_PINCTRL_PFC_R8A73A4)       += pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)       += pfc-r8a7740.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 181ea98a63b7..dc3609f0c60b 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -1,5 +1,7 @@
 /*
- * SuperH Pin Function Controller support.
+ * Pin Control and GPIO driver for SuperH Pin Function Controller.
+ *
+ * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
  *
  * Copyright (C) 2008 Magnus Damm
  * Copyright (C) 2009 - 2012 Paul Mundt
@@ -17,7 +19,7 @@
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/pinctrl/machine.h>
@@ -503,7 +505,6 @@ static const struct of_device_id sh_pfc_of_table[] = {
 #endif
         { },
 };
-MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
 #endif
 
 static int sh_pfc_probe(struct platform_device *pdev)
@@ -518,7 +519,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
 
 #ifdef CONFIG_OF
         if (np)
-                info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
+                info = of_device_get_match_data(&pdev->dev);
         else
 #endif
                 info = platid ? (const void *)platid->driver_data : NULL;
@@ -558,7 +559,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
         if (unlikely(ret != 0))
                 return ret;
 
-#ifdef CONFIG_GPIO_SH_PFC
+#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
         /*
          * Then the GPIO chip
          */
@@ -584,7 +585,7 @@ static int sh_pfc_remove(struct platform_device *pdev)
 {
         struct sh_pfc *pfc = platform_get_drvdata(pdev);
 
-#ifdef CONFIG_GPIO_SH_PFC
+#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
         sh_pfc_unregister_gpiochip(pfc);
 #endif
         sh_pfc_unregister_pinctrl(pfc);
@@ -632,7 +633,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
         { "sh-pfc", 0 },
         { },
 };
-MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
 
 static struct platform_driver sh_pfc_driver = {
         .probe          = sh_pfc_probe,
@@ -649,13 +649,3 @@ static int __init sh_pfc_init(void)
         return platform_driver_register(&sh_pfc_driver);
 }
 postcore_initcall(sh_pfc_init);
-
-static void __exit sh_pfc_exit(void)
-{
-        platform_driver_unregister(&sh_pfc_driver);
-}
-module_exit(sh_pfc_exit);
-
-MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
-MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index ad09a670c2ff..411d0887ba19 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -561,82 +561,82 @@ static const u16 pinmux_data[] = {
         PINMUX_SINGLE(AVS2),
 
         /* IPSR0 */
-        PINMUX_IPSR_DATA(IP0_1_0,       PRESETOUT),
-        PINMUX_IPSR_DATA(IP0_1_0,       PWM1),
+        PINMUX_IPSR_GPSR(IP0_1_0,       PRESETOUT),
+        PINMUX_IPSR_GPSR(IP0_1_0,       PWM1),
 
-        PINMUX_IPSR_DATA(IP0_4_2,       AUDATA0),
-        PINMUX_IPSR_DATA(IP0_4_2,       ARM_TRACEDATA_0),
+        PINMUX_IPSR_GPSR(IP0_4_2,       AUDATA0),
+        PINMUX_IPSR_GPSR(IP0_4_2,       ARM_TRACEDATA_0),
         PINMUX_IPSR_MSEL(IP0_4_2,       GPSCLK_C,       SEL_GPS_C),
-        PINMUX_IPSR_DATA(IP0_4_2,       USB_OVC0),
-        PINMUX_IPSR_DATA(IP0_4_2,       TX2_E),
+        PINMUX_IPSR_GPSR(IP0_4_2,       USB_OVC0),
+        PINMUX_IPSR_GPSR(IP0_4_2,       TX2_E),
         PINMUX_IPSR_MSEL(IP0_4_2,       SDA2_B,         SEL_I2C2_B),
 
-        PINMUX_IPSR_DATA(IP0_7_5,       AUDATA1),
-        PINMUX_IPSR_DATA(IP0_7_5,       ARM_TRACEDATA_1),
+        PINMUX_IPSR_GPSR(IP0_7_5,       AUDATA1),
+        PINMUX_IPSR_GPSR(IP0_7_5,       ARM_TRACEDATA_1),
         PINMUX_IPSR_MSEL(IP0_7_5,       GPSIN_C,        SEL_GPS_C),
-        PINMUX_IPSR_DATA(IP0_7_5,       USB_OVC1),
+        PINMUX_IPSR_GPSR(IP0_7_5,       USB_OVC1),
         PINMUX_IPSR_MSEL(IP0_7_5,       RX2_E,          SEL_SCIF2_E),
         PINMUX_IPSR_MSEL(IP0_7_5,       SCL2_B,         SEL_I2C2_B),
 
         PINMUX_IPSR_MSEL(IP0_11_8,      SD1_DAT2_A,     SEL_SD1_A),
-        PINMUX_IPSR_DATA(IP0_11_8,      MMC_D2),
-        PINMUX_IPSR_DATA(IP0_11_8,      BS),
-        PINMUX_IPSR_DATA(IP0_11_8,      ATADIR0_A),
-        PINMUX_IPSR_DATA(IP0_11_8,      SDSELF_A),
-        PINMUX_IPSR_DATA(IP0_11_8,      PWM4_B),
+        PINMUX_IPSR_GPSR(IP0_11_8,      MMC_D2),
+        PINMUX_IPSR_GPSR(IP0_11_8,      BS),
+        PINMUX_IPSR_GPSR(IP0_11_8,      ATADIR0_A),
+        PINMUX_IPSR_GPSR(IP0_11_8,      SDSELF_A),
+        PINMUX_IPSR_GPSR(IP0_11_8,      PWM4_B),
 
         PINMUX_IPSR_MSEL(IP0_14_12,     SD1_DAT3_A,     SEL_SD1_A),
-        PINMUX_IPSR_DATA(IP0_14_12,     MMC_D3),
-        PINMUX_IPSR_DATA(IP0_14_12,     A0),
-        PINMUX_IPSR_DATA(IP0_14_12,     ATAG0_A),
+        PINMUX_IPSR_GPSR(IP0_14_12,     MMC_D3),
+        PINMUX_IPSR_GPSR(IP0_14_12,     A0),
+        PINMUX_IPSR_GPSR(IP0_14_12,     ATAG0_A),
         PINMUX_IPSR_MSEL(IP0_14_12,     REMOCON_B,      SEL_REMOCON_B),
 
-        PINMUX_IPSR_DATA(IP0_15,        A4),
-        PINMUX_IPSR_DATA(IP0_16,        A5),
-        PINMUX_IPSR_DATA(IP0_17,        A6),
-        PINMUX_IPSR_DATA(IP0_18,        A7),
-        PINMUX_IPSR_DATA(IP0_19,        A8),
-        PINMUX_IPSR_DATA(IP0_20,        A9),
-        PINMUX_IPSR_DATA(IP0_21,        A10),
-        PINMUX_IPSR_DATA(IP0_22,        A11),
-        PINMUX_IPSR_DATA(IP0_23,        A12),
-        PINMUX_IPSR_DATA(IP0_24,        A13),
-        PINMUX_IPSR_DATA(IP0_25,        A14),
-        PINMUX_IPSR_DATA(IP0_26,        A15),
-        PINMUX_IPSR_DATA(IP0_27,        A16),
-        PINMUX_IPSR_DATA(IP0_28,        A17),
-        PINMUX_IPSR_DATA(IP0_29,        A18),
-        PINMUX_IPSR_DATA(IP0_30,        A19),
+        PINMUX_IPSR_GPSR(IP0_15,        A4),
+        PINMUX_IPSR_GPSR(IP0_16,        A5),
+        PINMUX_IPSR_GPSR(IP0_17,        A6),
+        PINMUX_IPSR_GPSR(IP0_18,        A7),
+        PINMUX_IPSR_GPSR(IP0_19,        A8),
+        PINMUX_IPSR_GPSR(IP0_20,        A9),
+        PINMUX_IPSR_GPSR(IP0_21,        A10),
+        PINMUX_IPSR_GPSR(IP0_22,        A11),
+        PINMUX_IPSR_GPSR(IP0_23,        A12),
+        PINMUX_IPSR_GPSR(IP0_24,        A13),
+        PINMUX_IPSR_GPSR(IP0_25,        A14),
+        PINMUX_IPSR_GPSR(IP0_26,        A15),
+        PINMUX_IPSR_GPSR(IP0_27,        A16),
+        PINMUX_IPSR_GPSR(IP0_28,        A17),
+        PINMUX_IPSR_GPSR(IP0_29,        A18),
+        PINMUX_IPSR_GPSR(IP0_30,        A19),
 
         /* IPSR1 */
-        PINMUX_IPSR_DATA(IP1_0,         A20),
+        PINMUX_IPSR_GPSR(IP1_0,         A20),
         PINMUX_IPSR_MSEL(IP1_0,         HSPI_CS1_B,     SEL_HSPI1_B),
 
-        PINMUX_IPSR_DATA(IP1_1,         A21),
+        PINMUX_IPSR_GPSR(IP1_1,         A21),
         PINMUX_IPSR_MSEL(IP1_1,         HSPI_CLK1_B,    SEL_HSPI1_B),
 
-        PINMUX_IPSR_DATA(IP1_4_2,       A22),
+        PINMUX_IPSR_GPSR(IP1_4_2,       A22),
         PINMUX_IPSR_MSEL(IP1_4_2,       HRTS0_B,        SEL_HSCIF0_B),
         PINMUX_IPSR_MSEL(IP1_4_2,       RX2_B,          SEL_SCIF2_B),
         PINMUX_IPSR_MSEL(IP1_4_2,       DREQ2_A,        SEL_DREQ2_A),
 
-        PINMUX_IPSR_DATA(IP1_7_5,       A23),
-        PINMUX_IPSR_DATA(IP1_7_5,       HTX0_B),
-        PINMUX_IPSR_DATA(IP1_7_5,       TX2_B),
-        PINMUX_IPSR_DATA(IP1_7_5,       DACK2_A),
+        PINMUX_IPSR_GPSR(IP1_7_5,       A23),
+        PINMUX_IPSR_GPSR(IP1_7_5,       HTX0_B),
+        PINMUX_IPSR_GPSR(IP1_7_5,       TX2_B),
+        PINMUX_IPSR_GPSR(IP1_7_5,       DACK2_A),
         PINMUX_IPSR_MSEL(IP1_7_5,       TS_SDEN0_A,     SEL_TSIF0_A),
 
         PINMUX_IPSR_MSEL(IP1_10_8,      SD1_CD_A,       SEL_SD1_A),
-        PINMUX_IPSR_DATA(IP1_10_8,      MMC_D6),
-        PINMUX_IPSR_DATA(IP1_10_8,      A24),
+        PINMUX_IPSR_GPSR(IP1_10_8,      MMC_D6),
+        PINMUX_IPSR_GPSR(IP1_10_8,      A24),
         PINMUX_IPSR_MSEL(IP1_10_8,      DREQ1_A,        SEL_DREQ1_A),
         PINMUX_IPSR_MSEL(IP1_10_8,      HRX0_B,         SEL_HSCIF0_B),
         PINMUX_IPSR_MSEL(IP1_10_8,      TS_SPSYNC0_A,   SEL_TSIF0_A),
 
         PINMUX_IPSR_MSEL(IP1_14_11,     SD1_WP_A,       SEL_SD1_A),
-        PINMUX_IPSR_DATA(IP1_14_11,     MMC_D7),
-        PINMUX_IPSR_DATA(IP1_14_11,     A25),
-        PINMUX_IPSR_DATA(IP1_14_11,     DACK1_A),
+        PINMUX_IPSR_GPSR(IP1_14_11,     MMC_D7),
+        PINMUX_IPSR_GPSR(IP1_14_11,     A25),
+        PINMUX_IPSR_GPSR(IP1_14_11,     DACK1_A),
         PINMUX_IPSR_MSEL(IP1_14_11,     HCTS0_B,        SEL_HSCIF0_B),
         PINMUX_IPSR_MSEL(IP1_14_11,     RX3_C,          SEL_SCIF3_C),
         PINMUX_IPSR_MSEL(IP1_14_11,     TS_SDAT0_A,     SEL_TSIF0_A),
@@ -654,54 +654,54 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_NOGM(IP1_20_18,     SDA2_A,         SEL_I2C2_A),
         PINMUX_IPSR_NOGM(IP1_20_18,     SCK2_B,         SEL_SCIF2_B),
 
-        PINMUX_IPSR_DATA(IP1_23_21,     MMC_D5),
-        PINMUX_IPSR_DATA(IP1_23_21,     ATADIR0_B),
-        PINMUX_IPSR_DATA(IP1_23_21,     RD_WR),
+        PINMUX_IPSR_GPSR(IP1_23_21,     MMC_D5),
+        PINMUX_IPSR_GPSR(IP1_23_21,     ATADIR0_B),
+        PINMUX_IPSR_GPSR(IP1_23_21,     RD_WR),
 
-        PINMUX_IPSR_DATA(IP1_24,        WE1),
-        PINMUX_IPSR_DATA(IP1_24,        ATAWR0_B),
+        PINMUX_IPSR_GPSR(IP1_24,        WE1),
+        PINMUX_IPSR_GPSR(IP1_24,        ATAWR0_B),
 
         PINMUX_IPSR_MSEL(IP1_27_25,     SSI_WS1_B,      SEL_SSI1_B),
-        PINMUX_IPSR_DATA(IP1_27_25,     EX_CS0),
+        PINMUX_IPSR_GPSR(IP1_27_25,     EX_CS0),
         PINMUX_IPSR_MSEL(IP1_27_25,     SCL2_A,         SEL_I2C2_A),
-        PINMUX_IPSR_DATA(IP1_27_25,     TX3_C),
+        PINMUX_IPSR_GPSR(IP1_27_25,     TX3_C),
         PINMUX_IPSR_MSEL(IP1_27_25,     TS_SCK0_A,      SEL_TSIF0_A),
 
-        PINMUX_IPSR_DATA(IP1_29_28,     EX_CS1),
-        PINMUX_IPSR_DATA(IP1_29_28,     MMC_D4),
+        PINMUX_IPSR_GPSR(IP1_29_28,     EX_CS1),
+        PINMUX_IPSR_GPSR(IP1_29_28,     MMC_D4),
 
         /* IPSR2 */
-        PINMUX_IPSR_DATA(IP2_2_0,       SD1_CLK_A),
-        PINMUX_IPSR_DATA(IP2_2_0,       MMC_CLK),
-        PINMUX_IPSR_DATA(IP2_2_0,       ATACS00),
-        PINMUX_IPSR_DATA(IP2_2_0,       EX_CS2),
+        PINMUX_IPSR_GPSR(IP2_2_0,       SD1_CLK_A),
+        PINMUX_IPSR_GPSR(IP2_2_0,       MMC_CLK),
+        PINMUX_IPSR_GPSR(IP2_2_0,       ATACS00),
+        PINMUX_IPSR_GPSR(IP2_2_0,       EX_CS2),
 
         PINMUX_IPSR_MSEL(IP2_5_3,       SD1_CMD_A,      SEL_SD1_A),
-        PINMUX_IPSR_DATA(IP2_5_3,       MMC_CMD),
-        PINMUX_IPSR_DATA(IP2_5_3,       ATACS10),
-        PINMUX_IPSR_DATA(IP2_5_3,       EX_CS3),
+        PINMUX_IPSR_GPSR(IP2_5_3,       MMC_CMD),
+        PINMUX_IPSR_GPSR(IP2_5_3,       ATACS10),
+        PINMUX_IPSR_GPSR(IP2_5_3,       EX_CS3),
 
         PINMUX_IPSR_MSEL(IP2_8_6,       SD1_DAT0_A,     SEL_SD1_A),
-        PINMUX_IPSR_DATA(IP2_8_6,       MMC_D0),
-        PINMUX_IPSR_DATA(IP2_8_6,       ATARD0),
-        PINMUX_IPSR_DATA(IP2_8_6,       EX_CS4),
+        PINMUX_IPSR_GPSR(IP2_8_6,       MMC_D0),
+        PINMUX_IPSR_GPSR(IP2_8_6,       ATARD0),
+        PINMUX_IPSR_GPSR(IP2_8_6,       EX_CS4),
         PINMUX_IPSR_MSEL(IP2_8_6,       EX_WAIT1_A,     SEL_WAIT1_A),
 
         PINMUX_IPSR_MSEL(IP2_11_9,      SD1_DAT1_A,     SEL_SD1_A),
-        PINMUX_IPSR_DATA(IP2_11_9,      MMC_D1),
-        PINMUX_IPSR_DATA(IP2_11_9,      ATAWR0_A),
-        PINMUX_IPSR_DATA(IP2_11_9,      EX_CS5),
+        PINMUX_IPSR_GPSR(IP2_11_9,      MMC_D1),
+        PINMUX_IPSR_GPSR(IP2_11_9,      ATAWR0_A),
+        PINMUX_IPSR_GPSR(IP2_11_9,      EX_CS5),
         PINMUX_IPSR_MSEL(IP2_11_9,      EX_WAIT2_A,     SEL_WAIT2_A),
 
         PINMUX_IPSR_MSEL(IP2_13_12,     DREQ0_A,        SEL_DREQ0_A),
         PINMUX_IPSR_MSEL(IP2_13_12,     RX3_A,          SEL_SCIF3_A),
 
-        PINMUX_IPSR_DATA(IP2_16_14,     DACK0),
-        PINMUX_IPSR_DATA(IP2_16_14,     TX3_A),
-        PINMUX_IPSR_DATA(IP2_16_14,     DRACK0),
+        PINMUX_IPSR_GPSR(IP2_16_14,     DACK0),
+        PINMUX_IPSR_GPSR(IP2_16_14,     TX3_A),
+        PINMUX_IPSR_GPSR(IP2_16_14,     DRACK0),
 
-        PINMUX_IPSR_DATA(IP2_17,        EX_WAIT0),
-        PINMUX_IPSR_DATA(IP2_17,        PWM0_C),
+        PINMUX_IPSR_GPSR(IP2_17,        EX_WAIT0),
+        PINMUX_IPSR_GPSR(IP2_17,        PWM0_C),
 
         PINMUX_IPSR_NOGP(IP2_18,        D0),
         PINMUX_IPSR_NOGP(IP2_19,        D1),
@@ -716,33 +716,33 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_NOGP(IP2_28,        D10),
         PINMUX_IPSR_NOGP(IP2_29,        D11),
 
-        PINMUX_IPSR_DATA(IP2_30,        RD_WR_B),
-        PINMUX_IPSR_DATA(IP2_30,        IRQ0),
+        PINMUX_IPSR_GPSR(IP2_30,        RD_WR_B),
+        PINMUX_IPSR_GPSR(IP2_30,        IRQ0),
 
-        PINMUX_IPSR_DATA(IP2_31,        MLB_CLK),
+        PINMUX_IPSR_GPSR(IP2_31,        MLB_CLK),
         PINMUX_IPSR_MSEL(IP2_31,        IRQ1_A,         SEL_IRQ1_A),
 
         /* IPSR3 */
-        PINMUX_IPSR_DATA(IP3_1_0,       MLB_SIG),
+        PINMUX_IPSR_GPSR(IP3_1_0,       MLB_SIG),
         PINMUX_IPSR_MSEL(IP3_1_0,       RX5_B,          SEL_SCIF5_B),
         PINMUX_IPSR_MSEL(IP3_1_0,       SDA3_A,         SEL_I2C3_A),
         PINMUX_IPSR_MSEL(IP3_1_0,       IRQ2_A,         SEL_IRQ2_A),
 
-        PINMUX_IPSR_DATA(IP3_4_2,       MLB_DAT),
-        PINMUX_IPSR_DATA(IP3_4_2,       TX5_B),
+        PINMUX_IPSR_GPSR(IP3_4_2,       MLB_DAT),
+        PINMUX_IPSR_GPSR(IP3_4_2,       TX5_B),
         PINMUX_IPSR_MSEL(IP3_4_2,       SCL3_A,         SEL_I2C3_A),
         PINMUX_IPSR_MSEL(IP3_4_2,       IRQ3_A,         SEL_IRQ3_A),
-        PINMUX_IPSR_DATA(IP3_4_2,       SDSELF_B),
+        PINMUX_IPSR_GPSR(IP3_4_2,       SDSELF_B),
 
         PINMUX_IPSR_MSEL(IP3_7_5,       SD1_CMD_B,      SEL_SD1_B),
-        PINMUX_IPSR_DATA(IP3_7_5,       SCIF_CLK),
-        PINMUX_IPSR_DATA(IP3_7_5,       AUDIO_CLKOUT_B),
+        PINMUX_IPSR_GPSR(IP3_7_5,       SCIF_CLK),
+        PINMUX_IPSR_GPSR(IP3_7_5,       AUDIO_CLKOUT_B),
         PINMUX_IPSR_MSEL(IP3_7_5,       CAN_CLK_B,      SEL_CANCLK_B),
         PINMUX_IPSR_MSEL(IP3_7_5,       SDA3_B,         SEL_I2C3_B),
 
-        PINMUX_IPSR_DATA(IP3_9_8,       SD1_CLK_B),
-        PINMUX_IPSR_DATA(IP3_9_8,       HTX0_A),
-        PINMUX_IPSR_DATA(IP3_9_8,       TX0_A),
+        PINMUX_IPSR_GPSR(IP3_9_8,       SD1_CLK_B),
+        PINMUX_IPSR_GPSR(IP3_9_8,       HTX0_A),
+        PINMUX_IPSR_GPSR(IP3_9_8,       TX0_A),
 
         PINMUX_IPSR_MSEL(IP3_12_10,     SD1_DAT0_B,     SEL_SD1_B),
         PINMUX_IPSR_MSEL(IP3_12_10,     HRX0_A,         SEL_HSCIF0_A),
@@ -750,513 +750,513 @@ static const u16 pinmux_data[] = {
 
         PINMUX_IPSR_MSEL(IP3_15_13,     SD1_DAT1_B,     SEL_SD1_B),
         PINMUX_IPSR_MSEL(IP3_15_13,     HSCK0,          SEL_HSCIF0_A),
-        PINMUX_IPSR_DATA(IP3_15_13,     SCK0),
+        PINMUX_IPSR_GPSR(IP3_15_13,     SCK0),
         PINMUX_IPSR_MSEL(IP3_15_13,     SCL3_B,         SEL_I2C3_B),
 
         PINMUX_IPSR_MSEL(IP3_18_16,     SD1_DAT2_B,     SEL_SD1_B),
         PINMUX_IPSR_MSEL(IP3_18_16,     HCTS0_A,        SEL_HSCIF0_A),
-        PINMUX_IPSR_DATA(IP3_18_16,     CTS0),
+        PINMUX_IPSR_GPSR(IP3_18_16,     CTS0),
 
         PINMUX_IPSR_MSEL(IP3_20_19,     SD1_DAT3_B,     SEL_SD1_B),
         PINMUX_IPSR_MSEL(IP3_20_19,     HRTS0_A,        SEL_HSCIF0_A),
-        PINMUX_IPSR_DATA(IP3_20_19,     RTS0),
+        PINMUX_IPSR_GPSR(IP3_20_19,     RTS0),
 
-        PINMUX_IPSR_DATA(IP3_23_21,     SSI_SCK4),
-        PINMUX_IPSR_DATA(IP3_23_21,     DU0_DR0),
-        PINMUX_IPSR_DATA(IP3_23_21,     LCDOUT0),
-        PINMUX_IPSR_DATA(IP3_23_21,     AUDATA2),
-        PINMUX_IPSR_DATA(IP3_23_21,     ARM_TRACEDATA_2),
+        PINMUX_IPSR_GPSR(IP3_23_21,     SSI_SCK4),
+        PINMUX_IPSR_GPSR(IP3_23_21,     DU0_DR0),
+        PINMUX_IPSR_GPSR(IP3_23_21,     LCDOUT0),
+        PINMUX_IPSR_GPSR(IP3_23_21,     AUDATA2),
+        PINMUX_IPSR_GPSR(IP3_23_21,     ARM_TRACEDATA_2),
         PINMUX_IPSR_MSEL(IP3_23_21,     SDA3_C,         SEL_I2C3_C),
-        PINMUX_IPSR_DATA(IP3_23_21,     ADICHS1),
+        PINMUX_IPSR_GPSR(IP3_23_21,     ADICHS1),
         PINMUX_IPSR_MSEL(IP3_23_21,     TS_SDEN0_B,     SEL_TSIF0_B),
 
-        PINMUX_IPSR_DATA(IP3_26_24,     SSI_WS4),
-        PINMUX_IPSR_DATA(IP3_26_24,     DU0_DR1),
-        PINMUX_IPSR_DATA(IP3_26_24,     LCDOUT1),
-        PINMUX_IPSR_DATA(IP3_26_24,     AUDATA3),
-        PINMUX_IPSR_DATA(IP3_26_24,     ARM_TRACEDATA_3),
+        PINMUX_IPSR_GPSR(IP3_26_24,     SSI_WS4),
+        PINMUX_IPSR_GPSR(IP3_26_24,     DU0_DR1),
+        PINMUX_IPSR_GPSR(IP3_26_24,     LCDOUT1),
+        PINMUX_IPSR_GPSR(IP3_26_24,     AUDATA3),
+        PINMUX_IPSR_GPSR(IP3_26_24,     ARM_TRACEDATA_3),
         PINMUX_IPSR_MSEL(IP3_26_24,     SCL3_C,         SEL_I2C3_C),
-        PINMUX_IPSR_DATA(IP3_26_24,     ADICHS2),
+        PINMUX_IPSR_GPSR(IP3_26_24,     ADICHS2),
         PINMUX_IPSR_MSEL(IP3_26_24,     TS_SPSYNC0_B,   SEL_TSIF0_B),
 
-        PINMUX_IPSR_DATA(IP3_27,        DU0_DR2),
-        PINMUX_IPSR_DATA(IP3_27,        LCDOUT2),
+        PINMUX_IPSR_GPSR(IP3_27,        DU0_DR2),
+        PINMUX_IPSR_GPSR(IP3_27,        LCDOUT2),
 
-        PINMUX_IPSR_DATA(IP3_28,        DU0_DR3),
-        PINMUX_IPSR_DATA(IP3_28,        LCDOUT3),
+        PINMUX_IPSR_GPSR(IP3_28,        DU0_DR3),
+        PINMUX_IPSR_GPSR(IP3_28,        LCDOUT3),
 
-        PINMUX_IPSR_DATA(IP3_29,        DU0_DR4),
-        PINMUX_IPSR_DATA(IP3_29,        LCDOUT4),
+        PINMUX_IPSR_GPSR(IP3_29,        DU0_DR4),
+        PINMUX_IPSR_GPSR(IP3_29,        LCDOUT4),
 
-        PINMUX_IPSR_DATA(IP3_30,        DU0_DR5),
-        PINMUX_IPSR_DATA(IP3_30,        LCDOUT5),
+        PINMUX_IPSR_GPSR(IP3_30,        DU0_DR5),
+        PINMUX_IPSR_GPSR(IP3_30,        LCDOUT5),
 
-        PINMUX_IPSR_DATA(IP3_31,        DU0_DR6),
-        PINMUX_IPSR_DATA(IP3_31,        LCDOUT6),
+        PINMUX_IPSR_GPSR(IP3_31,        DU0_DR6),
+        PINMUX_IPSR_GPSR(IP3_31,        LCDOUT6),
 
         /* IPSR4 */
-        PINMUX_IPSR_DATA(IP4_0,         DU0_DR7),
-        PINMUX_IPSR_DATA(IP4_0,         LCDOUT7),
-
-        PINMUX_IPSR_DATA(IP4_3_1,       DU0_DG0),
-        PINMUX_IPSR_DATA(IP4_3_1,       LCDOUT8),
-        PINMUX_IPSR_DATA(IP4_3_1,       AUDATA4),
-        PINMUX_IPSR_DATA(IP4_3_1,       ARM_TRACEDATA_4),
-        PINMUX_IPSR_DATA(IP4_3_1,       TX1_D),
-        PINMUX_IPSR_DATA(IP4_3_1,       CAN0_TX_A),
-        PINMUX_IPSR_DATA(IP4_3_1,       ADICHS0),
-
-        PINMUX_IPSR_DATA(IP4_6_4,       DU0_DG1),
-        PINMUX_IPSR_DATA(IP4_6_4,       LCDOUT9),
-        PINMUX_IPSR_DATA(IP4_6_4,       AUDATA5),
-        PINMUX_IPSR_DATA(IP4_6_4,       ARM_TRACEDATA_5),
+        PINMUX_IPSR_GPSR(IP4_0,         DU0_DR7),
+        PINMUX_IPSR_GPSR(IP4_0,         LCDOUT7),
+
+        PINMUX_IPSR_GPSR(IP4_3_1,       DU0_DG0),
+        PINMUX_IPSR_GPSR(IP4_3_1,       LCDOUT8),
+        PINMUX_IPSR_GPSR(IP4_3_1,       AUDATA4),
+        PINMUX_IPSR_GPSR(IP4_3_1,       ARM_TRACEDATA_4),
+        PINMUX_IPSR_GPSR(IP4_3_1,       TX1_D),
+        PINMUX_IPSR_GPSR(IP4_3_1,       CAN0_TX_A),
+        PINMUX_IPSR_GPSR(IP4_3_1,       ADICHS0),
+
+        PINMUX_IPSR_GPSR(IP4_6_4,       DU0_DG1),
+        PINMUX_IPSR_GPSR(IP4_6_4,       LCDOUT9),
+        PINMUX_IPSR_GPSR(IP4_6_4,       AUDATA5),
+        PINMUX_IPSR_GPSR(IP4_6_4,       ARM_TRACEDATA_5),
         PINMUX_IPSR_MSEL(IP4_6_4,       RX1_D,          SEL_SCIF1_D),
         PINMUX_IPSR_MSEL(IP4_6_4,       CAN0_RX_A,      SEL_CAN0_A),
-        PINMUX_IPSR_DATA(IP4_6_4,       ADIDATA),
+        PINMUX_IPSR_GPSR(IP4_6_4,       ADIDATA),
 
-        PINMUX_IPSR_DATA(IP4_7,         DU0_DG2),
-        PINMUX_IPSR_DATA(IP4_7,         LCDOUT10),
+        PINMUX_IPSR_GPSR(IP4_7,         DU0_DG2),
+        PINMUX_IPSR_GPSR(IP4_7,         LCDOUT10),
 
-        PINMUX_IPSR_DATA(IP4_8,         DU0_DG3),
-        PINMUX_IPSR_DATA(IP4_8,         LCDOUT11),
+        PINMUX_IPSR_GPSR(IP4_8,         DU0_DG3),
+        PINMUX_IPSR_GPSR(IP4_8,         LCDOUT11),
 
-        PINMUX_IPSR_DATA(IP4_10_9,      DU0_DG4),
-        PINMUX_IPSR_DATA(IP4_10_9,      LCDOUT12),
+        PINMUX_IPSR_GPSR(IP4_10_9,      DU0_DG4),
+        PINMUX_IPSR_GPSR(IP4_10_9,      LCDOUT12),
         PINMUX_IPSR_MSEL(IP4_10_9,      RX0_B,          SEL_SCIF0_B),
 
-        PINMUX_IPSR_DATA(IP4_12_11,     DU0_DG5),
-        PINMUX_IPSR_DATA(IP4_12_11,     LCDOUT13),
-        PINMUX_IPSR_DATA(IP4_12_11,     TX0_B),
+        PINMUX_IPSR_GPSR(IP4_12_11,     DU0_DG5),
+        PINMUX_IPSR_GPSR(IP4_12_11,     LCDOUT13),
+        PINMUX_IPSR_GPSR(IP4_12_11,     TX0_B),
 
-        PINMUX_IPSR_DATA(IP4_14_13,     DU0_DG6),
-        PINMUX_IPSR_DATA(IP4_14_13,     LCDOUT14),
+        PINMUX_IPSR_GPSR(IP4_14_13,     DU0_DG6),
+        PINMUX_IPSR_GPSR(IP4_14_13,     LCDOUT14),
         PINMUX_IPSR_MSEL(IP4_14_13,     RX4_A,          SEL_SCIF4_A),
 
-        PINMUX_IPSR_DATA(IP4_16_15,     DU0_DG7),
-        PINMUX_IPSR_DATA(IP4_16_15,     LCDOUT15),
-        PINMUX_IPSR_DATA(IP4_16_15,     TX4_A),
+        PINMUX_IPSR_GPSR(IP4_16_15,     DU0_DG7),
+        PINMUX_IPSR_GPSR(IP4_16_15,     LCDOUT15),
+        PINMUX_IPSR_GPSR(IP4_16_15,     TX4_A),
 
         PINMUX_IPSR_MSEL(IP4_20_17,     SSI_SCK2_B,     SEL_SSI2_B),
         PINMUX_DATA(VI0_R0_B_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_B), /* see sel_vi0 */
         PINMUX_DATA(VI0_R0_D_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_D), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP4_20_17,     DU0_DB0),
-        PINMUX_IPSR_DATA(IP4_20_17,     LCDOUT16),
-        PINMUX_IPSR_DATA(IP4_20_17,     AUDATA6),
-        PINMUX_IPSR_DATA(IP4_20_17,     ARM_TRACEDATA_6),
+        PINMUX_IPSR_GPSR(IP4_20_17,     DU0_DB0),
+        PINMUX_IPSR_GPSR(IP4_20_17,     LCDOUT16),
+        PINMUX_IPSR_GPSR(IP4_20_17,     AUDATA6),
+        PINMUX_IPSR_GPSR(IP4_20_17,     ARM_TRACEDATA_6),
         PINMUX_IPSR_MSEL(IP4_20_17,     GPSCLK_A,       SEL_GPS_A),
-        PINMUX_IPSR_DATA(IP4_20_17,     PWM0_A),
-        PINMUX_IPSR_DATA(IP4_20_17,     ADICLK),
+        PINMUX_IPSR_GPSR(IP4_20_17,     PWM0_A),
+        PINMUX_IPSR_GPSR(IP4_20_17,     ADICLK),
         PINMUX_IPSR_MSEL(IP4_20_17,     TS_SDAT0_B,     SEL_TSIF0_B),
 
-        PINMUX_IPSR_DATA(IP4_24_21,     AUDIO_CLKC),
+        PINMUX_IPSR_GPSR(IP4_24_21,     AUDIO_CLKC),
         PINMUX_DATA(VI0_R1_B_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_B), /* see sel_vi0 */
         PINMUX_DATA(VI0_R1_D_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_D), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP4_24_21,     DU0_DB1),
-        PINMUX_IPSR_DATA(IP4_24_21,     LCDOUT17),
-        PINMUX_IPSR_DATA(IP4_24_21,     AUDATA7),
-        PINMUX_IPSR_DATA(IP4_24_21,     ARM_TRACEDATA_7),
+        PINMUX_IPSR_GPSR(IP4_24_21,     DU0_DB1),
+        PINMUX_IPSR_GPSR(IP4_24_21,     LCDOUT17),
+        PINMUX_IPSR_GPSR(IP4_24_21,     AUDATA7),
+        PINMUX_IPSR_GPSR(IP4_24_21,     ARM_TRACEDATA_7),
         PINMUX_IPSR_MSEL(IP4_24_21,     GPSIN_A,        SEL_GPS_A),
-        PINMUX_IPSR_DATA(IP4_24_21,     ADICS_SAMP),
+        PINMUX_IPSR_GPSR(IP4_24_21,     ADICS_SAMP),
         PINMUX_IPSR_MSEL(IP4_24_21,     TS_SCK0_B,      SEL_TSIF0_B),
 
         PINMUX_DATA(VI0_R2_B_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_B), /* see sel_vi0 */
         PINMUX_DATA(VI0_R2_D_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_D), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP4_26_25,     DU0_DB2),
-        PINMUX_IPSR_DATA(IP4_26_25,     LCDOUT18),
+        PINMUX_IPSR_GPSR(IP4_26_25,     DU0_DB2),
+        PINMUX_IPSR_GPSR(IP4_26_25,     LCDOUT18),
 
         PINMUX_IPSR_MSEL(IP4_28_27,     VI0_R3_B,       SEL_VI0_B),
-        PINMUX_IPSR_DATA(IP4_28_27,     DU0_DB3),
-        PINMUX_IPSR_DATA(IP4_28_27,     LCDOUT19),
+        PINMUX_IPSR_GPSR(IP4_28_27,     DU0_DB3),
+        PINMUX_IPSR_GPSR(IP4_28_27,     LCDOUT19),
 
         PINMUX_DATA(VI0_R4_B_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_B), /* see sel_vi0 */
         PINMUX_DATA(VI0_R4_D_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_D), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP4_30_29,     DU0_DB4),
-        PINMUX_IPSR_DATA(IP4_30_29,     LCDOUT20),
+        PINMUX_IPSR_GPSR(IP4_30_29,     DU0_DB4),
+        PINMUX_IPSR_GPSR(IP4_30_29,     LCDOUT20),
 
         /* IPSR5 */
         PINMUX_DATA(VI0_R5_B_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_B), /* see sel_vi0 */
         PINMUX_DATA(VI0_R5_D_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_D), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP5_1_0,       DU0_DB5),
-        PINMUX_IPSR_DATA(IP5_1_0,       LCDOUT21),
+        PINMUX_IPSR_GPSR(IP5_1_0,       DU0_DB5),
+        PINMUX_IPSR_GPSR(IP5_1_0,       LCDOUT21),
 
         PINMUX_IPSR_MSEL(IP5_3_2,       VI1_DATA10_B,   SEL_VI1_B),
-        PINMUX_IPSR_DATA(IP5_3_2,       DU0_DB6),
-        PINMUX_IPSR_DATA(IP5_3_2,       LCDOUT22),
+        PINMUX_IPSR_GPSR(IP5_3_2,       DU0_DB6),
+        PINMUX_IPSR_GPSR(IP5_3_2,       LCDOUT22),
 
         PINMUX_IPSR_MSEL(IP5_5_4,       VI1_DATA11_B,   SEL_VI1_B),
-        PINMUX_IPSR_DATA(IP5_5_4,       DU0_DB7),
-        PINMUX_IPSR_DATA(IP5_5_4,       LCDOUT23),
+        PINMUX_IPSR_GPSR(IP5_5_4,       DU0_DB7),
+        PINMUX_IPSR_GPSR(IP5_5_4,       LCDOUT23),
 
-        PINMUX_IPSR_DATA(IP5_6,         DU0_DOTCLKIN),
-        PINMUX_IPSR_DATA(IP5_6,         QSTVA_QVS),
+        PINMUX_IPSR_GPSR(IP5_6,         DU0_DOTCLKIN),
+        PINMUX_IPSR_GPSR(IP5_6,         QSTVA_QVS),
 
-        PINMUX_IPSR_DATA(IP5_7,         DU0_DOTCLKO_UT0),
-        PINMUX_IPSR_DATA(IP5_7,         QCLK),
+        PINMUX_IPSR_GPSR(IP5_7,         DU0_DOTCLKO_UT0),
+        PINMUX_IPSR_GPSR(IP5_7,         QCLK),
 
-        PINMUX_IPSR_DATA(IP5_9_8,       DU0_DOTCLKO_UT1),
-        PINMUX_IPSR_DATA(IP5_9_8,       QSTVB_QVE),
-        PINMUX_IPSR_DATA(IP5_9_8,       AUDIO_CLKOUT_A),
+        PINMUX_IPSR_GPSR(IP5_9_8,       DU0_DOTCLKO_UT1),
+        PINMUX_IPSR_GPSR(IP5_9_8,       QSTVB_QVE),
+        PINMUX_IPSR_GPSR(IP5_9_8,       AUDIO_CLKOUT_A),
         PINMUX_IPSR_MSEL(IP5_9_8,       REMOCON_C,      SEL_REMOCON_C),
 
         PINMUX_IPSR_MSEL(IP5_11_10,     SSI_WS2_B,      SEL_SSI2_B),
-        PINMUX_IPSR_DATA(IP5_11_10,     DU0_EXHSYNC_DU0_HSYNC),
-        PINMUX_IPSR_DATA(IP5_11_10,     QSTH_QHS),
+        PINMUX_IPSR_GPSR(IP5_11_10,     DU0_EXHSYNC_DU0_HSYNC),
+        PINMUX_IPSR_GPSR(IP5_11_10,     QSTH_QHS),
 
-        PINMUX_IPSR_DATA(IP5_12,        DU0_EXVSYNC_DU0_VSYNC),
-        PINMUX_IPSR_DATA(IP5_12,        QSTB_QHE),
+        PINMUX_IPSR_GPSR(IP5_12,        DU0_EXVSYNC_DU0_VSYNC),
+        PINMUX_IPSR_GPSR(IP5_12,        QSTB_QHE),
 
-        PINMUX_IPSR_DATA(IP5_14_13,     DU0_EXODDF_DU0_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP5_14_13,     QCPV_QDE),
+        PINMUX_IPSR_GPSR(IP5_14_13,     DU0_EXODDF_DU0_ODDF_DISP_CDE),
+        PINMUX_IPSR_GPSR(IP5_14_13,     QCPV_QDE),
         PINMUX_IPSR_MSEL(IP5_14_13,     FMCLK_D,        SEL_FM_D),
 
         PINMUX_IPSR_MSEL(IP5_17_15,     SSI_SCK1_A,     SEL_SSI1_A),
-        PINMUX_IPSR_DATA(IP5_17_15,     DU0_DISP),
-        PINMUX_IPSR_DATA(IP5_17_15,     QPOLA),
-        PINMUX_IPSR_DATA(IP5_17_15,     AUDCK),
-        PINMUX_IPSR_DATA(IP5_17_15,     ARM_TRACECLK),
-        PINMUX_IPSR_DATA(IP5_17_15,     BPFCLK_D),
+        PINMUX_IPSR_GPSR(IP5_17_15,     DU0_DISP),
+        PINMUX_IPSR_GPSR(IP5_17_15,     QPOLA),
+        PINMUX_IPSR_GPSR(IP5_17_15,     AUDCK),
+        PINMUX_IPSR_GPSR(IP5_17_15,     ARM_TRACECLK),
+        PINMUX_IPSR_GPSR(IP5_17_15,     BPFCLK_D),
 
         PINMUX_IPSR_MSEL(IP5_20_18,     SSI_WS1_A,      SEL_SSI1_A),
-        PINMUX_IPSR_DATA(IP5_20_18,     DU0_CDE),
-        PINMUX_IPSR_DATA(IP5_20_18,     QPOLB),
-        PINMUX_IPSR_DATA(IP5_20_18,     AUDSYNC),
-        PINMUX_IPSR_DATA(IP5_20_18,     ARM_TRACECTL),
+        PINMUX_IPSR_GPSR(IP5_20_18,     DU0_CDE),
+        PINMUX_IPSR_GPSR(IP5_20_18,     QPOLB),
+        PINMUX_IPSR_GPSR(IP5_20_18,     AUDSYNC),
+        PINMUX_IPSR_GPSR(IP5_20_18,     ARM_TRACECTL),
         PINMUX_IPSR_MSEL(IP5_20_18,     FMIN_D,         SEL_FM_D),
 
         PINMUX_IPSR_MSEL(IP5_22_21,     SD1_CD_B,       SEL_SD1_B),
-        PINMUX_IPSR_DATA(IP5_22_21,     SSI_SCK78),
+        PINMUX_IPSR_GPSR(IP5_22_21,     SSI_SCK78),
         PINMUX_IPSR_MSEL(IP5_22_21,     HSPI_RX0_B,     SEL_HSPI0_B),
-        PINMUX_IPSR_DATA(IP5_22_21,     TX1_B),
+        PINMUX_IPSR_GPSR(IP5_22_21,     TX1_B),
 
         PINMUX_IPSR_MSEL(IP5_25_23,     SD1_WP_B,       SEL_SD1_B),
-        PINMUX_IPSR_DATA(IP5_25_23,     SSI_WS78),
+        PINMUX_IPSR_GPSR(IP5_25_23,     SSI_WS78),
         PINMUX_IPSR_MSEL(IP5_25_23,     HSPI_CLK0_B,    SEL_HSPI0_B),
         PINMUX_IPSR_MSEL(IP5_25_23,     RX1_B,          SEL_SCIF1_B),
         PINMUX_IPSR_MSEL(IP5_25_23,     CAN_CLK_D,      SEL_CANCLK_D),
 
-        PINMUX_IPSR_DATA(IP5_28_26,     SSI_SDATA8),
+        PINMUX_IPSR_GPSR(IP5_28_26,     SSI_SDATA8),
         PINMUX_IPSR_MSEL(IP5_28_26,     SSI_SCK2_A,     SEL_SSI2_A),
         PINMUX_IPSR_MSEL(IP5_28_26,     HSPI_CS0_B,     SEL_HSPI0_B),
-        PINMUX_IPSR_DATA(IP5_28_26,     TX2_A),
-        PINMUX_IPSR_DATA(IP5_28_26,     CAN0_TX_B),
+        PINMUX_IPSR_GPSR(IP5_28_26,     TX2_A),
+        PINMUX_IPSR_GPSR(IP5_28_26,     CAN0_TX_B),
 
-        PINMUX_IPSR_DATA(IP5_30_29,     SSI_SDATA7),
-        PINMUX_IPSR_DATA(IP5_30_29,     HSPI_TX0_B),
+        PINMUX_IPSR_GPSR(IP5_30_29,     SSI_SDATA7),
+        PINMUX_IPSR_GPSR(IP5_30_29,     HSPI_TX0_B),
         PINMUX_IPSR_MSEL(IP5_30_29,     RX2_A,          SEL_SCIF2_A),
         PINMUX_IPSR_MSEL(IP5_30_29,     CAN0_RX_B,      SEL_CAN0_B),
 
         /* IPSR6 */
-        PINMUX_IPSR_DATA(IP6_1_0,       SSI_SCK6),
+        PINMUX_IPSR_GPSR(IP6_1_0,       SSI_SCK6),
         PINMUX_IPSR_MSEL(IP6_1_0,       HSPI_RX2_A,     SEL_HSPI2_A),
         PINMUX_IPSR_MSEL(IP6_1_0,       FMCLK_B,        SEL_FM_B),
-        PINMUX_IPSR_DATA(IP6_1_0,       CAN1_TX_B),
+        PINMUX_IPSR_GPSR(IP6_1_0,       CAN1_TX_B),
 
-        PINMUX_IPSR_DATA(IP6_4_2,       SSI_WS6),
+        PINMUX_IPSR_GPSR(IP6_4_2,       SSI_WS6),
         PINMUX_IPSR_MSEL(IP6_4_2,       HSPI_CLK2_A,    SEL_HSPI2_A),
-        PINMUX_IPSR_DATA(IP6_4_2,       BPFCLK_B),
+        PINMUX_IPSR_GPSR(IP6_4_2,       BPFCLK_B),
         PINMUX_IPSR_MSEL(IP6_4_2,       CAN1_RX_B,      SEL_CAN1_B),
 
-        PINMUX_IPSR_DATA(IP6_6_5,       SSI_SDATA6),
-        PINMUX_IPSR_DATA(IP6_6_5,       HSPI_TX2_A),
+        PINMUX_IPSR_GPSR(IP6_6_5,       SSI_SDATA6),
+        PINMUX_IPSR_GPSR(IP6_6_5,       HSPI_TX2_A),
         PINMUX_IPSR_MSEL(IP6_6_5,       FMIN_B,         SEL_FM_B),
 
-        PINMUX_IPSR_DATA(IP6_7,         SSI_SCK5),
+        PINMUX_IPSR_GPSR(IP6_7,         SSI_SCK5),
         PINMUX_IPSR_MSEL(IP6_7,         RX4_C,          SEL_SCIF4_C),
 
-        PINMUX_IPSR_DATA(IP6_8,         SSI_WS5),
-        PINMUX_IPSR_DATA(IP6_8,         TX4_C),
+        PINMUX_IPSR_GPSR(IP6_8,         SSI_WS5),
+        PINMUX_IPSR_GPSR(IP6_8,         TX4_C),
 
-        PINMUX_IPSR_DATA(IP6_9,         SSI_SDATA5),
+        PINMUX_IPSR_GPSR(IP6_9,         SSI_SDATA5),
         PINMUX_IPSR_MSEL(IP6_9,         RX0_D,          SEL_SCIF0_D),
 
-        PINMUX_IPSR_DATA(IP6_10,        SSI_WS34),
-        PINMUX_IPSR_DATA(IP6_10,        ARM_TRACEDATA_8),
+        PINMUX_IPSR_GPSR(IP6_10,        SSI_WS34),
+        PINMUX_IPSR_GPSR(IP6_10,        ARM_TRACEDATA_8),
 
-        PINMUX_IPSR_DATA(IP6_12_11,     SSI_SDATA4),
+        PINMUX_IPSR_GPSR(IP6_12_11,     SSI_SDATA4),
         PINMUX_IPSR_MSEL(IP6_12_11,     SSI_WS2_A,      SEL_SSI2_A),
-        PINMUX_IPSR_DATA(IP6_12_11,     ARM_TRACEDATA_9),
+        PINMUX_IPSR_GPSR(IP6_12_11,     ARM_TRACEDATA_9),
 
-        PINMUX_IPSR_DATA(IP6_13,        SSI_SDATA3),
-        PINMUX_IPSR_DATA(IP6_13,        ARM_TRACEDATA_10),
+        PINMUX_IPSR_GPSR(IP6_13,        SSI_SDATA3),
+        PINMUX_IPSR_GPSR(IP6_13,        ARM_TRACEDATA_10),
 
-        PINMUX_IPSR_DATA(IP6_15_14,     SSI_SCK012),
-        PINMUX_IPSR_DATA(IP6_15_14,     ARM_TRACEDATA_11),
-        PINMUX_IPSR_DATA(IP6_15_14,     TX0_D),
+        PINMUX_IPSR_GPSR(IP6_15_14,     SSI_SCK012),
+        PINMUX_IPSR_GPSR(IP6_15_14,     ARM_TRACEDATA_11),
+        PINMUX_IPSR_GPSR(IP6_15_14,     TX0_D),
 
-        PINMUX_IPSR_DATA(IP6_16,        SSI_WS012),
-        PINMUX_IPSR_DATA(IP6_16,        ARM_TRACEDATA_12),
+        PINMUX_IPSR_GPSR(IP6_16,        SSI_WS012),
+        PINMUX_IPSR_GPSR(IP6_16,        ARM_TRACEDATA_12),
 
-        PINMUX_IPSR_DATA(IP6_18_17,     SSI_SDATA2),
+        PINMUX_IPSR_GPSR(IP6_18_17,     SSI_SDATA2),
         PINMUX_IPSR_MSEL(IP6_18_17,     HSPI_CS2_A,     SEL_HSPI2_A),
-        PINMUX_IPSR_DATA(IP6_18_17,     ARM_TRACEDATA_13),
+        PINMUX_IPSR_GPSR(IP6_18_17,     ARM_TRACEDATA_13),
         PINMUX_IPSR_MSEL(IP6_18_17,     SDA1_A,         SEL_I2C1_A),
 
-        PINMUX_IPSR_DATA(IP6_20_19,     SSI_SDATA1),
-        PINMUX_IPSR_DATA(IP6_20_19,     ARM_TRACEDATA_14),
+        PINMUX_IPSR_GPSR(IP6_20_19,     SSI_SDATA1),
+        PINMUX_IPSR_GPSR(IP6_20_19,     ARM_TRACEDATA_14),
         PINMUX_IPSR_MSEL(IP6_20_19,     SCL1_A,         SEL_I2C1_A),
         PINMUX_IPSR_MSEL(IP6_20_19,     SCK2_A,         SEL_SCIF2_A),
 
-        PINMUX_IPSR_DATA(IP6_21,        SSI_SDATA0),
-        PINMUX_IPSR_DATA(IP6_21,        ARM_TRACEDATA_15),
+        PINMUX_IPSR_GPSR(IP6_21,        SSI_SDATA0),
+        PINMUX_IPSR_GPSR(IP6_21,        ARM_TRACEDATA_15),
 
-        PINMUX_IPSR_DATA(IP6_23_22,     SD0_CLK),
-        PINMUX_IPSR_DATA(IP6_23_22,     SUB_TDO),
+        PINMUX_IPSR_GPSR(IP6_23_22,     SD0_CLK),
+        PINMUX_IPSR_GPSR(IP6_23_22,     SUB_TDO),
 
-        PINMUX_IPSR_DATA(IP6_25_24,     SD0_CMD),
-        PINMUX_IPSR_DATA(IP6_25_24,     SUB_TRST),
+        PINMUX_IPSR_GPSR(IP6_25_24,     SD0_CMD),
+        PINMUX_IPSR_GPSR(IP6_25_24,     SUB_TRST),
 
-        PINMUX_IPSR_DATA(IP6_27_26,     SD0_DAT0),
-        PINMUX_IPSR_DATA(IP6_27_26,     SUB_TMS),
+        PINMUX_IPSR_GPSR(IP6_27_26,     SD0_DAT0),
+        PINMUX_IPSR_GPSR(IP6_27_26,     SUB_TMS),
 
-        PINMUX_IPSR_DATA(IP6_29_28,     SD0_DAT1),
-        PINMUX_IPSR_DATA(IP6_29_28,     SUB_TCK),
+        PINMUX_IPSR_GPSR(IP6_29_28,     SD0_DAT1),
+        PINMUX_IPSR_GPSR(IP6_29_28,     SUB_TCK),
 
-        PINMUX_IPSR_DATA(IP6_31_30,     SD0_DAT2),
-        PINMUX_IPSR_DATA(IP6_31_30,     SUB_TDI),
+        PINMUX_IPSR_GPSR(IP6_31_30,     SD0_DAT2),
+        PINMUX_IPSR_GPSR(IP6_31_30,     SUB_TDI),
 
         /* IPSR7 */
-        PINMUX_IPSR_DATA(IP7_1_0,       SD0_DAT3),
+        PINMUX_IPSR_GPSR(IP7_1_0,       SD0_DAT3),
         PINMUX_IPSR_MSEL(IP7_1_0,       IRQ1_B,         SEL_IRQ1_B),
 
-        PINMUX_IPSR_DATA(IP7_3_2,       SD0_CD),
-        PINMUX_IPSR_DATA(IP7_3_2,       TX5_A),
+        PINMUX_IPSR_GPSR(IP7_3_2,       SD0_CD),
+        PINMUX_IPSR_GPSR(IP7_3_2,       TX5_A),
 
-        PINMUX_IPSR_DATA(IP7_5_4,       SD0_WP),
+        PINMUX_IPSR_GPSR(IP7_5_4,       SD0_WP),
         PINMUX_IPSR_MSEL(IP7_5_4,       RX5_A,          SEL_SCIF5_A),
 
-        PINMUX_IPSR_DATA(IP7_8_6,       VI1_CLKENB),
+        PINMUX_IPSR_GPSR(IP7_8_6,       VI1_CLKENB),
         PINMUX_IPSR_MSEL(IP7_8_6,       HSPI_CLK0_A,    SEL_HSPI0_A),
-        PINMUX_IPSR_DATA(IP7_8_6,       HTX1_A),
+        PINMUX_IPSR_GPSR(IP7_8_6,       HTX1_A),
         PINMUX_IPSR_MSEL(IP7_8_6,       RTS1_C,         SEL_SCIF1_C),
 
-        PINMUX_IPSR_DATA(IP7_11_9,      VI1_FIELD),
+        PINMUX_IPSR_GPSR(IP7_11_9,      VI1_FIELD),
         PINMUX_IPSR_MSEL(IP7_11_9,      HSPI_CS0_A,     SEL_HSPI0_A),
         PINMUX_IPSR_MSEL(IP7_11_9,      HRX1_A,         SEL_HSCIF1_A),
         PINMUX_IPSR_MSEL(IP7_11_9,      SCK1_C,         SEL_SCIF1_C),
 
-        PINMUX_IPSR_DATA(IP7_14_12,     VI1_HSYNC),
+        PINMUX_IPSR_GPSR(IP7_14_12,     VI1_HSYNC),
         PINMUX_IPSR_MSEL(IP7_14_12,     HSPI_RX0_A,     SEL_HSPI0_A),
         PINMUX_IPSR_MSEL(IP7_14_12,     HRTS1_A,        SEL_HSCIF1_A),
         PINMUX_IPSR_MSEL(IP7_14_12,     FMCLK_A,        SEL_FM_A),
         PINMUX_IPSR_MSEL(IP7_14_12,     RX1_C,          SEL_SCIF1_C),
 
-        PINMUX_IPSR_DATA(IP7_17_15,     VI1_VSYNC),
-        PINMUX_IPSR_DATA(IP7_17_15,     HSPI_TX0),
+        PINMUX_IPSR_GPSR(IP7_17_15,     VI1_VSYNC),
+        PINMUX_IPSR_GPSR(IP7_17_15,     HSPI_TX0),
         PINMUX_IPSR_MSEL(IP7_17_15,     HCTS1_A,        SEL_HSCIF1_A),
-        PINMUX_IPSR_DATA(IP7_17_15,     BPFCLK_A),
-        PINMUX_IPSR_DATA(IP7_17_15,     TX1_C),
+        PINMUX_IPSR_GPSR(IP7_17_15,     BPFCLK_A),
+        PINMUX_IPSR_GPSR(IP7_17_15,     TX1_C),
 
-        PINMUX_IPSR_DATA(IP7_20_18,     TCLK0),
+        PINMUX_IPSR_GPSR(IP7_20_18,     TCLK0),
         PINMUX_IPSR_MSEL(IP7_20_18,     HSCK1_A,        SEL_HSCIF1_A),
         PINMUX_IPSR_MSEL(IP7_20_18,     FMIN_A,         SEL_FM_A),
         PINMUX_IPSR_MSEL(IP7_20_18,     IRQ2_C,         SEL_IRQ2_C),
         PINMUX_IPSR_MSEL(IP7_20_18,     CTS1_C,         SEL_SCIF1_C),
-        PINMUX_IPSR_DATA(IP7_20_18,     SPEEDIN),
+        PINMUX_IPSR_GPSR(IP7_20_18,     SPEEDIN),
 
-        PINMUX_IPSR_DATA(IP7_21,        VI0_CLK),
+        PINMUX_IPSR_GPSR(IP7_21,        VI0_CLK),
         PINMUX_IPSR_MSEL(IP7_21,        CAN_CLK_A,      SEL_CANCLK_A),
 
-        PINMUX_IPSR_DATA(IP7_24_22,     VI0_CLKENB),
+        PINMUX_IPSR_GPSR(IP7_24_22,     VI0_CLKENB),
         PINMUX_IPSR_MSEL(IP7_24_22,     SD2_DAT2_B,     SEL_SD2_B),
-        PINMUX_IPSR_DATA(IP7_24_22,     VI1_DATA0),
-        PINMUX_IPSR_DATA(IP7_24_22,     DU1_DG6),
+        PINMUX_IPSR_GPSR(IP7_24_22,     VI1_DATA0),
+        PINMUX_IPSR_GPSR(IP7_24_22,     DU1_DG6),
         PINMUX_IPSR_MSEL(IP7_24_22,     HSPI_RX1_A,     SEL_HSPI1_A),
         PINMUX_IPSR_MSEL(IP7_24_22,     RX4_B,          SEL_SCIF4_B),
 
-        PINMUX_IPSR_DATA(IP7_28_25,     VI0_FIELD),
+        PINMUX_IPSR_GPSR(IP7_28_25,     VI0_FIELD),
         PINMUX_IPSR_MSEL(IP7_28_25,     SD2_DAT3_B,     SEL_SD2_B),
         PINMUX_DATA(VI0_R3_C_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_C), /* see sel_vi0 */
         PINMUX_DATA(VI0_R3_D_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_D), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP7_28_25,     VI1_DATA1),
-        PINMUX_IPSR_DATA(IP7_28_25,     DU1_DG7),
+        PINMUX_IPSR_GPSR(IP7_28_25,     VI1_DATA1),
+        PINMUX_IPSR_GPSR(IP7_28_25,     DU1_DG7),
         PINMUX_IPSR_MSEL(IP7_28_25,     HSPI_CLK1_A,    SEL_HSPI1_A),
-        PINMUX_IPSR_DATA(IP7_28_25,     TX4_B),
+        PINMUX_IPSR_GPSR(IP7_28_25,     TX4_B),
 
-        PINMUX_IPSR_DATA(IP7_31_29,     VI0_HSYNC),
+        PINMUX_IPSR_GPSR(IP7_31_29,     VI0_HSYNC),
         PINMUX_IPSR_MSEL(IP7_31_29,     SD2_CD_B,       SEL_SD2_B),
-        PINMUX_IPSR_DATA(IP7_31_29,     VI1_DATA2),
-        PINMUX_IPSR_DATA(IP7_31_29,     DU1_DR2),
+        PINMUX_IPSR_GPSR(IP7_31_29,     VI1_DATA2),
+        PINMUX_IPSR_GPSR(IP7_31_29,     DU1_DR2),
         PINMUX_IPSR_MSEL(IP7_31_29,     HSPI_CS1_A,     SEL_HSPI1_A),
         PINMUX_IPSR_MSEL(IP7_31_29,     RX3_B,          SEL_SCIF3_B),
 
         /* IPSR8 */
-        PINMUX_IPSR_DATA(IP8_2_0,       VI0_VSYNC),
+        PINMUX_IPSR_GPSR(IP8_2_0,       VI0_VSYNC),
         PINMUX_IPSR_MSEL(IP8_2_0,       SD2_WP_B,       SEL_SD2_B),
-        PINMUX_IPSR_DATA(IP8_2_0,       VI1_DATA3),
-        PINMUX_IPSR_DATA(IP8_2_0,       DU1_DR3),
-        PINMUX_IPSR_DATA(IP8_2_0,       HSPI_TX1_A),
-        PINMUX_IPSR_DATA(IP8_2_0,       TX3_B),
+        PINMUX_IPSR_GPSR(IP8_2_0,       VI1_DATA3),
+        PINMUX_IPSR_GPSR(IP8_2_0,       DU1_DR3),
+        PINMUX_IPSR_GPSR(IP8_2_0,       HSPI_TX1_A),
+        PINMUX_IPSR_GPSR(IP8_2_0,       TX3_B),
 
-        PINMUX_IPSR_DATA(IP8_5_3,       VI0_DATA0_VI0_B0),
-        PINMUX_IPSR_DATA(IP8_5_3,       DU1_DG2),
+        PINMUX_IPSR_GPSR(IP8_5_3,       VI0_DATA0_VI0_B0),
+        PINMUX_IPSR_GPSR(IP8_5_3,       DU1_DG2),
         PINMUX_IPSR_MSEL(IP8_5_3,       IRQ2_B,         SEL_IRQ2_B),
         PINMUX_IPSR_MSEL(IP8_5_3,       RX3_D,          SEL_SCIF3_D),
 
-        PINMUX_IPSR_DATA(IP8_8_6,       VI0_DATA1_VI0_B1),
-        PINMUX_IPSR_DATA(IP8_8_6,       DU1_DG3),
+        PINMUX_IPSR_GPSR(IP8_8_6,       VI0_DATA1_VI0_B1),
+        PINMUX_IPSR_GPSR(IP8_8_6,       DU1_DG3),
         PINMUX_IPSR_MSEL(IP8_8_6,       IRQ3_B,         SEL_IRQ3_B),
-        PINMUX_IPSR_DATA(IP8_8_6,       TX3_D),
+        PINMUX_IPSR_GPSR(IP8_8_6,       TX3_D),
 
-        PINMUX_IPSR_DATA(IP8_10_9,      VI0_DATA2_VI0_B2),
-        PINMUX_IPSR_DATA(IP8_10_9,      DU1_DG4),
+        PINMUX_IPSR_GPSR(IP8_10_9,      VI0_DATA2_VI0_B2),
+        PINMUX_IPSR_GPSR(IP8_10_9,      DU1_DG4),
         PINMUX_IPSR_MSEL(IP8_10_9,      RX0_C,          SEL_SCIF0_C),
 
-        PINMUX_IPSR_DATA(IP8_13_11,     VI0_DATA3_VI0_B3),
-        PINMUX_IPSR_DATA(IP8_13_11,     DU1_DG5),
-        PINMUX_IPSR_DATA(IP8_13_11,     TX1_A),
-        PINMUX_IPSR_DATA(IP8_13_11,     TX0_C),
+        PINMUX_IPSR_GPSR(IP8_13_11,     VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_GPSR(IP8_13_11,     DU1_DG5),
+        PINMUX_IPSR_GPSR(IP8_13_11,     TX1_A),
+        PINMUX_IPSR_GPSR(IP8_13_11,     TX0_C),
 
-        PINMUX_IPSR_DATA(IP8_15_14,     VI0_DATA4_VI0_B4),
-        PINMUX_IPSR_DATA(IP8_15_14,     DU1_DB2),
+        PINMUX_IPSR_GPSR(IP8_15_14,     VI0_DATA4_VI0_B4),
+        PINMUX_IPSR_GPSR(IP8_15_14,     DU1_DB2),
         PINMUX_IPSR_MSEL(IP8_15_14,     RX1_A,          SEL_SCIF1_A),
 
-        PINMUX_IPSR_DATA(IP8_18_16,     VI0_DATA5_VI0_B5),
-        PINMUX_IPSR_DATA(IP8_18_16,     DU1_DB3),
+        PINMUX_IPSR_GPSR(IP8_18_16,     VI0_DATA5_VI0_B5),
+        PINMUX_IPSR_GPSR(IP8_18_16,     DU1_DB3),
         PINMUX_IPSR_MSEL(IP8_18_16,     SCK1_A,         SEL_SCIF1_A),
-        PINMUX_IPSR_DATA(IP8_18_16,     PWM4),
+        PINMUX_IPSR_GPSR(IP8_18_16,     PWM4),
         PINMUX_IPSR_MSEL(IP8_18_16,     HSCK1_B,        SEL_HSCIF1_B),
 
-        PINMUX_IPSR_DATA(IP8_21_19,     VI0_DATA6_VI0_G0),
-        PINMUX_IPSR_DATA(IP8_21_19,     DU1_DB4),
+        PINMUX_IPSR_GPSR(IP8_21_19,     VI0_DATA6_VI0_G0),
+        PINMUX_IPSR_GPSR(IP8_21_19,     DU1_DB4),
         PINMUX_IPSR_MSEL(IP8_21_19,     CTS1_A,         SEL_SCIF1_A),
-        PINMUX_IPSR_DATA(IP8_21_19,     PWM5),
+        PINMUX_IPSR_GPSR(IP8_21_19,     PWM5),
 
-        PINMUX_IPSR_DATA(IP8_23_22,     VI0_DATA7_VI0_G1),
-        PINMUX_IPSR_DATA(IP8_23_22,     DU1_DB5),
+        PINMUX_IPSR_GPSR(IP8_23_22,     VI0_DATA7_VI0_G1),
+        PINMUX_IPSR_GPSR(IP8_23_22,     DU1_DB5),
         PINMUX_IPSR_MSEL(IP8_23_22,     RTS1_A,         SEL_SCIF1_A),
 
-        PINMUX_IPSR_DATA(IP8_26_24,     VI0_G2),
-        PINMUX_IPSR_DATA(IP8_26_24,     SD2_CLK_B),
-        PINMUX_IPSR_DATA(IP8_26_24,     VI1_DATA4),
-        PINMUX_IPSR_DATA(IP8_26_24,     DU1_DR4),
-        PINMUX_IPSR_DATA(IP8_26_24,     HTX1_B),
+        PINMUX_IPSR_GPSR(IP8_26_24,     VI0_G2),
+        PINMUX_IPSR_GPSR(IP8_26_24,     SD2_CLK_B),
+        PINMUX_IPSR_GPSR(IP8_26_24,     VI1_DATA4),
+        PINMUX_IPSR_GPSR(IP8_26_24,     DU1_DR4),
+        PINMUX_IPSR_GPSR(IP8_26_24,     HTX1_B),
 
-        PINMUX_IPSR_DATA(IP8_29_27,     VI0_G3),
+        PINMUX_IPSR_GPSR(IP8_29_27,     VI0_G3),
         PINMUX_IPSR_MSEL(IP8_29_27,     SD2_CMD_B,      SEL_SD2_B),
-        PINMUX_IPSR_DATA(IP8_29_27,     VI1_DATA5),
-        PINMUX_IPSR_DATA(IP8_29_27,     DU1_DR5),
+        PINMUX_IPSR_GPSR(IP8_29_27,     VI1_DATA5),
+        PINMUX_IPSR_GPSR(IP8_29_27,     DU1_DR5),
         PINMUX_IPSR_MSEL(IP8_29_27,     HRX1_B,         SEL_HSCIF1_B),
 
         /* IPSR9 */
-        PINMUX_IPSR_DATA(IP9_2_0,       VI0_G4),
+        PINMUX_IPSR_GPSR(IP9_2_0,       VI0_G4),
         PINMUX_IPSR_MSEL(IP9_2_0,       SD2_DAT0_B,     SEL_SD2_B),
-        PINMUX_IPSR_DATA(IP9_2_0,       VI1_DATA6),
-        PINMUX_IPSR_DATA(IP9_2_0,       DU1_DR6),
+        PINMUX_IPSR_GPSR(IP9_2_0,       VI1_DATA6),
+        PINMUX_IPSR_GPSR(IP9_2_0,       DU1_DR6),
         PINMUX_IPSR_MSEL(IP9_2_0,       HRTS1_B,        SEL_HSCIF1_B),
 
-        PINMUX_IPSR_DATA(IP9_5_3,       VI0_G5),
+        PINMUX_IPSR_GPSR(IP9_5_3,       VI0_G5),
         PINMUX_IPSR_MSEL(IP9_5_3,       SD2_DAT1_B,     SEL_SD2_B),
-        PINMUX_IPSR_DATA(IP9_5_3,       VI1_DATA7),
-        PINMUX_IPSR_DATA(IP9_5_3,       DU1_DR7),
+        PINMUX_IPSR_GPSR(IP9_5_3,       VI1_DATA7),
+        PINMUX_IPSR_GPSR(IP9_5_3,       DU1_DR7),
         PINMUX_IPSR_MSEL(IP9_5_3,       HCTS1_B,        SEL_HSCIF1_B),
 
         PINMUX_DATA(VI0_R0_A_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_A), /* see sel_vi0 */
         PINMUX_DATA(VI0_R0_C_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_C), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP9_8_6,       VI1_CLK),
-        PINMUX_IPSR_DATA(IP9_8_6,       ETH_REF_CLK),
-        PINMUX_IPSR_DATA(IP9_8_6,       DU1_DOTCLKIN),
+        PINMUX_IPSR_GPSR(IP9_8_6,       VI1_CLK),
+        PINMUX_IPSR_GPSR(IP9_8_6,       ETH_REF_CLK),
+        PINMUX_IPSR_GPSR(IP9_8_6,       DU1_DOTCLKIN),
 
         PINMUX_DATA(VI0_R1_A_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_A), /* see sel_vi0 */
         PINMUX_DATA(VI0_R1_C_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_C), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP9_11_9,      VI1_DATA8),
-        PINMUX_IPSR_DATA(IP9_11_9,      DU1_DB6),
-        PINMUX_IPSR_DATA(IP9_11_9,      ETH_TXD0),
-        PINMUX_IPSR_DATA(IP9_11_9,      PWM2),
-        PINMUX_IPSR_DATA(IP9_11_9,      TCLK1),
+        PINMUX_IPSR_GPSR(IP9_11_9,      VI1_DATA8),
+        PINMUX_IPSR_GPSR(IP9_11_9,      DU1_DB6),
+        PINMUX_IPSR_GPSR(IP9_11_9,      ETH_TXD0),
+        PINMUX_IPSR_GPSR(IP9_11_9,      PWM2),
+        PINMUX_IPSR_GPSR(IP9_11_9,      TCLK1),
 
         PINMUX_DATA(VI0_R2_A_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_A), /* see sel_vi0 */
         PINMUX_DATA(VI0_R2_C_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_C), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP9_14_12,     VI1_DATA9),
-        PINMUX_IPSR_DATA(IP9_14_12,     DU1_DB7),
-        PINMUX_IPSR_DATA(IP9_14_12,     ETH_TXD1),
-        PINMUX_IPSR_DATA(IP9_14_12,     PWM3),
+        PINMUX_IPSR_GPSR(IP9_14_12,     VI1_DATA9),
+        PINMUX_IPSR_GPSR(IP9_14_12,     DU1_DB7),
+        PINMUX_IPSR_GPSR(IP9_14_12,     ETH_TXD1),
+        PINMUX_IPSR_GPSR(IP9_14_12,     PWM3),
 
         PINMUX_IPSR_MSEL(IP9_17_15,     VI0_R3_A,       SEL_VI0_A),
-        PINMUX_IPSR_DATA(IP9_17_15,     ETH_CRS_DV),
-        PINMUX_IPSR_DATA(IP9_17_15,     IECLK),
+        PINMUX_IPSR_GPSR(IP9_17_15,     ETH_CRS_DV),
+        PINMUX_IPSR_GPSR(IP9_17_15,     IECLK),
         PINMUX_IPSR_MSEL(IP9_17_15,     SCK2_C,         SEL_SCIF2_C),
 
         PINMUX_DATA(VI0_R4_A_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_A), /* see sel_vi0 */
         PINMUX_DATA(VI0_R3_C_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_C), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP9_20_18,     ETH_TX_EN),
-        PINMUX_IPSR_DATA(IP9_20_18,     IETX),
-        PINMUX_IPSR_DATA(IP9_20_18,     TX2_C),
+        PINMUX_IPSR_GPSR(IP9_20_18,     ETH_TX_EN),
+        PINMUX_IPSR_GPSR(IP9_20_18,     IETX),
+        PINMUX_IPSR_GPSR(IP9_20_18,     TX2_C),
 
         PINMUX_DATA(VI0_R5_A_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_A), /* see sel_vi0 */
         PINMUX_DATA(VI0_R5_C_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_C), /* see sel_vi0 */
-        PINMUX_IPSR_DATA(IP9_23_21,     ETH_RX_ER),
+        PINMUX_IPSR_GPSR(IP9_23_21,     ETH_RX_ER),
         PINMUX_IPSR_MSEL(IP9_23_21,     FMCLK_C,        SEL_FM_C),
-        PINMUX_IPSR_DATA(IP9_23_21,     IERX),
+        PINMUX_IPSR_GPSR(IP9_23_21,     IERX),
         PINMUX_IPSR_MSEL(IP9_23_21,     RX2_C,          SEL_SCIF2_C),
 
         PINMUX_IPSR_MSEL(IP9_26_24,     VI1_DATA10_A,   SEL_VI1_A),
-        PINMUX_IPSR_DATA(IP9_26_24,     DU1_DOTCLKOUT),
-        PINMUX_IPSR_DATA(IP9_26_24,     ETH_RXD0),
-        PINMUX_IPSR_DATA(IP9_26_24,     BPFCLK_C),
-        PINMUX_IPSR_DATA(IP9_26_24,     TX2_D),
+        PINMUX_IPSR_GPSR(IP9_26_24,     DU1_DOTCLKOUT),
+        PINMUX_IPSR_GPSR(IP9_26_24,     ETH_RXD0),
+        PINMUX_IPSR_GPSR(IP9_26_24,     BPFCLK_C),
+        PINMUX_IPSR_GPSR(IP9_26_24,     TX2_D),
         PINMUX_IPSR_MSEL(IP9_26_24,     SDA2_C,         SEL_I2C2_C),
 
         PINMUX_IPSR_MSEL(IP9_29_27,     VI1_DATA11_A,   SEL_VI1_A),
-        PINMUX_IPSR_DATA(IP9_29_27,     DU1_EXHSYNC_DU1_HSYNC),
-        PINMUX_IPSR_DATA(IP9_29_27,     ETH_RXD1),
+        PINMUX_IPSR_GPSR(IP9_29_27,     DU1_EXHSYNC_DU1_HSYNC),
+        PINMUX_IPSR_GPSR(IP9_29_27,     ETH_RXD1),
         PINMUX_IPSR_MSEL(IP9_29_27,     FMIN_C,         SEL_FM_C),
         PINMUX_IPSR_MSEL(IP9_29_27,     RX2_D,          SEL_SCIF2_D),
         PINMUX_IPSR_MSEL(IP9_29_27,     SCL2_C,         SEL_I2C2_C),
 
         /* IPSR10 */
-        PINMUX_IPSR_DATA(IP10_2_0,      SD2_CLK_A),
-        PINMUX_IPSR_DATA(IP10_2_0,      DU1_EXVSYNC_DU1_VSYNC),
-        PINMUX_IPSR_DATA(IP10_2_0,      ATARD1),
-        PINMUX_IPSR_DATA(IP10_2_0,      ETH_MDC),
+        PINMUX_IPSR_GPSR(IP10_2_0,      SD2_CLK_A),
+        PINMUX_IPSR_GPSR(IP10_2_0,      DU1_EXVSYNC_DU1_VSYNC),
+        PINMUX_IPSR_GPSR(IP10_2_0,      ATARD1),
+        PINMUX_IPSR_GPSR(IP10_2_0,      ETH_MDC),
         PINMUX_IPSR_MSEL(IP10_2_0,      SDA1_B,         SEL_I2C1_B),
 
         PINMUX_IPSR_MSEL(IP10_5_3,      SD2_CMD_A,      SEL_SD2_A),
-        PINMUX_IPSR_DATA(IP10_5_3,      DU1_EXODDF_DU1_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP10_5_3,      ATAWR1),
-        PINMUX_IPSR_DATA(IP10_5_3,      ETH_MDIO),
+        PINMUX_IPSR_GPSR(IP10_5_3,      DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        PINMUX_IPSR_GPSR(IP10_5_3,      ATAWR1),
+        PINMUX_IPSR_GPSR(IP10_5_3,      ETH_MDIO),
         PINMUX_IPSR_MSEL(IP10_5_3,      SCL1_B,         SEL_I2C1_B),
 
         PINMUX_IPSR_MSEL(IP10_8_6,      SD2_DAT0_A,     SEL_SD2_A),
-        PINMUX_IPSR_DATA(IP10_8_6,      DU1_DISP),
-        PINMUX_IPSR_DATA(IP10_8_6,      ATACS01),
+        PINMUX_IPSR_GPSR(IP10_8_6,      DU1_DISP),
+        PINMUX_IPSR_GPSR(IP10_8_6,      ATACS01),
         PINMUX_IPSR_MSEL(IP10_8_6,      DREQ1_B,        SEL_DREQ1_B),
-        PINMUX_IPSR_DATA(IP10_8_6,      ETH_LINK),
+        PINMUX_IPSR_GPSR(IP10_8_6,      ETH_LINK),
         PINMUX_IPSR_MSEL(IP10_8_6,      CAN1_RX_A,      SEL_CAN1_A),
 
         PINMUX_IPSR_MSEL(IP10_12_9,     SD2_DAT1_A,     SEL_SD2_A),
-        PINMUX_IPSR_DATA(IP10_12_9,     DU1_CDE),
-        PINMUX_IPSR_DATA(IP10_12_9,     ATACS11),
-        PINMUX_IPSR_DATA(IP10_12_9,     DACK1_B),
-        PINMUX_IPSR_DATA(IP10_12_9,     ETH_MAGIC),
-        PINMUX_IPSR_DATA(IP10_12_9,     CAN1_TX_A),
-        PINMUX_IPSR_DATA(IP10_12_9,     PWM6),
+        PINMUX_IPSR_GPSR(IP10_12_9,     DU1_CDE),
+        PINMUX_IPSR_GPSR(IP10_12_9,     ATACS11),
+        PINMUX_IPSR_GPSR(IP10_12_9,     DACK1_B),
+        PINMUX_IPSR_GPSR(IP10_12_9,     ETH_MAGIC),
+        PINMUX_IPSR_GPSR(IP10_12_9,     CAN1_TX_A),
+        PINMUX_IPSR_GPSR(IP10_12_9,     PWM6),
 
         PINMUX_IPSR_MSEL(IP10_15_13,    SD2_DAT2_A,     SEL_SD2_A),
-        PINMUX_IPSR_DATA(IP10_15_13,    VI1_DATA12),
+        PINMUX_IPSR_GPSR(IP10_15_13,    VI1_DATA12),
         PINMUX_IPSR_MSEL(IP10_15_13,    DREQ2_B,        SEL_DREQ2_B),
-        PINMUX_IPSR_DATA(IP10_15_13,    ATADIR1),
+        PINMUX_IPSR_GPSR(IP10_15_13,    ATADIR1),
         PINMUX_IPSR_MSEL(IP10_15_13,    HSPI_CLK2_B,    SEL_HSPI2_B),
         PINMUX_IPSR_MSEL(IP10_15_13,    GPSCLK_B,       SEL_GPS_B),
 
         PINMUX_IPSR_MSEL(IP10_18_16,    SD2_DAT3_A,     SEL_SD2_A),
-        PINMUX_IPSR_DATA(IP10_18_16,    VI1_DATA13),
-        PINMUX_IPSR_DATA(IP10_18_16,    DACK2_B),
-        PINMUX_IPSR_DATA(IP10_18_16,    ATAG1),
+        PINMUX_IPSR_GPSR(IP10_18_16,    VI1_DATA13),
+        PINMUX_IPSR_GPSR(IP10_18_16,    DACK2_B),
+        PINMUX_IPSR_GPSR(IP10_18_16,    ATAG1),
         PINMUX_IPSR_MSEL(IP10_18_16,    HSPI_CS2_B,     SEL_HSPI2_B),
         PINMUX_IPSR_MSEL(IP10_18_16,    GPSIN_B,        SEL_GPS_B),
 
         PINMUX_IPSR_MSEL(IP10_21_19,    SD2_CD_A,       SEL_SD2_A),
-        PINMUX_IPSR_DATA(IP10_21_19,    VI1_DATA14),
+        PINMUX_IPSR_GPSR(IP10_21_19,    VI1_DATA14),
         PINMUX_IPSR_MSEL(IP10_21_19,    EX_WAIT1_B,     SEL_WAIT1_B),
         PINMUX_IPSR_MSEL(IP10_21_19,    DREQ0_B,        SEL_DREQ0_B),
         PINMUX_IPSR_MSEL(IP10_21_19,    HSPI_RX2_B,     SEL_HSPI2_B),
         PINMUX_IPSR_MSEL(IP10_21_19,    REMOCON_A,      SEL_REMOCON_A),
 
         PINMUX_IPSR_MSEL(IP10_24_22,    SD2_WP_A,       SEL_SD2_A),
-        PINMUX_IPSR_DATA(IP10_24_22,    VI1_DATA15),
+        PINMUX_IPSR_GPSR(IP10_24_22,    VI1_DATA15),
         PINMUX_IPSR_MSEL(IP10_24_22,    EX_WAIT2_B,     SEL_WAIT2_B),
-        PINMUX_IPSR_DATA(IP10_24_22,    DACK0_B),
-        PINMUX_IPSR_DATA(IP10_24_22,    HSPI_TX2_B),
+        PINMUX_IPSR_GPSR(IP10_24_22,    DACK0_B),
+        PINMUX_IPSR_GPSR(IP10_24_22,    HSPI_TX2_B),
         PINMUX_IPSR_MSEL(IP10_24_22,    CAN_CLK_C,      SEL_CANCLK_C),
 };
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index bd17eccb6a89..5bef934f823d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -611,577 +611,577 @@ static const u16 pinmux_data[] = {
         PINMUX_SINGLE(USB_PENC0),
         PINMUX_SINGLE(USB_PENC1),
 
-        PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
+        PINMUX_IPSR_GPSR(IP0_2_0, USB_PENC2),
         PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP0_2_0, PWM1),
+        PINMUX_IPSR_GPSR(IP0_2_0, PWM1),
         PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
         PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
         PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2),
-        PINMUX_IPSR_DATA(IP0_5_3, BS),
-        PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
-        PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
-        PINMUX_IPSR_DATA(IP0_5_3, FD2),
-        PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
-        PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
+        PINMUX_IPSR_GPSR(IP0_5_3, BS),
+        PINMUX_IPSR_GPSR(IP0_5_3, SD1_DAT2),
+        PINMUX_IPSR_GPSR(IP0_5_3, MMC0_D2),
+        PINMUX_IPSR_GPSR(IP0_5_3, FD2),
+        PINMUX_IPSR_GPSR(IP0_5_3, ATADIR0),
+        PINMUX_IPSR_GPSR(IP0_5_3, SDSELF),
         PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0),
-        PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
-        PINMUX_IPSR_DATA(IP0_7_6, A0),
-        PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
-        PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
-        PINMUX_IPSR_DATA(IP0_7_6, FD3),
-        PINMUX_IPSR_DATA(IP0_9_8, A20),
-        PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
-        PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
-        PINMUX_IPSR_DATA(IP0_11_10, A21),
+        PINMUX_IPSR_GPSR(IP0_5_3, TX4_C),
+        PINMUX_IPSR_GPSR(IP0_7_6, A0),
+        PINMUX_IPSR_GPSR(IP0_7_6, SD1_DAT3),
+        PINMUX_IPSR_GPSR(IP0_7_6, MMC0_D3),
+        PINMUX_IPSR_GPSR(IP0_7_6, FD3),
+        PINMUX_IPSR_GPSR(IP0_9_8, A20),
+        PINMUX_IPSR_GPSR(IP0_9_8, TX5_D),
+        PINMUX_IPSR_GPSR(IP0_9_8, HSPI_TX2_B),
+        PINMUX_IPSR_GPSR(IP0_11_10, A21),
         PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3),
         PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
-        PINMUX_IPSR_DATA(IP0_13_12, A22),
+        PINMUX_IPSR_GPSR(IP0_13_12, A22),
         PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3),
         PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
-        PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
-        PINMUX_IPSR_DATA(IP0_15_14, A23),
-        PINMUX_IPSR_DATA(IP0_15_14, FCLE),
+        PINMUX_IPSR_GPSR(IP0_13_12, VI1_R0),
+        PINMUX_IPSR_GPSR(IP0_15_14, A23),
+        PINMUX_IPSR_GPSR(IP0_15_14, FCLE),
         PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
-        PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
-        PINMUX_IPSR_DATA(IP0_18_16, A24),
-        PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
-        PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
-        PINMUX_IPSR_DATA(IP0_18_16, FD4),
+        PINMUX_IPSR_GPSR(IP0_15_14, VI1_R1),
+        PINMUX_IPSR_GPSR(IP0_18_16, A24),
+        PINMUX_IPSR_GPSR(IP0_18_16, SD1_CD),
+        PINMUX_IPSR_GPSR(IP0_18_16, MMC0_D4),
+        PINMUX_IPSR_GPSR(IP0_18_16, FD4),
         PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
-        PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
+        PINMUX_IPSR_GPSR(IP0_18_16, VI1_R2),
         PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
-        PINMUX_IPSR_DATA(IP0_22_19, A25),
-        PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
-        PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
-        PINMUX_IPSR_DATA(IP0_22_19, FD5),
+        PINMUX_IPSR_GPSR(IP0_22_19, A25),
+        PINMUX_IPSR_GPSR(IP0_22_19, SD1_WP),
+        PINMUX_IPSR_GPSR(IP0_22_19, MMC0_D5),
+        PINMUX_IPSR_GPSR(IP0_22_19, FD5),
         PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
-        PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
-        PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
+        PINMUX_IPSR_GPSR(IP0_22_19, VI1_R3),
+        PINMUX_IPSR_GPSR(IP0_22_19, TX5_B),
         PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
         PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
-        PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
-        PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
-        PINMUX_IPSR_DATA(IP0_25, CS0),
+        PINMUX_IPSR_GPSR(IP0_24_23, CLKOUT),
+        PINMUX_IPSR_GPSR(IP0_24_23, TX3C_IRDA_TX_C),
+        PINMUX_IPSR_GPSR(IP0_24_23, PWM0_B),
+        PINMUX_IPSR_GPSR(IP0_25, CS0),
         PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
-        PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
-        PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
-        PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
-        PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
-        PINMUX_IPSR_DATA(IP0_30_28, FWE),
-        PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
-        PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
+        PINMUX_IPSR_GPSR(IP0_27_26, CS1_A26),
+        PINMUX_IPSR_GPSR(IP0_27_26, HSPI_TX2),
+        PINMUX_IPSR_GPSR(IP0_27_26, SDSELF_B),
+        PINMUX_IPSR_GPSR(IP0_30_28, RD_WR),
+        PINMUX_IPSR_GPSR(IP0_30_28, FWE),
+        PINMUX_IPSR_GPSR(IP0_30_28, ATAG0),
+        PINMUX_IPSR_GPSR(IP0_30_28, VI1_R7),
         PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2),
 
-        PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
+        PINMUX_IPSR_GPSR(IP1_1_0, EX_CS0),
         PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
-        PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
-        PINMUX_IPSR_DATA(IP1_1_0, FD6),
-        PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
-        PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
-        PINMUX_IPSR_DATA(IP1_3_2, FD7),
-        PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
-        PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
-        PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
-        PINMUX_IPSR_DATA(IP1_6_4, FALE),
-        PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
-        PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
-        PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
-        PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
-        PINMUX_IPSR_DATA(IP1_10_7, FRE),
-        PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
-        PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
+        PINMUX_IPSR_GPSR(IP1_1_0, MMC0_D6),
+        PINMUX_IPSR_GPSR(IP1_1_0, FD6),
+        PINMUX_IPSR_GPSR(IP1_3_2, EX_CS1),
+        PINMUX_IPSR_GPSR(IP1_3_2, MMC0_D7),
+        PINMUX_IPSR_GPSR(IP1_3_2, FD7),
+        PINMUX_IPSR_GPSR(IP1_6_4, EX_CS2),
+        PINMUX_IPSR_GPSR(IP1_6_4, SD1_CLK),
+        PINMUX_IPSR_GPSR(IP1_6_4, MMC0_CLK),
+        PINMUX_IPSR_GPSR(IP1_6_4, FALE),
+        PINMUX_IPSR_GPSR(IP1_6_4, ATACS00),
+        PINMUX_IPSR_GPSR(IP1_10_7, EX_CS3),
+        PINMUX_IPSR_GPSR(IP1_10_7, SD1_CMD),
+        PINMUX_IPSR_GPSR(IP1_10_7, MMC0_CMD),
+        PINMUX_IPSR_GPSR(IP1_10_7, FRE),
+        PINMUX_IPSR_GPSR(IP1_10_7, ATACS10),
+        PINMUX_IPSR_GPSR(IP1_10_7, VI1_R4),
         PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1),
         PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
         PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
         PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
-        PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
-        PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
-        PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
-        PINMUX_IPSR_DATA(IP1_14_11, FD0),
-        PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
-        PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
+        PINMUX_IPSR_GPSR(IP1_14_11, EX_CS4),
+        PINMUX_IPSR_GPSR(IP1_14_11, SD1_DAT0),
+        PINMUX_IPSR_GPSR(IP1_14_11, MMC0_D0),
+        PINMUX_IPSR_GPSR(IP1_14_11, FD0),
+        PINMUX_IPSR_GPSR(IP1_14_11, ATARD0),
+        PINMUX_IPSR_GPSR(IP1_14_11, VI1_R5),
         PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1),
-        PINMUX_IPSR_DATA(IP1_14_11, HTX1),
-        PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
-        PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
+        PINMUX_IPSR_GPSR(IP1_14_11, HTX1),
+        PINMUX_IPSR_GPSR(IP1_14_11, TX2_E),
+        PINMUX_IPSR_GPSR(IP1_14_11, TX0_B),
         PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
-        PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
-        PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
-        PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
-        PINMUX_IPSR_DATA(IP1_18_15, FD1),
-        PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
-        PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
+        PINMUX_IPSR_GPSR(IP1_18_15, EX_CS5),
+        PINMUX_IPSR_GPSR(IP1_18_15, SD1_DAT1),
+        PINMUX_IPSR_GPSR(IP1_18_15, MMC0_D1),
+        PINMUX_IPSR_GPSR(IP1_18_15, FD1),
+        PINMUX_IPSR_GPSR(IP1_18_15, ATAWR0),
+        PINMUX_IPSR_GPSR(IP1_18_15, VI1_R6),
         PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4),
         PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1),
         PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0),
-        PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
-        PINMUX_IPSR_DATA(IP1_20_19, PWM2),
+        PINMUX_IPSR_GPSR(IP1_20_19, MLB_CLK),
+        PINMUX_IPSR_GPSR(IP1_20_19, PWM2),
         PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0),
-        PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
-        PINMUX_IPSR_DATA(IP1_22_21, PWM3),
-        PINMUX_IPSR_DATA(IP1_22_21, TX4),
-        PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
-        PINMUX_IPSR_DATA(IP1_24_23, PWM4),
+        PINMUX_IPSR_GPSR(IP1_22_21, MLB_SIG),
+        PINMUX_IPSR_GPSR(IP1_22_21, PWM3),
+        PINMUX_IPSR_GPSR(IP1_22_21, TX4),
+        PINMUX_IPSR_GPSR(IP1_24_23, MLB_DAT),
+        PINMUX_IPSR_GPSR(IP1_24_23, PWM4),
         PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0),
-        PINMUX_IPSR_DATA(IP1_28_25, HTX0),
-        PINMUX_IPSR_DATA(IP1_28_25, TX1),
-        PINMUX_IPSR_DATA(IP1_28_25, SDATA),
+        PINMUX_IPSR_GPSR(IP1_28_25, HTX0),
+        PINMUX_IPSR_GPSR(IP1_28_25, TX1),
+        PINMUX_IPSR_GPSR(IP1_28_25, SDATA),
         PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2),
-        PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
+        PINMUX_IPSR_GPSR(IP1_28_25, SUB_TCK),
+        PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE2),
+        PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE10),
+        PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE18),
+        PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE26),
+        PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE34),
 
         PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0),
         PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
+        PINMUX_IPSR_GPSR(IP2_3_0, SCKZ),
         PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
-        PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
+        PINMUX_IPSR_GPSR(IP2_3_0, SUB_TDI),
+        PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE3),
+        PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE11),
+        PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE19),
+        PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE27),
+        PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE35),
         PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0),
         PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_7_4, MTS),
-        PINMUX_IPSR_DATA(IP2_7_4, PWM5),
+        PINMUX_IPSR_GPSR(IP2_7_4, MTS),
+        PINMUX_IPSR_GPSR(IP2_7_4, PWM5),
         PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2),
         PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
-        PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
+        PINMUX_IPSR_GPSR(IP2_7_4, SUB_TDO),
+        PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE0),
+        PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE8),
+        PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE16),
+        PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE24),
+        PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE32),
         PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0),
         PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_11_8, STM),
-        PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
+        PINMUX_IPSR_GPSR(IP2_11_8, STM),
+        PINMUX_IPSR_GPSR(IP2_11_8, PWM0_D),
         PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2),
         PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
-        PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
+        PINMUX_IPSR_GPSR(IP2_11_8, SUB_TRST),
         PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1),
-        PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
+        PINMUX_IPSR_GPSR(IP2_11_8, CC5_OSCOUT),
         PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0),
         PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_15_12, MDATA),
-        PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
-        PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
-        PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
-        PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
+        PINMUX_IPSR_GPSR(IP2_15_12, MDATA),
+        PINMUX_IPSR_GPSR(IP2_15_12, TX0_C),
+        PINMUX_IPSR_GPSR(IP2_15_12, SUB_TMS),
+        PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE1),
+        PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE9),
+        PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE17),
+        PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE25),
+        PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE33),
+        PINMUX_IPSR_GPSR(IP2_18_16, DU0_DR0),
+        PINMUX_IPSR_GPSR(IP2_18_16, LCDOUT0),
         PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0),
         PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
-        PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
-        PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
-        PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
-        PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
-        PINMUX_IPSR_DATA(IP2_21_19, DACK0),
-        PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
+        PINMUX_IPSR_GPSR(IP2_18_16, AUDATA0),
+        PINMUX_IPSR_GPSR(IP2_18_16, TX5_C),
+        PINMUX_IPSR_GPSR(IP2_21_19, DU0_DR1),
+        PINMUX_IPSR_GPSR(IP2_21_19, LCDOUT1),
+        PINMUX_IPSR_GPSR(IP2_21_19, DACK0),
+        PINMUX_IPSR_GPSR(IP2_21_19, DRACK0),
         PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
-        PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
+        PINMUX_IPSR_GPSR(IP2_21_19, AUDATA1),
         PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2),
-        PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
-        PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
-        PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
-        PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
-        PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
-        PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
-        PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
-        PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
-        PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
-        PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
-        PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
-        PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
-        PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
-        PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
+        PINMUX_IPSR_GPSR(IP2_22, DU0_DR2),
+        PINMUX_IPSR_GPSR(IP2_22, LCDOUT2),
+        PINMUX_IPSR_GPSR(IP2_23, DU0_DR3),
+        PINMUX_IPSR_GPSR(IP2_23, LCDOUT3),
+        PINMUX_IPSR_GPSR(IP2_24, DU0_DR4),
+        PINMUX_IPSR_GPSR(IP2_24, LCDOUT4),
+        PINMUX_IPSR_GPSR(IP2_25, DU0_DR5),
+        PINMUX_IPSR_GPSR(IP2_25, LCDOUT5),
+        PINMUX_IPSR_GPSR(IP2_26, DU0_DR6),
+        PINMUX_IPSR_GPSR(IP2_26, LCDOUT6),
+        PINMUX_IPSR_GPSR(IP2_27, DU0_DR7),
+        PINMUX_IPSR_GPSR(IP2_27, LCDOUT7),
+        PINMUX_IPSR_GPSR(IP2_30_28, DU0_DG0),
+        PINMUX_IPSR_GPSR(IP2_30_28, LCDOUT8),
         PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0),
         PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0),
-        PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
+        PINMUX_IPSR_GPSR(IP2_30_28, AUDATA2),
 
-        PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
-        PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
-        PINMUX_IPSR_DATA(IP3_2_0, DACK1),
+        PINMUX_IPSR_GPSR(IP3_2_0, DU0_DG1),
+        PINMUX_IPSR_GPSR(IP3_2_0, LCDOUT9),
+        PINMUX_IPSR_GPSR(IP3_2_0, DACK1),
         PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0),
-        PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
-        PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
-        PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
-        PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
-        PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
-        PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
-        PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
-        PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
-        PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
-        PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
-        PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
-        PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
-        PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
-        PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
-        PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
-        PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
+        PINMUX_IPSR_GPSR(IP3_2_0, AUDATA3),
+        PINMUX_IPSR_GPSR(IP3_3, DU0_DG2),
+        PINMUX_IPSR_GPSR(IP3_3, LCDOUT10),
+        PINMUX_IPSR_GPSR(IP3_4, DU0_DG3),
+        PINMUX_IPSR_GPSR(IP3_4, LCDOUT11),
+        PINMUX_IPSR_GPSR(IP3_5, DU0_DG4),
+        PINMUX_IPSR_GPSR(IP3_5, LCDOUT12),
+        PINMUX_IPSR_GPSR(IP3_6, DU0_DG5),
+        PINMUX_IPSR_GPSR(IP3_6, LCDOUT13),
+        PINMUX_IPSR_GPSR(IP3_7, DU0_DG6),
+        PINMUX_IPSR_GPSR(IP3_7, LCDOUT14),
+        PINMUX_IPSR_GPSR(IP3_8, DU0_DG7),
+        PINMUX_IPSR_GPSR(IP3_8, LCDOUT15),
+        PINMUX_IPSR_GPSR(IP3_11_9, DU0_DB0),
+        PINMUX_IPSR_GPSR(IP3_11_9, LCDOUT16),
+        PINMUX_IPSR_GPSR(IP3_11_9, EX_WAIT1),
         PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0),
         PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0),
-        PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
-        PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
-        PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
-        PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
+        PINMUX_IPSR_GPSR(IP3_11_9, AUDATA4),
+        PINMUX_IPSR_GPSR(IP3_14_12, DU0_DB1),
+        PINMUX_IPSR_GPSR(IP3_14_12, LCDOUT17),
+        PINMUX_IPSR_GPSR(IP3_14_12, EX_WAIT2),
         PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0),
         PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
-        PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
+        PINMUX_IPSR_GPSR(IP3_14_12, AUDATA5),
         PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2),
-        PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
-        PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
-        PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
-        PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
-        PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
-        PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
-        PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
-        PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
-        PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
-        PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
-        PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
-        PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
-        PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
-        PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
-        PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
+        PINMUX_IPSR_GPSR(IP3_15, DU0_DB2),
+        PINMUX_IPSR_GPSR(IP3_15, LCDOUT18),
+        PINMUX_IPSR_GPSR(IP3_16, DU0_DB3),
+        PINMUX_IPSR_GPSR(IP3_16, LCDOUT19),
+        PINMUX_IPSR_GPSR(IP3_17, DU0_DB4),
+        PINMUX_IPSR_GPSR(IP3_17, LCDOUT20),
+        PINMUX_IPSR_GPSR(IP3_18, DU0_DB5),
+        PINMUX_IPSR_GPSR(IP3_18, LCDOUT21),
+        PINMUX_IPSR_GPSR(IP3_19, DU0_DB6),
+        PINMUX_IPSR_GPSR(IP3_19, LCDOUT22),
+        PINMUX_IPSR_GPSR(IP3_20, DU0_DB7),
+        PINMUX_IPSR_GPSR(IP3_20, LCDOUT23),
+        PINMUX_IPSR_GPSR(IP3_22_21, DU0_DOTCLKIN),
+        PINMUX_IPSR_GPSR(IP3_22_21, QSTVA_QVS),
+        PINMUX_IPSR_GPSR(IP3_22_21, TX3_D_IRDA_TX_D),
         PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1),
-        PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
-        PINMUX_IPSR_DATA(IP3_23, QCLK),
-        PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
-        PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
+        PINMUX_IPSR_GPSR(IP3_23, DU0_DOTCLKOUT0),
+        PINMUX_IPSR_GPSR(IP3_23, QCLK),
+        PINMUX_IPSR_GPSR(IP3_26_24, DU0_DOTCLKOUT1),
+        PINMUX_IPSR_GPSR(IP3_26_24, QSTVB_QVE),
         PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
         PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1),
         PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2),
-        PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
-        PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
-        PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
-        PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
-        PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
-        PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
-        PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
-        PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
-        PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
+        PINMUX_IPSR_GPSR(IP3_26_24, DACK0_B),
+        PINMUX_IPSR_GPSR(IP3_26_24, DRACK0_B),
+        PINMUX_IPSR_GPSR(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
+        PINMUX_IPSR_GPSR(IP3_27, QSTH_QHS),
+        PINMUX_IPSR_GPSR(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
+        PINMUX_IPSR_GPSR(IP3_28, QSTB_QHE),
+        PINMUX_IPSR_GPSR(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+        PINMUX_IPSR_GPSR(IP3_31_29, QCPV_QDE),
+        PINMUX_IPSR_GPSR(IP3_31_29, CAN1_TX),
+        PINMUX_IPSR_GPSR(IP3_31_29, TX2_C),
         PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2),
-        PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
+        PINMUX_IPSR_GPSR(IP3_31_29, REMOCON),
 
-        PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
-        PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
+        PINMUX_IPSR_GPSR(IP4_1_0, DU0_DISP),
+        PINMUX_IPSR_GPSR(IP4_1_0, QPOLA),
         PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
         PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2),
-        PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
-        PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
-        PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
+        PINMUX_IPSR_GPSR(IP4_4_2, DU0_CDE),
+        PINMUX_IPSR_GPSR(IP4_4_2, QPOLB),
+        PINMUX_IPSR_GPSR(IP4_4_2, CAN1_RX),
         PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2),
         PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
         PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
         PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
-        PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
-        PINMUX_IPSR_DATA(IP4_7_5, PWM6),
-        PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
-        PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
-        PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
+        PINMUX_IPSR_GPSR(IP4_7_5, DU1_DR0),
+        PINMUX_IPSR_GPSR(IP4_7_5, VI2_DATA0_VI2_B0),
+        PINMUX_IPSR_GPSR(IP4_7_5, PWM6),
+        PINMUX_IPSR_GPSR(IP4_7_5, SD3_CLK),
+        PINMUX_IPSR_GPSR(IP4_7_5, TX3_E_IRDA_TX_E),
+        PINMUX_IPSR_GPSR(IP4_7_5, AUDCK),
         PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
-        PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
-        PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
-        PINMUX_IPSR_DATA(IP4_10_8, PWM0),
-        PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
+        PINMUX_IPSR_GPSR(IP4_10_8, DU1_DR1),
+        PINMUX_IPSR_GPSR(IP4_10_8, VI2_DATA1_VI2_B1),
+        PINMUX_IPSR_GPSR(IP4_10_8, PWM0),
+        PINMUX_IPSR_GPSR(IP4_10_8, SD3_CMD),
         PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
-        PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
+        PINMUX_IPSR_GPSR(IP4_10_8, AUDSYNC),
         PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
-        PINMUX_IPSR_DATA(IP4_11, VI2_G0),
-        PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
-        PINMUX_IPSR_DATA(IP4_12, VI2_G1),
-        PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
-        PINMUX_IPSR_DATA(IP4_13, VI2_G2),
-        PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
-        PINMUX_IPSR_DATA(IP4_14, VI2_G3),
-        PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
-        PINMUX_IPSR_DATA(IP4_15, VI2_G4),
-        PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
-        PINMUX_IPSR_DATA(IP4_16, VI2_G5),
-        PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
-        PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
+        PINMUX_IPSR_GPSR(IP4_11, DU1_DR2),
+        PINMUX_IPSR_GPSR(IP4_11, VI2_G0),
+        PINMUX_IPSR_GPSR(IP4_12, DU1_DR3),
+        PINMUX_IPSR_GPSR(IP4_12, VI2_G1),
+        PINMUX_IPSR_GPSR(IP4_13, DU1_DR4),
+        PINMUX_IPSR_GPSR(IP4_13, VI2_G2),
+        PINMUX_IPSR_GPSR(IP4_14, DU1_DR5),
+        PINMUX_IPSR_GPSR(IP4_14, VI2_G3),
+        PINMUX_IPSR_GPSR(IP4_15, DU1_DR6),
+        PINMUX_IPSR_GPSR(IP4_15, VI2_G4),
+        PINMUX_IPSR_GPSR(IP4_16, DU1_DR7),
+        PINMUX_IPSR_GPSR(IP4_16, VI2_G5),
+        PINMUX_IPSR_GPSR(IP4_19_17, DU1_DG0),
+        PINMUX_IPSR_GPSR(IP4_19_17, VI2_DATA2_VI2_B2),
         PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1),
-        PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
+        PINMUX_IPSR_GPSR(IP4_19_17, SD3_DAT2),
         PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4),
-        PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
-        PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
-        PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
-        PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
+        PINMUX_IPSR_GPSR(IP4_19_17, AUDATA6),
+        PINMUX_IPSR_GPSR(IP4_19_17, TX0_D),
+        PINMUX_IPSR_GPSR(IP4_22_20, DU1_DG1),
+        PINMUX_IPSR_GPSR(IP4_22_20, VI2_DATA3_VI2_B3),
         PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1),
-        PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
+        PINMUX_IPSR_GPSR(IP4_22_20, SD3_DAT3),
         PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0),
-        PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
+        PINMUX_IPSR_GPSR(IP4_22_20, AUDATA7),
         PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
-        PINMUX_IPSR_DATA(IP4_23, VI2_G6),
-        PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
-        PINMUX_IPSR_DATA(IP4_24, VI2_G7),
-        PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
-        PINMUX_IPSR_DATA(IP4_25, VI2_R0),
-        PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
-        PINMUX_IPSR_DATA(IP4_26, VI2_R1),
-        PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
-        PINMUX_IPSR_DATA(IP4_27, VI2_R2),
-        PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
-        PINMUX_IPSR_DATA(IP4_28, VI2_R3),
-        PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
-        PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
+        PINMUX_IPSR_GPSR(IP4_23, DU1_DG2),
+        PINMUX_IPSR_GPSR(IP4_23, VI2_G6),
+        PINMUX_IPSR_GPSR(IP4_24, DU1_DG3),
+        PINMUX_IPSR_GPSR(IP4_24, VI2_G7),
+        PINMUX_IPSR_GPSR(IP4_25, DU1_DG4),
+        PINMUX_IPSR_GPSR(IP4_25, VI2_R0),
+        PINMUX_IPSR_GPSR(IP4_26, DU1_DG5),
+        PINMUX_IPSR_GPSR(IP4_26, VI2_R1),
+        PINMUX_IPSR_GPSR(IP4_27, DU1_DG6),
+        PINMUX_IPSR_GPSR(IP4_27, VI2_R2),
+        PINMUX_IPSR_GPSR(IP4_28, DU1_DG7),
+        PINMUX_IPSR_GPSR(IP4_28, VI2_R3),
+        PINMUX_IPSR_GPSR(IP4_31_29, DU1_DB0),
+        PINMUX_IPSR_GPSR(IP4_31_29, VI2_DATA4_VI2_B4),
         PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1),
-        PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
-        PINMUX_IPSR_DATA(IP4_31_29, TX5),
+        PINMUX_IPSR_GPSR(IP4_31_29, SD3_DAT0),
+        PINMUX_IPSR_GPSR(IP4_31_29, TX5),
         PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3),
 
-        PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
-        PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
+        PINMUX_IPSR_GPSR(IP5_2_0, DU1_DB1),
+        PINMUX_IPSR_GPSR(IP5_2_0, VI2_DATA5_VI2_B5),
         PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1),
-        PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
+        PINMUX_IPSR_GPSR(IP5_2_0, SD3_DAT1),
         PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0),
         PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
-        PINMUX_IPSR_DATA(IP5_3, VI2_R4),
-        PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
-        PINMUX_IPSR_DATA(IP5_4, VI2_R5),
-        PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
-        PINMUX_IPSR_DATA(IP5_5, VI2_R6),
-        PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
-        PINMUX_IPSR_DATA(IP5_6, VI2_R7),
-        PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
+        PINMUX_IPSR_GPSR(IP5_3, DU1_DB2),
+        PINMUX_IPSR_GPSR(IP5_3, VI2_R4),
+        PINMUX_IPSR_GPSR(IP5_4, DU1_DB3),
+        PINMUX_IPSR_GPSR(IP5_4, VI2_R5),
+        PINMUX_IPSR_GPSR(IP5_5, DU1_DB4),
+        PINMUX_IPSR_GPSR(IP5_5, VI2_R6),
+        PINMUX_IPSR_GPSR(IP5_6, DU1_DB5),
+        PINMUX_IPSR_GPSR(IP5_6, VI2_R7),
+        PINMUX_IPSR_GPSR(IP5_7, DU1_DB6),
         PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3),
-        PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
+        PINMUX_IPSR_GPSR(IP5_8, DU1_DB7),
         PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3),
-        PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
-        PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
+        PINMUX_IPSR_GPSR(IP5_10_9, DU1_DOTCLKIN),
+        PINMUX_IPSR_GPSR(IP5_10_9, VI2_CLKENB),
         PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
         PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3),
-        PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
-        PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
+        PINMUX_IPSR_GPSR(IP5_12_11, DU1_DOTCLKOUT),
+        PINMUX_IPSR_GPSR(IP5_12_11, VI2_FIELD),
         PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3),
-        PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
-        PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
-        PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
-        PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
-        PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
-        PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
-        PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
-        PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
-        PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
-        PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
-        PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
-        PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
-        PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
-        PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
-        PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
+        PINMUX_IPSR_GPSR(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
+        PINMUX_IPSR_GPSR(IP5_14_13, VI2_HSYNC),
+        PINMUX_IPSR_GPSR(IP5_14_13, VI3_HSYNC),
+        PINMUX_IPSR_GPSR(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
+        PINMUX_IPSR_GPSR(IP5_16_15, VI2_VSYNC),
+        PINMUX_IPSR_GPSR(IP5_16_15, VI3_VSYNC),
+        PINMUX_IPSR_GPSR(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        PINMUX_IPSR_GPSR(IP5_20_17, VI2_CLK),
+        PINMUX_IPSR_GPSR(IP5_20_17, TX3_B_IRDA_TX_B),
+        PINMUX_IPSR_GPSR(IP5_20_17, SD3_CD),
+        PINMUX_IPSR_GPSR(IP5_20_17, HSPI_TX1),
+        PINMUX_IPSR_GPSR(IP5_20_17, VI1_CLKENB),
+        PINMUX_IPSR_GPSR(IP5_20_17, VI3_CLKENB),
+        PINMUX_IPSR_GPSR(IP5_20_17, AUDIO_CLKC),
+        PINMUX_IPSR_GPSR(IP5_20_17, TX2_D),
+        PINMUX_IPSR_GPSR(IP5_20_17, SPEEDIN),
         PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
-        PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
+        PINMUX_IPSR_GPSR(IP5_23_21, DU1_DISP),
+        PINMUX_IPSR_GPSR(IP5_23_21, VI2_DATA6_VI2_B6),
         PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0),
-        PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
+        PINMUX_IPSR_GPSR(IP5_23_21, QSTVA_B_QVS_B),
         PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
         PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3),
-        PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
+        PINMUX_IPSR_GPSR(IP5_23_21, AUDIO_CLKOUT_B),
         PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
-        PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
+        PINMUX_IPSR_GPSR(IP5_27_24, DU1_CDE),
+        PINMUX_IPSR_GPSR(IP5_27_24, VI2_DATA7_VI2_B7),
         PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
-        PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
+        PINMUX_IPSR_GPSR(IP5_27_24, SD3_WP),
         PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
-        PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
-        PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
-        PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
+        PINMUX_IPSR_GPSR(IP5_27_24, VI1_FIELD),
+        PINMUX_IPSR_GPSR(IP5_27_24, VI3_FIELD),
+        PINMUX_IPSR_GPSR(IP5_27_24, AUDIO_CLKOUT),
         PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
         PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
-        PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
-        PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
-        PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
-        PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
-        PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
-
-        PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
-        PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
-        PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
-        PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
-        PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
-        PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
-        PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
-        PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
-        PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
-        PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
-        PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
-        PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
-        PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
-        PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
-        PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
-        PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
-        PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
+        PINMUX_IPSR_GPSR(IP5_28, AUDIO_CLKA),
+        PINMUX_IPSR_GPSR(IP5_28, CAN_TXCLK),
+        PINMUX_IPSR_GPSR(IP5_30_29, AUDIO_CLKB),
+        PINMUX_IPSR_GPSR(IP5_30_29, USB_OVC2),
+        PINMUX_IPSR_GPSR(IP5_30_29, CAN_DEBUGOUT0),
+        PINMUX_IPSR_GPSR(IP5_30_29, MOUT0),
+
+        PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK0129),
+        PINMUX_IPSR_GPSR(IP6_1_0, CAN_DEBUGOUT1),
+        PINMUX_IPSR_GPSR(IP6_1_0, MOUT1),
+        PINMUX_IPSR_GPSR(IP6_3_2, SSI_WS0129),
+        PINMUX_IPSR_GPSR(IP6_3_2, CAN_DEBUGOUT2),
+        PINMUX_IPSR_GPSR(IP6_3_2, MOUT2),
+        PINMUX_IPSR_GPSR(IP6_5_4, SSI_SDATA0),
+        PINMUX_IPSR_GPSR(IP6_5_4, CAN_DEBUGOUT3),
+        PINMUX_IPSR_GPSR(IP6_5_4, MOUT5),
+        PINMUX_IPSR_GPSR(IP6_7_6, SSI_SDATA1),
+        PINMUX_IPSR_GPSR(IP6_7_6, CAN_DEBUGOUT4),
+        PINMUX_IPSR_GPSR(IP6_7_6, MOUT6),
+        PINMUX_IPSR_GPSR(IP6_8, SSI_SDATA2),
+        PINMUX_IPSR_GPSR(IP6_8, CAN_DEBUGOUT5),
+        PINMUX_IPSR_GPSR(IP6_11_9, SSI_SCK34),
+        PINMUX_IPSR_GPSR(IP6_11_9, CAN_DEBUGOUT6),
+        PINMUX_IPSR_GPSR(IP6_11_9, CAN0_TX_B),
         PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0),
         PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
-        PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
-        PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
+        PINMUX_IPSR_GPSR(IP6_14_12, SSI_WS34),
+        PINMUX_IPSR_GPSR(IP6_14_12, CAN_DEBUGOUT7),
         PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
-        PINMUX_IPSR_DATA(IP6_14_12, IETX),
+        PINMUX_IPSR_GPSR(IP6_14_12, IETX),
         PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
-        PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
-        PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
-        PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
+        PINMUX_IPSR_GPSR(IP6_17_15, SSI_SDATA3),
+        PINMUX_IPSR_GPSR(IP6_17_15, PWM0_C),
+        PINMUX_IPSR_GPSR(IP6_17_15, CAN_DEBUGOUT8),
         PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
         PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0),
         PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
         PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1),
-        PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
-        PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
+        PINMUX_IPSR_GPSR(IP6_19_18, SSI_SDATA4),
+        PINMUX_IPSR_GPSR(IP6_19_18, CAN_DEBUGOUT9),
         PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
-        PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
-        PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
-        PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
+        PINMUX_IPSR_GPSR(IP6_22_20, SSI_SCK5),
+        PINMUX_IPSR_GPSR(IP6_22_20, ADICLK),
+        PINMUX_IPSR_GPSR(IP6_22_20, CAN_DEBUGOUT10),
         PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0),
         PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3),
-        PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
+        PINMUX_IPSR_GPSR(IP6_24_23, SSI_WS5),
         PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
-        PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
-        PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
-        PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
+        PINMUX_IPSR_GPSR(IP6_24_23, CAN_DEBUGOUT11),
+        PINMUX_IPSR_GPSR(IP6_24_23, TX3_IRDA_TX),
+        PINMUX_IPSR_GPSR(IP6_26_25, SSI_SDATA5),
         PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0),
-        PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
+        PINMUX_IPSR_GPSR(IP6_26_25, CAN_DEBUGOUT12),
         PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
-        PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
-        PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
-        PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
+        PINMUX_IPSR_GPSR(IP6_30_29, SSI_SCK6),
+        PINMUX_IPSR_GPSR(IP6_30_29, ADICHS0),
+        PINMUX_IPSR_GPSR(IP6_30_29, CAN0_TX),
         PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1),
 
-        PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
-        PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
+        PINMUX_IPSR_GPSR(IP7_1_0, SSI_WS6),
+        PINMUX_IPSR_GPSR(IP7_1_0, ADICHS1),
         PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0),
-        PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
-        PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
-        PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
+        PINMUX_IPSR_GPSR(IP7_1_0, IETX_B),
+        PINMUX_IPSR_GPSR(IP7_3_2, SSI_SDATA6),
+        PINMUX_IPSR_GPSR(IP7_3_2, ADICHS2),
         PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
         PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1),
         PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
-        PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
+        PINMUX_IPSR_GPSR(IP7_6_4, CAN_DEBUGOUT13),
         PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1),
         PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
         PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
         PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0),
-        PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
+        PINMUX_IPSR_GPSR(IP7_9_7, CAN_DEBUGOUT14),
         PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1),
         PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
         PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
         PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
-        PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
+        PINMUX_IPSR_GPSR(IP7_12_10, CAN_DEBUGOUT15),
         PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1),
         PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2),
-        PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
+        PINMUX_IPSR_GPSR(IP7_12_10, HSPI_TX1_C),
         PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
-        PINMUX_IPSR_DATA(IP7_14_13, VSP),
+        PINMUX_IPSR_GPSR(IP7_14_13, VSP),
         PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1),
         PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
-        PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
-        PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
+        PINMUX_IPSR_GPSR(IP7_16_15, SD0_CLK),
+        PINMUX_IPSR_GPSR(IP7_16_15, ATACS01),
         PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
-        PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
-        PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
-        PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
-        PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
-        PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
+        PINMUX_IPSR_GPSR(IP7_18_17, SD0_CMD),
+        PINMUX_IPSR_GPSR(IP7_18_17, ATACS11),
+        PINMUX_IPSR_GPSR(IP7_18_17, TX1_B),
+        PINMUX_IPSR_GPSR(IP7_18_17, CC5_TDO),
+        PINMUX_IPSR_GPSR(IP7_20_19, SD0_DAT0),
+        PINMUX_IPSR_GPSR(IP7_20_19, ATADIR1),
         PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
-        PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
-        PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
+        PINMUX_IPSR_GPSR(IP7_20_19, CC5_TRST),
+        PINMUX_IPSR_GPSR(IP7_22_21, SD0_DAT1),
+        PINMUX_IPSR_GPSR(IP7_22_21, ATAG1),
         PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1),
-        PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
-        PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
-        PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
-        PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
-        PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
-        PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
-        PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
+        PINMUX_IPSR_GPSR(IP7_22_21, CC5_TMS),
+        PINMUX_IPSR_GPSR(IP7_24_23, SD0_DAT2),
+        PINMUX_IPSR_GPSR(IP7_24_23, ATARD1),
+        PINMUX_IPSR_GPSR(IP7_24_23, TX2_B),
+        PINMUX_IPSR_GPSR(IP7_24_23, CC5_TCK),
+        PINMUX_IPSR_GPSR(IP7_26_25, SD0_DAT3),
+        PINMUX_IPSR_GPSR(IP7_26_25, ATAWR1),
         PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1),
-        PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
-        PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
+        PINMUX_IPSR_GPSR(IP7_26_25, CC5_TDI),
+        PINMUX_IPSR_GPSR(IP7_28_27, SD0_CD),
         PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0),
         PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
-        PINMUX_IPSR_DATA(IP7_30_29, DACK2),
+        PINMUX_IPSR_GPSR(IP7_30_29, SD0_WP),
+        PINMUX_IPSR_GPSR(IP7_30_29, DACK2),
         PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1),
 
-        PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
+        PINMUX_IPSR_GPSR(IP8_3_0, HSPI_CLK0),
         PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
-        PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
-        PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
+        PINMUX_IPSR_GPSR(IP8_3_0, USB_OVC0),
+        PINMUX_IPSR_GPSR(IP8_3_0, AD_CLK),
+        PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE4),
+        PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE12),
+        PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE20),
+        PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE28),
+        PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE36),
+        PINMUX_IPSR_GPSR(IP8_7_4, HSPI_CS0),
         PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
-        PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
-        PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
-        PINMUX_IPSR_DATA(IP8_11_8, TX0),
-        PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
-        PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
-        PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
+        PINMUX_IPSR_GPSR(IP8_7_4, USB_OVC1),
+        PINMUX_IPSR_GPSR(IP8_7_4, AD_DI),
+        PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE5),
+        PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE13),
+        PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE21),
+        PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE29),
+        PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE37),
+        PINMUX_IPSR_GPSR(IP8_11_8, HSPI_TX0),
+        PINMUX_IPSR_GPSR(IP8_11_8, TX0),
+        PINMUX_IPSR_GPSR(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
+        PINMUX_IPSR_GPSR(IP8_11_8, AD_DO),
+        PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE6),
+        PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE14),
+        PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE22),
+        PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE30),
+        PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE38),
+        PINMUX_IPSR_GPSR(IP8_15_12, HSPI_RX0),
         PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
-        PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
-        PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
-        PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
-        PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
-        PINMUX_IPSR_DATA(IP8_18, BPFCLK),
-        PINMUX_IPSR_DATA(IP8_18, PCMWE),
-        PINMUX_IPSR_DATA(IP8_19, FMIN),
-        PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
-        PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
-        PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
-        PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
-        PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
-        PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
-        PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
-        PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
+        PINMUX_IPSR_GPSR(IP8_15_12, CAN_STEP0),
+        PINMUX_IPSR_GPSR(IP8_15_12, AD_NCS),
+        PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE7),
+        PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE15),
+        PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE23),
+        PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE31),
+        PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE39),
+        PINMUX_IPSR_GPSR(IP8_17_16, FMCLK),
+        PINMUX_IPSR_GPSR(IP8_17_16, RDS_CLK),
+        PINMUX_IPSR_GPSR(IP8_17_16, PCMOE),
+        PINMUX_IPSR_GPSR(IP8_18, BPFCLK),
+        PINMUX_IPSR_GPSR(IP8_18, PCMWE),
+        PINMUX_IPSR_GPSR(IP8_19, FMIN),
+        PINMUX_IPSR_GPSR(IP8_19, RDS_DATA),
+        PINMUX_IPSR_GPSR(IP8_20, VI0_CLK),
+        PINMUX_IPSR_GPSR(IP8_20, MMC1_CLK),
+        PINMUX_IPSR_GPSR(IP8_22_21, VI0_CLKENB),
+        PINMUX_IPSR_GPSR(IP8_22_21, TX1_C),
+        PINMUX_IPSR_GPSR(IP8_22_21, HTX1_B),
+        PINMUX_IPSR_GPSR(IP8_22_21, MT1_SYNC),
+        PINMUX_IPSR_GPSR(IP8_24_23, VI0_FIELD),
         PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
+        PINMUX_IPSR_GPSR(IP8_27_25, VI0_HSYNC),
         PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2),
-        PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
-        PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
+        PINMUX_IPSR_GPSR(IP8_27_25, TX4_D),
+        PINMUX_IPSR_GPSR(IP8_27_25, MMC1_CMD),
         PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
+        PINMUX_IPSR_GPSR(IP8_30_28, VI0_VSYNC),
         PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3),
@@ -1189,216 +1189,216 @@ static const u16 pinmux_data[] = {
 
         PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
+        PINMUX_IPSR_GPSR(IP9_1_0, MT1_VCXO),
         PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
-        PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
-        PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
-        PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
-        PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
-        PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
-        PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
-        PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
-        PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
-        PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
-        PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
-        PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
-        PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
-        PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
-        PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
-        PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
+        PINMUX_IPSR_GPSR(IP9_3_2, MT1_PWM),
+        PINMUX_IPSR_GPSR(IP9_4, VI0_DATA2_VI0_B2),
+        PINMUX_IPSR_GPSR(IP9_4, MMC1_D0),
+        PINMUX_IPSR_GPSR(IP9_5, VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_GPSR(IP9_5, MMC1_D1),
+        PINMUX_IPSR_GPSR(IP9_6, VI0_DATA4_VI0_B4),
+        PINMUX_IPSR_GPSR(IP9_6, MMC1_D2),
+        PINMUX_IPSR_GPSR(IP9_7, VI0_DATA5_VI0_B5),
+        PINMUX_IPSR_GPSR(IP9_7, MMC1_D3),
+        PINMUX_IPSR_GPSR(IP9_9_8, VI0_DATA6_VI0_B6),
+        PINMUX_IPSR_GPSR(IP9_9_8, MMC1_D4),
+        PINMUX_IPSR_GPSR(IP9_9_8, ARM_TRACEDATA_0),
+        PINMUX_IPSR_GPSR(IP9_11_10, VI0_DATA7_VI0_B7),
+        PINMUX_IPSR_GPSR(IP9_11_10, MMC1_D5),
+        PINMUX_IPSR_GPSR(IP9_11_10, ARM_TRACEDATA_1),
+        PINMUX_IPSR_GPSR(IP9_13_12, VI0_G0),
         PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
         PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0),
-        PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
-        PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
+        PINMUX_IPSR_GPSR(IP9_13_12, ARM_TRACEDATA_2),
+        PINMUX_IPSR_GPSR(IP9_15_14, VI0_G1),
         PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
         PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0),
-        PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
-        PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
-        PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
-        PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
-        PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
-        PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
-        PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
-        PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
-        PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
-        PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
-        PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
-        PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
-        PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
+        PINMUX_IPSR_GPSR(IP9_15_14, ARM_TRACEDATA_3),
+        PINMUX_IPSR_GPSR(IP9_18_16, VI0_G2),
+        PINMUX_IPSR_GPSR(IP9_18_16, ETH_TXD1),
+        PINMUX_IPSR_GPSR(IP9_18_16, MMC1_D6),
+        PINMUX_IPSR_GPSR(IP9_18_16, ARM_TRACEDATA_4),
+        PINMUX_IPSR_GPSR(IP9_18_16, TS_SPSYNC0),
+        PINMUX_IPSR_GPSR(IP9_21_19, VI0_G3),
+        PINMUX_IPSR_GPSR(IP9_21_19, ETH_CRS_DV),
+        PINMUX_IPSR_GPSR(IP9_21_19, MMC1_D7),
+        PINMUX_IPSR_GPSR(IP9_21_19, ARM_TRACEDATA_5),
+        PINMUX_IPSR_GPSR(IP9_21_19, TS_SDAT0),
+        PINMUX_IPSR_GPSR(IP9_23_22, VI0_G4),
+        PINMUX_IPSR_GPSR(IP9_23_22, ETH_TX_EN),
         PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
-        PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
-        PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
+        PINMUX_IPSR_GPSR(IP9_23_22, ARM_TRACEDATA_6),
+        PINMUX_IPSR_GPSR(IP9_25_24, VI0_G5),
+        PINMUX_IPSR_GPSR(IP9_25_24, ETH_RX_ER),
         PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
-        PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
-        PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
+        PINMUX_IPSR_GPSR(IP9_25_24, ARM_TRACEDATA_7),
+        PINMUX_IPSR_GPSR(IP9_27_26, VI0_G6),
+        PINMUX_IPSR_GPSR(IP9_27_26, ETH_RXD0),
         PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
-        PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
-        PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
+        PINMUX_IPSR_GPSR(IP9_27_26, ARM_TRACEDATA_8),
+        PINMUX_IPSR_GPSR(IP9_29_28, VI0_G7),
+        PINMUX_IPSR_GPSR(IP9_29_28, ETH_RXD1),
         PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
+        PINMUX_IPSR_GPSR(IP9_29_28, ARM_TRACEDATA_9),
 
-        PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
+        PINMUX_IPSR_GPSR(IP10_2_0, VI0_R0),
         PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
         PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
-        PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
+        PINMUX_IPSR_GPSR(IP10_2_0, ARM_TRACEDATA_10),
         PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
-        PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
+        PINMUX_IPSR_GPSR(IP10_5_3, VI0_R1),
         PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
-        PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
-        PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
-        PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
-        PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
-        PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
-        PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
-        PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
+        PINMUX_IPSR_GPSR(IP10_5_3, DACK1_B),
+        PINMUX_IPSR_GPSR(IP10_5_3, ARM_TRACEDATA_11),
+        PINMUX_IPSR_GPSR(IP10_5_3, DACK0_C),
+        PINMUX_IPSR_GPSR(IP10_5_3, DRACK0_C),
+        PINMUX_IPSR_GPSR(IP10_8_6, VI0_R2),
+        PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK),
+        PINMUX_IPSR_GPSR(IP10_8_6, SD2_CLK_B),
         PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0),
-        PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
-        PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
-        PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
+        PINMUX_IPSR_GPSR(IP10_8_6, ARM_TRACEDATA_12),
+        PINMUX_IPSR_GPSR(IP10_11_9, VI0_R3),
+        PINMUX_IPSR_GPSR(IP10_11_9, ETH_MAGIC),
         PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
         PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0),
-        PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
-        PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
-        PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
+        PINMUX_IPSR_GPSR(IP10_11_9, ARM_TRACEDATA_13),
+        PINMUX_IPSR_GPSR(IP10_14_12, VI0_R4),
+        PINMUX_IPSR_GPSR(IP10_14_12, ETH_REFCLK),
         PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1),
         PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
-        PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
-        PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
-        PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
-        PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
-        PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
+        PINMUX_IPSR_GPSR(IP10_14_12, ARM_TRACEDATA_14),
+        PINMUX_IPSR_GPSR(IP10_14_12, MT1_CLK),
+        PINMUX_IPSR_GPSR(IP10_14_12, TS_SCK0),
+        PINMUX_IPSR_GPSR(IP10_17_15, VI0_R5),
+        PINMUX_IPSR_GPSR(IP10_17_15, ETH_TXD0),
         PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1),
         PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
-        PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
-        PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
-        PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
-        PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
-        PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
+        PINMUX_IPSR_GPSR(IP10_17_15, ARM_TRACEDATA_15),
+        PINMUX_IPSR_GPSR(IP10_17_15, MT1_D),
+        PINMUX_IPSR_GPSR(IP10_17_15, TS_SDEN0),
+        PINMUX_IPSR_GPSR(IP10_20_18, VI0_R6),
+        PINMUX_IPSR_GPSR(IP10_20_18, ETH_MDC),
         PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
-        PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
-        PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
-        PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
+        PINMUX_IPSR_GPSR(IP10_20_18, HSPI_TX1_B),
+        PINMUX_IPSR_GPSR(IP10_20_18, TRACECLK),
+        PINMUX_IPSR_GPSR(IP10_20_18, MT1_BEN),
         PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
-        PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
-        PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
-        PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
+        PINMUX_IPSR_GPSR(IP10_23_21, VI0_R7),
+        PINMUX_IPSR_GPSR(IP10_23_21, ETH_MDIO),
+        PINMUX_IPSR_GPSR(IP10_23_21, DACK2_C),
         PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
         PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
-        PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
-        PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
-        PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
+        PINMUX_IPSR_GPSR(IP10_23_21, TRACECTL),
+        PINMUX_IPSR_GPSR(IP10_23_21, MT1_PEN),
+        PINMUX_IPSR_GPSR(IP10_25_24, VI1_CLK),
         PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0),
         PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0),
-        PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
-        PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
-        PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
+        PINMUX_IPSR_GPSR(IP10_28_26, VI1_HSYNC),
+        PINMUX_IPSR_GPSR(IP10_28_26, VI3_CLK),
+        PINMUX_IPSR_GPSR(IP10_28_26, SSI_SCK4),
         PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
-        PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
-        PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
-        PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
-        PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
+        PINMUX_IPSR_GPSR(IP10_31_29, VI1_VSYNC),
+        PINMUX_IPSR_GPSR(IP10_31_29, AUDIO_CLKOUT_C),
+        PINMUX_IPSR_GPSR(IP10_31_29, SSI_WS4),
+        PINMUX_IPSR_GPSR(IP10_31_29, SIM_CLK),
         PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
-        PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
+        PINMUX_IPSR_GPSR(IP10_31_29, SPV_TRST),
         PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0),
 
-        PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
+        PINMUX_IPSR_GPSR(IP11_2_0, VI1_DATA0_VI1_B0),
         PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
-        PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
-        PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
-        PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
+        PINMUX_IPSR_GPSR(IP11_2_0, SIM_RST),
+        PINMUX_IPSR_GPSR(IP11_2_0, SPV_TCK),
+        PINMUX_IPSR_GPSR(IP11_2_0, ADICLK_B),
+        PINMUX_IPSR_GPSR(IP11_5_3, VI1_DATA1_VI1_B1),
         PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
-        PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
+        PINMUX_IPSR_GPSR(IP11_5_3, MT0_CLK),
+        PINMUX_IPSR_GPSR(IP11_5_3, SPV_TMS),
         PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
+        PINMUX_IPSR_GPSR(IP11_8_6, VI1_DATA2_VI1_B2),
         PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
-        PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
+        PINMUX_IPSR_GPSR(IP11_8_6, MT0_D),
+        PINMUX_IPSR_GPSR(IP11_8_6, SPVTDI),
         PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
+        PINMUX_IPSR_GPSR(IP11_11_9, VI1_DATA3_VI1_B3),
         PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
-        PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
-        PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
-        PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
-        PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
-        PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
-        PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
+        PINMUX_IPSR_GPSR(IP11_11_9, MT0_BEN),
+        PINMUX_IPSR_GPSR(IP11_11_9, SPV_TDO),
+        PINMUX_IPSR_GPSR(IP11_11_9, ADICHS0_B),
+        PINMUX_IPSR_GPSR(IP11_14_12, VI1_DATA4_VI1_B4),
+        PINMUX_IPSR_GPSR(IP11_14_12, SD2_CLK),
+        PINMUX_IPSR_GPSR(IP11_14_12, MT0_PEN),
+        PINMUX_IPSR_GPSR(IP11_14_12, SPA_TRST),
         PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
-        PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
-        PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
+        PINMUX_IPSR_GPSR(IP11_14_12, ADICHS1_B),
+        PINMUX_IPSR_GPSR(IP11_17_15, VI1_DATA5_VI1_B5),
         PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
-        PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
+        PINMUX_IPSR_GPSR(IP11_17_15, MT0_SYNC),
+        PINMUX_IPSR_GPSR(IP11_17_15, SPA_TCK),
         PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
-        PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
-        PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
+        PINMUX_IPSR_GPSR(IP11_17_15, ADICHS2_B),
+        PINMUX_IPSR_GPSR(IP11_20_18, VI1_DATA6_VI1_B6),
         PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
-        PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
-        PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
-        PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
+        PINMUX_IPSR_GPSR(IP11_20_18, MT0_VCXO),
+        PINMUX_IPSR_GPSR(IP11_20_18, SPA_TMS),
+        PINMUX_IPSR_GPSR(IP11_20_18, HSPI_TX1_D),
+        PINMUX_IPSR_GPSR(IP11_23_21, VI1_DATA7_VI1_B7),
         PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
-        PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
+        PINMUX_IPSR_GPSR(IP11_23_21, MT0_PWM),
+        PINMUX_IPSR_GPSR(IP11_23_21, SPA_TDI),
         PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
-        PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
-        PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
-        PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
+        PINMUX_IPSR_GPSR(IP11_26_24, VI1_G0),
+        PINMUX_IPSR_GPSR(IP11_26_24, VI3_DATA0),
+        PINMUX_IPSR_GPSR(IP11_26_24, TS_SCK1),
         PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
-        PINMUX_IPSR_DATA(IP11_26_24, TX2),
-        PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
+        PINMUX_IPSR_GPSR(IP11_26_24, TX2),
+        PINMUX_IPSR_GPSR(IP11_26_24, SPA_TDO),
         PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
-        PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
-        PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
-        PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
-        PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
+        PINMUX_IPSR_GPSR(IP11_29_27, VI1_G1),
+        PINMUX_IPSR_GPSR(IP11_29_27, VI3_DATA1),
+        PINMUX_IPSR_GPSR(IP11_29_27, SSI_SCK1),
+        PINMUX_IPSR_GPSR(IP11_29_27, TS_SDEN1),
+        PINMUX_IPSR_GPSR(IP11_29_27, DACK2_B),
         PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0),
         PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
 
-        PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
-        PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
-        PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
-        PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
+        PINMUX_IPSR_GPSR(IP12_2_0, VI1_G2),
+        PINMUX_IPSR_GPSR(IP12_2_0, VI3_DATA2),
+        PINMUX_IPSR_GPSR(IP12_2_0, SSI_WS1),
+        PINMUX_IPSR_GPSR(IP12_2_0, TS_SPSYNC1),
         PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0),
         PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
-        PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
-        PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
-        PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
+        PINMUX_IPSR_GPSR(IP12_5_3, VI1_G3),
+        PINMUX_IPSR_GPSR(IP12_5_3, VI3_DATA3),
+        PINMUX_IPSR_GPSR(IP12_5_3, SSI_SCK2),
+        PINMUX_IPSR_GPSR(IP12_5_3, TS_SDAT1),
         PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2),
-        PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
-        PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
-        PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
-        PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
+        PINMUX_IPSR_GPSR(IP12_5_3, HTX0_B),
+        PINMUX_IPSR_GPSR(IP12_8_6, VI1_G4),
+        PINMUX_IPSR_GPSR(IP12_8_6, VI3_DATA4),
+        PINMUX_IPSR_GPSR(IP12_8_6, SSI_WS2),
         PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2),
-        PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
+        PINMUX_IPSR_GPSR(IP12_8_6, SIM_RST_B),
         PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
-        PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
+        PINMUX_IPSR_GPSR(IP12_11_9, VI1_G5),
+        PINMUX_IPSR_GPSR(IP12_11_9, VI3_DATA5),
         PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0),
-        PINMUX_IPSR_DATA(IP12_11_9, FSE),
-        PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
+        PINMUX_IPSR_GPSR(IP12_11_9, FSE),
+        PINMUX_IPSR_GPSR(IP12_11_9, TX4_B),
         PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1),
-        PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
-        PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
+        PINMUX_IPSR_GPSR(IP12_14_12, VI1_G6),
+        PINMUX_IPSR_GPSR(IP12_14_12, VI3_DATA6),
         PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0),
-        PINMUX_IPSR_DATA(IP12_14_12, FRB),
+        PINMUX_IPSR_GPSR(IP12_14_12, FRB),
         PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1),
-        PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
-        PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
-        PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
+        PINMUX_IPSR_GPSR(IP12_14_12, SIM_CLK_B),
+        PINMUX_IPSR_GPSR(IP12_17_15, VI1_G7),
+        PINMUX_IPSR_GPSR(IP12_17_15, VI3_DATA7),
         PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0),
-        PINMUX_IPSR_DATA(IP12_17_15, FCE),
+        PINMUX_IPSR_GPSR(IP12_17_15, FCE),
         PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
 };
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index a8b629bc7a55..0f4d48f9400b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -799,47 +799,47 @@ static const u16 pinmux_data[] = {
         PINMUX_SINGLE(DU_DOTCLKIN0),
         PINMUX_SINGLE(DU_DOTCLKIN2),
 
-        PINMUX_IPSR_DATA(IP0_2_0, D0),
+        PINMUX_IPSR_GPSR(IP0_2_0, D0),
         PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
         PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
         PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
-        PINMUX_IPSR_DATA(IP0_5_3, D1),
+        PINMUX_IPSR_GPSR(IP0_5_3, D1),
         PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
         PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
         PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
-        PINMUX_IPSR_DATA(IP0_8_6, D2),
+        PINMUX_IPSR_GPSR(IP0_8_6, D2),
         PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
         PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
         PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
-        PINMUX_IPSR_DATA(IP0_11_9, D3),
+        PINMUX_IPSR_GPSR(IP0_11_9, D3),
         PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
         PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
         PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
-        PINMUX_IPSR_DATA(IP0_15_12, D4),
+        PINMUX_IPSR_GPSR(IP0_15_12, D4),
         PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
         PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
         PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
         PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP0_19_16, D5),
+        PINMUX_IPSR_GPSR(IP0_19_16, D5),
         PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
         PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
         PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
         PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP0_22_20, D6),
+        PINMUX_IPSR_GPSR(IP0_22_20, D6),
         PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
         PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
         PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
-        PINMUX_IPSR_DATA(IP0_26_23, D7),
+        PINMUX_IPSR_GPSR(IP0_26_23, D7),
         PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
         PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
         PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
@@ -847,81 +847,81 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
         PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
-        PINMUX_IPSR_DATA(IP0_30_27, D8),
+        PINMUX_IPSR_GPSR(IP0_30_27, D8),
         PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
-        PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
+        PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
         PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
 
-        PINMUX_IPSR_DATA(IP1_3_0, D9),
+        PINMUX_IPSR_GPSR(IP1_3_0, D9),
         PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
-        PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
+        PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
         PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
-        PINMUX_IPSR_DATA(IP1_7_4, D10),
+        PINMUX_IPSR_GPSR(IP1_7_4, D10),
         PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
-        PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
+        PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
         PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
-        PINMUX_IPSR_DATA(IP1_11_8, D11),
+        PINMUX_IPSR_GPSR(IP1_11_8, D11),
         PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
-        PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
+        PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
         PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
-        PINMUX_IPSR_DATA(IP1_14_12, D12),
+        PINMUX_IPSR_GPSR(IP1_14_12, D12),
         PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
-        PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
+        PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
         PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
-        PINMUX_IPSR_DATA(IP1_17_15, D13),
-        PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
+        PINMUX_IPSR_GPSR(IP1_17_15, D13),
+        PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
         PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
-        PINMUX_IPSR_DATA(IP1_21_18, D14),
+        PINMUX_IPSR_GPSR(IP1_21_18, D14),
         PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
-        PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
+        PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
         PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
         PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
-        PINMUX_IPSR_DATA(IP1_25_22, D15),
+        PINMUX_IPSR_GPSR(IP1_25_22, D15),
         PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
-        PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
+        PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
         PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
         PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
-        PINMUX_IPSR_DATA(IP1_27_26, A0),
-        PINMUX_IPSR_DATA(IP1_27_26, PWM3),
-        PINMUX_IPSR_DATA(IP1_29_28, A1),
-        PINMUX_IPSR_DATA(IP1_29_28, PWM4),
+        PINMUX_IPSR_GPSR(IP1_27_26, A0),
+        PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
+        PINMUX_IPSR_GPSR(IP1_29_28, A1),
+        PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
 
-        PINMUX_IPSR_DATA(IP2_2_0, A2),
-        PINMUX_IPSR_DATA(IP2_2_0, PWM5),
+        PINMUX_IPSR_GPSR(IP2_2_0, A2),
+        PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
         PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
-        PINMUX_IPSR_DATA(IP2_5_3, A3),
-        PINMUX_IPSR_DATA(IP2_5_3, PWM6),
+        PINMUX_IPSR_GPSR(IP2_5_3, A3),
+        PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
         PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
-        PINMUX_IPSR_DATA(IP2_8_6, A4),
+        PINMUX_IPSR_GPSR(IP2_8_6, A4),
         PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
-        PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
-        PINMUX_IPSR_DATA(IP2_11_9, A5),
+        PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
+        PINMUX_IPSR_GPSR(IP2_11_9, A5),
         PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
-        PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
-        PINMUX_IPSR_DATA(IP2_14_12, A6),
+        PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
+        PINMUX_IPSR_GPSR(IP2_14_12, A6),
         PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
-        PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
-        PINMUX_IPSR_DATA(IP2_17_15, A7),
+        PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
+        PINMUX_IPSR_GPSR(IP2_17_15, A7),
         PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
-        PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
-        PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
-        PINMUX_IPSR_DATA(IP2_21_18, A8),
+        PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
+        PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
+        PINMUX_IPSR_GPSR(IP2_21_18, A8),
         PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
         PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
         PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
@@ -929,7 +929,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
         PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
         PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP2_25_22, A9),
+        PINMUX_IPSR_GPSR(IP2_25_22, A9),
         PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
         PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
         PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
@@ -937,392 +937,392 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
         PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
         PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP2_28_26, A10),
+        PINMUX_IPSR_GPSR(IP2_28_26, A10),
         PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
-        PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
+        PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
         PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
 
-        PINMUX_IPSR_DATA(IP3_3_0, A11),
+        PINMUX_IPSR_GPSR(IP3_3_0, A11),
         PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
-        PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
+        PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
         PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
+        PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
         PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP3_7_4, A12),
+        PINMUX_IPSR_GPSR(IP3_7_4, A12),
         PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
-        PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
+        PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
         PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
+        PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
         PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP3_11_8, A13),
+        PINMUX_IPSR_GPSR(IP3_11_8, A13),
         PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
-        PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
-        PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
+        PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
+        PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
         PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
+        PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
         PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP3_14_12, A14),
+        PINMUX_IPSR_GPSR(IP3_14_12, A14),
         PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
-        PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
-        PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
-        PINMUX_IPSR_DATA(IP3_17_15, A15),
+        PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
+        PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
+        PINMUX_IPSR_GPSR(IP3_17_15, A15),
         PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
-        PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
-        PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
-        PINMUX_IPSR_DATA(IP3_19_18, A16),
-        PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
-        PINMUX_IPSR_DATA(IP3_22_20, A17),
+        PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
+        PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
+        PINMUX_IPSR_GPSR(IP3_19_18, A16),
+        PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
+        PINMUX_IPSR_GPSR(IP3_22_20, A17),
         PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
-        PINMUX_IPSR_DATA(IP3_25_23, A18),
+        PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
+        PINMUX_IPSR_GPSR(IP3_25_23, A18),
         PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
-        PINMUX_IPSR_DATA(IP3_28_26, A19),
+        PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
+        PINMUX_IPSR_GPSR(IP3_28_26, A19),
         PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
+        PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
         PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
-        PINMUX_IPSR_DATA(IP3_31_29, A20),
-        PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
+        PINMUX_IPSR_GPSR(IP3_31_29, A20),
+        PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
         PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
+        PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
 
-        PINMUX_IPSR_DATA(IP4_2_0, A21),
-        PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
+        PINMUX_IPSR_GPSR(IP4_2_0, A21),
+        PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
         PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
-        PINMUX_IPSR_DATA(IP4_5_3, A22),
-        PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
+        PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
+        PINMUX_IPSR_GPSR(IP4_5_3, A22),
+        PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
         PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
-        PINMUX_IPSR_DATA(IP4_8_6, A23),
-        PINMUX_IPSR_DATA(IP4_8_6, IO2),
+        PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
+        PINMUX_IPSR_GPSR(IP4_8_6, A23),
+        PINMUX_IPSR_GPSR(IP4_8_6, IO2),
         PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
-        PINMUX_IPSR_DATA(IP4_11_9, A24),
-        PINMUX_IPSR_DATA(IP4_11_9, IO3),
+        PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
+        PINMUX_IPSR_GPSR(IP4_11_9, A24),
+        PINMUX_IPSR_GPSR(IP4_11_9, IO3),
         PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
         PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP4_14_12, A25),
-        PINMUX_IPSR_DATA(IP4_14_12, SSL),
+        PINMUX_IPSR_GPSR(IP4_14_12, A25),
+        PINMUX_IPSR_GPSR(IP4_14_12, SSL),
         PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
         PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
+        PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
         PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
+        PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
         PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
-        PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
-        PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
+        PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
+        PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
         PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
         PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
         PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
+        PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
         PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
+        PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
         PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
-        PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
-        PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
+        PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
+        PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
         PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
-        PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
-        PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
+        PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
+        PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
+        PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
         PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
+        PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
         PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
+        PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
 
-        PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
-        PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
-        PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
+        PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
+        PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
+        PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
         PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
-        PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
+        PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
+        PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
-        PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
+        PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
         PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
         PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
         PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
+        PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
         PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
-        PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
+        PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
         PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
         PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
-        PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
+        PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
         PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
+        PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
         PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
-        PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
+        PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
         PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
-        PINMUX_IPSR_DATA(IP5_12_10, BS_N),
+        PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
         PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
         PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
-        PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
+        PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
         PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
-        PINMUX_IPSR_DATA(IP5_14_13, RD_N),
+        PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
         PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
         PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
-        PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
+        PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
         PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
+        PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
         PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
-        PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
-        PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
+        PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
+        PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
         PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
         PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
         PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
         PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
         PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
+        PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
         PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
         PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
         PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
+        PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
         PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
         PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
         PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
-        PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
-        PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
+        PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
+        PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
         PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
         PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
         PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
-        PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
+        PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
         PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
+        PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
         PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
         PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
 
-        PINMUX_IPSR_DATA(IP6_2_0, DACK0),
-        PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
-        PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
+        PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
+        PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
+        PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
         PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
         PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
-        PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
+        PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
         PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
         PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
-        PINMUX_IPSR_DATA(IP6_8_6, DACK1),
-        PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
-        PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
+        PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
+        PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
+        PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
         PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
         PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
-        PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
+        PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
         PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
-        PINMUX_IPSR_DATA(IP6_13_11, DACK2),
-        PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
-        PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
+        PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
+        PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
+        PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
         PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
         PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
-        PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
+        PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
         PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
         PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
         PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
-        PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
+        PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
         PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
         PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
         PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
-        PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
+        PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
         PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
         PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
         PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
-        PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
+        PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
         PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
         PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
         PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
         PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
-        PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
+        PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
         PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
         PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
         PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
-        PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
+        PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
         PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
         PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
 
-        PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
+        PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
         PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
         PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
         PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
-        PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
+        PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
         PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
         PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
-        PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
+        PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
         PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
         PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
-        PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
+        PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
         PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
-        PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
+        PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
         PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
         PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
-        PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
+        PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
         PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
         PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
-        PINMUX_IPSR_DATA(IP7_18_16, PWM0),
+        PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
         PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
         PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
         PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
-        PINMUX_IPSR_DATA(IP7_21_19, PWM1),
+        PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
         PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
         PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
         PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
-        PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
-        PINMUX_IPSR_DATA(IP7_24_22, PWM2),
-        PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
+        PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
+        PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
+        PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
         PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
-        PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
+        PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
         PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
-        PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1),
-        PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
-        PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
+        PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
+        PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
+        PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
         PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
-        PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
-        PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
+        PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
+        PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
         PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
-        PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
-        PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
+        PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
+        PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
 
         PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
-        PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
-        PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
+        PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
+        PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
         PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
-        PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
-        PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
+        PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
+        PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
         PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
-        PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
-        PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
+        PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
+        PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
         PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
-        PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
-        PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
+        PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
+        PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
         PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
-        PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
-        PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
+        PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
+        PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
         PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
-        PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
+        PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
         PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
-        PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
+        PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
         PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
+        PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
         PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
-        PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
+        PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
         PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
-        PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
+        PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
         PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
-        PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
+        PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
         PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
-        PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
+        PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
         PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
         PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
-        PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
+        PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
         PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
+        PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
         PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
-        PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
+        PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
+        PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
         PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
+        PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
         PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
         PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
 
-        PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
+        PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
         PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
         PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
+        PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
         PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
         PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
+        PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
         PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
         PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
+        PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
         PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
         PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
-        PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
+        PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
+        PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
         PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
-        PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
+        PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
         PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
         PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
         PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
-        PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
+        PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
+        PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
         PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
-        PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
+        PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
         PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
         PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
         PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
-        PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
-        PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
-        PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
-        PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
+        PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
+        PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
+        PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
+        PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
         PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
-        PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
-        PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
+        PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
+        PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
         PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
-        PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
-        PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
+        PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
+        PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
         PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
-        PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
-        PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
+        PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
+        PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
         PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
-        PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
-        PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
+        PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
+        PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
         PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
-        PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
-        PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
+        PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
+        PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
         PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
-        PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
+        PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
         PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
@@ -1330,24 +1330,24 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
         PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
 
-        PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
-        PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
+        PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
+        PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
         PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
-        PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
+        PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
         PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
         PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
         PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
-        PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
-        PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
+        PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
+        PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
         PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
         PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
         PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
-        PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
-        PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
+        PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
+        PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
         PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
         PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
@@ -1355,8 +1355,8 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
         PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
-        PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
-        PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
+        PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
+        PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
         PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
         PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
@@ -1364,8 +1364,8 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
         PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
-        PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
-        PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
+        PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
+        PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
         PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
         PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
@@ -1373,26 +1373,26 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
         PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
-        PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
-        PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
+        PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
+        PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
         PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
         PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
         PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
         PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
-        PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
-        PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
+        PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
+        PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
         PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
         PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
         PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
         PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
-        PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
-        PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
+        PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
+        PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
         PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
-        PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
+        PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
         PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
@@ -1400,164 +1400,164 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
 
-        PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
-        PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
+        PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
+        PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
         PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
-        PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
+        PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
         PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
         PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
         PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
         PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
-        PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
-        PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
-        PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
-        PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
-        PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
-        PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
-        PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
-        PINMUX_IPSR_DATA(IP11_8_7, STM_N),
-        PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
-        PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
-        PINMUX_IPSR_DATA(IP11_10_9, MDATA),
-        PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
-        PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
-        PINMUX_IPSR_DATA(IP11_12_11, SDATA),
-        PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
-        PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
-        PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
-        PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
-        PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
+        PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
+        PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
+        PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
+        PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
+        PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
+        PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
+        PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
+        PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
+        PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
+        PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
+        PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
+        PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
+        PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
+        PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
+        PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
+        PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
+        PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
+        PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
+        PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
         PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
-        PINMUX_IPSR_DATA(IP11_17_15, VSP),
+        PINMUX_IPSR_GPSR(IP11_17_15, VSP),
         PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
-        PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
-        PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
+        PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
+        PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
         PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
         PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
         PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
         PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
-        PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
+        PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
         PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
         PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
-        PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
+        PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
         PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
         PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
         PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
-        PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
+        PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
         PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
         PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
-        PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
+        PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
         PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
-        PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
+        PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
 
-        PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
+        PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
         PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
-        PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
-        PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
+        PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
+        PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
         PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
-        PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
-        PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
+        PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
+        PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
         PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
-        PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
-        PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
+        PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
+        PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
         PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
-        PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
-        PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
-        PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
-        PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
+        PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
+        PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
+        PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
+        PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
         PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
         PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
-        PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
-        PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
+        PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
+        PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
         PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
         PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
-        PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
-        PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
-        PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
+        PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
+        PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
+        PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
         PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
         PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
         PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
-        PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
-        PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
+        PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
+        PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
         PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
         PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
         PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
         PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
-        PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
-        PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
+        PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
+        PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
         PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
         PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
         PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
         PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
-        PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
-        PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
+        PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
+        PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
         PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
         PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
-        PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
+        PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
         PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
         PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
         PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
-        PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
-        PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
-        PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
+        PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
+        PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
+        PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
         PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
         PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
         PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
-        PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
-        PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
-        PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
+        PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
+        PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
+        PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
 
         PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
         PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
         PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
-        PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
-        PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
-        PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
+        PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
+        PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
+        PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
         PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
         PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
         PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
-        PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
-        PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
-        PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
+        PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
+        PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
+        PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
         PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
         PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
         PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
         PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
-        PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
-        PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
-        PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
+        PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
+        PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
+        PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
         PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
         PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
-        PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
-        PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
-        PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
+        PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
+        PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
+        PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
         PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
         PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
         PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
         PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
-        PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
-        PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
-        PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
+        PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
+        PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
+        PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
         PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
         PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
         PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
-        PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
-        PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
-        PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
-        PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
+        PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
+        PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
+        PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
+        PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
         PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
         PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
         PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
-        PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
-        PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
-        PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
-        PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
+        PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
+        PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
+        PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
+        PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
         PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
         PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
         PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
@@ -1565,161 +1565,161 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
         PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
         PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
-        PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
+        PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
         PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
-        PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
+        PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
         PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
         PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
-        PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
+        PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
         PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
-        PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
-        PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
+        PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
+        PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
         PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
-        PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
+        PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
 
-        PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
+        PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
         PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
         PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
-        PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
+        PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
         PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
-        PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
-        PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
+        PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
+        PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
         PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
         PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
-        PINMUX_IPSR_DATA(IP14_5_3, SCK0),
-        PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
-        PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
-        PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
+        PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
+        PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
+        PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
+        PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
         PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
         PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
         PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
         PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
-        PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
+        PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
+        PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
         PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
         PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
-        PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
+        PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
+        PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
         PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
         PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
-        PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
+        PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
         PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
-        PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
-        PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
-        PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
+        PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
+        PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
+        PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
         PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
         PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
         PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
         PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
-        PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
-        PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
-        PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
-        PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
-        PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
+        PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
+        PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
+        PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
+        PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
+        PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
         PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
         PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
         PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
+        PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
+        PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
         PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
         PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
         PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
-        PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
+        PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
+        PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
         PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
         PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
-        PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
+        PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
         PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
-        PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
-        PINMUX_IPSR_DATA(IP14_27_25, QCLK),
+        PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
+        PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
         PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
         PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
-        PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
+        PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
         PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
-        PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
-        PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
+        PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
+        PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
         PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
 
         PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
         PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
-        PINMUX_IPSR_DATA(IP15_2_0, SCK2),
+        PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
         PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
-        PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
-        PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
+        PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
+        PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
         PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
         PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
         PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
         PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
-        PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
-        PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
+        PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
+        PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
         PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
         PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
         PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
         PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
         PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
-        PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
-        PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
+        PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
+        PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
         PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
         PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
-        PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
+        PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
         PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
-        PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
-        PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
+        PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
+        PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
         PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
         PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
-        PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
-        PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
+        PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
+        PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
         PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
-        PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
-        PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
+        PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
+        PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
         PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
-        PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
-        PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
-        PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
+        PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
+        PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
+        PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
         PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
-        PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
-        PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
-        PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
+        PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
+        PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
+        PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
         PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
         PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
-        PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
-        PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
-        PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
-        PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
+        PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
+        PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
+        PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
+        PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
         PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
-        PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
-        PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
-        PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
-        PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
+        PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
+        PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
+        PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
+        PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
         PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
         PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
-        PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
-        PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
-        PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
+        PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
+        PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
+        PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
         PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
-        PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
-        PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
-        PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
+        PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
+        PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
+        PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
 
         PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
-        PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
-        PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
-        PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
-        PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
+        PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
+        PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
+        PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
+        PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
         PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
         PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
         PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
         PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
-        PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
-        PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
-        PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
-        PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
+        PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
+        PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
+        PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
+        PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
         PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
-        PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
-        PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
-        PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
+        PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
+        PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
+        PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
         PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
 
         PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 4cfbb94ad5d0..01abbd5b4e49 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -792,171 +792,171 @@ static const u16 pinmux_data[] = {
         PINMUX_SINGLE(SD1_CLK),
 
         /* IPSR0 */
-        PINMUX_IPSR_DATA(IP0_0, D0),
-        PINMUX_IPSR_DATA(IP0_1, D1),
-        PINMUX_IPSR_DATA(IP0_2, D2),
-        PINMUX_IPSR_DATA(IP0_3, D3),
-        PINMUX_IPSR_DATA(IP0_4, D4),
-        PINMUX_IPSR_DATA(IP0_5, D5),
-        PINMUX_IPSR_DATA(IP0_6, D6),
-        PINMUX_IPSR_DATA(IP0_7, D7),
-        PINMUX_IPSR_DATA(IP0_8, D8),
-        PINMUX_IPSR_DATA(IP0_9, D9),
-        PINMUX_IPSR_DATA(IP0_10, D10),
-        PINMUX_IPSR_DATA(IP0_11, D11),
-        PINMUX_IPSR_DATA(IP0_12, D12),
-        PINMUX_IPSR_DATA(IP0_13, D13),
-        PINMUX_IPSR_DATA(IP0_14, D14),
-        PINMUX_IPSR_DATA(IP0_15, D15),
-        PINMUX_IPSR_DATA(IP0_18_16, A0),
+        PINMUX_IPSR_GPSR(IP0_0, D0),
+        PINMUX_IPSR_GPSR(IP0_1, D1),
+        PINMUX_IPSR_GPSR(IP0_2, D2),
+        PINMUX_IPSR_GPSR(IP0_3, D3),
+        PINMUX_IPSR_GPSR(IP0_4, D4),
+        PINMUX_IPSR_GPSR(IP0_5, D5),
+        PINMUX_IPSR_GPSR(IP0_6, D6),
+        PINMUX_IPSR_GPSR(IP0_7, D7),
+        PINMUX_IPSR_GPSR(IP0_8, D8),
+        PINMUX_IPSR_GPSR(IP0_9, D9),
+        PINMUX_IPSR_GPSR(IP0_10, D10),
+        PINMUX_IPSR_GPSR(IP0_11, D11),
+        PINMUX_IPSR_GPSR(IP0_12, D12),
+        PINMUX_IPSR_GPSR(IP0_13, D13),
+        PINMUX_IPSR_GPSR(IP0_14, D14),
+        PINMUX_IPSR_GPSR(IP0_15, D15),
+        PINMUX_IPSR_GPSR(IP0_18_16, A0),
         PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
         PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
         PINMUX_IPSR_MSEL(IP0_18_16, SCL0_C, SEL_IIC0_2),
-        PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
-        PINMUX_IPSR_DATA(IP0_20_19, A1),
+        PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
+        PINMUX_IPSR_GPSR(IP0_20_19, A1),
         PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
-        PINMUX_IPSR_DATA(IP0_22_21, A2),
+        PINMUX_IPSR_GPSR(IP0_22_21, A2),
         PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
-        PINMUX_IPSR_DATA(IP0_24_23, A3),
+        PINMUX_IPSR_GPSR(IP0_24_23, A3),
         PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
-        PINMUX_IPSR_DATA(IP0_26_25, A4),
+        PINMUX_IPSR_GPSR(IP0_26_25, A4),
         PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
-        PINMUX_IPSR_DATA(IP0_28_27, A5),
+        PINMUX_IPSR_GPSR(IP0_28_27, A5),
         PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
-        PINMUX_IPSR_DATA(IP0_30_29, A6),
+        PINMUX_IPSR_GPSR(IP0_30_29, A6),
         PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 
         /* IPSR1 */
-        PINMUX_IPSR_DATA(IP1_1_0, A7),
+        PINMUX_IPSR_GPSR(IP1_1_0, A7),
         PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
-        PINMUX_IPSR_DATA(IP1_3_2, A8),
+        PINMUX_IPSR_GPSR(IP1_3_2, A8),
         PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
         PINMUX_IPSR_MSEL(IP1_3_2, SCL0, SEL_IIC0_0),
-        PINMUX_IPSR_DATA(IP1_5_4, A9),
+        PINMUX_IPSR_GPSR(IP1_5_4, A9),
         PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
         PINMUX_IPSR_MSEL(IP1_5_4, SDA0, SEL_IIC0_0),
-        PINMUX_IPSR_DATA(IP1_7_6, A10),
+        PINMUX_IPSR_GPSR(IP1_7_6, A10),
         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
-        PINMUX_IPSR_DATA(IP1_10_8, A11),
+        PINMUX_IPSR_GPSR(IP1_10_8, A11),
         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
         PINMUX_IPSR_MSEL(IP1_10_8, SCL3_D, SEL_IIC3_3),
         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
-        PINMUX_IPSR_DATA(IP1_13_11, A12),
+        PINMUX_IPSR_GPSR(IP1_13_11, A12),
         PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
         PINMUX_IPSR_MSEL(IP1_13_11, SDA3_D, SEL_IIC3_3),
         PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
-        PINMUX_IPSR_DATA(IP1_16_14, A13),
+        PINMUX_IPSR_GPSR(IP1_16_14, A13),
         PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
         PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
         PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
-        PINMUX_IPSR_DATA(IP1_19_17, A14),
+        PINMUX_IPSR_GPSR(IP1_19_17, A14),
         PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
         PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
         PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
         PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
-        PINMUX_IPSR_DATA(IP1_22_20, A15),
+        PINMUX_IPSR_GPSR(IP1_22_20, A15),
         PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
-        PINMUX_IPSR_DATA(IP1_25_23, A16),
+        PINMUX_IPSR_GPSR(IP1_25_23, A16),
         PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
         PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
         PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
-        PINMUX_IPSR_DATA(IP1_28_26, A17),
+        PINMUX_IPSR_GPSR(IP1_28_26, A17),
         PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
         PINMUX_IPSR_MSEL(IP1_28_26, SDA0_C, SEL_IIC0_2),
-        PINMUX_IPSR_DATA(IP1_31_29, A18),
+        PINMUX_IPSR_GPSR(IP1_31_29, A18),
         PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
         PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
         PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 
         /* IPSR2 */
-        PINMUX_IPSR_DATA(IP2_2_0, A19),
-        PINMUX_IPSR_DATA(IP2_2_0, DACK1),
+        PINMUX_IPSR_GPSR(IP2_2_0, A19),
+        PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
         PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
-        PINMUX_IPSR_DATA(IP2_2_0, A20),
+        PINMUX_IPSR_GPSR(IP2_2_0, A20),
         PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
-        PINMUX_IPSR_DATA(IP2_6_5, A21),
+        PINMUX_IPSR_GPSR(IP2_6_5, A21),
         PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
         PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
-        PINMUX_IPSR_DATA(IP2_9_7, A22),
+        PINMUX_IPSR_GPSR(IP2_9_7, A22),
         PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
         PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
         PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
         PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
-        PINMUX_IPSR_DATA(IP2_12_10, A23),
+        PINMUX_IPSR_GPSR(IP2_12_10, A23),
         PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
         PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
         PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
         PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
-        PINMUX_IPSR_DATA(IP2_15_13, A24),
+        PINMUX_IPSR_GPSR(IP2_15_13, A24),
         PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
         PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
         PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
         PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
-        PINMUX_IPSR_DATA(IP2_18_16, A25),
+        PINMUX_IPSR_GPSR(IP2_18_16, A25),
         PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
         PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
         PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
         PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
         PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
-        PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
+        PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
         PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
         PINMUX_IPSR_MSEL(IP2_20_19, SCL1, SEL_IIC1_0),
-        PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
+        PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
         PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
         PINMUX_IPSR_MSEL(IP2_22_21, SDA1, SEL_IIC1_0),
-        PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
+        PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
         PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
-        PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
+        PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
         PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
         PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
-        PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
+        PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
         PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
         PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
-        PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
+        PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
 
         /* IPSR3 */
-        PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
+        PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
         PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
         PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
-        PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
-        PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
-        PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
+        PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
+        PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
+        PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
         PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
         PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
-        PINMUX_IPSR_DATA(IP3_5_3, PWM1),
-        PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
-        PINMUX_IPSR_DATA(IP3_8_6, BS_N),
-        PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
+        PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
+        PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
+        PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
+        PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
         PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
         PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
-        PINMUX_IPSR_DATA(IP3_8_6, PWM2),
-        PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
-        PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
+        PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
+        PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
+        PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
         PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
         PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
         PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
         PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
-        PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
+        PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
         PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
         PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
-        PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
+        PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
         PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
         PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
         PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
-        PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
+        PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
         PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
         PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
-        PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
-        PINMUX_IPSR_DATA(IP3_19_18, PWM3),
-        PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
-        PINMUX_IPSR_DATA(IP3_21_20, DACK0),
-        PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
+        PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
+        PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
+        PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
+        PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
+        PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
         PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
         PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
         PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
@@ -995,61 +995,61 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP4_9_8, SDA1_B, SEL_IIC1_1),
         PINMUX_IPSR_MSEL(IP4_9_8, SDA8_B, SEL_IIC8_1),
         PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
-        PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
+        PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
         PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),
         PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
+        PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
         PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),
         PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
         PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
+        PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
         PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
-        PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
-        PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
-        PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
-        PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
+        PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
+        PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
+        PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
+        PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
         PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
+        PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
         PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
+        PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
         PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
-        PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
+        PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
         PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
         PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
-        PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
+        PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
 
         /* IPSR5 */
-        PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
+        PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
         PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
         PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
-        PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
-        PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
+        PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
+        PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
         PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
         PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
-        PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
-        PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
+        PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
+        PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
         PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
         PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
-        PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
-        PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
+        PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
+        PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
         PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
-        PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
-        PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
+        PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
+        PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
         PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
-        PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
+        PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
         PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
         PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
         PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
@@ -1080,307 +1080,307 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
         PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
         PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
-        PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
+        PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
         PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
         PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
         PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
         PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
         PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
-        PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
+        PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
         PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
         PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),
         PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
-        PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
+        PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
         PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
-        PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
-        PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
+        PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
+        PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
         PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
-        PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
-        PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
+        PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
+        PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
         PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
-        PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
-        PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
+        PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
+        PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
         PINMUX_IPSR_MSEL(IP6_15_14, SCL4_C, SEL_IIC4_2),
         PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
-        PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
-        PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
+        PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
+        PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
         PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
         PINMUX_IPSR_MSEL(IP6_18_16, SDA4_C, SEL_IIC4_2),
         PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
-        PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
-        PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
+        PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
+        PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
         PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
         PINMUX_IPSR_MSEL(IP6_20_19, SCL1_E, SEL_IIC1_4),
         PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
-        PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
+        PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
         PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
         PINMUX_IPSR_MSEL(IP6_23_21, SDA1_E, SEL_IIC1_4),
         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
-        PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
+        PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
         PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
         PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
+        PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
         PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
         PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
 
         /* IPSR7 */
-        PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
+        PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
         PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
         PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
-        PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
+        PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
+        PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
         PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
         PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
-        PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
-        PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
+        PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
+        PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
         PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
         PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
-        PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
-        PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
+        PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
+        PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
         PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
-        PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
-        PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
+        PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
+        PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
         PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
-        PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
-        PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
+        PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
+        PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
         PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
-        PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
-        PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
+        PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
+        PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
         PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
-        PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
-        PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
+        PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
+        PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
         PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
-        PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
-        PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
+        PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
+        PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
         PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
-        PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
-        PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
+        PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
+        PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
         PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
         PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
         PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
-        PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
-        PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
+        PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
+        PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
         PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
         PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
         PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
-        PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
-        PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
+        PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
+        PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
         PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
+        PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
         PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
         PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
 
         /* IPSR8 */
-        PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
-        PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
+        PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
+        PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
         PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
-        PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
-        PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
+        PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
+        PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
         PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
-        PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
-        PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
+        PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
+        PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
         PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
         PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
-        PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
-        PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
+        PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
+        PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
         PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
-        PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
-        PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
+        PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
+        PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
         PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
         PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
-        PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
-        PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
+        PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
+        PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
         PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
         PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
         PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
-        PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
-        PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
+        PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
+        PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
         PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
         PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
         PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
-        PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
-        PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
+        PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
+        PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
         PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
+        PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
         PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
         PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
-        PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
-        PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
+        PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
+        PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
         PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
-        PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
-        PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
+        PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
+        PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
         PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
         PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
-        PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
-        PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
+        PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
+        PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
         PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
         PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
         PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
 
         /* IPSR9 */
-        PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
-        PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
+        PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
+        PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
         PINMUX_IPSR_MSEL(IP9_2_0, SCL3_C, SEL_IIC3_2),
         PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
         PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
-        PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
-        PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
+        PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
+        PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
         PINMUX_IPSR_MSEL(IP9_5_3, SDA3_C, SEL_IIC3_2),
         PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
         PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
         PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
-        PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
-        PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
-        PINMUX_IPSR_DATA(IP9_7, QCLK),
-        PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
-        PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
+        PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
+        PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
+        PINMUX_IPSR_GPSR(IP9_7, QCLK),
+        PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
+        PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
         PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
         PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
         PINMUX_IPSR_MSEL(IP9_10_8, SCL2_B, SEL_IIC2_1),
-        PINMUX_IPSR_DATA(IP9_10_8, PWM4),
-        PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
-        PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
-        PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
-        PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
-        PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
+        PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
+        PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
+        PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
+        PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
+        PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
+        PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
         PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
         PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
         PINMUX_IPSR_MSEL(IP9_15_13, SDA2_B, SEL_IIC2_1),
-        PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
-        PINMUX_IPSR_DATA(IP9_16, QPOLA),
-        PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
-        PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
-        PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
-        PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
+        PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
+        PINMUX_IPSR_GPSR(IP9_16, QPOLA),
+        PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
+        PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
+        PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
+        PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
         PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
         PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
         PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
-        PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
+        PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
         PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
         PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
         PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
-        PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
+        PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
         PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
         PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
         PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
-        PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
+        PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
         PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
         PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
         PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
-        PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
         PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
         PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
-        PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
+        PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
         PINMUX_IPSR_MSEL(IP9_31_29, SCL8, SEL_IIC8_0),
         PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
         PINMUX_IPSR_MSEL(IP9_31_29, SCL4, SEL_IIC4_0),
         PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
         PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
-        PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
+        PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
 
         /* IPSR10 */
-        PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
+        PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
         PINMUX_IPSR_MSEL(IP10_2_0, SDA8, SEL_IIC8_0),
         PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
         PINMUX_IPSR_MSEL(IP10_2_0, SDA4, SEL_IIC4_0),
         PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
         PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
-        PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
-        PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
-        PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
+        PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
+        PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
+        PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
         PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
         PINMUX_IPSR_MSEL(IP10_5_3, SCL3_B, SEL_IIC3_1),
         PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
         PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
-        PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
-        PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
-        PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
+        PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
+        PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
+        PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
         PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
         PINMUX_IPSR_MSEL(IP10_8_6, SDA3_B, SEL_IIC3_1),
         PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
         PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
-        PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
-        PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
-        PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
+        PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
+        PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
+        PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
         PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
         PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
-        PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
-        PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
+        PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
+        PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
         PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
         PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
         PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
         PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
         PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
-        PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
-        PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
+        PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
+        PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
         PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
-        PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
-        PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
+        PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
+        PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
         PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
-        PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
-        PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
+        PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
+        PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
         PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
-        PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
-        PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
-        PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
+        PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
+        PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
+        PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
         PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
-        PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
-        PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
-        PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
+        PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
+        PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
+        PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
         PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
-        PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
-        PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
+        PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
+        PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
         PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
-        PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
-        PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
+        PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
+        PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
         PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
         PINMUX_IPSR_MSEL(IP10_31_29, SCL1_D, SEL_IIC1_3),
 
         /* IPSR11 */
-        PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
-        PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
+        PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
+        PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
         PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
         PINMUX_IPSR_MSEL(IP11_2_0, SDA1_D, SEL_IIC1_3),
-        PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
-        PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
+        PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
+        PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
         PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP11_5_3, SCL4_B, SEL_IIC4_1),
-        PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
+        PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
         PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
         PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
@@ -1388,180 +1388,180 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
         PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
         PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
+        PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
         PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
         PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
         PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
+        PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
         PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
         PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
         PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
+        PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
         PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
+        PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
         PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
+        PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
         PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
+        PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
         PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
+        PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
         PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
+        PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
         PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
+        PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
         PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
+        PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
         PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
+        PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
         PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
+        PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
         PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
-        PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
-        PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
-        PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
+        PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
+        PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
+        PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
         PINMUX_IPSR_MSEL(IP11_29_28, SCL2_C, SEL_IIC2_2),
-        PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
-        PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
+        PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
+        PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
         PINMUX_IPSR_MSEL(IP11_31_30, SDA2_C, SEL_IIC2_2),
 
         /* IPSR12 */
-        PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
-        PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
+        PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
+        PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
         PINMUX_IPSR_MSEL(IP12_1_0, SCL3, SEL_IIC3_0),
         PINMUX_IPSR_MSEL(IP12_1_0, SCL7, SEL_IIC7_0),
-        PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
-        PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
+        PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
+        PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
         PINMUX_IPSR_MSEL(IP12_3_2, SDA3, SEL_IIC3_0),
         PINMUX_IPSR_MSEL(IP12_3_2, SDA7, SEL_IIC7_0),
-        PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
-        PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
+        PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
+        PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
         PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
         PINMUX_IPSR_MSEL(IP12_6_4, SCL2_D, SEL_IIC2_3),
         PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
-        PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
-        PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
+        PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
+        PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
         PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
         PINMUX_IPSR_MSEL(IP12_9_7, SDA2_D, SEL_IIC2_3),
         PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
-        PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
-        PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
+        PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
+        PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
         PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
         PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
         PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
-        PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
-        PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
+        PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
+        PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
         PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
         PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
         PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
-        PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
-        PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
+        PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
+        PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
         PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
         PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
-        PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
-        PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
+        PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
+        PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
         PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
-        PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
-        PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
+        PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
+        PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
         PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
-        PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
-        PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
+        PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
+        PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
         PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
         PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
-        PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
+        PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
         PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
         PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
         PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
-        PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
+        PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
         PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
         PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
 
         /* IPSR13 */
         PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
-        PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
+        PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
         PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
         PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
         PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
-        PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
+        PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
         PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
         PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
-        PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
+        PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
         PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
         PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
-        PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
-        PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
+        PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
+        PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
         PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
-        PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
+        PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
         PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
-        PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
+        PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
         PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
-        PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
+        PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
         PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
-        PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
+        PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
         PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
-        PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
+        PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
         PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
-        PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
+        PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
         PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
-        PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
+        PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
         PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
         PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
         PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
         PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
         PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
-        PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
+        PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
         PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
         PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
         PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
         PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
         PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
-        PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
+        PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
         PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
-        PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
+        PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
         PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
-        PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
+        PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
         PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
-        PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
+        PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
         PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
-        PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
+        PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
         PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
-        PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
-        PINMUX_IPSR_DATA(IP13_30_28, PWM0),
-        PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
+        PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
+        PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
+        PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
         PINMUX_IPSR_MSEL(IP13_30_28, SCL1_C, SEL_IIC1_2),
 
         /* IPSR14 */
-        PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
-        PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
+        PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
+        PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
         PINMUX_IPSR_MSEL(IP14_1_0, SDA1_C, SEL_IIC1_2),
-        PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
-        PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
-        PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
-        PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
-        PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
-        PINMUX_IPSR_DATA(IP14_4, MMC_D0),
-        PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
-        PINMUX_IPSR_DATA(IP14_5, MMC_D1),
-        PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
-        PINMUX_IPSR_DATA(IP14_6, MMC_D2),
-        PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
-        PINMUX_IPSR_DATA(IP14_7, MMC_D3),
-        PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
-        PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
+        PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
+        PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
+        PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
+        PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
+        PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
+        PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
+        PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
+        PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
+        PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
+        PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
+        PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
+        PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
+        PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
+        PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
         PINMUX_IPSR_MSEL(IP14_10_8, SCL8_C, SEL_IIC8_2),
         PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
         PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
-        PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
-        PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
+        PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
+        PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
         PINMUX_IPSR_MSEL(IP14_13_11, SDA8_C, SEL_IIC8_2),
         PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
         PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
@@ -1569,40 +1569,40 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
         PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
-        PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
+        PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
         PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
         PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
         PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
-        PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
+        PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
         PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
         PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
-        PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
+        PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
         PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
         PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
-        PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
+        PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
         PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
         PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
         PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
         PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
         PINMUX_IPSR_MSEL(IP14_28_26, SCL7_C, SEL_IIC7_2),
-        PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
+        PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
         PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
         PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
         PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
         PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
         PINMUX_IPSR_MSEL(IP14_31_29, SDA7_C, SEL_IIC7_2),
-        PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
+        PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
 
         /* IPSR15 */
         PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
         PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
         PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
-        PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
+        PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
         PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
         PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
         PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
@@ -1611,19 +1611,19 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
         PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
-        PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
+        PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
         PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
         PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
-        PINMUX_IPSR_DATA(IP15_11_9, PWM5),
-        PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
+        PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
+        PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
         PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
         PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
-        PINMUX_IPSR_DATA(IP15_14_12, PWM6),
-        PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
+        PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
+        PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
         PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
         PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
@@ -1638,7 +1638,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
         PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
-        PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
+        PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
         PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
         PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
         PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
@@ -1654,25 +1654,25 @@ static const u16 pinmux_data[] = {
         /* IPSR16 */
         PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
-        PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
+        PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
         PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
         PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
-        PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
+        PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
         PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
         PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
-        PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK),
+        PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
         PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
         PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
-        PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
-        PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
+        PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
+        PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
         PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
         PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
-        PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
-        PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
+        PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
+        PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
         PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
 };
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index 3718c7846bfd..38912cff597b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -1,9 +1,9 @@
 /*
  * r8a7794 processor support - PFC hardware block.
  *
- * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014-2015 Renesas Electronics Corporation
  * Copyright (C) 2015 Renesas Solutions Corp.
- * Copyright (C) 2015 Cogent  Embedded, Inc., <source@cogentembedded.com>
+ * Copyright (C) 2015-2016 Cogent Embedded, Inc., <source@cogentembedded.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2
@@ -623,848 +623,848 @@ static const u16 pinmux_data[] = {
         PINMUX_SINGLE(SD1_DATA3),
 
         /* IPSR0 */
-        PINMUX_IPSR_DATA(IP0_0, SD1_CD),
+        PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
         PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
-        PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
-        PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
+        PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
+        PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
         PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
-        PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
-        PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
-        PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
-        PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
-        PINMUX_IPSR_DATA(IP0_12, MMC_D0),
-        PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
-        PINMUX_IPSR_DATA(IP0_13, MMC_D1),
-        PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
-        PINMUX_IPSR_DATA(IP0_14, MMC_D2),
-        PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
-        PINMUX_IPSR_DATA(IP0_15, MMC_D3),
-        PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
-        PINMUX_IPSR_DATA(IP0_16, MMC_D4),
-        PINMUX_IPSR_DATA(IP0_16, SD2_CD),
-        PINMUX_IPSR_DATA(IP0_17, MMC_D5),
-        PINMUX_IPSR_DATA(IP0_17, SD2_WP),
-        PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
+        PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
+        PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
+        PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
+        PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
+        PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
+        PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
+        PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
+        PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
+        PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
+        PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
+        PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
+        PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
+        PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
+        PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
+        PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
+        PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
+        PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
         PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
         PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
         PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
-        PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
+        PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
         PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
         PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
         PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
-        PINMUX_IPSR_DATA(IP0_23_22, D0),
+        PINMUX_IPSR_GPSR(IP0_23_22, D0),
         PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
-        PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
-        PINMUX_IPSR_DATA(IP0_24, D1),
+        PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
+        PINMUX_IPSR_GPSR(IP0_24, D1),
         PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
-        PINMUX_IPSR_DATA(IP0_25, D2),
+        PINMUX_IPSR_GPSR(IP0_25, D2),
         PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
-        PINMUX_IPSR_DATA(IP0_27_26, D3),
+        PINMUX_IPSR_GPSR(IP0_27_26, D3),
         PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
         PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
-        PINMUX_IPSR_DATA(IP0_29_28, D4),
+        PINMUX_IPSR_GPSR(IP0_29_28, D4),
         PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
         PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
-        PINMUX_IPSR_DATA(IP0_31_30, D5),
+        PINMUX_IPSR_GPSR(IP0_31_30, D5),
         PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
         PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
 
         /* IPSR1 */
-        PINMUX_IPSR_DATA(IP1_1_0, D6),
+        PINMUX_IPSR_GPSR(IP1_1_0, D6),
         PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
         PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
-        PINMUX_IPSR_DATA(IP1_3_2, D7),
-        PINMUX_IPSR_DATA(IP1_3_2, IRQ3),
+        PINMUX_IPSR_GPSR(IP1_3_2, D7),
+        PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
         PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
-        PINMUX_IPSR_DATA(IP1_3_2, PWM6_B),
-        PINMUX_IPSR_DATA(IP1_5_4, D8),
-        PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX),
+        PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
+        PINMUX_IPSR_GPSR(IP1_5_4, D8),
+        PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
         PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
-        PINMUX_IPSR_DATA(IP1_7_6, D9),
-        PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX),
+        PINMUX_IPSR_GPSR(IP1_7_6, D9),
+        PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
         PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
-        PINMUX_IPSR_DATA(IP1_10_8, D10),
-        PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK),
+        PINMUX_IPSR_GPSR(IP1_10_8, D10),
+        PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
         PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
-        PINMUX_IPSR_DATA(IP1_10_8, IRQ6),
-        PINMUX_IPSR_DATA(IP1_10_8, PWM5_C),
-        PINMUX_IPSR_DATA(IP1_12_11, D11),
-        PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N),
+        PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
+        PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
+        PINMUX_IPSR_GPSR(IP1_12_11, D11),
+        PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
         PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
-        PINMUX_IPSR_DATA(IP1_14_13, D12),
-        PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N),
+        PINMUX_IPSR_GPSR(IP1_14_13, D12),
+        PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
         PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
-        PINMUX_IPSR_DATA(IP1_17_15, D13),
+        PINMUX_IPSR_GPSR(IP1_17_15, D13),
         PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
-        PINMUX_IPSR_DATA(IP1_17_15, TANS1),
-        PINMUX_IPSR_DATA(IP1_17_15, PWM2_C),
+        PINMUX_IPSR_GPSR(IP1_17_15, TANS1),
+        PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
         PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
-        PINMUX_IPSR_DATA(IP1_19_18, D14),
+        PINMUX_IPSR_GPSR(IP1_19_18, D14),
         PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
         PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1),
-        PINMUX_IPSR_DATA(IP1_21_20, D15),
+        PINMUX_IPSR_GPSR(IP1_21_20, D15),
         PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
         PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1),
-        PINMUX_IPSR_DATA(IP1_23_22, A0),
-        PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK),
-        PINMUX_IPSR_DATA(IP1_23_22, PWM3_B),
-        PINMUX_IPSR_DATA(IP1_24, A1),
-        PINMUX_IPSR_DATA(IP1_24, SCIFB1_TXD),
-        PINMUX_IPSR_DATA(IP1_26, A3),
-        PINMUX_IPSR_DATA(IP1_26, SCIFB0_SCK),
-        PINMUX_IPSR_DATA(IP1_27, A4),
-        PINMUX_IPSR_DATA(IP1_27, SCIFB0_TXD),
-        PINMUX_IPSR_DATA(IP1_29_28, A5),
-        PINMUX_IPSR_DATA(IP1_29_28, SCIFB0_RXD),
-        PINMUX_IPSR_DATA(IP1_29_28, PWM4_B),
-        PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C),
-        PINMUX_IPSR_DATA(IP1_31_30, A6),
-        PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N),
+        PINMUX_IPSR_GPSR(IP1_23_22, A0),
+        PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
+        PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
+        PINMUX_IPSR_GPSR(IP1_24, A1),
+        PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
+        PINMUX_IPSR_GPSR(IP1_26, A3),
+        PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
+        PINMUX_IPSR_GPSR(IP1_27, A4),
+        PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
+        PINMUX_IPSR_GPSR(IP1_29_28, A5),
+        PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
+        PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
+        PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
+        PINMUX_IPSR_GPSR(IP1_31_30, A6),
+        PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
         PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
-        PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C),
+        PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
 
         /* IPSR2 */
-        PINMUX_IPSR_DATA(IP2_1_0, A7),
-        PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N),
+        PINMUX_IPSR_GPSR(IP2_1_0, A7),
+        PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
         PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
-        PINMUX_IPSR_DATA(IP2_3_2, A8),
+        PINMUX_IPSR_GPSR(IP2_3_2, A8),
         PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
         PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
-        PINMUX_IPSR_DATA(IP2_5_4, A9),
+        PINMUX_IPSR_GPSR(IP2_5_4, A9),
         PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
         PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
-        PINMUX_IPSR_DATA(IP2_7_6, A10),
+        PINMUX_IPSR_GPSR(IP2_7_6, A10),
         PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
         PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1),
-        PINMUX_IPSR_DATA(IP2_9_8, A11),
+        PINMUX_IPSR_GPSR(IP2_9_8, A11),
         PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
         PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1),
-        PINMUX_IPSR_DATA(IP2_11_10, A12),
+        PINMUX_IPSR_GPSR(IP2_11_10, A12),
         PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
         PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
-        PINMUX_IPSR_DATA(IP2_13_12, A13),
+        PINMUX_IPSR_GPSR(IP2_13_12, A13),
         PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
         PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
-        PINMUX_IPSR_DATA(IP2_15_14, A14),
+        PINMUX_IPSR_GPSR(IP2_15_14, A14),
         PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
         PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
-        PINMUX_IPSR_DATA(IP2_17_16, A15),
+        PINMUX_IPSR_GPSR(IP2_17_16, A15),
         PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
         PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
-        PINMUX_IPSR_DATA(IP2_20_18, A16),
+        PINMUX_IPSR_GPSR(IP2_20_18, A16),
         PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
         PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
         PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
         PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
         PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
-        PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B),
-        PINMUX_IPSR_DATA(IP2_23_21, A17),
+        PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
+        PINMUX_IPSR_GPSR(IP2_23_21, A17),
         PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
         PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
         PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
         PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
-        PINMUX_IPSR_DATA(IP2_26_24, A18),
+        PINMUX_IPSR_GPSR(IP2_26_24, A18),
         PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
         PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
         PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
         PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
-        PINMUX_IPSR_DATA(IP2_29_27, A19),
+        PINMUX_IPSR_GPSR(IP2_29_27, A19),
         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
-        PINMUX_IPSR_DATA(IP2_29_27, PWM4),
-        PINMUX_IPSR_DATA(IP2_29_27, TPUTO2),
-        PINMUX_IPSR_DATA(IP2_29_27, MOUT0),
-        PINMUX_IPSR_DATA(IP2_31_30, A20),
-        PINMUX_IPSR_DATA(IP2_31_30, SPCLK),
-        PINMUX_IPSR_DATA(IP2_29_27, MOUT1),
+        PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
+        PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
+        PINMUX_IPSR_GPSR(IP2_29_27, MOUT0),
+        PINMUX_IPSR_GPSR(IP2_31_30, A20),
+        PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
+        PINMUX_IPSR_GPSR(IP2_29_27, MOUT1),
 
         /* IPSR3 */
-        PINMUX_IPSR_DATA(IP3_1_0, A21),
-        PINMUX_IPSR_DATA(IP3_1_0, MOSI_IO0),
-        PINMUX_IPSR_DATA(IP3_1_0, MOUT2),
-        PINMUX_IPSR_DATA(IP3_3_2, A22),
-        PINMUX_IPSR_DATA(IP3_3_2, MISO_IO1),
-        PINMUX_IPSR_DATA(IP3_3_2, MOUT5),
-        PINMUX_IPSR_DATA(IP3_3_2, ATADIR1_N),
-        PINMUX_IPSR_DATA(IP3_5_4, A23),
-        PINMUX_IPSR_DATA(IP3_5_4, IO2),
-        PINMUX_IPSR_DATA(IP3_5_4, MOUT6),
-        PINMUX_IPSR_DATA(IP3_5_4, ATAWR1_N),
-        PINMUX_IPSR_DATA(IP3_7_6, A24),
-        PINMUX_IPSR_DATA(IP3_7_6, IO3),
-        PINMUX_IPSR_DATA(IP3_7_6, EX_WAIT2),
-        PINMUX_IPSR_DATA(IP3_9_8, A25),
-        PINMUX_IPSR_DATA(IP3_9_8, SSL),
-        PINMUX_IPSR_DATA(IP3_9_8, ATARD1_N),
-        PINMUX_IPSR_DATA(IP3_10, CS0_N),
-        PINMUX_IPSR_DATA(IP3_10, VI1_DATA8),
-        PINMUX_IPSR_DATA(IP3_11, CS1_N_A26),
-        PINMUX_IPSR_DATA(IP3_11, VI1_DATA9),
-        PINMUX_IPSR_DATA(IP3_12, EX_CS0_N),
-        PINMUX_IPSR_DATA(IP3_12, VI1_DATA10),
-        PINMUX_IPSR_DATA(IP3_14_13, EX_CS1_N),
-        PINMUX_IPSR_DATA(IP3_14_13, TPUTO3_B),
-        PINMUX_IPSR_DATA(IP3_14_13, SCIFB2_RXD),
-        PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11),
-        PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N),
-        PINMUX_IPSR_DATA(IP3_17_15, PWM0),
+        PINMUX_IPSR_GPSR(IP3_1_0, A21),
+        PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
+        PINMUX_IPSR_GPSR(IP3_1_0, MOUT2),
+        PINMUX_IPSR_GPSR(IP3_3_2, A22),
+        PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
+        PINMUX_IPSR_GPSR(IP3_3_2, MOUT5),
+        PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
+        PINMUX_IPSR_GPSR(IP3_5_4, A23),
+        PINMUX_IPSR_GPSR(IP3_5_4, IO2),
+        PINMUX_IPSR_GPSR(IP3_5_4, MOUT6),
+        PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
+        PINMUX_IPSR_GPSR(IP3_7_6, A24),
+        PINMUX_IPSR_GPSR(IP3_7_6, IO3),
+        PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
+        PINMUX_IPSR_GPSR(IP3_9_8, A25),
+        PINMUX_IPSR_GPSR(IP3_9_8, SSL),
+        PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
+        PINMUX_IPSR_GPSR(IP3_10, CS0_N),
+        PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
+        PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
+        PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
+        PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
+        PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
+        PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
+        PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
+        PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
+        PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
+        PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
+        PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
         PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
         PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
-        PINMUX_IPSR_DATA(IP3_17_15, TPUTO3),
-        PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD),
+        PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
+        PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
         PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
-        PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N),
+        PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
         PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
         PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
         PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
         PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
-        PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK),
+        PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
         PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
-        PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N),
+        PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
         PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
         PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
         PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
         PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
-        PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N),
+        PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
         PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
-        PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N),
+        PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
         PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
         PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
         PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
         PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
-        PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N),
+        PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
         PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
-        PINMUX_IPSR_DATA(IP3_29_27, BS_N),
-        PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
-        PINMUX_IPSR_DATA(IP3_29_27, PWM1_C),
-        PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C),
-        PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N),
+        PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
+        PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
+        PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
+        PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
+        PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
         PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
-        PINMUX_IPSR_DATA(IP3_30, RD_N),
-        PINMUX_IPSR_DATA(IP3_30, ATACS11_N),
-        PINMUX_IPSR_DATA(IP3_31, RD_WR_N),
-        PINMUX_IPSR_DATA(IP3_31, ATAG1_N),
+        PINMUX_IPSR_GPSR(IP3_30, RD_N),
+        PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
+        PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
+        PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
 
         /* IPSR4 */
-        PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0),
+        PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
         PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
         PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0),
-        PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0),
-        PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16),
+        PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0),
+        PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
+        PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
         PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
         PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
-        PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0),
-        PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1),
-        PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17),
+        PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0),
+        PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
+        PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
         PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
         PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
-        PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1),
-        PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2),
-        PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18),
-        PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE2),
-        PINMUX_IPSR_DATA(IP4_11_10, DU0_DR3),
-        PINMUX_IPSR_DATA(IP4_11_10, LCDOUT19),
-        PINMUX_IPSR_DATA(IP4_11_10, CC50_STATE3),
-        PINMUX_IPSR_DATA(IP4_13_12, DU0_DR4),
-        PINMUX_IPSR_DATA(IP4_13_12, LCDOUT20),
-        PINMUX_IPSR_DATA(IP4_13_12, CC50_STATE4),
-        PINMUX_IPSR_DATA(IP4_15_14, DU0_DR5),
-        PINMUX_IPSR_DATA(IP4_15_14, LCDOUT21),
-        PINMUX_IPSR_DATA(IP4_15_14, CC50_STATE5),
-        PINMUX_IPSR_DATA(IP4_17_16, DU0_DR6),
-        PINMUX_IPSR_DATA(IP4_17_16, LCDOUT22),
-        PINMUX_IPSR_DATA(IP4_17_16, CC50_STATE6),
-        PINMUX_IPSR_DATA(IP4_19_18, DU0_DR7),
-        PINMUX_IPSR_DATA(IP4_19_18, LCDOUT23),
-        PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7),
-        PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0),
-        PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8),
+        PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1),
+        PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
+        PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
+        PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2),
+        PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
+        PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
+        PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3),
+        PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
+        PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
+        PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4),
+        PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
+        PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
+        PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5),
+        PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
+        PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
+        PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6),
+        PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
+        PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
+        PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7),
+        PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
+        PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
         PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
         PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
-        PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8),
-        PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1),
-        PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9),
+        PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8),
+        PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
+        PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
         PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
         PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
-        PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9),
-        PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2),
-        PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10),
-        PINMUX_IPSR_DATA(IP4_27_26, CC50_STATE10),
-        PINMUX_IPSR_DATA(IP4_29_28, DU0_DG3),
-        PINMUX_IPSR_DATA(IP4_29_28, LCDOUT11),
-        PINMUX_IPSR_DATA(IP4_29_28, CC50_STATE11),
-        PINMUX_IPSR_DATA(IP4_31_30, DU0_DG4),
-        PINMUX_IPSR_DATA(IP4_31_30, LCDOUT12),
-        PINMUX_IPSR_DATA(IP4_31_30, CC50_STATE12),
+        PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9),
+        PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
+        PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
+        PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10),
+        PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
+        PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
+        PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11),
+        PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
+        PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
+        PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12),
 
         /* IPSR5 */
-        PINMUX_IPSR_DATA(IP5_1_0, DU0_DG5),
-        PINMUX_IPSR_DATA(IP5_1_0, LCDOUT13),
-        PINMUX_IPSR_DATA(IP5_1_0, CC50_STATE13),
-        PINMUX_IPSR_DATA(IP5_3_2, DU0_DG6),
-        PINMUX_IPSR_DATA(IP5_3_2, LCDOUT14),
-        PINMUX_IPSR_DATA(IP5_3_2, CC50_STATE14),
-        PINMUX_IPSR_DATA(IP5_5_4, DU0_DG7),
-        PINMUX_IPSR_DATA(IP5_5_4, LCDOUT15),
-        PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15),
-        PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0),
-        PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0),
+        PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
+        PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
+        PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13),
+        PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
+        PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
+        PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14),
+        PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
+        PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
+        PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15),
+        PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
+        PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
         PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
         PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
-        PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16),
-        PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1),
-        PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1),
+        PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16),
+        PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
+        PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
         PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
         PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
         PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
-        PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17),
-        PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2),
-        PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2),
-        PINMUX_IPSR_DATA(IP5_13_12, CC50_STATE18),
-        PINMUX_IPSR_DATA(IP5_15_14, DU0_DB3),
-        PINMUX_IPSR_DATA(IP5_15_14, LCDOUT3),
-        PINMUX_IPSR_DATA(IP5_15_14, CC50_STATE19),
-        PINMUX_IPSR_DATA(IP5_17_16, DU0_DB4),
-        PINMUX_IPSR_DATA(IP5_17_16, LCDOUT4),
-        PINMUX_IPSR_DATA(IP5_17_16, CC50_STATE20),
-        PINMUX_IPSR_DATA(IP5_19_18, DU0_DB5),
-        PINMUX_IPSR_DATA(IP5_19_18, LCDOUT5),
-        PINMUX_IPSR_DATA(IP5_19_18, CC50_STATE21),
-        PINMUX_IPSR_DATA(IP5_21_20, DU0_DB6),
-        PINMUX_IPSR_DATA(IP5_21_20, LCDOUT6),
-        PINMUX_IPSR_DATA(IP5_21_20, CC50_STATE22),
-        PINMUX_IPSR_DATA(IP5_23_22, DU0_DB7),
-        PINMUX_IPSR_DATA(IP5_23_22, LCDOUT7),
-        PINMUX_IPSR_DATA(IP5_23_22, CC50_STATE23),
-        PINMUX_IPSR_DATA(IP5_25_24, DU0_DOTCLKIN),
-        PINMUX_IPSR_DATA(IP5_25_24, QSTVA_QVS),
-        PINMUX_IPSR_DATA(IP5_25_24, CC50_STATE24),
-        PINMUX_IPSR_DATA(IP5_27_26, DU0_DOTCLKOUT0),
-        PINMUX_IPSR_DATA(IP5_27_26, QCLK),
-        PINMUX_IPSR_DATA(IP5_27_26, CC50_STATE25),
-        PINMUX_IPSR_DATA(IP5_29_28, DU0_DOTCLKOUT1),
-        PINMUX_IPSR_DATA(IP5_29_28, QSTVB_QVE),
-        PINMUX_IPSR_DATA(IP5_29_28, CC50_STATE26),
-        PINMUX_IPSR_DATA(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
-        PINMUX_IPSR_DATA(IP5_31_30, QSTH_QHS),
-        PINMUX_IPSR_DATA(IP5_31_30, CC50_STATE27),
+        PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17),
+        PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
+        PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
+        PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18),
+        PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
+        PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
+        PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19),
+        PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
+        PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
+        PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20),
+        PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
+        PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
+        PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21),
+        PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
+        PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
+        PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22),
+        PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
+        PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
+        PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23),
+        PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
+        PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
+        PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24),
+        PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
+        PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
+        PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25),
+        PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
+        PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
+        PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26),
+        PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
+        PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
+        PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27),
 
         /* IPSR6 */
-        PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
-        PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
-        PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
-        PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
-        PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
-        PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
-        PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
-        PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
-        PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
-        PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
-        PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
-        PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
-        PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
-        PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
-        PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
-        PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
-        PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
-        PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
-        PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
-        PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
-        PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
-        PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
-        PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
-        PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
-        PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
-        PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
-        PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
-        PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
-        PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
-        PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
+        PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
+        PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
+        PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28),
+        PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+        PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
+        PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29),
+        PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
+        PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
+        PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30),
+        PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
+        PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
+        PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31),
+        PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
+        PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
+        PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
+        PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
+        PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
+        PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
+        PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
+        PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
+        PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
+        PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
+        PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
+        PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
+        PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
+        PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
+        PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
+        PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
+        PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
+        PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
         PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
         PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
         PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
-        PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
-        PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
+        PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
+        PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
         PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
         PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
         PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
-        PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
-        PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
+        PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
+        PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
         PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
         PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
         PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
-        PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
-        PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
+        PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
+        PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
         PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
         PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
         PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
-        PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
+        PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
         PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
+        PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
         PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
         PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
-        PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
+        PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
         PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
 
         /* IPSR7 */
         PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
+        PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
         PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
         PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
-        PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
+        PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
         PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
         PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
+        PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
         PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
-        PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
+        PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
         PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
         PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
+        PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
-        PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
+        PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
         PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
         PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
+        PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
         PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
         PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
-        PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
+        PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
         PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
+        PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
         PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
         PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
-        PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
+        PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
         PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
         PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
+        PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
         PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
-        PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
+        PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
         PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
         PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
+        PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
         PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
         PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
-        PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
+        PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
         PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
         PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
+        PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
         PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
         PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
-        PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
+        PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
         PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
         PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
+        PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
         PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
-        PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
+        PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
         PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
         PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
+        PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
         PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
         PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
-        PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
+        PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
         PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
-        PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
-        PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
+        PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
+        PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
 
         /* IPSR8 */
         PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
-        PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
+        PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
         PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
         PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
-        PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
+        PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
         PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
         PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
-        PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
+        PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
         PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
         PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
-        PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
+        PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
         PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
-        PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
+        PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
         PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
         PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
-        PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
+        PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
         PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
-        PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
-        PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
+        PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
+        PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
         PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
         PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
-        PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
+        PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
-        PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
-        PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
+        PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
+        PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
         PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
         PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
-        PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
+        PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
         PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
         PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
         PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
+        PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
         PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
         PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
         PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
-        PINMUX_IPSR_DATA(IP8_19_17, PWM5),
+        PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
         PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
-        PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
+        PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
         PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
-        PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
+        PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
         PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
         PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
-        PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
+        PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
         PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
-        PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
+        PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
         PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
         PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
         PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
-        PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
-        PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
+        PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
+        PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
         PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
         PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
-        PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
+        PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
         PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
         PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
-        PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
-        PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
+        PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
+        PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
         PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
         PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
         PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
-        PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
+        PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
         PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
         PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
-        PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
+        PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
         PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
         PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
         PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
         PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
 
         /* IPSR9 */
-        PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD),
+        PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
         PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
         PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
-        PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3),
+        PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
         PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
         PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
         PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
         PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
-        PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK),
-        PINMUX_IPSR_DATA(IP9_5_3, IRQ0),
+        PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
+        PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
         PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
-        PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4),
+        PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
         PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
-        PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C),
-        PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC),
-        PINMUX_IPSR_DATA(IP9_8_6, PWM1),
+        PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
+        PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
+        PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
         PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
-        PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5),
+        PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
         PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
         PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
-        PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1),
+        PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
         PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
         PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
-        PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6),
+        PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
         PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
         PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
         PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
-        PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2),
+        PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
         PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
         PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
-        PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7),
+        PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
         PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
         PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
         PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
         PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
-        PINMUX_IPSR_DATA(IP9_16_15, PWM6),
-        PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0),
+        PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
+        PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
         PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
-        PINMUX_IPSR_DATA(IP9_18_17, TPUTO1),
-        PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1),
-        PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK),
-        PINMUX_IPSR_DATA(IP9_21_19, PWM2),
+        PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
+        PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
+        PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
+        PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
         PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
-        PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2),
+        PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
         PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
         PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
         PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
         PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
         PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
-        PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3),
+        PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
         PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
-        PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
-        PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32),
+        PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
+        PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32),
         PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
         PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
-        PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4),
+        PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
         PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
-        PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0),
-        PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33),
+        PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0),
+        PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33),
         PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP9_30_28, PWM3),
+        PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
         PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
-        PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5),
+        PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
         PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
-        PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK),
-        PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34),
+        PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK),
+        PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34),
 
         /* IPSR10 */
         PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
         PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
-        PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6),
+        PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
         PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
-        PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0),
-        PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35),
+        PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0),
+        PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35),
         PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
         PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
-        PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7),
+        PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
         PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
-        PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1),
-        PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36),
+        PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1),
+        PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36),
         PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
         PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
-        PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0),
+        PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
         PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
-        PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP),
-        PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2),
-        PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37),
+        PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP),
+        PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2),
+        PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37),
         PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
         PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
-        PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1),
+        PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
         PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
-        PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1),
-        PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3),
-        PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38),
+        PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1),
+        PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3),
+        PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38),
         PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
-        PINMUX_IPSR_DATA(IP10_14_12, IRQ1),
-        PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2),
+        PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
+        PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
         PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
-        PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN),
-        PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4),
-        PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39),
+        PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN),
+        PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4),
+        PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39),
         PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
-        PINMUX_IPSR_DATA(IP10_17_15, IRQ2),
+        PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
         PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
-        PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3),
+        PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
         PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
-        PINMUX_IPSR_DATA(IP10_17_15, TANS2),
-        PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5),
-        PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT),
+        PINMUX_IPSR_GPSR(IP10_17_15, TANS2),
+        PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5),
+        PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT),
         PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
         PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
         PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
-        PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4),
+        PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
         PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
         PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
-        PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6),
+        PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6),
         PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
         PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
         PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
         PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
-        PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5),
+        PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
         PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
         PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
-        PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7),
+        PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7),
         PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
         PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
         PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
-        PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6),
+        PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
         PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
         PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
-        PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8),
+        PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8),
         PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
         PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
-        PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7),
+        PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
         PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
-        PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9),
+        PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9),
         PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
         PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
-        PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN),
-        PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10),
+        PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
+        PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10),
 
         /* IPSR11 */
         PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
         PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
         PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
-        PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
-        PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
+        PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
+        PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11),
         PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
         PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
         PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
-        PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
-        PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
+        PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
+        PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12),
         PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
         PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
-        PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
-        PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
+        PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
+        PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13),
         PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
         PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
         PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
-        PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
-        PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
+        PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
+        PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14),
         PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
         PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
         PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
-        PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
+        PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15),
         PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
         PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
         PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
-        PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
+        PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
         PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
         PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
         PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
-        PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
+        PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
         PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
         PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
-        PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
+        PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
         PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
         PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
-        PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
-        PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
+        PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N),
+        PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
         PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
         PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
         PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
-        PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
+        PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N),
+        PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
         PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
         PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
         PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
+        PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
         PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
-        PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
+        PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
         PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
 
         /* IPSR12 */
-        PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34),
+        PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
         PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
         PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
         PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
         PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
-        PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34),
+        PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
         PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
         PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
         PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
         PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
-        PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3),
+        PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
         PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
         PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
         PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
         PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
-        PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N),
+        PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
         PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
-        PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK),
+        PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
         PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
-        PINMUX_IPSR_DATA(IP12_10_9, IRD_TX),
+        PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX),
         PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
-        PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG),
+        PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
         PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
-        PINMUX_IPSR_DATA(IP12_12_11, IRD_RX),
+        PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX),
         PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
-        PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT),
+        PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
         PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
-        PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK),
+        PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK),
         PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
         PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP12_17_15, PWM1_B),
-        PINMUX_IPSR_DATA(IP12_17_15, IRQ9),
+        PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
+        PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
         PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
-        PINMUX_IPSR_DATA(IP12_17_15, DACK2),
+        PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
         PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
         PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
         PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
         PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
-        PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK),
+        PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
         PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
         PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
         PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
         PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
         PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
         PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
-        PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0),
+        PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
         PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
         PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
         PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
         PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
         PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1),
+        PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
         PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
-        PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N),
+        PINMUX_IPSR_GPSR(IP12_26_24, ATAG0_N),
         PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
         PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
         PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2),
+        PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
         PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
-        PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N),
+        PINMUX_IPSR_GPSR(IP12_29_27, ATAWR0_N),
         PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
 
         /* IPSR13 */
         PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
         PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
-        PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3),
+        PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
         PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
-        PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N),
+        PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
         PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
         PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
         PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
-        PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4),
+        PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
         PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
-        PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N),
+        PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
         PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
         PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
         PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
-        PINMUX_IPSR_DATA(IP13_8_6, PWM2_B),
-        PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5),
+        PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
+        PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
         PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
-        PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1),
+        PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
         PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
         PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
         PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
         PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
-        PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6),
-        PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N),
+        PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
+        PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
         PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
         PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
         PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
         PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
-        PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7),
-        PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N),
+        PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
+        PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
         PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
         PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
         PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
         PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
-        PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB),
+        PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
         PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
         PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
         PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
         PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
         PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
         PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
-        PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD),
+        PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
         PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
         PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
         PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
@@ -1472,7 +1472,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
         PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
         PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
-        PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N),
+        PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
         PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
         PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
         PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
@@ -1480,7 +1480,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
         PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
         PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
-        PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N),
+        PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
         PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
         PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
         PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
@@ -1491,6 +1491,197 @@ static const struct sh_pfc_pin pinmux_pins[] = {
         PINMUX_GPIO_GP_ALL(),
 };
 
+/* - Audio Clock ------------------------------------------------------------ */
+static const unsigned int audio_clka_pins[] = {
+        /* CLKA */
+        RCAR_GP_PIN(5, 20),
+};
+static const unsigned int audio_clka_mux[] = {
+        AUDIO_CLKA_MARK,
+};
+static const unsigned int audio_clka_b_pins[] = {
+        /* CLKA */
+        RCAR_GP_PIN(3, 25),
+};
+static const unsigned int audio_clka_b_mux[] = {
+        AUDIO_CLKA_B_MARK,
+};
+static const unsigned int audio_clka_c_pins[] = {
+        /* CLKA */
+        RCAR_GP_PIN(4, 20),
+};
+static const unsigned int audio_clka_c_mux[] = {
+        AUDIO_CLKA_C_MARK,
+};
+static const unsigned int audio_clka_d_pins[] = {
+        /* CLKA */
+        RCAR_GP_PIN(5, 0),
+};
+static const unsigned int audio_clka_d_mux[] = {
+        AUDIO_CLKA_D_MARK,
+};
+static const unsigned int audio_clkb_pins[] = {
+        /* CLKB */
+        RCAR_GP_PIN(5, 21),
+};
+static const unsigned int audio_clkb_mux[] = {
+        AUDIO_CLKB_MARK,
+};
+static const unsigned int audio_clkb_b_pins[] = {
+        /* CLKB */
+        RCAR_GP_PIN(3, 26),
+};
+static const unsigned int audio_clkb_b_mux[] = {
+        AUDIO_CLKB_B_MARK,
+};
+static const unsigned int audio_clkb_c_pins[] = {
+        /* CLKB */
+        RCAR_GP_PIN(4, 21),
+};
+static const unsigned int audio_clkb_c_mux[] = {
+        AUDIO_CLKB_C_MARK,
+};
+static const unsigned int audio_clkc_pins[] = {
+        /* CLKC */
+        RCAR_GP_PIN(5, 22),
+};
+static const unsigned int audio_clkc_mux[] = {
+        AUDIO_CLKC_MARK,
+};
+static const unsigned int audio_clkc_b_pins[] = {
+        /* CLKC */
+        RCAR_GP_PIN(3, 29),
+};
+static const unsigned int audio_clkc_b_mux[] = {
+        AUDIO_CLKC_B_MARK,
+};
+static const unsigned int audio_clkc_c_pins[] = {
+        /* CLKC */
+        RCAR_GP_PIN(4, 22),
+};
+static const unsigned int audio_clkc_c_mux[] = {
+        AUDIO_CLKC_C_MARK,
+};
+static const unsigned int audio_clkout_pins[] = {
+        /* CLKOUT */
+        RCAR_GP_PIN(5, 23),
+};
+static const unsigned int audio_clkout_mux[] = {
+        AUDIO_CLKOUT_MARK,
+};
+static const unsigned int audio_clkout_b_pins[] = {
+        /* CLKOUT */
+        RCAR_GP_PIN(3, 12),
+};
+static const unsigned int audio_clkout_b_mux[] = {
+        AUDIO_CLKOUT_B_MARK,
+};
+static const unsigned int audio_clkout_c_pins[] = {
+        /* CLKOUT */
+        RCAR_GP_PIN(4, 23),
+};
+static const unsigned int audio_clkout_c_mux[] = {
+        AUDIO_CLKOUT_C_MARK,
+};
+/* - AVB -------------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+        RCAR_GP_PIN(3, 26),
+};
+static const unsigned int avb_link_mux[] = {
+        AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+        RCAR_GP_PIN(3, 27),
+};
+static const unsigned int avb_magic_mux[] = {
+        AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+        RCAR_GP_PIN(3, 28),
+};
+static const unsigned int avb_phy_int_mux[] = {
+        AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdio_pins[] = {
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int avb_mdio_mux[] = {
+        AVB_MDC_MARK, AVB_MDIO_MARK,
+};
+static const unsigned int avb_mii_pins[] = {
+        RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+        RCAR_GP_PIN(3, 17),
+
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+        RCAR_GP_PIN(3, 5),
+
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+        RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
+        RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int avb_mii_mux[] = {
+        AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+        AVB_TXD3_MARK,
+
+        AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+        AVB_RXD3_MARK,
+
+        AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+        AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
+        AVB_TX_CLK_MARK, AVB_COL_MARK,
+};
+static const unsigned int avb_gmii_pins[] = {
+        RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+        RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+        RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+        RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+        RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+        RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
+        RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
+        RCAR_GP_PIN(3, 11),
+};
+static const unsigned int avb_gmii_mux[] = {
+        AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+        AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
+        AVB_TXD6_MARK, AVB_TXD7_MARK,
+
+        AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+        AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
+        AVB_RXD6_MARK, AVB_RXD7_MARK,
+
+        AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+        AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
+        AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
+        AVB_COL_MARK,
+};
+static const unsigned int avb_avtp_capture_pins[] = {
+        RCAR_GP_PIN(5, 11),
+};
+static const unsigned int avb_avtp_capture_mux[] = {
+        AVB_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb_avtp_match_pins[] = {
+        RCAR_GP_PIN(5, 12),
+};
+static const unsigned int avb_avtp_match_mux[] = {
+        AVB_AVTP_MATCH_MARK,
+};
+static const unsigned int avb_avtp_capture_b_pins[] = {
+        RCAR_GP_PIN(1, 1),
+};
+static const unsigned int avb_avtp_capture_b_mux[] = {
+        AVB_AVTP_CAPTURE_B_MARK,
+};
+static const unsigned int avb_avtp_match_b_pins[] = {
+        RCAR_GP_PIN(1, 2),
+};
+static const unsigned int avb_avtp_match_b_mux[] = {
+        AVB_AVTP_MATCH_B_MARK,
+};
 /* - ETH -------------------------------------------------------------------- */
 static const unsigned int eth_link_pins[] = {
         /* LINK */
@@ -2751,6 +2942,245 @@ static const unsigned int sdhi2_wp_pins[] = {
 static const unsigned int sdhi2_wp_mux[] = {
         SD2_WP_MARK,
 };
+/* - SSI -------------------------------------------------------------------- */
+static const unsigned int ssi0_data_pins[] = {
+        /* SDATA0 */
+        RCAR_GP_PIN(5, 3),
+};
+static const unsigned int ssi0_data_mux[] = {
+        SSI_SDATA0_MARK,
+};
+static const unsigned int ssi0129_ctrl_pins[] = {
+        /* SCK0129, WS0129 */
+        RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int ssi0129_ctrl_mux[] = {
+        SSI_SCK0129_MARK, SSI_WS0129_MARK,
+};
+static const unsigned int ssi1_data_pins[] = {
+        /* SDATA1 */
+        RCAR_GP_PIN(5, 13),
+};
+static const unsigned int ssi1_data_mux[] = {
+        SSI_SDATA1_MARK,
+};
+static const unsigned int ssi1_ctrl_pins[] = {
+        /* SCK1, WS1 */
+        RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
+};
+static const unsigned int ssi1_ctrl_mux[] = {
+        SSI_SCK1_MARK, SSI_WS1_MARK,
+};
+static const unsigned int ssi1_data_b_pins[] = {
+        /* SDATA1 */
+        RCAR_GP_PIN(4, 13),
+};
+static const unsigned int ssi1_data_b_mux[] = {
+        SSI_SDATA1_B_MARK,
+};
+static const unsigned int ssi1_ctrl_b_pins[] = {
+        /* SCK1, WS1 */
+        RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+};
+static const unsigned int ssi1_ctrl_b_mux[] = {
+        SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
+};
+static const unsigned int ssi2_data_pins[] = {
+        /* SDATA2 */
+        RCAR_GP_PIN(5, 16),
+};
+static const unsigned int ssi2_data_mux[] = {
+        SSI_SDATA2_MARK,
+};
+static const unsigned int ssi2_ctrl_pins[] = {
+        /* SCK2, WS2 */
+        RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+};
+static const unsigned int ssi2_ctrl_mux[] = {
+        SSI_SCK2_MARK, SSI_WS2_MARK,
+};
+static const unsigned int ssi2_data_b_pins[] = {
+        /* SDATA2 */
+        RCAR_GP_PIN(4, 16),
+};
+static const unsigned int ssi2_data_b_mux[] = {
+        SSI_SDATA2_B_MARK,
+};
+static const unsigned int ssi2_ctrl_b_pins[] = {
+        /* SCK2, WS2 */
+        RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+};
+static const unsigned int ssi2_ctrl_b_mux[] = {
+        SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
+};
+static const unsigned int ssi3_data_pins[] = {
+        /* SDATA3 */
+        RCAR_GP_PIN(5, 6),
+};
+static const unsigned int ssi3_data_mux[] = {
+        SSI_SDATA3_MARK
+};
+static const unsigned int ssi34_ctrl_pins[] = {
+        /* SCK34, WS34 */
+        RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
+};
+static const unsigned int ssi34_ctrl_mux[] = {
+        SSI_SCK34_MARK, SSI_WS34_MARK,
+};
+static const unsigned int ssi4_data_pins[] = {
+        /* SDATA4 */
+        RCAR_GP_PIN(5, 9),
+};
+static const unsigned int ssi4_data_mux[] = {
+        SSI_SDATA4_MARK,
+};
+static const unsigned int ssi4_ctrl_pins[] = {
+        /* SCK4, WS4 */
+        RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+};
+static const unsigned int ssi4_ctrl_mux[] = {
+        SSI_SCK4_MARK, SSI_WS4_MARK,
+};
+static const unsigned int ssi4_data_b_pins[] = {
+        /* SDATA4 */
+        RCAR_GP_PIN(4, 22),
+};
+static const unsigned int ssi4_data_b_mux[] = {
+        SSI_SDATA4_B_MARK,
+};
+static const unsigned int ssi4_ctrl_b_pins[] = {
+        /* SCK4, WS4 */
+        RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int ssi4_ctrl_b_mux[] = {
+        SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
+};
+static const unsigned int ssi5_data_pins[] = {
+        /* SDATA5 */
+        RCAR_GP_PIN(4, 26),
+};
+static const unsigned int ssi5_data_mux[] = {
+        SSI_SDATA5_MARK,
+};
+static const unsigned int ssi5_ctrl_pins[] = {
+        /* SCK5, WS5 */
+        RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
+};
+static const unsigned int ssi5_ctrl_mux[] = {
+        SSI_SCK5_MARK, SSI_WS5_MARK,
+};
+static const unsigned int ssi5_data_b_pins[] = {
+        /* SDATA5 */
+        RCAR_GP_PIN(3, 21),
+};
+static const unsigned int ssi5_data_b_mux[] = {
+        SSI_SDATA5_B_MARK,
+};
+static const unsigned int ssi5_ctrl_b_pins[] = {
+        /* SCK5, WS5 */
+        RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
+};
+static const unsigned int ssi5_ctrl_b_mux[] = {
+        SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
+};
+static const unsigned int ssi6_data_pins[] = {
+        /* SDATA6 */
+        RCAR_GP_PIN(4, 29),
+};
+static const unsigned int ssi6_data_mux[] = {
+        SSI_SDATA6_MARK,
+};
+static const unsigned int ssi6_ctrl_pins[] = {
+        /* SCK6, WS6 */
+        RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
+};
+static const unsigned int ssi6_ctrl_mux[] = {
+        SSI_SCK6_MARK, SSI_WS6_MARK,
+};
+static const unsigned int ssi6_data_b_pins[] = {
+        /* SDATA6 */
+        RCAR_GP_PIN(3, 24),
+};
+static const unsigned int ssi6_data_b_mux[] = {
+        SSI_SDATA6_B_MARK,
+};
+static const unsigned int ssi6_ctrl_b_pins[] = {
+        /* SCK6, WS6 */
+        RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+};
+static const unsigned int ssi6_ctrl_b_mux[] = {
+        SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
+};
+static const unsigned int ssi7_data_pins[] = {
+        /* SDATA7 */
+        RCAR_GP_PIN(5, 0),
+};
+static const unsigned int ssi7_data_mux[] = {
+        SSI_SDATA7_MARK,
+};
+static const unsigned int ssi78_ctrl_pins[] = {
+        /* SCK78, WS78 */
+        RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
+};
+static const unsigned int ssi78_ctrl_mux[] = {
+        SSI_SCK78_MARK, SSI_WS78_MARK,
+};
+static const unsigned int ssi7_data_b_pins[] = {
+        /* SDATA7 */
+        RCAR_GP_PIN(3, 27),
+};
+static const unsigned int ssi7_data_b_mux[] = {
+        SSI_SDATA7_B_MARK,
+};
+static const unsigned int ssi78_ctrl_b_pins[] = {
+        /* SCK78, WS78 */
+        RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int ssi78_ctrl_b_mux[] = {
+        SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
+};
+static const unsigned int ssi8_data_pins[] = {
+        /* SDATA8 */
+        RCAR_GP_PIN(5, 10),
+};
+static const unsigned int ssi8_data_mux[] = {
+        SSI_SDATA8_MARK,
+};
+static const unsigned int ssi8_data_b_pins[] = {
+        /* SDATA8 */
+        RCAR_GP_PIN(3, 28),
+};
+static const unsigned int ssi8_data_b_mux[] = {
+        SSI_SDATA8_B_MARK,
+};
+static const unsigned int ssi9_data_pins[] = {
+        /* SDATA9 */
+        RCAR_GP_PIN(5, 19),
+};
+static const unsigned int ssi9_data_mux[] = {
+        SSI_SDATA9_MARK,
+};
+static const unsigned int ssi9_ctrl_pins[] = {
+        /* SCK9, WS9 */
+        RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
+};
+static const unsigned int ssi9_ctrl_mux[] = {
+        SSI_SCK9_MARK, SSI_WS9_MARK,
+};
+static const unsigned int ssi9_data_b_pins[] = {
+        /* SDATA9 */
+        RCAR_GP_PIN(4, 19),
+};
+static const unsigned int ssi9_data_b_mux[] = {
+        SSI_SDATA9_B_MARK,
+};
+static const unsigned int ssi9_ctrl_b_pins[] = {
+        /* SCK9, WS9 */
+        RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
+};
+static const unsigned int ssi9_ctrl_b_mux[] = {
+        SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
+};
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
         RCAR_GP_PIN(5, 24), /* PWEN */
@@ -2911,6 +3341,29 @@ static const unsigned int vin1_clk_mux[] = {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(audio_clka),
+        SH_PFC_PIN_GROUP(audio_clka_b),
+        SH_PFC_PIN_GROUP(audio_clka_c),
+        SH_PFC_PIN_GROUP(audio_clka_d),
+        SH_PFC_PIN_GROUP(audio_clkb),
+        SH_PFC_PIN_GROUP(audio_clkb_b),
+        SH_PFC_PIN_GROUP(audio_clkb_c),
+        SH_PFC_PIN_GROUP(audio_clkc),
+        SH_PFC_PIN_GROUP(audio_clkc_b),
+        SH_PFC_PIN_GROUP(audio_clkc_c),
+        SH_PFC_PIN_GROUP(audio_clkout),
+        SH_PFC_PIN_GROUP(audio_clkout_b),
+        SH_PFC_PIN_GROUP(audio_clkout_c),
+        SH_PFC_PIN_GROUP(avb_link),
+        SH_PFC_PIN_GROUP(avb_magic),
+        SH_PFC_PIN_GROUP(avb_phy_int),
+        SH_PFC_PIN_GROUP(avb_mdio),
+        SH_PFC_PIN_GROUP(avb_mii),
+        SH_PFC_PIN_GROUP(avb_gmii),
+        SH_PFC_PIN_GROUP(avb_avtp_capture),
+        SH_PFC_PIN_GROUP(avb_avtp_match),
+        SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+        SH_PFC_PIN_GROUP(avb_avtp_match_b),
         SH_PFC_PIN_GROUP(eth_link),
         SH_PFC_PIN_GROUP(eth_magic),
         SH_PFC_PIN_GROUP(eth_mdio),
@@ -3084,6 +3537,40 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_ctrl),
         SH_PFC_PIN_GROUP(sdhi2_cd),
         SH_PFC_PIN_GROUP(sdhi2_wp),
+        SH_PFC_PIN_GROUP(ssi0_data),
+        SH_PFC_PIN_GROUP(ssi0129_ctrl),
+        SH_PFC_PIN_GROUP(ssi1_data),
+        SH_PFC_PIN_GROUP(ssi1_ctrl),
+        SH_PFC_PIN_GROUP(ssi1_data_b),
+        SH_PFC_PIN_GROUP(ssi1_ctrl_b),
+        SH_PFC_PIN_GROUP(ssi2_data),
+        SH_PFC_PIN_GROUP(ssi2_ctrl),
+        SH_PFC_PIN_GROUP(ssi2_data_b),
+        SH_PFC_PIN_GROUP(ssi2_ctrl_b),
+        SH_PFC_PIN_GROUP(ssi3_data),
+        SH_PFC_PIN_GROUP(ssi34_ctrl),
+        SH_PFC_PIN_GROUP(ssi4_data),
+        SH_PFC_PIN_GROUP(ssi4_ctrl),
+        SH_PFC_PIN_GROUP(ssi4_data_b),
+        SH_PFC_PIN_GROUP(ssi4_ctrl_b),
+        SH_PFC_PIN_GROUP(ssi5_data),
+        SH_PFC_PIN_GROUP(ssi5_ctrl),
+        SH_PFC_PIN_GROUP(ssi5_data_b),
+        SH_PFC_PIN_GROUP(ssi5_ctrl_b),
+        SH_PFC_PIN_GROUP(ssi6_data),
+        SH_PFC_PIN_GROUP(ssi6_ctrl),
+        SH_PFC_PIN_GROUP(ssi6_data_b),
+        SH_PFC_PIN_GROUP(ssi6_ctrl_b),
+        SH_PFC_PIN_GROUP(ssi7_data),
+        SH_PFC_PIN_GROUP(ssi78_ctrl),
+        SH_PFC_PIN_GROUP(ssi7_data_b),
+        SH_PFC_PIN_GROUP(ssi78_ctrl_b),
+        SH_PFC_PIN_GROUP(ssi8_data),
+        SH_PFC_PIN_GROUP(ssi8_data_b),
+        SH_PFC_PIN_GROUP(ssi9_data),
+        SH_PFC_PIN_GROUP(ssi9_ctrl),
+        SH_PFC_PIN_GROUP(ssi9_data_b),
+        SH_PFC_PIN_GROUP(ssi9_ctrl_b),
         SH_PFC_PIN_GROUP(usb0),
         SH_PFC_PIN_GROUP(usb1),
         VIN_DATA_PIN_GROUP(vin0_data, 24),
@@ -3106,6 +3593,35 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(vin1_clk),
 };
 
+static const char * const audio_clk_groups[] = {
+        "audio_clka",
+        "audio_clka_b",
+        "audio_clka_c",
+        "audio_clka_d",
+        "audio_clkb",
+        "audio_clkb_b",
+        "audio_clkb_c",
+        "audio_clkc",
+        "audio_clkc_b",
+        "audio_clkc_c",
+        "audio_clkout",
+        "audio_clkout_b",
+        "audio_clkout_c",
+};
+
+static const char * const avb_groups[] = {
+        "avb_link",
+        "avb_magic",
+        "avb_phy_int",
+        "avb_mdio",
+        "avb_mii",
+        "avb_gmii",
+        "avb_avtp_capture",
+        "avb_avtp_match",
+        "avb_avtp_capture_b",
+        "avb_avtp_match_b",
+};
+
 static const char * const eth_groups[] = {
         "eth_link",
         "eth_magic",
@@ -3381,6 +3897,43 @@ static const char * const sdhi2_groups[] = {
         "sdhi2_wp",
 };
 
+static const char * const ssi_groups[] = {
+        "ssi0_data",
+        "ssi0129_ctrl",
+        "ssi1_data",
+        "ssi1_ctrl",
+        "ssi1_data_b",
+        "ssi1_ctrl_b",
+        "ssi2_data",
+        "ssi2_ctrl",
+        "ssi2_data_b",
+        "ssi2_ctrl_b",
+        "ssi3_data",
+        "ssi34_ctrl",
+        "ssi4_data",
+        "ssi4_ctrl",
+        "ssi4_data_b",
+        "ssi4_ctrl_b",
+        "ssi5_data",
+        "ssi5_ctrl",
+        "ssi5_data_b",
+        "ssi5_ctrl_b",
+        "ssi6_data",
+        "ssi6_ctrl",
+        "ssi6_data_b",
+        "ssi6_ctrl_b",
+        "ssi7_data",
+        "ssi78_ctrl",
+        "ssi7_data_b",
+        "ssi78_ctrl_b",
+        "ssi8_data",
+        "ssi8_data_b",
+        "ssi9_data",
+        "ssi9_ctrl",
+        "ssi9_data_b",
+        "ssi9_ctrl_b",
+};
+
 static const char * const usb0_groups[] = {
         "usb0",
 };
@@ -3414,6 +3967,8 @@ static const char * const vin1_groups[] = {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(audio_clk),
+        SH_PFC_FUNCTION(avb),
         SH_PFC_FUNCTION(eth),
         SH_PFC_FUNCTION(hscif0),
         SH_PFC_FUNCTION(hscif1),
@@ -3448,6 +4003,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(ssi),
         SH_PFC_FUNCTION(usb0),
         SH_PFC_FUNCTION(usb1),
         SH_PFC_FUNCTION(vin0),
@@ -3974,6 +4530,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
                 /* IP6_3_2 [2] */
                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
+                0,
                 /* IP6_1_0 [2] */
                 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
         },
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index ce4f5cdb0579..5979dabc02fa 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -189,8 +189,8 @@
 #define GPSR6_4         F_(SSI_SDATA2_A,        IP14_7_4)
 #define GPSR6_3         F_(SSI_SDATA1_A,        IP14_3_0)
 #define GPSR6_2         F_(SSI_SDATA0,          IP13_31_28)
-#define GPSR6_1         F_(SSI_WS0129,          IP13_27_24)
-#define GPSR6_0         F_(SSI_SCK0129,         IP13_23_20)
+#define GPSR6_1         F_(SSI_WS01239,         IP13_27_24)
+#define GPSR6_0         F_(SSI_SCK01239,        IP13_23_20)
 
 /* GPSR7 */
 #define GPSR7_3         FM(HDMI1_CEC)
@@ -315,8 +315,8 @@
 #define IP13_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP13_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP13_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_23_20      FM(SSI_SCK0129)         F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_27_24      FM(SSI_WS0129)          F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP13_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP14_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP14_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -478,7 +478,6 @@ FM(IP16_31_28)	IP16_31_28
 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
-#define MOD_SEL2_2_1            FM(SEL_VSP_0)           FM(SEL_VSP_1)           FM(SEL_VSP_2)           FM(SEL_VSP_3)
 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 
 #define PINMUX_MOD_SELS\
@@ -512,7 +511,7 @@ MOD_SEL0_7_6 \
 MOD_SEL0_5_4            MOD_SEL1_5 \
                         MOD_SEL1_4 \
 MOD_SEL0_3              MOD_SEL1_3 \
-MOD_SEL0_2_1            MOD_SEL1_2              MOD_SEL2_2_1 \
+MOD_SEL0_2_1            MOD_SEL1_2 \
                         MOD_SEL1_1 \
                         MOD_SEL1_0              MOD_SEL2_0
 
@@ -569,18 +568,18 @@ static const u16 pinmux_data[] = {
         PINMUX_SINGLE(SSI_WS5),
 
         /* IPSR0 */
-        PINMUX_IPSR_DATA(IP0_3_0,       AVB_MDC),
+        PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 
-        PINMUX_IPSR_DATA(IP0_7_4,       AVB_MAGIC),
+        PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 
-        PINMUX_IPSR_DATA(IP0_11_8,      AVB_PHY_INT),
+        PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 
-        PINMUX_IPSR_DATA(IP0_15_12,     AVB_LINK),
+        PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 
@@ -592,126 +591,126 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_TANS_A,          SEL_SCIF4_0),
 
-        PINMUX_IPSR_DATA(IP0_27_24,     IRQ0),
-        PINMUX_IPSR_DATA(IP0_27_24,     QPOLB),
-        PINMUX_IPSR_DATA(IP0_27_24,     DU_CDE),
+        PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
+        PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
+        PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 
-        PINMUX_IPSR_DATA(IP0_31_28,     IRQ1),
-        PINMUX_IPSR_DATA(IP0_31_28,     QPOLA),
-        PINMUX_IPSR_DATA(IP0_31_28,     DU_DISP),
+        PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
+        PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
+        PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 
         /* IPSR1 */
-        PINMUX_IPSR_DATA(IP1_3_0,       IRQ2),
-        PINMUX_IPSR_DATA(IP1_3_0,       QCPV_QDE),
-        PINMUX_IPSR_DATA(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
+        PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
+        PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
+        PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 
-        PINMUX_IPSR_DATA(IP1_7_4,       IRQ3),
-        PINMUX_IPSR_DATA(IP1_7_4,       QSTVB_QVE),
-        PINMUX_IPSR_DATA(IP1_7_4,       A25),
-        PINMUX_IPSR_DATA(IP1_7_4,       DU_DOTCLKOUT1),
+        PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
+        PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
+        PINMUX_IPSR_GPSR(IP1_7_4,       A25),
+        PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 
-        PINMUX_IPSR_DATA(IP1_11_8,      IRQ4),
-        PINMUX_IPSR_DATA(IP1_11_8,      QSTH_QHS),
-        PINMUX_IPSR_DATA(IP1_11_8,      A24),
-        PINMUX_IPSR_DATA(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
+        PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
+        PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
+        PINMUX_IPSR_GPSR(IP1_11_8,      A24),
+        PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 
-        PINMUX_IPSR_DATA(IP1_15_12,     IRQ5),
-        PINMUX_IPSR_DATA(IP1_15_12,     QSTB_QHE),
-        PINMUX_IPSR_DATA(IP1_15_12,     A23),
-        PINMUX_IPSR_DATA(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
+        PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
+        PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
+        PINMUX_IPSR_GPSR(IP1_15_12,     A23),
+        PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 
-        PINMUX_IPSR_DATA(IP1_19_16,     PWM0),
-        PINMUX_IPSR_DATA(IP1_19_16,     AVB_AVTP_PPS),
-        PINMUX_IPSR_DATA(IP1_19_16,     A22),
+        PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
+        PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
+        PINMUX_IPSR_GPSR(IP1_19_16,     A22),
         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 
         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
-        PINMUX_IPSR_DATA(IP1_23_20,     A21),
+        PINMUX_IPSR_GPSR(IP1_23_20,     A21),
         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 
         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
-        PINMUX_IPSR_DATA(IP1_27_24,     A20),
+        PINMUX_IPSR_GPSR(IP1_27_24,     A20),
         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 
-        PINMUX_IPSR_DATA(IP1_31_28,     A0),
-        PINMUX_IPSR_DATA(IP1_31_28,     LCDOUT16),
+        PINMUX_IPSR_GPSR(IP1_31_28,     A0),
+        PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
-        PINMUX_IPSR_DATA(IP1_31_28,     VI4_DATA8),
-        PINMUX_IPSR_DATA(IP1_31_28,     DU_DB0),
+        PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
+        PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 
         /* IPSR2 */
-        PINMUX_IPSR_DATA(IP2_3_0,       A1),
-        PINMUX_IPSR_DATA(IP2_3_0,       LCDOUT17),
+        PINMUX_IPSR_GPSR(IP2_3_0,       A1),
+        PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
-        PINMUX_IPSR_DATA(IP2_3_0,       VI4_DATA9),
-        PINMUX_IPSR_DATA(IP2_3_0,       DU_DB1),
+        PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
+        PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 
-        PINMUX_IPSR_DATA(IP2_7_4,       A2),
-        PINMUX_IPSR_DATA(IP2_7_4,       LCDOUT18),
+        PINMUX_IPSR_GPSR(IP2_7_4,       A2),
+        PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
-        PINMUX_IPSR_DATA(IP2_7_4,       VI4_DATA10),
-        PINMUX_IPSR_DATA(IP2_7_4,       DU_DB2),
+        PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
+        PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 
-        PINMUX_IPSR_DATA(IP2_11_8,      A3),
-        PINMUX_IPSR_DATA(IP2_11_8,      LCDOUT19),
+        PINMUX_IPSR_GPSR(IP2_11_8,      A3),
+        PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
-        PINMUX_IPSR_DATA(IP2_11_8,      VI4_DATA11),
-        PINMUX_IPSR_DATA(IP2_11_8,      DU_DB3),
+        PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
+        PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 
-        PINMUX_IPSR_DATA(IP2_15_12,     A4),
-        PINMUX_IPSR_DATA(IP2_15_12,     LCDOUT20),
+        PINMUX_IPSR_GPSR(IP2_15_12,     A4),
+        PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
-        PINMUX_IPSR_DATA(IP2_15_12,     VI4_DATA12),
-        PINMUX_IPSR_DATA(IP2_15_12,     VI5_DATA12),
-        PINMUX_IPSR_DATA(IP2_15_12,     DU_DB4),
+        PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
+        PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
+        PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 
-        PINMUX_IPSR_DATA(IP2_19_16,     A5),
-        PINMUX_IPSR_DATA(IP2_19_16,     LCDOUT21),
+        PINMUX_IPSR_GPSR(IP2_19_16,     A5),
+        PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
-        PINMUX_IPSR_DATA(IP2_19_16,     VI4_DATA13),
-        PINMUX_IPSR_DATA(IP2_19_16,     VI5_DATA13),
-        PINMUX_IPSR_DATA(IP2_19_16,     DU_DB5),
+        PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
+        PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
+        PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 
-        PINMUX_IPSR_DATA(IP2_23_20,     A6),
-        PINMUX_IPSR_DATA(IP2_23_20,     LCDOUT22),
+        PINMUX_IPSR_GPSR(IP2_23_20,     A6),
+        PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
-        PINMUX_IPSR_DATA(IP2_23_20,     VI4_DATA14),
-        PINMUX_IPSR_DATA(IP2_23_20,     VI5_DATA14),
-        PINMUX_IPSR_DATA(IP2_23_20,     DU_DB6),
+        PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
+        PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
+        PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 
-        PINMUX_IPSR_DATA(IP2_27_24,     A7),
-        PINMUX_IPSR_DATA(IP2_27_24,     LCDOUT23),
+        PINMUX_IPSR_GPSR(IP2_27_24,     A7),
+        PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
-        PINMUX_IPSR_DATA(IP2_27_24,     VI4_DATA15),
-        PINMUX_IPSR_DATA(IP2_27_24,     VI5_DATA15),
-        PINMUX_IPSR_DATA(IP2_27_24,     DU_DB7),
+        PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
+        PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
+        PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 
-        PINMUX_IPSR_DATA(IP2_31_28,     A8),
+        PINMUX_IPSR_GPSR(IP2_31_28,     A8),
         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
@@ -720,99 +719,99 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 
         /* IPSR3 */
-        PINMUX_IPSR_DATA(IP3_3_0,       A9),
+        PINMUX_IPSR_GPSR(IP3_3_0,       A9),
         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
-        PINMUX_IPSR_DATA(IP3_3_0,       VI5_VSYNC_N),
+        PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 
-        PINMUX_IPSR_DATA(IP3_7_4,       A10),
+        PINMUX_IPSR_GPSR(IP3_7_4,       A10),
         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_TANS_B,          SEL_SCIF4_1),
-        PINMUX_IPSR_DATA(IP3_7_4,       VI5_HSYNC_N),
+        PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 
-        PINMUX_IPSR_DATA(IP3_11_8,      A11),
+        PINMUX_IPSR_GPSR(IP3_11_8,      A11),
         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
-        PINMUX_IPSR_DATA(IP3_11_8,      HSCK4),
-        PINMUX_IPSR_DATA(IP3_11_8,      VI5_FIELD),
+        PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
+        PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 
-        PINMUX_IPSR_DATA(IP3_15_12,     A12),
-        PINMUX_IPSR_DATA(IP3_15_12,     LCDOUT12),
+        PINMUX_IPSR_GPSR(IP3_15_12,     A12),
+        PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
-        PINMUX_IPSR_DATA(IP3_15_12,     VI5_DATA8),
-        PINMUX_IPSR_DATA(IP3_15_12,     DU_DG4),
+        PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
+        PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 
-        PINMUX_IPSR_DATA(IP3_19_16,     A13),
-        PINMUX_IPSR_DATA(IP3_19_16,     LCDOUT13),
+        PINMUX_IPSR_GPSR(IP3_19_16,     A13),
+        PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
-        PINMUX_IPSR_DATA(IP3_19_16,     VI5_DATA9),
-        PINMUX_IPSR_DATA(IP3_19_16,     DU_DG5),
+        PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
+        PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 
-        PINMUX_IPSR_DATA(IP3_23_20,     A14),
-        PINMUX_IPSR_DATA(IP3_23_20,     LCDOUT14),
+        PINMUX_IPSR_GPSR(IP3_23_20,     A14),
+        PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
-        PINMUX_IPSR_DATA(IP3_23_20,     HCTS4_N),
-        PINMUX_IPSR_DATA(IP3_23_20,     VI5_DATA10),
-        PINMUX_IPSR_DATA(IP3_23_20,     DU_DG6),
+        PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
+        PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
+        PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 
-        PINMUX_IPSR_DATA(IP3_27_24,     A15),
-        PINMUX_IPSR_DATA(IP3_27_24,     LCDOUT15),
+        PINMUX_IPSR_GPSR(IP3_27_24,     A15),
+        PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
-        PINMUX_IPSR_DATA(IP3_27_24,     HRTS4_N),
-        PINMUX_IPSR_DATA(IP3_27_24,     VI5_DATA11),
-        PINMUX_IPSR_DATA(IP3_27_24,     DU_DG7),
+        PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
+        PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
+        PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 
-        PINMUX_IPSR_DATA(IP3_31_28,     A16),
-        PINMUX_IPSR_DATA(IP3_31_28,     LCDOUT8),
-        PINMUX_IPSR_DATA(IP3_31_28,     VI4_FIELD),
-        PINMUX_IPSR_DATA(IP3_31_28,     DU_DG0),
+        PINMUX_IPSR_GPSR(IP3_31_28,     A16),
+        PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
+        PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
+        PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 
         /* IPSR4 */
-        PINMUX_IPSR_DATA(IP4_3_0,       A17),
-        PINMUX_IPSR_DATA(IP4_3_0,       LCDOUT9),
-        PINMUX_IPSR_DATA(IP4_3_0,       VI4_VSYNC_N),
-        PINMUX_IPSR_DATA(IP4_3_0,       DU_DG1),
-
-        PINMUX_IPSR_DATA(IP4_7_4,       A18),
-        PINMUX_IPSR_DATA(IP4_7_4,       LCDOUT10),
-        PINMUX_IPSR_DATA(IP4_7_4,       VI4_HSYNC_N),
-        PINMUX_IPSR_DATA(IP4_7_4,       DU_DG2),
-
-        PINMUX_IPSR_DATA(IP4_11_8,      A19),
-        PINMUX_IPSR_DATA(IP4_11_8,      LCDOUT11),
-        PINMUX_IPSR_DATA(IP4_11_8,      VI4_CLKENB),
-        PINMUX_IPSR_DATA(IP4_11_8,      DU_DG3),
-
-        PINMUX_IPSR_DATA(IP4_15_12,     CS0_N),
-        PINMUX_IPSR_DATA(IP4_15_12,     VI5_CLKENB),
-
-        PINMUX_IPSR_DATA(IP4_19_16,     CS1_N_A26),
-        PINMUX_IPSR_DATA(IP4_19_16,     VI5_CLK),
+        PINMUX_IPSR_GPSR(IP4_3_0,       A17),
+        PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
+        PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
+        PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
+
+        PINMUX_IPSR_GPSR(IP4_7_4,       A18),
+        PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
+        PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
+        PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
+
+        PINMUX_IPSR_GPSR(IP4_11_8,      A19),
+        PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
+        PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
+        PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
+
+        PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
+        PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
+
+        PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N_A26),
+        PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 
-        PINMUX_IPSR_DATA(IP4_23_20,     BS_N),
-        PINMUX_IPSR_DATA(IP4_23_20,     QSTVA_QVS),
+        PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
+        PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
-        PINMUX_IPSR_DATA(IP4_23_20,     SCK3),
-        PINMUX_IPSR_DATA(IP4_23_20,     HSCK3),
-        PINMUX_IPSR_DATA(IP4_23_20,     CAN1_TX),
-        PINMUX_IPSR_DATA(IP4_23_20,     CANFD1_TX),
+        PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
+        PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
+        PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
+        PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 
-        PINMUX_IPSR_DATA(IP4_27_24,     RD_N),
+        PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 
-        PINMUX_IPSR_DATA(IP4_31_28,     RD_WR_N),
+        PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
@@ -820,236 +819,236 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 
         /* IPSR5 */
-        PINMUX_IPSR_DATA(IP5_3_0,       WE0_N),
+        PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
-        PINMUX_IPSR_DATA(IP5_3_0,       CTS3_N),
-        PINMUX_IPSR_DATA(IP5_3_0,       HCTS3_N),
+        PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
+        PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
-        PINMUX_IPSR_DATA(IP5_3_0,       CAN_CLK),
+        PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 
-        PINMUX_IPSR_DATA(IP5_7_4,       WE1_N),
+        PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
-        PINMUX_IPSR_DATA(IP5_7_4,       RTS3_N_TANS),
-        PINMUX_IPSR_DATA(IP5_7_4,       HRTS3_N),
+        PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N_TANS),
+        PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
-        PINMUX_IPSR_DATA(IP5_7_4,       CAN1_RX),
-        PINMUX_IPSR_DATA(IP5_7_4,       CANFD1_RX),
+        PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
+        PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 
         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
-        PINMUX_IPSR_DATA(IP5_11_8,      QCLK),
-        PINMUX_IPSR_DATA(IP5_11_8,      VI4_CLK),
-        PINMUX_IPSR_DATA(IP5_11_8,      DU_DOTCLKOUT0),
+        PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
+        PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
+        PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 
-        PINMUX_IPSR_DATA(IP5_15_12,     D0),
+        PINMUX_IPSR_GPSR(IP5_15_12,     D0),
         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
-        PINMUX_IPSR_DATA(IP5_15_12,     VI4_DATA16),
-        PINMUX_IPSR_DATA(IP5_15_12,     VI5_DATA0),
+        PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
+        PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 
-        PINMUX_IPSR_DATA(IP5_19_16,     D1),
+        PINMUX_IPSR_GPSR(IP5_19_16,     D1),
         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
-        PINMUX_IPSR_DATA(IP5_19_16,     VI4_DATA17),
-        PINMUX_IPSR_DATA(IP5_19_16,     VI5_DATA1),
+        PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
+        PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 
-        PINMUX_IPSR_DATA(IP5_23_20,     D2),
+        PINMUX_IPSR_GPSR(IP5_23_20,     D2),
         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
-        PINMUX_IPSR_DATA(IP5_23_20,     VI4_DATA18),
-        PINMUX_IPSR_DATA(IP5_23_20,     VI5_DATA2),
+        PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
+        PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 
-        PINMUX_IPSR_DATA(IP5_27_24,     D3),
+        PINMUX_IPSR_GPSR(IP5_27_24,     D3),
         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
-        PINMUX_IPSR_DATA(IP5_27_24,     VI4_DATA19),
-        PINMUX_IPSR_DATA(IP5_27_24,     VI5_DATA3),
+        PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
+        PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 
-        PINMUX_IPSR_DATA(IP5_31_28,     D4),
+        PINMUX_IPSR_GPSR(IP5_31_28,     D4),
         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
-        PINMUX_IPSR_DATA(IP5_31_28,     VI4_DATA20),
-        PINMUX_IPSR_DATA(IP5_31_28,     VI5_DATA4),
+        PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
+        PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 
         /* IPSR6 */
-        PINMUX_IPSR_DATA(IP6_3_0,       D5),
+        PINMUX_IPSR_GPSR(IP6_3_0,       D5),
         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
-        PINMUX_IPSR_DATA(IP6_3_0,       VI4_DATA21),
-        PINMUX_IPSR_DATA(IP6_3_0,       VI5_DATA5),
+        PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
+        PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 
-        PINMUX_IPSR_DATA(IP6_7_4,       D6),
+        PINMUX_IPSR_GPSR(IP6_7_4,       D6),
         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
-        PINMUX_IPSR_DATA(IP6_7_4,       VI4_DATA22),
-        PINMUX_IPSR_DATA(IP6_7_4,       VI5_DATA6),
+        PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
+        PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 
-        PINMUX_IPSR_DATA(IP6_11_8,      D7),
+        PINMUX_IPSR_GPSR(IP6_11_8,      D7),
         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
-        PINMUX_IPSR_DATA(IP6_11_8,      VI4_DATA23),
-        PINMUX_IPSR_DATA(IP6_11_8,      VI5_DATA7),
+        PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
+        PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 
-        PINMUX_IPSR_DATA(IP6_15_12,     D8),
-        PINMUX_IPSR_DATA(IP6_15_12,     LCDOUT0),
+        PINMUX_IPSR_GPSR(IP6_15_12,     D8),
+        PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
-        PINMUX_IPSR_DATA(IP6_15_12,     DU_DR0),
+        PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 
-        PINMUX_IPSR_DATA(IP6_19_16,     D9),
-        PINMUX_IPSR_DATA(IP6_19_16,     LCDOUT1),
+        PINMUX_IPSR_GPSR(IP6_19_16,     D9),
+        PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
-        PINMUX_IPSR_DATA(IP6_19_16,     DU_DR1),
+        PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 
-        PINMUX_IPSR_DATA(IP6_23_20,     D10),
-        PINMUX_IPSR_DATA(IP6_23_20,     LCDOUT2),
+        PINMUX_IPSR_GPSR(IP6_23_20,     D10),
+        PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
-        PINMUX_IPSR_DATA(IP6_23_20,     DU_DR2),
+        PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 
-        PINMUX_IPSR_DATA(IP6_27_24,     D11),
-        PINMUX_IPSR_DATA(IP6_27_24,     LCDOUT3),
+        PINMUX_IPSR_GPSR(IP6_27_24,     D11),
+        PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_TANS_C,          SEL_SCIF4_2),
-        PINMUX_IPSR_DATA(IP6_27_24,     DU_DR3),
+        PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 
-        PINMUX_IPSR_DATA(IP6_31_28,     D12),
-        PINMUX_IPSR_DATA(IP6_31_28,     LCDOUT4),
+        PINMUX_IPSR_GPSR(IP6_31_28,     D12),
+        PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
-        PINMUX_IPSR_DATA(IP6_31_28,     DU_DR4),
+        PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 
         /* IPSR7 */
-        PINMUX_IPSR_DATA(IP7_3_0,       D13),
-        PINMUX_IPSR_DATA(IP7_3_0,       LCDOUT5),
+        PINMUX_IPSR_GPSR(IP7_3_0,       D13),
+        PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
-        PINMUX_IPSR_DATA(IP7_3_0,       DU_DR5),
+        PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 
-        PINMUX_IPSR_DATA(IP7_7_4,       D14),
-        PINMUX_IPSR_DATA(IP7_7_4,       LCDOUT6),
+        PINMUX_IPSR_GPSR(IP7_7_4,       D14),
+        PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
-        PINMUX_IPSR_DATA(IP7_7_4,       DU_DR6),
+        PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 
-        PINMUX_IPSR_DATA(IP7_11_8,      D15),
-        PINMUX_IPSR_DATA(IP7_11_8,      LCDOUT7),
+        PINMUX_IPSR_GPSR(IP7_11_8,      D15),
+        PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
-        PINMUX_IPSR_DATA(IP7_11_8,      DU_DR7),
+        PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 
-        PINMUX_IPSR_DATA(IP7_15_12,     FSCLKST),
+        PINMUX_IPSR_GPSR(IP7_15_12,     FSCLKST),
 
-        PINMUX_IPSR_DATA(IP7_19_16,     SD0_CLK),
+        PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 
-        PINMUX_IPSR_DATA(IP7_23_20,     SD0_CMD),
+        PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 
-        PINMUX_IPSR_DATA(IP7_27_24,     SD0_DAT0),
+        PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 
-        PINMUX_IPSR_DATA(IP7_31_28,     SD0_DAT1),
+        PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
 
         /* IPSR8 */
-        PINMUX_IPSR_DATA(IP8_3_0,       SD0_DAT2),
+        PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
 
-        PINMUX_IPSR_DATA(IP8_7_4,       SD0_DAT3),
+        PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
 
-        PINMUX_IPSR_DATA(IP8_11_8,      SD1_CLK),
+        PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
 
-        PINMUX_IPSR_DATA(IP8_15_12,     SD1_CMD),
+        PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
 
-        PINMUX_IPSR_DATA(IP8_19_16,     SD1_DAT0),
-        PINMUX_IPSR_DATA(IP8_19_16,     SD2_DAT4),
+        PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
+        PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
 
-        PINMUX_IPSR_DATA(IP8_23_20,     SD1_DAT1),
-        PINMUX_IPSR_DATA(IP8_23_20,     SD2_DAT5),
+        PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
+        PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
 
-        PINMUX_IPSR_DATA(IP8_27_24,     SD1_DAT2),
-        PINMUX_IPSR_DATA(IP8_27_24,     SD2_DAT6),
+        PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
+        PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
 
-        PINMUX_IPSR_DATA(IP8_31_28,     SD1_DAT3),
-        PINMUX_IPSR_DATA(IP8_31_28,     SD2_DAT7),
+        PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
+        PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
 
         /* IPSR9 */
-        PINMUX_IPSR_DATA(IP9_3_0,       SD2_CLK),
+        PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
 
-        PINMUX_IPSR_DATA(IP9_7_4,       SD2_DAT0),
+        PINMUX_IPSR_GPSR(IP9_7_4,       SD2_DAT0),
 
-        PINMUX_IPSR_DATA(IP9_11_8,      SD2_DAT1),
+        PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT1),
 
-        PINMUX_IPSR_DATA(IP9_15_12,     SD2_DAT2),
+        PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT2),
 
-        PINMUX_IPSR_DATA(IP9_19_16,     SD2_DAT3),
+        PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT3),
 
-        PINMUX_IPSR_DATA(IP9_23_20,     SD2_DS),
+        PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DS),
         PINMUX_IPSR_MSEL(IP9_23_20,     SATA_DEVSLP_B,          SEL_SATA_1),
 
-        PINMUX_IPSR_DATA(IP9_27_24,     SD3_DAT4),
+        PINMUX_IPSR_GPSR(IP9_27_24,     SD3_DAT4),
         PINMUX_IPSR_MSEL(IP9_27_24,     SD2_CD_A,               SEL_SDHI2_0),
 
-        PINMUX_IPSR_DATA(IP9_31_28,     SD3_DAT5),
+        PINMUX_IPSR_GPSR(IP9_31_28,     SD3_DAT5),
         PINMUX_IPSR_MSEL(IP9_31_28,     SD2_WP_A,               SEL_SDHI2_0),
 
         /* IPSR10 */
-        PINMUX_IPSR_DATA(IP10_3_0,      SD3_DAT6),
-        PINMUX_IPSR_DATA(IP10_3_0,      SD3_CD),
+        PINMUX_IPSR_GPSR(IP10_3_0,      SD3_DAT6),
+        PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CD),
 
-        PINMUX_IPSR_DATA(IP10_7_4,      SD3_DAT7),
-        PINMUX_IPSR_DATA(IP10_7_4,      SD3_WP),
+        PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT7),
+        PINMUX_IPSR_GPSR(IP10_7_4,      SD3_WP),
 
-        PINMUX_IPSR_DATA(IP10_11_8,     SD0_CD),
+        PINMUX_IPSR_GPSR(IP10_11_8,     SD0_CD),
         PINMUX_IPSR_MSEL(IP10_11_8,     SCL2_B,                 SEL_I2C2_1),
         PINMUX_IPSR_MSEL(IP10_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
 
-        PINMUX_IPSR_DATA(IP10_15_12,    SD0_WP),
+        PINMUX_IPSR_GPSR(IP10_15_12,    SD0_WP),
         PINMUX_IPSR_MSEL(IP10_15_12,    SDA2_B,                 SEL_I2C2_1),
 
-        PINMUX_IPSR_DATA(IP10_19_16,    SD1_CD),
+        PINMUX_IPSR_GPSR(IP10_19_16,    SD1_CD),
         PINMUX_IPSR_MSEL(IP10_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
 
-        PINMUX_IPSR_DATA(IP10_23_20,    SD1_WP),
+        PINMUX_IPSR_GPSR(IP10_23_20,    SD1_WP),
         PINMUX_IPSR_MSEL(IP10_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
 
-        PINMUX_IPSR_DATA(IP10_27_24,    SCK0),
+        PINMUX_IPSR_GPSR(IP10_27_24,    SCK0),
         PINMUX_IPSR_MSEL(IP10_27_24,    HSCK1_B,                SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP10_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
         PINMUX_IPSR_MSEL(IP10_27_24,    AUDIO_CLKC_B,           SEL_ADG_1),
@@ -1057,38 +1056,38 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP10_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
         PINMUX_IPSR_MSEL(IP10_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
         PINMUX_IPSR_MSEL(IP10_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
-        PINMUX_IPSR_DATA(IP10_27_24,    ADICHS2),
+        PINMUX_IPSR_GPSR(IP10_27_24,    ADICHS2),
 
-        PINMUX_IPSR_DATA(IP10_31_28,    RX0),
+        PINMUX_IPSR_GPSR(IP10_31_28,    RX0),
         PINMUX_IPSR_MSEL(IP10_31_28,    HRX1_B,                 SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP10_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
         PINMUX_IPSR_MSEL(IP10_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
         PINMUX_IPSR_MSEL(IP10_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
 
         /* IPSR11 */
-        PINMUX_IPSR_DATA(IP11_3_0,      TX0),
+        PINMUX_IPSR_GPSR(IP11_3_0,      TX0),
         PINMUX_IPSR_MSEL(IP11_3_0,      HTX1_B,                 SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP11_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
         PINMUX_IPSR_MSEL(IP11_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
         PINMUX_IPSR_MSEL(IP11_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
 
-        PINMUX_IPSR_DATA(IP11_7_4,      CTS0_N),
+        PINMUX_IPSR_GPSR(IP11_7_4,      CTS0_N),
         PINMUX_IPSR_MSEL(IP11_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP11_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
         PINMUX_IPSR_MSEL(IP11_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
         PINMUX_IPSR_MSEL(IP11_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
         PINMUX_IPSR_MSEL(IP11_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
         PINMUX_IPSR_MSEL(IP11_7_4,      AUDIO_CLKOUT_C,         SEL_ADG_2),
-        PINMUX_IPSR_DATA(IP11_7_4,      ADICS_SAMP),
+        PINMUX_IPSR_GPSR(IP11_7_4,      ADICS_SAMP),
 
-        PINMUX_IPSR_DATA(IP11_11_8,     RTS0_N_TANS),
+        PINMUX_IPSR_GPSR(IP11_11_8,     RTS0_N_TANS),
         PINMUX_IPSR_MSEL(IP11_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
         PINMUX_IPSR_MSEL(IP11_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
         PINMUX_IPSR_MSEL(IP11_11_8,     AUDIO_CLKA_B,           SEL_ADG_1),
         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_A,                 SEL_I2C2_0),
         PINMUX_IPSR_MSEL(IP11_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
         PINMUX_IPSR_MSEL(IP11_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
-        PINMUX_IPSR_DATA(IP11_11_8,     ADICHS1),
+        PINMUX_IPSR_GPSR(IP11_11_8,     ADICHS1),
 
         PINMUX_IPSR_MSEL(IP11_15_12,    RX1_A,                  SEL_SCIF1_0),
         PINMUX_IPSR_MSEL(IP11_15_12,    HRX1_A,                 SEL_HSCIF1_0),
@@ -1102,29 +1101,29 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP11_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
         PINMUX_IPSR_MSEL(IP11_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
 
-        PINMUX_IPSR_DATA(IP11_23_20,    CTS1_N),
+        PINMUX_IPSR_GPSR(IP11_23_20,    CTS1_N),
         PINMUX_IPSR_MSEL(IP11_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP11_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
         PINMUX_IPSR_MSEL(IP11_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
         PINMUX_IPSR_MSEL(IP11_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
         PINMUX_IPSR_MSEL(IP11_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
-        PINMUX_IPSR_DATA(IP11_23_20,    ADIDATA),
+        PINMUX_IPSR_GPSR(IP11_23_20,    ADIDATA),
 
-        PINMUX_IPSR_DATA(IP11_27_24,    RTS1_N_TANS),
+        PINMUX_IPSR_GPSR(IP11_27_24,    RTS1_N_TANS),
         PINMUX_IPSR_MSEL(IP11_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
         PINMUX_IPSR_MSEL(IP11_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
         PINMUX_IPSR_MSEL(IP11_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
         PINMUX_IPSR_MSEL(IP11_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
-        PINMUX_IPSR_DATA(IP11_27_24,    ADICHS0),
+        PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS0),
 
-        PINMUX_IPSR_DATA(IP11_31_28,    SCK2),
+        PINMUX_IPSR_GPSR(IP11_31_28,    SCK2),
         PINMUX_IPSR_MSEL(IP11_31_28,    SCIF_CLK_B,             SEL_SCIF1_1),
         PINMUX_IPSR_MSEL(IP11_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
         PINMUX_IPSR_MSEL(IP11_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
-        PINMUX_IPSR_DATA(IP11_31_28,    ADICLK),
+        PINMUX_IPSR_GPSR(IP11_31_28,    ADICLK),
 
         /* IPSR12 */
         PINMUX_IPSR_MSEL(IP12_3_0,      TX2_A,                  SEL_SCIF2_0),
@@ -1141,7 +1140,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
         PINMUX_IPSR_MSEL(IP12_7_4,      FSO_CFE_1_B,            SEL_FSO_1),
 
-        PINMUX_IPSR_DATA(IP12_11_8,     HSCK0),
+        PINMUX_IPSR_GPSR(IP12_11_8,     HSCK0),
         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKB_A,           SEL_ADG_0),
         PINMUX_IPSR_MSEL(IP12_11_8,     SSI_SDATA1_B,           SEL_SSI_1),
@@ -1149,21 +1148,21 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP12_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
 
-        PINMUX_IPSR_DATA(IP12_15_12,    HRX0),
+        PINMUX_IPSR_GPSR(IP12_15_12,    HRX0),
         PINMUX_IPSR_MSEL(IP12_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
         PINMUX_IPSR_MSEL(IP12_15_12,    SSI_SDATA2_B,           SEL_SSI_1),
         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
         PINMUX_IPSR_MSEL(IP12_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
 
-        PINMUX_IPSR_DATA(IP12_19_16,    HTX0),
+        PINMUX_IPSR_GPSR(IP12_19_16,    HTX0),
         PINMUX_IPSR_MSEL(IP12_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
         PINMUX_IPSR_MSEL(IP12_19_16,    SSI_SDATA9_B,           SEL_SSI_1),
         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
         PINMUX_IPSR_MSEL(IP12_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
 
-        PINMUX_IPSR_DATA(IP12_23_20,    HCTS0_N),
+        PINMUX_IPSR_GPSR(IP12_23_20,    HCTS0_N),
         PINMUX_IPSR_MSEL(IP12_23_20,    RX2_B,                  SEL_SCIF2_1),
         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
         PINMUX_IPSR_MSEL(IP12_23_20,    SSI_SCK9_A,             SEL_SSI_0),
@@ -1172,7 +1171,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP12_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
         PINMUX_IPSR_MSEL(IP12_23_20,    AUDIO_CLKOUT1_A,        SEL_ADG_0),
 
-        PINMUX_IPSR_DATA(IP12_27_24,    HRTS0_N),
+        PINMUX_IPSR_GPSR(IP12_27_24,    HRTS0_N),
         PINMUX_IPSR_MSEL(IP12_27_24,    TX2_B,                  SEL_SCIF2_1),
         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
         PINMUX_IPSR_MSEL(IP12_27_24,    SSI_WS9_A,              SEL_SSI_0),
@@ -1180,20 +1179,20 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP12_27_24,    BPFCLK_A,               SEL_FM_0),
         PINMUX_IPSR_MSEL(IP12_27_24,    AUDIO_CLKOUT2_A,        SEL_ADG_0),
 
-        PINMUX_IPSR_DATA(IP12_31_28,    MSIOF0_SYNC),
+        PINMUX_IPSR_GPSR(IP12_31_28,    MSIOF0_SYNC),
         PINMUX_IPSR_MSEL(IP12_31_28,    AUDIO_CLKOUT_A,         SEL_ADG_0),
 
         /* IPSR13 */
-        PINMUX_IPSR_DATA(IP13_3_0,      MSIOF0_SS1),
-        PINMUX_IPSR_DATA(IP13_3_0,      RX5),
+        PINMUX_IPSR_GPSR(IP13_3_0,      MSIOF0_SS1),
+        PINMUX_IPSR_GPSR(IP13_3_0,      RX5),
         PINMUX_IPSR_MSEL(IP13_3_0,      AUDIO_CLKA_C,           SEL_ADG_2),
         PINMUX_IPSR_MSEL(IP13_3_0,      SSI_SCK2_A,             SEL_SSI_0),
         PINMUX_IPSR_MSEL(IP13_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
         PINMUX_IPSR_MSEL(IP13_3_0,      AUDIO_CLKOUT3_A,        SEL_ADG_0),
         PINMUX_IPSR_MSEL(IP13_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
 
-        PINMUX_IPSR_DATA(IP13_7_4,      MSIOF0_SS2),
-        PINMUX_IPSR_DATA(IP13_7_4,      TX5),
+        PINMUX_IPSR_GPSR(IP13_7_4,      MSIOF0_SS2),
+        PINMUX_IPSR_GPSR(IP13_7_4,      TX5),
         PINMUX_IPSR_MSEL(IP13_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
         PINMUX_IPSR_MSEL(IP13_7_4,      AUDIO_CLKC_A,           SEL_ADG_0),
         PINMUX_IPSR_MSEL(IP13_7_4,      SSI_WS2_A,              SEL_SSI_0),
@@ -1201,26 +1200,26 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP13_7_4,      AUDIO_CLKOUT_D,         SEL_ADG_3),
         PINMUX_IPSR_MSEL(IP13_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
 
-        PINMUX_IPSR_DATA(IP13_11_8,     MLB_CLK),
+        PINMUX_IPSR_GPSR(IP13_11_8,     MLB_CLK),
         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
         PINMUX_IPSR_MSEL(IP13_11_8,     SCL1_B,                 SEL_I2C1_1),
 
-        PINMUX_IPSR_DATA(IP13_15_12,    MLB_SIG),
+        PINMUX_IPSR_GPSR(IP13_15_12,    MLB_SIG),
         PINMUX_IPSR_MSEL(IP13_15_12,    RX1_B,                  SEL_SCIF1_1),
         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
         PINMUX_IPSR_MSEL(IP13_15_12,    SDA1_B,                 SEL_I2C1_1),
 
-        PINMUX_IPSR_DATA(IP13_19_16,    MLB_DAT),
+        PINMUX_IPSR_GPSR(IP13_19_16,    MLB_DAT),
         PINMUX_IPSR_MSEL(IP13_19_16,    TX1_B,                  SEL_SCIF1_1),
         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
 
-        PINMUX_IPSR_DATA(IP13_23_20,    SSI_SCK0129),
+        PINMUX_IPSR_GPSR(IP13_23_20,    SSI_SCK01239),
         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
 
-        PINMUX_IPSR_DATA(IP13_27_24,    SSI_WS0129),
+        PINMUX_IPSR_GPSR(IP13_27_24,    SSI_WS01239),
         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
 
-        PINMUX_IPSR_DATA(IP13_31_28,    SSI_SDATA0),
+        PINMUX_IPSR_GPSR(IP13_31_28,    SSI_SDATA0),
         PINMUX_IPSR_MSEL(IP13_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
 
         /* IPSR14 */
@@ -1229,16 +1228,16 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_SDATA2_A,           SEL_SSI_0),
         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_SCK1_B,             SEL_SSI_1),
 
-        PINMUX_IPSR_DATA(IP14_11_8,     SSI_SCK34),
+        PINMUX_IPSR_GPSR(IP14_11_8,     SSI_SCK34),
         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
         PINMUX_IPSR_MSEL(IP14_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
 
-        PINMUX_IPSR_DATA(IP14_15_12,    SSI_WS34),
+        PINMUX_IPSR_GPSR(IP14_15_12,    SSI_WS34),
         PINMUX_IPSR_MSEL(IP14_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
         PINMUX_IPSR_MSEL(IP14_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
 
-        PINMUX_IPSR_DATA(IP14_19_16,    SSI_SDATA3),
+        PINMUX_IPSR_GPSR(IP14_19_16,    SSI_SDATA3),
         PINMUX_IPSR_MSEL(IP14_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
         PINMUX_IPSR_MSEL(IP14_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
@@ -1246,7 +1245,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP14_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
         PINMUX_IPSR_MSEL(IP14_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
 
-        PINMUX_IPSR_DATA(IP14_23_20,    SSI_SCK4),
+        PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK4),
         PINMUX_IPSR_MSEL(IP14_23_20,    HRX2_A,                 SEL_HSCIF2_0),
         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
         PINMUX_IPSR_MSEL(IP14_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
@@ -1254,7 +1253,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP14_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
         PINMUX_IPSR_MSEL(IP14_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
 
-        PINMUX_IPSR_DATA(IP14_27_24,    SSI_WS4),
+        PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS4),
         PINMUX_IPSR_MSEL(IP14_27_24,    HTX2_A,                 SEL_HSCIF2_0),
         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
         PINMUX_IPSR_MSEL(IP14_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
@@ -1262,7 +1261,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP14_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
         PINMUX_IPSR_MSEL(IP14_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
 
-        PINMUX_IPSR_DATA(IP14_31_28,    SSI_SDATA4),
+        PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA4),
         PINMUX_IPSR_MSEL(IP14_31_28,    HSCK2_A,                SEL_HSCIF2_0),
         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
         PINMUX_IPSR_MSEL(IP14_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
@@ -1271,19 +1270,19 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP14_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
 
         /* IPSR15 */
-        PINMUX_IPSR_DATA(IP15_3_0,      SSI_SCK6),
-        PINMUX_IPSR_DATA(IP15_3_0,      USB2_PWEN),
+        PINMUX_IPSR_GPSR(IP15_3_0,      SSI_SCK6),
+        PINMUX_IPSR_GPSR(IP15_3_0,      USB2_PWEN),
         PINMUX_IPSR_MSEL(IP15_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
 
-        PINMUX_IPSR_DATA(IP15_7_4,      SSI_WS6),
-        PINMUX_IPSR_DATA(IP15_7_4,      USB2_OVC),
+        PINMUX_IPSR_GPSR(IP15_7_4,      SSI_WS6),
+        PINMUX_IPSR_GPSR(IP15_7_4,      USB2_OVC),
         PINMUX_IPSR_MSEL(IP15_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
 
-        PINMUX_IPSR_DATA(IP15_11_8,     SSI_SDATA6),
+        PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SDATA6),
         PINMUX_IPSR_MSEL(IP15_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
         PINMUX_IPSR_MSEL(IP15_11_8,     SATA_DEVSLP_A,          SEL_SATA_0),
 
-        PINMUX_IPSR_DATA(IP15_15_12,    SSI_SCK78),
+        PINMUX_IPSR_GPSR(IP15_15_12,    SSI_SCK78),
         PINMUX_IPSR_MSEL(IP15_15_12,    HRX2_B,                 SEL_HSCIF2_1),
         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
         PINMUX_IPSR_MSEL(IP15_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
@@ -1291,7 +1290,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP15_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
         PINMUX_IPSR_MSEL(IP15_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
 
-        PINMUX_IPSR_DATA(IP15_19_16,    SSI_WS78),
+        PINMUX_IPSR_GPSR(IP15_19_16,    SSI_WS78),
         PINMUX_IPSR_MSEL(IP15_19_16,    HTX2_B,                 SEL_HSCIF2_1),
         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
@@ -1299,7 +1298,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP15_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
         PINMUX_IPSR_MSEL(IP15_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
 
-        PINMUX_IPSR_DATA(IP15_23_20,    SSI_SDATA7),
+        PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SDATA7),
         PINMUX_IPSR_MSEL(IP15_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
@@ -1308,7 +1307,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP15_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
         PINMUX_IPSR_MSEL(IP15_23_20,    TCLK2_A,                SEL_TIMER_TMU_0),
 
-        PINMUX_IPSR_DATA(IP15_27_24,    SSI_SDATA8),
+        PINMUX_IPSR_GPSR(IP15_27_24,    SSI_SDATA8),
         PINMUX_IPSR_MSEL(IP15_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
@@ -1321,13 +1320,13 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK1_A,                SEL_HSCIF1_0),
         PINMUX_IPSR_MSEL(IP15_31_28,    SSI_WS1_B,              SEL_SSI_1),
-        PINMUX_IPSR_DATA(IP15_31_28,    SCK1),
+        PINMUX_IPSR_GPSR(IP15_31_28,    SCK1),
         PINMUX_IPSR_MSEL(IP15_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
-        PINMUX_IPSR_DATA(IP15_31_28,    SCK5),
+        PINMUX_IPSR_GPSR(IP15_31_28,    SCK5),
 
         /* IPSR16 */
         PINMUX_IPSR_MSEL(IP16_3_0,      AUDIO_CLKA_A,           SEL_ADG_0),
-        PINMUX_IPSR_DATA(IP16_3_0,      CC5_OSCOUT),
+        PINMUX_IPSR_GPSR(IP16_3_0,      CC5_OSCOUT),
 
         PINMUX_IPSR_MSEL(IP16_7_4,      AUDIO_CLKB_B,           SEL_ADG_1),
         PINMUX_IPSR_MSEL(IP16_7_4,      SCIF_CLK_A,             SEL_SCIF1_0),
@@ -1335,20 +1334,20 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP16_7_4,      REMOCON_A,              SEL_REMOCON_0),
         PINMUX_IPSR_MSEL(IP16_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
 
-        PINMUX_IPSR_DATA(IP16_11_8,     USB0_PWEN),
+        PINMUX_IPSR_GPSR(IP16_11_8,     USB0_PWEN),
         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
         PINMUX_IPSR_MSEL(IP16_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
         PINMUX_IPSR_MSEL(IP16_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
         PINMUX_IPSR_MSEL(IP16_11_8,     BPFCLK_B,               SEL_FM_1),
         PINMUX_IPSR_MSEL(IP16_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
 
-        PINMUX_IPSR_DATA(IP16_15_12,    USB0_OVC),
+        PINMUX_IPSR_GPSR(IP16_15_12,    USB0_OVC),
         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_D_C,               SEL_SIMCARD_2),
         PINMUX_IPSR_MSEL(IP16_11_8,     TS_SDAT1_D,             SEL_TSIF1_3),
         PINMUX_IPSR_MSEL(IP16_11_8,     STP_ISD_1_D,            SEL_SSP1_1_3),
         PINMUX_IPSR_MSEL(IP16_11_8,     RIF3_SYNC_B,            SEL_DRIF3_1),
 
-        PINMUX_IPSR_DATA(IP16_19_16,    USB1_PWEN),
+        PINMUX_IPSR_GPSR(IP16_19_16,    USB1_PWEN),
         PINMUX_IPSR_MSEL(IP16_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
         PINMUX_IPSR_MSEL(IP16_19_16,    SSI_SCK1_A,             SEL_SSI_0),
         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
@@ -1357,7 +1356,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP16_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
         PINMUX_IPSR_MSEL(IP16_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
 
-        PINMUX_IPSR_DATA(IP16_23_20,    USB1_OVC),
+        PINMUX_IPSR_GPSR(IP16_23_20,    USB1_OVC),
         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
         PINMUX_IPSR_MSEL(IP16_23_20,    SSI_WS1_A,              SEL_SSI_0),
         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
@@ -1366,7 +1365,7 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP16_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
         PINMUX_IPSR_MSEL(IP16_23_20,    REMOCON_B,              SEL_REMOCON_1),
 
-        PINMUX_IPSR_DATA(IP16_27_24,    USB30_PWEN),
+        PINMUX_IPSR_GPSR(IP16_27_24,    USB30_PWEN),
         PINMUX_IPSR_MSEL(IP16_27_24,    AUDIO_CLKOUT_B,         SEL_ADG_1),
         PINMUX_IPSR_MSEL(IP16_27_24,    SSI_SCK2_B,             SEL_SSI_1),
         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
@@ -1374,9 +1373,9 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP16_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
         PINMUX_IPSR_MSEL(IP16_27_24,    TCLK2_B,                SEL_TIMER_TMU_1),
-        PINMUX_IPSR_DATA(IP16_27_24,    TPU0TO0),
+        PINMUX_IPSR_GPSR(IP16_27_24,    TPU0TO0),
 
-        PINMUX_IPSR_DATA(IP16_31_28,    USB30_OVC),
+        PINMUX_IPSR_GPSR(IP16_31_28,    USB30_OVC),
         PINMUX_IPSR_MSEL(IP16_31_28,    AUDIO_CLKOUT1_B,        SEL_ADG_1),
         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS2_B,              SEL_SSI_1),
         PINMUX_IPSR_MSEL(IP16_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
@@ -1384,24 +1383,24 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
         PINMUX_IPSR_MSEL(IP16_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
         PINMUX_IPSR_MSEL(IP16_31_28,    FSO_TOE_B,              SEL_FSO_1),
-        PINMUX_IPSR_DATA(IP16_31_28,    TPU0TO1),
+        PINMUX_IPSR_GPSR(IP16_31_28,    TPU0TO1),
 
         /* IPSR17 */
-        PINMUX_IPSR_DATA(IP17_3_0,      USB31_PWEN),
+        PINMUX_IPSR_GPSR(IP17_3_0,      USB31_PWEN),
         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKOUT2_B,        SEL_ADG_1),
         PINMUX_IPSR_MSEL(IP17_3_0,      SSI_SCK9_B,             SEL_SSI_1),
         PINMUX_IPSR_MSEL(IP17_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
         PINMUX_IPSR_MSEL(IP17_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
         PINMUX_IPSR_MSEL(IP17_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
-        PINMUX_IPSR_DATA(IP17_3_0,      TPU0TO2),
+        PINMUX_IPSR_GPSR(IP17_3_0,      TPU0TO2),
 
-        PINMUX_IPSR_DATA(IP17_7_4,      USB31_OVC),
+        PINMUX_IPSR_GPSR(IP17_7_4,      USB31_OVC),
         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKOUT3_B,        SEL_ADG_1),
         PINMUX_IPSR_MSEL(IP17_7_4,      SSI_WS9_B,              SEL_SSI_1),
         PINMUX_IPSR_MSEL(IP17_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
         PINMUX_IPSR_MSEL(IP17_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
         PINMUX_IPSR_MSEL(IP17_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
-        PINMUX_IPSR_DATA(IP17_7_4,      TPU0TO3),
+        PINMUX_IPSR_GPSR(IP17_7_4,      TPU0TO3),
 
         /* I2C */
         PINMUX_IPSR_NOGP(0,             I2C_SEL_0_1),
@@ -1600,6 +1599,61 @@ static const unsigned int avb_avtp_capture_b_mux[] = {
         AVB_AVTP_CAPTURE_B_MARK,
 };
 
+/* - CAN ------------------------------------------------------------------ */
+static const unsigned int can0_data_a_pins[] = {
+        /* TX, RX */
+        RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
+};
+static const unsigned int can0_data_a_mux[] = {
+        CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
+};
+static const unsigned int can0_data_b_pins[] = {
+        /* TX, RX */
+        RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
+};
+static const unsigned int can0_data_b_mux[] = {
+        CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
+};
+static const unsigned int can1_data_pins[] = {
+        /* TX, RX */
+        RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
+};
+static const unsigned int can1_data_mux[] = {
+        CAN1_TX_MARK,           CAN1_RX_MARK,
+};
+
+/* - CAN Clock -------------------------------------------------------------- */
+static const unsigned int can_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(1, 25),
+};
+static const unsigned int can_clk_mux[] = {
+        CAN_CLK_MARK,
+};
+
+/* - CAN FD --------------------------------------------------------------- */
+static const unsigned int canfd0_data_a_pins[] = {
+        /* TX, RX */
+        RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
+};
+static const unsigned int canfd0_data_a_mux[] = {
+        CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
+};
+static const unsigned int canfd0_data_b_pins[] = {
+        /* TX, RX */
+        RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
+};
+static const unsigned int canfd0_data_b_mux[] = {
+        CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
+};
+static const unsigned int canfd1_data_pins[] = {
+        /* TX, RX */
+        RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
+};
+static const unsigned int canfd1_data_mux[] = {
+        CANFD1_TX_MARK,         CANFD1_RX_MARK,
+};
+
 /* - HSCIF0 ----------------------------------------------------------------- */
 static const unsigned int hscif0_data_pins[] = {
         /* RX, TX */
@@ -1836,6 +1890,50 @@ static const unsigned int i2c6_c_mux[] = {
         SDA6_C_MARK, SCL6_C_MARK,
 };
 
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+        /* IRQ0 */
+        RCAR_GP_PIN(2, 0),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+        IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+        /* IRQ1 */
+        RCAR_GP_PIN(2, 1),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+        IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+        /* IRQ2 */
+        RCAR_GP_PIN(2, 2),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+        IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+        /* IRQ3 */
+        RCAR_GP_PIN(2, 3),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+        IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+        /* IRQ4 */
+        RCAR_GP_PIN(2, 4),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+        IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+        /* IRQ5 */
+        RCAR_GP_PIN(2, 5),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+        IRQ5_MARK,
+};
+
 /* - MSIOF0 ----------------------------------------------------------------- */
 static const unsigned int msiof0_clk_pins[] = {
         /* SCK */
@@ -2492,6 +2590,105 @@ static const unsigned int msiof3_rxd_d_mux[] = {
         MSIOF3_RXD_D_MARK,
 };
 
+/* - PWM0 --------------------------------------------------------------------*/
+static const unsigned int pwm0_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 6),
+};
+static const unsigned int pwm0_mux[] = {
+        PWM0_MARK,
+};
+/* - PWM1 --------------------------------------------------------------------*/
+static const unsigned int pwm1_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 7),
+};
+static const unsigned int pwm1_a_mux[] = {
+        PWM1_A_MARK,
+};
+static const unsigned int pwm1_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 8),
+};
+static const unsigned int pwm1_b_mux[] = {
+        PWM1_B_MARK,
+};
+/* - PWM2 --------------------------------------------------------------------*/
+static const unsigned int pwm2_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 8),
+};
+static const unsigned int pwm2_a_mux[] = {
+        PWM2_A_MARK,
+};
+static const unsigned int pwm2_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 11),
+};
+static const unsigned int pwm2_b_mux[] = {
+        PWM2_B_MARK,
+};
+/* - PWM3 --------------------------------------------------------------------*/
+static const unsigned int pwm3_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 0),
+};
+static const unsigned int pwm3_a_mux[] = {
+        PWM3_A_MARK,
+};
+static const unsigned int pwm3_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 2),
+};
+static const unsigned int pwm3_b_mux[] = {
+        PWM3_B_MARK,
+};
+/* - PWM4 --------------------------------------------------------------------*/
+static const unsigned int pwm4_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 1),
+};
+static const unsigned int pwm4_a_mux[] = {
+        PWM4_A_MARK,
+};
+static const unsigned int pwm4_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 3),
+};
+static const unsigned int pwm4_b_mux[] = {
+        PWM4_B_MARK,
+};
+/* - PWM5 --------------------------------------------------------------------*/
+static const unsigned int pwm5_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 2),
+};
+static const unsigned int pwm5_a_mux[] = {
+        PWM5_A_MARK,
+};
+static const unsigned int pwm5_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 4),
+};
+static const unsigned int pwm5_b_mux[] = {
+        PWM5_B_MARK,
+};
+/* - PWM6 --------------------------------------------------------------------*/
+static const unsigned int pwm6_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 3),
+};
+static const unsigned int pwm6_a_mux[] = {
+        PWM6_A_MARK,
+};
+static const unsigned int pwm6_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 5),
+};
+static const unsigned int pwm6_b_mux[] = {
+        PWM6_B_MARK,
+};
+
 /* - SATA --------------------------------------------------------------------*/
 static const unsigned int sata0_devslp_a_pins[] = {
         /* DEVSLP */
@@ -2926,7 +3123,7 @@ static const unsigned int ssi01239_ctrl_pins[] = {
         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
 };
 static const unsigned int ssi01239_ctrl_mux[] = {
-        SSI_SCK0129_MARK, SSI_WS0129_MARK,
+        SSI_SCK01239_MARK, SSI_WS01239_MARK,
 };
 static const unsigned int ssi1_data_a_pins[] = {
         /* SDATA */
@@ -3090,6 +3287,31 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
 };
 
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+        /* PWEN, OVC */
+        RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+static const unsigned int usb0_mux[] = {
+        USB0_PWEN_MARK, USB0_OVC_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+        /* PWEN, OVC */
+        RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+};
+static const unsigned int usb1_mux[] = {
+        USB1_PWEN_MARK, USB1_OVC_MARK,
+};
+/* - USB2 ------------------------------------------------------------------- */
+static const unsigned int usb2_pins[] = {
+        /* PWEN, OVC */
+        RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
+};
+static const unsigned int usb2_mux[] = {
+        USB2_PWEN_MARK, USB2_OVC_MARK,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(audio_clk_a_a),
         SH_PFC_PIN_GROUP(audio_clk_a_b),
@@ -3117,6 +3339,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
         SH_PFC_PIN_GROUP(avb_avtp_match_b),
         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+        SH_PFC_PIN_GROUP(can0_data_a),
+        SH_PFC_PIN_GROUP(can0_data_b),
+        SH_PFC_PIN_GROUP(can1_data),
+        SH_PFC_PIN_GROUP(can_clk),
+        SH_PFC_PIN_GROUP(canfd0_data_a),
+        SH_PFC_PIN_GROUP(canfd0_data_b),
+        SH_PFC_PIN_GROUP(canfd1_data),
         SH_PFC_PIN_GROUP(hscif0_data),
         SH_PFC_PIN_GROUP(hscif0_clk),
         SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -3149,6 +3378,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(i2c6_a),
         SH_PFC_PIN_GROUP(i2c6_b),
         SH_PFC_PIN_GROUP(i2c6_c),
+        SH_PFC_PIN_GROUP(intc_ex_irq0),
+        SH_PFC_PIN_GROUP(intc_ex_irq1),
+        SH_PFC_PIN_GROUP(intc_ex_irq2),
+        SH_PFC_PIN_GROUP(intc_ex_irq3),
+        SH_PFC_PIN_GROUP(intc_ex_irq4),
+        SH_PFC_PIN_GROUP(intc_ex_irq5),
         SH_PFC_PIN_GROUP(msiof0_clk),
         SH_PFC_PIN_GROUP(msiof0_sync),
         SH_PFC_PIN_GROUP(msiof0_ss1),
@@ -3242,6 +3477,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(msiof3_ss1_d),
         SH_PFC_PIN_GROUP(msiof3_txd_d),
         SH_PFC_PIN_GROUP(msiof3_rxd_d),
+        SH_PFC_PIN_GROUP(pwm0),
+        SH_PFC_PIN_GROUP(pwm1_a),
+        SH_PFC_PIN_GROUP(pwm1_b),
+        SH_PFC_PIN_GROUP(pwm2_a),
+        SH_PFC_PIN_GROUP(pwm2_b),
+        SH_PFC_PIN_GROUP(pwm3_a),
+        SH_PFC_PIN_GROUP(pwm3_b),
+        SH_PFC_PIN_GROUP(pwm4_a),
+        SH_PFC_PIN_GROUP(pwm4_b),
+        SH_PFC_PIN_GROUP(pwm5_a),
+        SH_PFC_PIN_GROUP(pwm5_b),
+        SH_PFC_PIN_GROUP(pwm6_a),
+        SH_PFC_PIN_GROUP(pwm6_b),
         SH_PFC_PIN_GROUP(sata0_devslp_a),
         SH_PFC_PIN_GROUP(sata0_devslp_b),
         SH_PFC_PIN_GROUP(scif0_data),
@@ -3322,6 +3570,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(ssi9_data_b),
         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+        SH_PFC_PIN_GROUP(usb0),
+        SH_PFC_PIN_GROUP(usb1),
+        SH_PFC_PIN_GROUP(usb2),
 };
 
 static const char * const audio_clk_groups[] = {
@@ -3356,6 +3607,28 @@ static const char * const avb_groups[] = {
         "avb_avtp_capture_b",
 };
 
+static const char * const can0_groups[] = {
+        "can0_data_a",
+        "can0_data_b",
+};
+
+static const char * const can1_groups[] = {
+        "can1_data",
+};
+
+static const char * const can_clk_groups[] = {
+        "can_clk",
+};
+
+static const char * const canfd0_groups[] = {
+        "canfd0_data_a",
+        "canfd0_data_b",
+};
+
+static const char * const canfd1_groups[] = {
+        "canfd1_data",
+};
+
 static const char * const hscif0_groups[] = {
         "hscif0_data",
         "hscif0_clk",
@@ -3412,6 +3685,15 @@ static const char * const i2c6_groups[] = {
         "i2c6_c",
 };
 
+static const char * const intc_ex_groups[] = {
+        "intc_ex_irq0",
+        "intc_ex_irq1",
+        "intc_ex_irq2",
+        "intc_ex_irq3",
+        "intc_ex_irq4",
+        "intc_ex_irq5",
+};
+
 static const char * const msiof0_groups[] = {
         "msiof0_clk",
         "msiof0_sync",
@@ -3517,6 +3799,40 @@ static const char * const msiof3_groups[] = {
         "msiof3_rxd_d",
 };
 
+static const char * const pwm0_groups[] = {
+        "pwm0",
+};
+
+static const char * const pwm1_groups[] = {
+        "pwm1_a",
+        "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+        "pwm2_a",
+        "pwm2_b",
+};
+
+static const char * const pwm3_groups[] = {
+        "pwm3_a",
+        "pwm3_b",
+};
+
+static const char * const pwm4_groups[] = {
+        "pwm4_a",
+        "pwm4_b",
+};
+
+static const char * const pwm5_groups[] = {
+        "pwm5_a",
+        "pwm5_b",
+};
+
+static const char * const pwm6_groups[] = {
+        "pwm6_a",
+        "pwm6_b",
+};
+
 static const char * const sata0_groups[] = {
         "sata0_devslp_a",
         "sata0_devslp_b",
@@ -3636,9 +3952,26 @@ static const char * const ssi_groups[] = {
         "ssi9_ctrl_b",
 };
 
+static const char * const usb0_groups[] = {
+        "usb0",
+};
+
+static const char * const usb1_groups[] = {
+        "usb1",
+};
+
+static const char * const usb2_groups[] = {
+        "usb2",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(audio_clk),
         SH_PFC_FUNCTION(avb),
+        SH_PFC_FUNCTION(can0),
+        SH_PFC_FUNCTION(can1),
+        SH_PFC_FUNCTION(can_clk),
+        SH_PFC_FUNCTION(canfd0),
+        SH_PFC_FUNCTION(canfd1),
         SH_PFC_FUNCTION(hscif0),
         SH_PFC_FUNCTION(hscif1),
         SH_PFC_FUNCTION(hscif2),
@@ -3647,10 +3980,18 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(i2c1),
         SH_PFC_FUNCTION(i2c2),
         SH_PFC_FUNCTION(i2c6),
+        SH_PFC_FUNCTION(intc_ex),
         SH_PFC_FUNCTION(msiof0),
         SH_PFC_FUNCTION(msiof1),
         SH_PFC_FUNCTION(msiof2),
         SH_PFC_FUNCTION(msiof3),
+        SH_PFC_FUNCTION(pwm0),
+        SH_PFC_FUNCTION(pwm1),
+        SH_PFC_FUNCTION(pwm2),
+        SH_PFC_FUNCTION(pwm3),
+        SH_PFC_FUNCTION(pwm4),
+        SH_PFC_FUNCTION(pwm5),
+        SH_PFC_FUNCTION(pwm6),
         SH_PFC_FUNCTION(sata0),
         SH_PFC_FUNCTION(scif0),
         SH_PFC_FUNCTION(scif1),
@@ -3664,6 +4005,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(sdhi2),
         SH_PFC_FUNCTION(sdhi3),
         SH_PFC_FUNCTION(ssi),
+        SH_PFC_FUNCTION(usb0),
+        SH_PFC_FUNCTION(usb1),
+        SH_PFC_FUNCTION(usb2),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -4213,7 +4557,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                 0, 0, 0, 0, 0, 0, 0, 0,
                 /* RESERVED 3 */
                 0, 0,
-                MOD_SEL2_2_1
+                /* RESERVED 2, 1 */
+                0, 0, 0, 0,
                 MOD_SEL2_0 }
         },
         { },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index b0b328b3130b..6502e676d368 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -591,547 +591,547 @@ static const u16 pinmux_data[] = {
         PINMUX_SINGLE(IRQ3_B),
 
         /* IPSR0 */
-        PINMUX_IPSR_DATA(IP0_1_0, A0),
-        PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN),
+        PINMUX_IPSR_GPSR(IP0_1_0, A0),
+        PINMUX_IPSR_GPSR(IP0_1_0, ST0_CLKIN),
         PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
 
-        PINMUX_IPSR_DATA(IP0_3_2, A1),
-        PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ),
+        PINMUX_IPSR_GPSR(IP0_3_2, A1),
+        PINMUX_IPSR_GPSR(IP0_3_2, ST0_REQ),
         PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
 
-        PINMUX_IPSR_DATA(IP0_5_4, A2),
-        PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC),
+        PINMUX_IPSR_GPSR(IP0_5_4, A2),
+        PINMUX_IPSR_GPSR(IP0_5_4, ST0_SYC),
         PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
 
-        PINMUX_IPSR_DATA(IP0_7_6, A3),
-        PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD),
+        PINMUX_IPSR_GPSR(IP0_7_6, A3),
+        PINMUX_IPSR_GPSR(IP0_7_6, ST0_VLD),
         PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
 
-        PINMUX_IPSR_DATA(IP0_9_8, A4),
-        PINMUX_IPSR_DATA(IP0_9_8, ST0_D0),
+        PINMUX_IPSR_GPSR(IP0_9_8, A4),
+        PINMUX_IPSR_GPSR(IP0_9_8, ST0_D0),
         PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
 
-        PINMUX_IPSR_DATA(IP0_11_10, A5),
-        PINMUX_IPSR_DATA(IP0_11_10, ST0_D1),
+        PINMUX_IPSR_GPSR(IP0_11_10, A5),
+        PINMUX_IPSR_GPSR(IP0_11_10, ST0_D1),
         PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
 
-        PINMUX_IPSR_DATA(IP0_13_12, A6),
-        PINMUX_IPSR_DATA(IP0_13_12, ST0_D2),
+        PINMUX_IPSR_GPSR(IP0_13_12, A6),
+        PINMUX_IPSR_GPSR(IP0_13_12, ST0_D2),
         PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
 
-        PINMUX_IPSR_DATA(IP0_15_14, A7),
-        PINMUX_IPSR_DATA(IP0_15_14, ST0_D3),
+        PINMUX_IPSR_GPSR(IP0_15_14, A7),
+        PINMUX_IPSR_GPSR(IP0_15_14, ST0_D3),
         PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
 
-        PINMUX_IPSR_DATA(IP0_17_16, A8),
-        PINMUX_IPSR_DATA(IP0_17_16, ST0_D4),
+        PINMUX_IPSR_GPSR(IP0_17_16, A8),
+        PINMUX_IPSR_GPSR(IP0_17_16, ST0_D4),
         PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
 
-        PINMUX_IPSR_DATA(IP0_19_18, A9),
-        PINMUX_IPSR_DATA(IP0_19_18, ST0_D5),
+        PINMUX_IPSR_GPSR(IP0_19_18, A9),
+        PINMUX_IPSR_GPSR(IP0_19_18, ST0_D5),
         PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
 
-        PINMUX_IPSR_DATA(IP0_21_20, A10),
-        PINMUX_IPSR_DATA(IP0_21_20, ST0_D6),
+        PINMUX_IPSR_GPSR(IP0_21_20, A10),
+        PINMUX_IPSR_GPSR(IP0_21_20, ST0_D6),
         PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
 
-        PINMUX_IPSR_DATA(IP0_23_22, A11),
-        PINMUX_IPSR_DATA(IP0_23_22, ST0_D7),
+        PINMUX_IPSR_GPSR(IP0_23_22, A11),
+        PINMUX_IPSR_GPSR(IP0_23_22, ST0_D7),
         PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
 
-        PINMUX_IPSR_DATA(IP0_25_24, A12),
+        PINMUX_IPSR_GPSR(IP0_25_24, A12),
         PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
 
-        PINMUX_IPSR_DATA(IP0_27_26, A13),
+        PINMUX_IPSR_GPSR(IP0_27_26, A13),
         PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
 
-        PINMUX_IPSR_DATA(IP0_29_28, A14),
+        PINMUX_IPSR_GPSR(IP0_29_28, A14),
         PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
 
-        PINMUX_IPSR_DATA(IP0_31_30, A15),
-        PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN),
+        PINMUX_IPSR_GPSR(IP0_31_30, A15),
+        PINMUX_IPSR_GPSR(IP0_31_30, ST0_VCO_CLKIN),
         PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
 
 
         /* IPSR1 */
-        PINMUX_IPSR_DATA(IP1_1_0, A16),
-        PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM),
+        PINMUX_IPSR_GPSR(IP1_1_0, A16),
+        PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM),
         PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
 
-        PINMUX_IPSR_DATA(IP1_3_2, A17),
-        PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN),
+        PINMUX_IPSR_GPSR(IP1_3_2, A17),
+        PINMUX_IPSR_GPSR(IP1_3_2, ST1_VCO_CLKIN),
         PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
 
-        PINMUX_IPSR_DATA(IP1_5_4, A18),
-        PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM),
+        PINMUX_IPSR_GPSR(IP1_5_4, A18),
+        PINMUX_IPSR_GPSR(IP1_5_4, ST1_PWM),
         PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
 
-        PINMUX_IPSR_DATA(IP1_7_6, A19),
-        PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN),
+        PINMUX_IPSR_GPSR(IP1_7_6, A19),
+        PINMUX_IPSR_GPSR(IP1_7_6, ST1_CLKIN),
         PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
         PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
 
-        PINMUX_IPSR_DATA(IP1_9_8, A20),
-        PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ),
+        PINMUX_IPSR_GPSR(IP1_9_8, A20),
+        PINMUX_IPSR_GPSR(IP1_9_8, ST1_REQ),
         PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
 
-        PINMUX_IPSR_DATA(IP1_11_10, A21),
-        PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC),
+        PINMUX_IPSR_GPSR(IP1_11_10, A21),
+        PINMUX_IPSR_GPSR(IP1_11_10, ST1_SYC),
         PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
 
-        PINMUX_IPSR_DATA(IP1_13_12, A22),
-        PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD),
+        PINMUX_IPSR_GPSR(IP1_13_12, A22),
+        PINMUX_IPSR_GPSR(IP1_13_12, ST1_VLD),
         PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
 
-        PINMUX_IPSR_DATA(IP1_15_14, A23),
-        PINMUX_IPSR_DATA(IP1_15_14, ST1_D0),
+        PINMUX_IPSR_GPSR(IP1_15_14, A23),
+        PINMUX_IPSR_GPSR(IP1_15_14, ST1_D0),
         PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
 
-        PINMUX_IPSR_DATA(IP1_17_16, A24),
+        PINMUX_IPSR_GPSR(IP1_17_16, A24),
         PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
-        PINMUX_IPSR_DATA(IP1_17_16, ST1_D1),
+        PINMUX_IPSR_GPSR(IP1_17_16, ST1_D1),
 
-        PINMUX_IPSR_DATA(IP1_19_18, A25),
+        PINMUX_IPSR_GPSR(IP1_19_18, A25),
         PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
-        PINMUX_IPSR_DATA(IP1_17_16, ST1_D2),
+        PINMUX_IPSR_GPSR(IP1_17_16, ST1_D2),
 
-        PINMUX_IPSR_DATA(IP1_22_20, D0),
+        PINMUX_IPSR_GPSR(IP1_22_20, D0),
         PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
         PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0),
-        PINMUX_IPSR_DATA(IP1_22_20, ST1_D3),
+        PINMUX_IPSR_GPSR(IP1_22_20, ST1_D3),
         PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0),
 
-        PINMUX_IPSR_DATA(IP1_25_23, D1),
+        PINMUX_IPSR_GPSR(IP1_25_23, D1),
         PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
         PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0),
-        PINMUX_IPSR_DATA(IP1_25_23, ST1_D4),
+        PINMUX_IPSR_GPSR(IP1_25_23, ST1_D4),
         PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0),
 
-        PINMUX_IPSR_DATA(IP1_28_26, D2),
+        PINMUX_IPSR_GPSR(IP1_28_26, D2),
         PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
         PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0),
-        PINMUX_IPSR_DATA(IP1_28_26, ST1_D5),
+        PINMUX_IPSR_GPSR(IP1_28_26, ST1_D5),
         PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0),
 
-        PINMUX_IPSR_DATA(IP1_31_29, D3),
+        PINMUX_IPSR_GPSR(IP1_31_29, D3),
         PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
         PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0),
-        PINMUX_IPSR_DATA(IP1_31_29, ST1_D6),
+        PINMUX_IPSR_GPSR(IP1_31_29, ST1_D6),
         PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0),
 
         /* IPSR2 */
-        PINMUX_IPSR_DATA(IP2_2_0, D4),
+        PINMUX_IPSR_GPSR(IP2_2_0, D4),
         PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
         PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0),
-        PINMUX_IPSR_DATA(IP2_2_0, ST1_D7),
+        PINMUX_IPSR_GPSR(IP2_2_0, ST1_D7),
         PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0),
 
-        PINMUX_IPSR_DATA(IP2_4_3, D5),
+        PINMUX_IPSR_GPSR(IP2_4_3, D5),
         PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
         PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0),
         PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0),
 
-        PINMUX_IPSR_DATA(IP2_7_5, D6),
+        PINMUX_IPSR_GPSR(IP2_7_5, D6),
         PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
         PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0),
         PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
         PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0),
 
-        PINMUX_IPSR_DATA(IP2_10_8, D7),
+        PINMUX_IPSR_GPSR(IP2_10_8, D7),
         PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
         PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0),
         PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0),
         PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0),
 
-        PINMUX_IPSR_DATA(IP2_13_11, D8),
+        PINMUX_IPSR_GPSR(IP2_13_11, D8),
         PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
         PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
         PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0),
         PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0),
         PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
 
-        PINMUX_IPSR_DATA(IP2_16_14, D9),
+        PINMUX_IPSR_GPSR(IP2_16_14, D9),
         PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
         PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
         PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0),
         PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0),
         PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
 
-        PINMUX_IPSR_DATA(IP2_19_17, D10),
+        PINMUX_IPSR_GPSR(IP2_19_17, D10),
         PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
         PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
         PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0),
         PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
 
-        PINMUX_IPSR_DATA(IP2_22_20, D11),
+        PINMUX_IPSR_GPSR(IP2_22_20, D11),
         PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
         PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
         PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0),
 
-        PINMUX_IPSR_DATA(IP2_24_23, D12),
+        PINMUX_IPSR_GPSR(IP2_24_23, D12),
         PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0),
         PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
 
-        PINMUX_IPSR_DATA(IP2_27_25, D13),
+        PINMUX_IPSR_GPSR(IP2_27_25, D13),
         PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1),
         PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0),
         PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
 
-        PINMUX_IPSR_DATA(IP2_30_28, D14),
+        PINMUX_IPSR_GPSR(IP2_30_28, D14),
         PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1),
         PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0),
         PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
 
         /* IPSR3 */
-        PINMUX_IPSR_DATA(IP3_1_0, D15),
+        PINMUX_IPSR_GPSR(IP3_1_0, D15),
         PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1),
 
-        PINMUX_IPSR_DATA(IP3_2, CS1_A26),
+        PINMUX_IPSR_GPSR(IP3_2, CS1_A26),
         PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1),
 
-        PINMUX_IPSR_DATA(IP3_5_3, EX_CS1),
+        PINMUX_IPSR_GPSR(IP3_5_3, EX_CS1),
         PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1),
-        PINMUX_IPSR_DATA(IP3_5_3, ATACS0),
+        PINMUX_IPSR_GPSR(IP3_5_3, ATACS0),
         PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1),
-        PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0),
+        PINMUX_IPSR_GPSR(IP3_5_3, ET0_ETXD0),
 
-        PINMUX_IPSR_DATA(IP3_8_6, EX_CS2),
+        PINMUX_IPSR_GPSR(IP3_8_6, EX_CS2),
         PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1),
-        PINMUX_IPSR_DATA(IP3_8_6, ATACS1),
+        PINMUX_IPSR_GPSR(IP3_8_6, ATACS1),
         PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
         PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
 
-        PINMUX_IPSR_DATA(IP3_11_9, EX_CS3),
+        PINMUX_IPSR_GPSR(IP3_11_9, EX_CS3),
         PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
-        PINMUX_IPSR_DATA(IP3_11_9, ATARD),
+        PINMUX_IPSR_GPSR(IP3_11_9, ATARD),
         PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
         PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
 
-        PINMUX_IPSR_DATA(IP3_14_12, EX_CS4),
+        PINMUX_IPSR_GPSR(IP3_14_12, EX_CS4),
         PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
-        PINMUX_IPSR_DATA(IP3_14_12, ATAWR),
+        PINMUX_IPSR_GPSR(IP3_14_12, ATAWR),
         PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
         PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
 
-        PINMUX_IPSR_DATA(IP3_17_15, EX_CS5),
+        PINMUX_IPSR_GPSR(IP3_17_15, EX_CS5),
         PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
-        PINMUX_IPSR_DATA(IP3_17_15, ATADIR),
+        PINMUX_IPSR_GPSR(IP3_17_15, ATADIR),
         PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1),
         PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
 
-        PINMUX_IPSR_DATA(IP3_19_18, RD_WR),
-        PINMUX_IPSR_DATA(IP3_19_18, TCLK0),
+        PINMUX_IPSR_GPSR(IP3_19_18, RD_WR),
+        PINMUX_IPSR_GPSR(IP3_19_18, TCLK0),
         PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
-        PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4),
+        PINMUX_IPSR_GPSR(IP3_19_18, ET0_ETXD4),
 
-        PINMUX_IPSR_DATA(IP3_20, EX_WAIT0),
+        PINMUX_IPSR_GPSR(IP3_20, EX_WAIT0),
         PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1),
 
-        PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1),
+        PINMUX_IPSR_GPSR(IP3_23_21, EX_WAIT1),
         PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
-        PINMUX_IPSR_DATA(IP3_23_21, DREQ2),
+        PINMUX_IPSR_GPSR(IP3_23_21, DREQ2),
         PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
         PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
         PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
 
-        PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2),
+        PINMUX_IPSR_GPSR(IP3_26_24, EX_WAIT2),
         PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
-        PINMUX_IPSR_DATA(IP3_26_24, DACK2),
+        PINMUX_IPSR_GPSR(IP3_26_24, DACK2),
         PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
         PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
         PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
 
-        PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
+        PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
         PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
-        PINMUX_IPSR_DATA(IP3_29_27, ATAG),
+        PINMUX_IPSR_GPSR(IP3_29_27, ATAG),
         PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0),
-        PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7),
+        PINMUX_IPSR_GPSR(IP3_29_27, ET0_ETXD7),
 
         /* IPSR4 */
         PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
         PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD),
+        PINMUX_IPSR_GPSR(IP4_2_0, VI0_FIELD),
         PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
-        PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7),
+        PINMUX_IPSR_GPSR(IP4_2_0, ET0_ERXD7),
 
         PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
         PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC),
+        PINMUX_IPSR_GPSR(IP4_5_3, VI0_HSYNC),
         PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
-        PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV),
+        PINMUX_IPSR_GPSR(IP4_5_3, ET0_RX_DV),
 
         PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
         PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC),
+        PINMUX_IPSR_GPSR(IP4_8_6, VI0_VSYNC),
         PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
-        PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER),
+        PINMUX_IPSR_GPSR(IP4_8_6, ET0_RX_ER),
 
         PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0),
         PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0),
+        PINMUX_IPSR_GPSR(IP4_11_9, VI0_DATA0_VI0_B0),
         PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
-        PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS),
+        PINMUX_IPSR_GPSR(IP4_11_9, ET0_CRS),
 
         PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0),
         PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1),
+        PINMUX_IPSR_GPSR(IP4_14_12, VI0_DATA1_VI0_B1),
         PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
-        PINMUX_IPSR_DATA(IP4_14_12, ET0_COL),
+        PINMUX_IPSR_GPSR(IP4_14_12, ET0_COL),
 
         PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2),
+        PINMUX_IPSR_GPSR(IP4_17_15, VI0_DATA2_VI0_B2),
         PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
-        PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC),
+        PINMUX_IPSR_GPSR(IP4_17_15, ET0_MDC),
 
         PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_GPSR(IP4_19_18, VI0_DATA3_VI0_B3),
         PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
 
         PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4),
+        PINMUX_IPSR_GPSR(IP4_21_20, VI0_DATA4_VI0_B4),
         PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
 
         PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5),
+        PINMUX_IPSR_GPSR(IP4_23_22, VI0_DATA5_VI0_B5),
         PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
 
         PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0),
+        PINMUX_IPSR_GPSR(IP4_25_24, VI0_DATA6_VI0_G0),
         PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
 
         PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1),
+        PINMUX_IPSR_GPSR(IP4_27_26, VI0_DATA7_VI0_G1),
 
         PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP4_29_28, VI0_G2),
+        PINMUX_IPSR_GPSR(IP4_29_28, VI0_G2),
 
         PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0),
-        PINMUX_IPSR_DATA(IP4_31_30, VI0_G3),
+        PINMUX_IPSR_GPSR(IP4_31_30, VI0_G3),
 
         /* IPSR5 */
         PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
         PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0),
-        PINMUX_IPSR_DATA(IP5_2_0, VI0_G4),
+        PINMUX_IPSR_GPSR(IP5_2_0, VI0_G4),
         PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
 
         PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
         PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0),
-        PINMUX_IPSR_DATA(IP5_5_3, VI0_G5),
+        PINMUX_IPSR_GPSR(IP5_5_3, VI0_G5),
         PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
 
         PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
         PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0),
-        PINMUX_IPSR_DATA(IP4_8_6, VI0_R0),
+        PINMUX_IPSR_GPSR(IP4_8_6, VI0_R0),
         PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
 
         PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
         PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0),
-        PINMUX_IPSR_DATA(IP5_11_9, VI0_R1),
+        PINMUX_IPSR_GPSR(IP5_11_9, VI0_R1),
         PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
 
         PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
         PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0),
-        PINMUX_IPSR_DATA(IP5_14_12, VI0_R2),
+        PINMUX_IPSR_GPSR(IP5_14_12, VI0_R2),
         PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
 
         PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
         PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0),
-        PINMUX_IPSR_DATA(IP5_17_15, VI0_R3),
+        PINMUX_IPSR_GPSR(IP5_17_15, VI0_R3),
         PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
 
         PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
         PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0),
-        PINMUX_IPSR_DATA(IP5_20_18, VI0_R4),
+        PINMUX_IPSR_GPSR(IP5_20_18, VI0_R4),
         PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
 
         PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
         PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0),
-        PINMUX_IPSR_DATA(IP5_22_21, VI0_R5),
+        PINMUX_IPSR_GPSR(IP5_22_21, VI0_R5),
 
-        PINMUX_IPSR_DATA(IP5_24_23, REF125CK),
-        PINMUX_IPSR_DATA(IP5_24_23, ADTRG),
+        PINMUX_IPSR_GPSR(IP5_24_23, REF125CK),
+        PINMUX_IPSR_GPSR(IP5_24_23, ADTRG),
         PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2),
-        PINMUX_IPSR_DATA(IP5_26_25, REF50CK),
+        PINMUX_IPSR_GPSR(IP5_26_25, REF50CK),
         PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3),
         PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
 
         /* IPSR6 */
-        PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0),
+        PINMUX_IPSR_GPSR(IP6_2_0, DU0_DR0),
         PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
         PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3),
         PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0),
         PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
-        PINMUX_IPSR_DATA(IP6_2_0, HIFD00),
+        PINMUX_IPSR_GPSR(IP6_2_0, HIFD00),
 
-        PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1),
+        PINMUX_IPSR_GPSR(IP6_5_3, DU0_DR1),
         PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1),
         PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3),
         PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0),
         PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
-        PINMUX_IPSR_DATA(IP6_5_3, HIFD01),
+        PINMUX_IPSR_GPSR(IP6_5_3, HIFD01),
 
-        PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2),
+        PINMUX_IPSR_GPSR(IP6_7_6, DU0_DR2),
         PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1),
         PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
-        PINMUX_IPSR_DATA(IP6_7_6, HIFD02),
+        PINMUX_IPSR_GPSR(IP6_7_6, HIFD02),
 
-        PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3),
+        PINMUX_IPSR_GPSR(IP6_9_8, DU0_DR3),
         PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1),
         PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
-        PINMUX_IPSR_DATA(IP6_9_8, HIFD03),
+        PINMUX_IPSR_GPSR(IP6_9_8, HIFD03),
 
-        PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4),
+        PINMUX_IPSR_GPSR(IP6_11_10, DU0_DR4),
         PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2),
         PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
-        PINMUX_IPSR_DATA(IP6_11_10, HIFD04),
+        PINMUX_IPSR_GPSR(IP6_11_10, HIFD04),
 
-        PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5),
+        PINMUX_IPSR_GPSR(IP6_13_12, DU0_DR5),
         PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1),
         PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
-        PINMUX_IPSR_DATA(IP6_13_12, HIFD05),
+        PINMUX_IPSR_GPSR(IP6_13_12, HIFD05),
 
-        PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6),
+        PINMUX_IPSR_GPSR(IP6_15_14, DU0_DR6),
         PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
-        PINMUX_IPSR_DATA(IP6_15_14, HIFD06),
+        PINMUX_IPSR_GPSR(IP6_15_14, HIFD06),
 
-        PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7),
+        PINMUX_IPSR_GPSR(IP6_17_16, DU0_DR7),
         PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
-        PINMUX_IPSR_DATA(IP6_17_16, HIFD07),
+        PINMUX_IPSR_GPSR(IP6_17_16, HIFD07),
 
-        PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0),
+        PINMUX_IPSR_GPSR(IP6_20_18, DU0_DG0),
         PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
         PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0),
         PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
-        PINMUX_IPSR_DATA(IP6_20_18, HIFD08),
+        PINMUX_IPSR_GPSR(IP6_20_18, HIFD08),
 
-        PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1),
+        PINMUX_IPSR_GPSR(IP6_23_21, DU0_DG1),
         PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
         PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
-        PINMUX_IPSR_DATA(IP6_23_21, HIFD09),
+        PINMUX_IPSR_GPSR(IP6_23_21, HIFD09),
 
         /* IPSR7 */
-        PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2),
+        PINMUX_IPSR_GPSR(IP7_2_0, DU0_DG2),
         PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2),
         PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
         PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
-        PINMUX_IPSR_DATA(IP7_2_0, HIFD10),
+        PINMUX_IPSR_GPSR(IP7_2_0, HIFD10),
 
-        PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3),
+        PINMUX_IPSR_GPSR(IP7_5_3, DU0_DG3),
         PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2),
         PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
         PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
-        PINMUX_IPSR_DATA(IP7_5_3, HIFD11),
+        PINMUX_IPSR_GPSR(IP7_5_3, HIFD11),
 
-        PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4),
+        PINMUX_IPSR_GPSR(IP7_8_6, DU0_DG4),
         PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2),
         PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
         PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
-        PINMUX_IPSR_DATA(IP7_8_6, HIFD12),
+        PINMUX_IPSR_GPSR(IP7_8_6, HIFD12),
 
-        PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5),
+        PINMUX_IPSR_GPSR(IP7_11_9, DU0_DG5),
         PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2),
         PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
         PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
-        PINMUX_IPSR_DATA(IP7_11_9, HIFD13),
+        PINMUX_IPSR_GPSR(IP7_11_9, HIFD13),
 
-        PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6),
+        PINMUX_IPSR_GPSR(IP7_14_12, DU0_DG6),
         PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2),
         PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
         PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
-        PINMUX_IPSR_DATA(IP7_14_12, HIFD14),
+        PINMUX_IPSR_GPSR(IP7_14_12, HIFD14),
 
-        PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7),
+        PINMUX_IPSR_GPSR(IP7_17_15, DU0_DG7),
         PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2),
         PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
         PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
-        PINMUX_IPSR_DATA(IP7_17_15, HIFD15),
+        PINMUX_IPSR_GPSR(IP7_17_15, HIFD15),
 
-        PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0),
+        PINMUX_IPSR_GPSR(IP7_20_18, DU0_DB0),
         PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2),
         PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
         PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
-        PINMUX_IPSR_DATA(IP7_20_18, HIFCS),
+        PINMUX_IPSR_GPSR(IP7_20_18, HIFCS),
 
-        PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1),
+        PINMUX_IPSR_GPSR(IP7_23_21, DU0_DB1),
         PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2),
         PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
         PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
-        PINMUX_IPSR_DATA(IP7_23_21, HIFWR),
+        PINMUX_IPSR_GPSR(IP7_23_21, HIFWR),
 
-        PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2),
+        PINMUX_IPSR_GPSR(IP7_26_24, DU0_DB2),
         PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1),
         PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
         PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
 
-        PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3),
+        PINMUX_IPSR_GPSR(IP7_28_27, DU0_DB3),
         PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1),
         PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
-        PINMUX_IPSR_DATA(IP7_28_27, HIFRD),
+        PINMUX_IPSR_GPSR(IP7_28_27, HIFRD),
 
-        PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4),
-        PINMUX_IPSR_DATA(IP7_30_29, HIFINT),
+        PINMUX_IPSR_GPSR(IP7_30_29, DU0_DB4),
+        PINMUX_IPSR_GPSR(IP7_30_29, HIFINT),
 
         /* IPSR8 */
-        PINMUX_IPSR_DATA(IP8_1_0, DU0_DB5),
-        PINMUX_IPSR_DATA(IP8_1_0, HIFDREQ),
+        PINMUX_IPSR_GPSR(IP8_1_0, DU0_DB5),
+        PINMUX_IPSR_GPSR(IP8_1_0, HIFDREQ),
 
-        PINMUX_IPSR_DATA(IP8_3_2, DU0_DB6),
-        PINMUX_IPSR_DATA(IP8_3_2, HIFRDY),
+        PINMUX_IPSR_GPSR(IP8_3_2, DU0_DB6),
+        PINMUX_IPSR_GPSR(IP8_3_2, HIFRDY),
 
-        PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7),
+        PINMUX_IPSR_GPSR(IP8_5_4, DU0_DB7),
         PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
         PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1),
 
-        PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN),
+        PINMUX_IPSR_GPSR(IP8_7_6, DU0_DOTCLKIN),
         PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
         PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
 
-        PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT),
+        PINMUX_IPSR_GPSR(IP8_9_8, DU0_DOTCLKOUT),
         PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
         PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
 
-        PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
+        PINMUX_IPSR_GPSR(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
         PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
         PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
 
-        PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
+        PINMUX_IPSR_GPSR(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
         PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
         PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
 
-        PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF),
+        PINMUX_IPSR_GPSR(IP8_15_14, DU0_EXODDF_DU0_ODDF),
         PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
         PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
         PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
 
-        PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP),
+        PINMUX_IPSR_GPSR(IP8_17_16, DU0_DISP),
         PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
         PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1),
         PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
 
-        PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE),
+        PINMUX_IPSR_GPSR(IP8_19_18, DU0_CDE),
         PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1),
         PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
         PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
@@ -1139,12 +1139,12 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0),
         PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
         PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4),
-        PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0),
+        PINMUX_IPSR_GPSR(IP8_22_20, ET0_ERXD0),
 
         PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0),
         PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
         PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4),
-        PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1),
+        PINMUX_IPSR_GPSR(IP8_25_23, ET0_ERXD1),
 
         PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0),
         PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0),
@@ -1220,26 +1220,26 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
 
         /* IPSE10 */
-        PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23),
+        PINMUX_IPSR_GPSR(IP10_2_0, SSI_SCK23),
         PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1),
         PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3),
         PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1),
         PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
 
-        PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23),
+        PINMUX_IPSR_GPSR(IP10_5_3, SSI_WS23),
         PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1),
         PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3),
         PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
         PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1),
         PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
 
-        PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2),
+        PINMUX_IPSR_GPSR(IP10_8_6, SSI_SDATA2),
         PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1),
         PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2),
         PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1),
         PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
 
-        PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3),
+        PINMUX_IPSR_GPSR(IP10_11_9, SSI_SDATA3),
         PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1),
         PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2),
         PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1),
@@ -1254,13 +1254,13 @@ static const u16 pinmux_data[] = {
         PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
         PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1),
 
-        PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC),
+        PINMUX_IPSR_GPSR(IP10_18_16, AUDIO_CLKC),
         PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4),
         PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
         PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1),
         PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
 
-        PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT),
+        PINMUX_IPSR_GPSR(IP10_21_19, AUDIO_CLKOUT),
         PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4),
         PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
         PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1),
@@ -1271,85 +1271,85 @@ static const u16 pinmux_data[] = {
 
         PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
         PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3),
-        PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK),
+        PINMUX_IPSR_GPSR(IP10_24_23, MLB_CLK),
 
         PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
         PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1),
 
         PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
         PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1),
-        PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG),
+        PINMUX_IPSR_GPSR(IP10_27_26, MLB_SIG),
 
         PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
         PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2),
-        PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT),
+        PINMUX_IPSR_GPSR(IP10_29_28, MLB_DAT),
 
         /* IPSR11 */
-        PINMUX_IPSR_DATA(IP11_0, SCL1),
+        PINMUX_IPSR_GPSR(IP11_0, SCL1),
         PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
 
-        PINMUX_IPSR_DATA(IP11_1, SDA1),
+        PINMUX_IPSR_GPSR(IP11_1, SDA1),
         PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4),
 
-        PINMUX_IPSR_DATA(IP11_2, SDA0),
+        PINMUX_IPSR_GPSR(IP11_2, SDA0),
         PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0),
 
-        PINMUX_IPSR_DATA(IP11_3, SDSELF),
+        PINMUX_IPSR_GPSR(IP11_3, SDSELF),
         PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3),
 
         PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
         PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
-        PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK),
+        PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK),
         PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
-        PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4),
+        PINMUX_IPSR_GPSR(IP11_6_4, ET0_ERXD4),
 
         PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0),
         PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
-        PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB),
+        PINMUX_IPSR_GPSR(IP11_9_7, VI0_CLKENB),
         PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
-        PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5),
+        PINMUX_IPSR_GPSR(IP11_9_7, ET0_ERXD5),
 
         PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0),
         PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
         PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
-        PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6),
+        PINMUX_IPSR_GPSR(IP11_11_10, ET0_ERXD6),
 
         PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
         PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0),
 
-        PINMUX_IPSR_DATA(IP11_15_13, PENC1),
+        PINMUX_IPSR_GPSR(IP11_15_13, PENC1),
         PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3),
         PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B,  SEL_RCAN1_1),
         PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3),
         PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1),
 
-        PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1),
+        PINMUX_IPSR_GPSR(IP11_18_16, USB_OVC1),
         PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3),
         PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
         PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3),
         PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1),
 
-        PINMUX_IPSR_DATA(IP11_20_19, DREQ0),
+        PINMUX_IPSR_GPSR(IP11_20_19, DREQ0),
         PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
-        PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN),
+        PINMUX_IPSR_GPSR(IP11_20_19, ET0_TX_EN),
 
-        PINMUX_IPSR_DATA(IP11_22_21, DACK0),
+        PINMUX_IPSR_GPSR(IP11_22_21, DACK0),
         PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
-        PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER),
+        PINMUX_IPSR_GPSR(IP11_22_21, ET0_TX_ER),
 
-        PINMUX_IPSR_DATA(IP11_25_23, DREQ1),
+        PINMUX_IPSR_GPSR(IP11_25_23, DREQ1),
         PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
         PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1),
         PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
         PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
 
-        PINMUX_IPSR_DATA(IP11_27_26, DACK1),
+        PINMUX_IPSR_GPSR(IP11_27_26, DACK1),
         PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
         PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1),
         PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
 
-        PINMUX_IPSR_DATA(IP11_28, PRESETOUT),
-        PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
+        PINMUX_IPSR_GPSR(IP11_28, PRESETOUT),
+        PINMUX_IPSR_GPSR(IP11_28, ST_CLKOUT),
 };
 
 static const struct sh_pfc_pin pinmux_pins[] = {
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 2123ab49d6a5..a490834e2089 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -100,10 +100,31 @@ struct pinmux_cfg_reg {
         const u8 *var_field_width;
 };
 
+/*
+ * Describe a config register consisting of several fields of the same width
+ *   - name: Register name (unused, for documentation purposes only)
+ *   - r: Physical register address
+ *   - r_width: Width of the register (in bits)
+ *   - f_width: Width of the fixed-width register fields (in bits)
+ * This macro must be followed by initialization data: For each register field
+ * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
+ * one for each possible combination of the register field bit values.
+ */
 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
         .reg = r, .reg_width = r_width, .field_width = f_width,         \
         .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
 
+/*
+ * Describe a config register consisting of several fields of different widths
+ *   - name: Register name (unused, for documentation purposes only)
+ *   - r: Physical register address
+ *   - r_width: Width of the register (in bits)
+ *   - var_fw0, var_fwn...: List of widths of the register fields (in bits),
+ *                          From left to right (i.e. MSB to LSB)
+ * This macro must be followed by initialization data: For each register field
+ * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
+ * one for each possible combination of the register field bit values.
+ */
 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
         .reg = r, .reg_width = r_width, \
         .var_field_width = (const u8 [r_width]) \
@@ -116,6 +137,14 @@ struct pinmux_data_reg {
         const u16 *enum_ids;
 };
 
+/*
+ * Describe a data register
+ *   - name: Register name (unused, for documentation purposes only)
+ *   - r: Physical register address
+ *   - r_width: Width of the register (in bits)
+ * This macro must be followed by initialization data: For each register bit
+ * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
+ */
 #define PINMUX_DATA_REG(name, r, r_width) \
         .reg = r, .reg_width = r_width, \
         .enum_ids = (const u16 [r_width]) \
@@ -124,6 +153,10 @@ struct pinmux_irq {
         const short *gpios;
 };
 
+/*
+ * Describe the mapping from GPIOs to a single IRQ
+ *   - ids...: List of GPIOs that are mapped to the same IRQ
+ */
 #define PINMUX_IRQ(ids...)                         \
         { .gpios = (const short []) { ids, -1 } }
 
@@ -185,18 +218,65 @@ struct sh_pfc_soc_info {
  * sh_pfc_soc_info pinmux_data array macros
  */
 
+/*
+ * Describe generic pinmux data
+ *   - data_or_mark: *_DATA or *_MARK enum ID
+ *   - ids...: List of enum IDs to associate with data_or_mark
+ */
 #define PINMUX_DATA(data_or_mark, ids...)       data_or_mark, ids, 0
 
-#define PINMUX_IPSR_NOGP(ispr, fn)                                      \
+/*
+ * Describe a pinmux configuration without GPIO function that needs
+ * configuration in a Peripheral Function Select Register (IPSR)
+ *   - ipsr: IPSR field (unused, for documentation purposes only)
+ *   - fn: Function name, referring to a field in the IPSR
+ */
+#define PINMUX_IPSR_NOGP(ipsr, fn)                                      \
         PINMUX_DATA(fn##_MARK, FN_##fn)
-#define PINMUX_IPSR_DATA(ipsr, fn)                                      \
+
+/*
+ * Describe a pinmux configuration with GPIO function that needs configuration
+ * in both a Peripheral Function Select Register (IPSR) and in a
+ * GPIO/Peripheral Function Select Register (GPSR)
+ *   - ipsr: IPSR field
+ *   - fn: Function name, also referring to the IPSR field
+ */
+#define PINMUX_IPSR_GPSR(ipsr, fn)                                      \
         PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
-#define PINMUX_IPSR_NOGM(ispr, fn, ms)                                  \
-        PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
-#define PINMUX_IPSR_NOFN(ipsr, fn, ms)                                  \
-        PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
-#define PINMUX_IPSR_MSEL(ipsr, fn, ms)                                  \
-        PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
+
+/*
+ * Describe a pinmux configuration without GPIO function that needs
+ * configuration in a Peripheral Function Select Register (IPSR), and where the
+ * pinmux function has a representation in a Module Select Register (MOD_SEL).
+ *   - ipsr: IPSR field (unused, for documentation purposes only)
+ *   - fn: Function name, also referring to the IPSR field
+ *   - msel: Module selector
+ */
+#define PINMUX_IPSR_NOGM(ipsr, fn, msel)                                \
+        PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
+
+/*
+ * Describe a pinmux configuration with GPIO function where the pinmux function
+ * has no representation in a Peripheral Function Select Register (IPSR), but
+ * instead solely depends on a group selection.
+ *   - gpsr: GPSR field
+ *   - fn: Function name, also referring to the GPSR field
+ *   - gsel: Group selector
+ */
+#define PINMUX_IPSR_NOFN(gpsr, fn, gsel)                                \
+        PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
+
+/*
+ * Describe a pinmux configuration with GPIO function that needs configuration
+ * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
+ * Function Select Register (GPSR), and where the pinmux function has a
+ * representation in a Module Select Register (MOD_SEL).
+ *   - ipsr: IPSR field
+ *   - fn: Function name, also referring to the IPSR field
+ *   - msel: Module selector
+ */
+#define PINMUX_IPSR_MSEL(ipsr, fn, msel)                                \
+        PINMUX_DATA(fn##_MARK, FN_##msel, FN_##ipsr, FN_##fn)
 
 /*
  * Describe a pinmux configuration for a single-function pin with GPIO
@@ -381,7 +461,7 @@ struct sh_pfc_soc_info {
         PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
 
 /*
- * PORTnCR macro
+ * PORTnCR helper macro for SH-Mobile/R-Mobile
  */
 #define PORTCR(nr, reg)                                                 \
         {                                                               \
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
new file mode 100644
index 000000000000..0f28841b2332
--- /dev/null
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -0,0 +1,16 @@
+if ARCH_STM32 || COMPILE_TEST
+
+config PINCTRL_STM32
+        bool
+        depends on OF
+        select PINMUX
+        select GENERIC_PINCONF
+        select GPIOLIB
+
+config PINCTRL_STM32F429
+        bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429
+        depends on OF
+        default MACH_STM32F429
+        select PINCTRL_STM32
+
+endif
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
new file mode 100644
index 000000000000..fc17d4238845
--- /dev/null
+++ b/drivers/pinctrl/stm32/Makefile
@@ -0,0 +1,5 @@
+# Core
+obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_STM32F429) += pinctrl-stm32f429.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
new file mode 100644
index 000000000000..8deb566ed4cd
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -0,0 +1,829 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ *
+ * Heavily based on Mediatek's pinctrl driver
+ */
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-stm32.h"
+
+#define STM32_GPIO_MODER        0x00
+#define STM32_GPIO_TYPER        0x04
+#define STM32_GPIO_SPEEDR       0x08
+#define STM32_GPIO_PUPDR        0x0c
+#define STM32_GPIO_IDR          0x10
+#define STM32_GPIO_ODR          0x14
+#define STM32_GPIO_BSRR         0x18
+#define STM32_GPIO_LCKR         0x1c
+#define STM32_GPIO_AFRL         0x20
+#define STM32_GPIO_AFRH         0x24
+
+#define STM32_GPIO_PINS_PER_BANK 16
+
+#define gpio_range_to_bank(chip) \
+                container_of(chip, struct stm32_gpio_bank, range)
+
+static const char * const stm32_gpio_functions[] = {
+        "gpio", "af0", "af1",
+        "af2", "af3", "af4",
+        "af5", "af6", "af7",
+        "af8", "af9", "af10",
+        "af11", "af12", "af13",
+        "af14", "af15", "analog",
+};
+
+struct stm32_pinctrl_group {
+        const char *name;
+        unsigned long config;
+        unsigned pin;
+};
+
+struct stm32_gpio_bank {
+        void __iomem *base;
+        struct clk *clk;
+        spinlock_t lock;
+        struct gpio_chip gpio_chip;
+        struct pinctrl_gpio_range range;
+};
+
+struct stm32_pinctrl {
+        struct device *dev;
+        struct pinctrl_dev *pctl_dev;
+        struct pinctrl_desc pctl_desc;
+        struct stm32_pinctrl_group *groups;
+        unsigned ngroups;
+        const char **grp_names;
+        struct stm32_gpio_bank *banks;
+        unsigned nbanks;
+        const struct stm32_pinctrl_match_data *match_data;
+};
+
+static inline int stm32_gpio_pin(int gpio)
+{
+        return gpio % STM32_GPIO_PINS_PER_BANK;
+}
+
+static inline u32 stm32_gpio_get_mode(u32 function)
+{
+        switch (function) {
+        case STM32_PIN_GPIO:
+                return 0;
+        case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
+                return 2;
+        case STM32_PIN_ANALOG:
+                return 3;
+        }
+
+        return 0;
+}
+
+static inline u32 stm32_gpio_get_alt(u32 function)
+{
+        switch (function) {
+        case STM32_PIN_GPIO:
+                return 0;
+        case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
+                return function - 1;
+        case STM32_PIN_ANALOG:
+                return 0;
+        }
+
+        return 0;
+}
+
+/* GPIO functions */
+
+static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
+        unsigned offset, int value)
+{
+        if (!value)
+                offset += STM32_GPIO_PINS_PER_BANK;
+
+        clk_enable(bank->clk);
+
+        writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
+
+        clk_disable(bank->clk);
+}
+
+static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        pinctrl_free_gpio(chip->base + offset);
+}
+
+static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+        int ret;
+
+        clk_enable(bank->clk);
+
+        ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
+
+        clk_disable(bank->clk);
+
+        return ret;
+}
+
+static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+
+        __stm32_gpio_set(bank, offset, value);
+}
+
+static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        return pinctrl_gpio_direction_input(chip->base + offset);
+}
+
+static int stm32_gpio_direction_output(struct gpio_chip *chip,
+        unsigned offset, int value)
+{
+        struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+
+        __stm32_gpio_set(bank, offset, value);
+        pinctrl_gpio_direction_output(chip->base + offset);
+
+        return 0;
+}
+
+static struct gpio_chip stm32_gpio_template = {
+        .request                = stm32_gpio_request,
+        .free                   = stm32_gpio_free,
+        .get                    = stm32_gpio_get,
+        .set                    = stm32_gpio_set,
+        .direction_input        = stm32_gpio_direction_input,
+        .direction_output       = stm32_gpio_direction_output,
+};
+
+/* Pinctrl functions */
+
+static struct stm32_pinctrl_group *
+stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
+{
+        int i;
+
+        for (i = 0; i < pctl->ngroups; i++) {
+                struct stm32_pinctrl_group *grp = pctl->groups + i;
+
+                if (grp->pin == pin)
+                        return grp;
+        }
+
+        return NULL;
+}
+
+static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
+                u32 pin_num, u32 fnum)
+{
+        int i;
+
+        for (i = 0; i < pctl->match_data->npins; i++) {
+                const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
+                const struct stm32_desc_function *func = pin->functions;
+
+                if (pin->pin.number != pin_num)
+                        continue;
+
+                while (func && func->name) {
+                        if (func->num == fnum)
+                                return true;
+                        func++;
+                }
+
+                break;
+        }
+
+        return false;
+}
+
+static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
+                u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
+                struct pinctrl_map **map, unsigned *reserved_maps,
+                unsigned *num_maps)
+{
+        if (*num_maps == *reserved_maps)
+                return -ENOSPC;
+
+        (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+        (*map)[*num_maps].data.mux.group = grp->name;
+
+        if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
+                dev_err(pctl->dev, "invalid function %d on pin %d .\n",
+                                fnum, pin);
+                return -EINVAL;
+        }
+
+        (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
+        (*num_maps)++;
+
+        return 0;
+}
+
+static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+                                      struct device_node *node,
+                                      struct pinctrl_map **map,
+                                      unsigned *reserved_maps,
+                                      unsigned *num_maps)
+{
+        struct stm32_pinctrl *pctl;
+        struct stm32_pinctrl_group *grp;
+        struct property *pins;
+        u32 pinfunc, pin, func;
+        unsigned long *configs;
+        unsigned int num_configs;
+        bool has_config = 0;
+        unsigned reserve = 0;
+        int num_pins, num_funcs, maps_per_pin, i, err;
+
+        pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        pins = of_find_property(node, "pinmux", NULL);
+        if (!pins) {
+                dev_err(pctl->dev, "missing pins property in node %s .\n",
+                                node->name);
+                return -EINVAL;
+        }
+
+        err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
+                &num_configs);
+        if (err)
+                return err;
+
+        if (num_configs)
+                has_config = 1;
+
+        num_pins = pins->length / sizeof(u32);
+        num_funcs = num_pins;
+        maps_per_pin = 0;
+        if (num_funcs)
+                maps_per_pin++;
+        if (has_config && num_pins >= 1)
+                maps_per_pin++;
+
+        if (!num_pins || !maps_per_pin)
+                return -EINVAL;
+
+        reserve = num_pins * maps_per_pin;
+
+        err = pinctrl_utils_reserve_map(pctldev, map,
+                        reserved_maps, num_maps, reserve);
+        if (err)
+                return err;
+
+        for (i = 0; i < num_pins; i++) {
+                err = of_property_read_u32_index(node, "pinmux",
+                                i, &pinfunc);
+                if (err)
+                        return err;
+
+                pin = STM32_GET_PIN_NO(pinfunc);
+                func = STM32_GET_PIN_FUNC(pinfunc);
+
+                if (pin >= pctl->match_data->npins) {
+                        dev_err(pctl->dev, "invalid pin number.\n");
+                        return -EINVAL;
+                }
+
+                if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
+                        dev_err(pctl->dev, "invalid function.\n");
+                        return -EINVAL;
+                }
+
+                grp = stm32_pctrl_find_group_by_pin(pctl, pin);
+                if (!grp) {
+                        dev_err(pctl->dev, "unable to match pin %d to group\n",
+                                        pin);
+                        return -EINVAL;
+                }
+
+                err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
+                                reserved_maps, num_maps);
+                if (err)
+                        return err;
+
+                if (has_config) {
+                        err = pinctrl_utils_add_map_configs(pctldev, map,
+                                        reserved_maps, num_maps, grp->name,
+                                        configs, num_configs,
+                                        PIN_MAP_TYPE_CONFIGS_GROUP);
+                        if (err)
+                                return err;
+                }
+        }
+
+        return 0;
+}
+
+static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                 struct device_node *np_config,
+                                 struct pinctrl_map **map, unsigned *num_maps)
+{
+        struct device_node *np;
+        unsigned reserved_maps;
+        int ret;
+
+        *map = NULL;
+        *num_maps = 0;
+        reserved_maps = 0;
+
+        for_each_child_of_node(np_config, np) {
+                ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
+                                &reserved_maps, num_maps);
+                if (ret < 0) {
+                        pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
+static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+        struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        return pctl->ngroups;
+}
+
+static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
+                                              unsigned group)
+{
+        struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        return pctl->groups[group].name;
+}
+
+static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
+                                      unsigned group,
+                                      const unsigned **pins,
+                                      unsigned *num_pins)
+{
+        struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        *pins = (unsigned *)&pctl->groups[group].pin;
+        *num_pins = 1;
+
+        return 0;
+}
+
+static const struct pinctrl_ops stm32_pctrl_ops = {
+        .dt_node_to_map         = stm32_pctrl_dt_node_to_map,
+        .dt_free_map            = pinctrl_utils_dt_free_map,
+        .get_groups_count       = stm32_pctrl_get_groups_count,
+        .get_group_name         = stm32_pctrl_get_group_name,
+        .get_group_pins         = stm32_pctrl_get_group_pins,
+};
+
+
+/* Pinmux functions */
+
+static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
+{
+        return ARRAY_SIZE(stm32_gpio_functions);
+}
+
+static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
+                                           unsigned selector)
+{
+        return stm32_gpio_functions[selector];
+}
+
+static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
+                                     unsigned function,
+                                     const char * const **groups,
+                                     unsigned * const num_groups)
+{
+        struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        *groups = pctl->grp_names;
+        *num_groups = pctl->ngroups;
+
+        return 0;
+}
+
+static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
+                int pin, u32 mode, u32 alt)
+{
+        u32 val;
+        int alt_shift = (pin % 8) * 4;
+        int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
+        unsigned long flags;
+
+        clk_enable(bank->clk);
+        spin_lock_irqsave(&bank->lock, flags);
+
+        val = readl_relaxed(bank->base + alt_offset);
+        val &= ~GENMASK(alt_shift + 3, alt_shift);
+        val |= (alt << alt_shift);
+        writel_relaxed(val, bank->base + alt_offset);
+
+        val = readl_relaxed(bank->base + STM32_GPIO_MODER);
+        val &= ~GENMASK(pin * 2 + 1, pin * 2);
+        val |= mode << (pin * 2);
+        writel_relaxed(val, bank->base + STM32_GPIO_MODER);
+
+        spin_unlock_irqrestore(&bank->lock, flags);
+        clk_disable(bank->clk);
+}
+
+static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
+                            unsigned function,
+                            unsigned group)
+{
+        bool ret;
+        struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct stm32_pinctrl_group *g = pctl->groups + group;
+        struct pinctrl_gpio_range *range;
+        struct stm32_gpio_bank *bank;
+        u32 mode, alt;
+        int pin;
+
+        ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
+        if (!ret) {
+                dev_err(pctl->dev, "invalid function %d on group %d .\n",
+                                function, group);
+                return -EINVAL;
+        }
+
+        range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
+        bank = gpio_range_to_bank(range);
+        pin = stm32_gpio_pin(g->pin);
+
+        mode = stm32_gpio_get_mode(function);
+        alt = stm32_gpio_get_alt(function);
+
+        stm32_pmx_set_mode(bank, pin, mode, alt);
+
+        return 0;
+}
+
+static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+                        struct pinctrl_gpio_range *range, unsigned gpio,
+                        bool input)
+{
+        struct stm32_gpio_bank *bank = gpio_range_to_bank(range);
+        int pin = stm32_gpio_pin(gpio);
+
+        stm32_pmx_set_mode(bank, pin, !input, 0);
+
+        return 0;
+}
+
+static const struct pinmux_ops stm32_pmx_ops = {
+        .get_functions_count    = stm32_pmx_get_funcs_cnt,
+        .get_function_name      = stm32_pmx_get_func_name,
+        .get_function_groups    = stm32_pmx_get_func_groups,
+        .set_mux                = stm32_pmx_set_mux,
+        .gpio_set_direction     = stm32_pmx_gpio_set_direction,
+};
+
+/* Pinconf functions */
+
+static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
+        unsigned offset, u32 drive)
+{
+        unsigned long flags;
+        u32 val;
+
+        clk_enable(bank->clk);
+        spin_lock_irqsave(&bank->lock, flags);
+
+        val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
+        val &= ~BIT(offset);
+        val |= drive << offset;
+        writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
+
+        spin_unlock_irqrestore(&bank->lock, flags);
+        clk_disable(bank->clk);
+}
+
+static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
+        unsigned offset, u32 speed)
+{
+        unsigned long flags;
+        u32 val;
+
+        clk_enable(bank->clk);
+        spin_lock_irqsave(&bank->lock, flags);
+
+        val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
+        val &= ~GENMASK(offset * 2 + 1, offset * 2);
+        val |= speed << (offset * 2);
+        writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
+
+        spin_unlock_irqrestore(&bank->lock, flags);
+        clk_disable(bank->clk);
+}
+
+static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
+        unsigned offset, u32 bias)
+{
+        unsigned long flags;
+        u32 val;
+
+        clk_enable(bank->clk);
+        spin_lock_irqsave(&bank->lock, flags);
+
+        val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
+        val &= ~GENMASK(offset * 2 + 1, offset * 2);
+        val |= bias << (offset * 2);
+        writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
+
+        spin_unlock_irqrestore(&bank->lock, flags);
+        clk_disable(bank->clk);
+}
+
+static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
+                unsigned int pin, enum pin_config_param param,
+                enum pin_config_param arg)
+{
+        struct pinctrl_gpio_range *range;
+        struct stm32_gpio_bank *bank;
+        int offset, ret = 0;
+
+        range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
+        bank = gpio_range_to_bank(range);
+        offset = stm32_gpio_pin(pin);
+
+        switch (param) {
+        case PIN_CONFIG_DRIVE_PUSH_PULL:
+                stm32_pconf_set_driving(bank, offset, 0);
+                break;
+        case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+                stm32_pconf_set_driving(bank, offset, 1);
+                break;
+        case PIN_CONFIG_SLEW_RATE:
+                stm32_pconf_set_speed(bank, offset, arg);
+                break;
+        case PIN_CONFIG_BIAS_DISABLE:
+                stm32_pconf_set_bias(bank, offset, 0);
+                break;
+        case PIN_CONFIG_BIAS_PULL_UP:
+                stm32_pconf_set_bias(bank, offset, 1);
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                stm32_pconf_set_bias(bank, offset, 2);
+                break;
+        case PIN_CONFIG_OUTPUT:
+                __stm32_gpio_set(bank, offset, arg);
+                ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false);
+                break;
+        default:
+                ret = -EINVAL;
+        }
+
+        return ret;
+}
+
+static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
+                                 unsigned group,
+                                 unsigned long *config)
+{
+        struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        *config = pctl->groups[group].config;
+
+        return 0;
+}
+
+static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
+                                 unsigned long *configs, unsigned num_configs)
+{
+        struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct stm32_pinctrl_group *g = &pctl->groups[group];
+        int i, ret;
+
+        for (i = 0; i < num_configs; i++) {
+                ret = stm32_pconf_parse_conf(pctldev, g->pin,
+                        pinconf_to_config_param(configs[i]),
+                        pinconf_to_config_argument(configs[i]));
+                if (ret < 0)
+                        return ret;
+
+                g->config = configs[i];
+        }
+
+        return 0;
+}
+
+static const struct pinconf_ops stm32_pconf_ops = {
+        .pin_config_group_get   = stm32_pconf_group_get,
+        .pin_config_group_set   = stm32_pconf_group_set,
+};
+
+static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
+        struct device_node *np)
+{
+        int bank_nr = pctl->nbanks;
+        struct stm32_gpio_bank *bank = &pctl->banks[bank_nr];
+        struct pinctrl_gpio_range *range = &bank->range;
+        struct device *dev = pctl->dev;
+        struct resource res;
+        struct reset_control *rstc;
+        int err, npins;
+
+        rstc = of_reset_control_get(np, NULL);
+        if (!IS_ERR(rstc))
+                reset_control_deassert(rstc);
+
+        if (of_address_to_resource(np, 0, &res))
+                return -ENODEV;
+
+        bank->base = devm_ioremap_resource(dev, &res);
+        if (IS_ERR(bank->base))
+                return PTR_ERR(bank->base);
+
+        bank->clk = of_clk_get_by_name(np, NULL);
+        if (IS_ERR(bank->clk)) {
+                dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
+                return PTR_ERR(bank->clk);
+        }
+
+        err = clk_prepare(bank->clk);
+        if (err) {
+                dev_err(dev, "failed to prepare clk (%d)\n", err);
+                return err;
+        }
+
+        npins = pctl->match_data->npins;
+        npins -= bank_nr * STM32_GPIO_PINS_PER_BANK;
+        if (npins < 0)
+                return -EINVAL;
+        else if (npins > STM32_GPIO_PINS_PER_BANK)
+                npins = STM32_GPIO_PINS_PER_BANK;
+
+        bank->gpio_chip = stm32_gpio_template;
+        bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
+        bank->gpio_chip.ngpio = npins;
+        bank->gpio_chip.of_node = np;
+        bank->gpio_chip.parent = dev;
+        spin_lock_init(&bank->lock);
+
+        of_property_read_string(np, "st,bank-name", &range->name);
+        bank->gpio_chip.label = range->name;
+
+        range->id = bank_nr;
+        range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK;
+        range->npins = bank->gpio_chip.ngpio;
+        range->gc = &bank->gpio_chip;
+        err = gpiochip_add_data(&bank->gpio_chip, bank);
+        if (err) {
+                dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
+                return err;
+        }
+
+        dev_info(dev, "%s bank added\n", range->name);
+        return 0;
+}
+
+static int stm32_pctrl_build_state(struct platform_device *pdev)
+{
+        struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
+        int i;
+
+        pctl->ngroups = pctl->match_data->npins;
+
+        /* Allocate groups */
+        pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
+                                    sizeof(*pctl->groups), GFP_KERNEL);
+        if (!pctl->groups)
+                return -ENOMEM;
+
+        /* We assume that one pin is one group, use pin name as group name. */
+        pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
+                                       sizeof(*pctl->grp_names), GFP_KERNEL);
+        if (!pctl->grp_names)
+                return -ENOMEM;
+
+        for (i = 0; i < pctl->match_data->npins; i++) {
+                const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
+                struct stm32_pinctrl_group *group = pctl->groups + i;
+
+                group->name = pin->pin.name;
+                group->pin = pin->pin.number;
+
+                pctl->grp_names[i] = pin->pin.name;
+        }
+
+        return 0;
+}
+
+int stm32_pctl_probe(struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct device_node *child;
+        const struct of_device_id *match;
+        struct device *dev = &pdev->dev;
+        struct stm32_pinctrl *pctl;
+        struct pinctrl_pin_desc *pins;
+        int i, ret, banks = 0;
+
+        if (!np)
+                return -EINVAL;
+
+        match = of_match_device(dev->driver->of_match_table, dev);
+        if (!match || !match->data)
+                return -EINVAL;
+
+        if (!of_find_property(np, "pins-are-numbered", NULL)) {
+                dev_err(dev, "only support pins-are-numbered format\n");
+                return -EINVAL;
+        }
+
+        pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
+        if (!pctl)
+                return -ENOMEM;
+
+        platform_set_drvdata(pdev, pctl);
+
+        pctl->dev = dev;
+        pctl->match_data = match->data;
+        ret = stm32_pctrl_build_state(pdev);
+        if (ret) {
+                dev_err(dev, "build state failed: %d\n", ret);
+                return -EINVAL;
+        }
+
+        for_each_child_of_node(np, child)
+                if (of_property_read_bool(child, "gpio-controller"))
+                        banks++;
+
+        if (!banks) {
+                dev_err(dev, "at least one GPIO bank is required\n");
+                return -EINVAL;
+        }
+
+        pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
+                        GFP_KERNEL);
+        if (!pctl->banks)
+                return -ENOMEM;
+
+        for_each_child_of_node(np, child) {
+                if (of_property_read_bool(child, "gpio-controller")) {
+                        ret = stm32_gpiolib_register_bank(pctl, child);
+                        if (ret)
+                                return ret;
+
+                        pctl->nbanks++;
+                }
+        }
+
+        pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
+                            GFP_KERNEL);
+        if (!pins)
+                return -ENOMEM;
+
+        for (i = 0; i < pctl->match_data->npins; i++)
+                pins[i] = pctl->match_data->pins[i].pin;
+
+        pctl->pctl_desc.name = dev_name(&pdev->dev);
+        pctl->pctl_desc.owner = THIS_MODULE;
+        pctl->pctl_desc.pins = pins;
+        pctl->pctl_desc.npins = pctl->match_data->npins;
+        pctl->pctl_desc.confops = &stm32_pconf_ops;
+        pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
+        pctl->pctl_desc.pmxops = &stm32_pmx_ops;
+        pctl->dev = &pdev->dev;
+
+        pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
+        if (!pctl->pctl_dev) {
+                dev_err(&pdev->dev, "Failed pinctrl registration\n");
+                return -EINVAL;
+        }
+
+        for (i = 0; i < pctl->nbanks; i++)
+                pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range);
+
+        dev_info(dev, "Pinctrl STM32 initialized\n");
+
+        return 0;
+}
+
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
new file mode 100644
index 000000000000..35ebc94c01e4
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+#ifndef __PINCTRL_STM32_H
+#define __PINCTRL_STM32_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
+#define STM32_PIN_NO(x) ((x) << 8)
+#define STM32_GET_PIN_NO(x) ((x) >> 8)
+#define STM32_GET_PIN_FUNC(x) ((x) & 0xff)
+
+#define STM32_PIN_GPIO          0
+#define STM32_PIN_AF(x)         ((x) + 1)
+#define STM32_PIN_ANALOG        (STM32_PIN_AF(15) + 1)
+
+struct stm32_desc_function {
+        const char *name;
+        const unsigned char num;
+};
+
+struct stm32_desc_pin {
+        struct pinctrl_pin_desc pin;
+        const struct stm32_desc_function *functions;
+};
+
+#define STM32_PIN(_pin, ...)                                    \
+        {                                                       \
+                .pin = _pin,                                    \
+                .functions = (struct stm32_desc_function[]){    \
+                        __VA_ARGS__, { } },                     \
+        }
+
+#define STM32_FUNCTION(_num, _name)             \
+        {                                                       \
+                .num = _num,                                    \
+                .name = _name,                                  \
+        }
+
+struct stm32_pinctrl_match_data {
+        const struct stm32_desc_pin *pins;
+        const unsigned int npins;
+};
+
+int stm32_pctl_probe(struct platform_device *pdev);
+
+#endif /* __PINCTRL_STM32_H */
+
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f429.c b/drivers/pinctrl/stm32/pinctrl-stm32f429.c
new file mode 100644
index 000000000000..e9b15dc0654b
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f429.c
@@ -0,0 +1,1591 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-stm32.h"
+
+static const struct stm32_desc_pin stm32f429_pins[] = {
+        STM32_PIN(
+                PINCTRL_PIN(0, "PA0"),
+                STM32_FUNCTION(0, "GPIOA0"),
+                STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+                STM32_FUNCTION(3, "TIM5_CH1"),
+                STM32_FUNCTION(4, "TIM8_ETR"),
+                STM32_FUNCTION(8, "USART2_CTS"),
+                STM32_FUNCTION(9, "UART4_TX"),
+                STM32_FUNCTION(12, "ETH_MII_CRS"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(1, "PA1"),
+                STM32_FUNCTION(0, "GPIOA1"),
+                STM32_FUNCTION(2, "TIM2_CH2"),
+                STM32_FUNCTION(3, "TIM5_CH2"),
+                STM32_FUNCTION(8, "USART2_RTS"),
+                STM32_FUNCTION(9, "UART4_RX"),
+                STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(2, "PA2"),
+                STM32_FUNCTION(0, "GPIOA2"),
+                STM32_FUNCTION(2, "TIM2_CH3"),
+                STM32_FUNCTION(3, "TIM5_CH3"),
+                STM32_FUNCTION(4, "TIM9_CH1"),
+                STM32_FUNCTION(8, "USART2_TX"),
+                STM32_FUNCTION(12, "ETH_MDIO"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(3, "PA3"),
+                STM32_FUNCTION(0, "GPIOA3"),
+                STM32_FUNCTION(2, "TIM2_CH4"),
+                STM32_FUNCTION(3, "TIM5_CH4"),
+                STM32_FUNCTION(4, "TIM9_CH2"),
+                STM32_FUNCTION(8, "USART2_RX"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
+                STM32_FUNCTION(12, "ETH_MII_COL"),
+                STM32_FUNCTION(15, "LCD_B5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(4, "PA4"),
+                STM32_FUNCTION(0, "GPIOA4"),
+                STM32_FUNCTION(6, "SPI1_NSS"),
+                STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
+                STM32_FUNCTION(8, "USART2_CK"),
+                STM32_FUNCTION(13, "OTG_HS_SOF"),
+                STM32_FUNCTION(14, "DCMI_HSYNC"),
+                STM32_FUNCTION(15, "LCD_VSYNC"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(5, "PA5"),
+                STM32_FUNCTION(0, "GPIOA5"),
+                STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+                STM32_FUNCTION(4, "TIM8_CH1N"),
+                STM32_FUNCTION(6, "SPI1_SCK"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_CK"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(6, "PA6"),
+                STM32_FUNCTION(0, "GPIOA6"),
+                STM32_FUNCTION(2, "TIM1_BKIN"),
+                STM32_FUNCTION(3, "TIM3_CH1"),
+                STM32_FUNCTION(4, "TIM8_BKIN"),
+                STM32_FUNCTION(6, "SPI1_MISO"),
+                STM32_FUNCTION(10, "TIM13_CH1"),
+                STM32_FUNCTION(14, "DCMI_PIXCLK"),
+                STM32_FUNCTION(15, "LCD_G2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(7, "PA7"),
+                STM32_FUNCTION(0, "GPIOA7"),
+                STM32_FUNCTION(2, "TIM1_CH1N"),
+                STM32_FUNCTION(3, "TIM3_CH2"),
+                STM32_FUNCTION(4, "TIM8_CH1N"),
+                STM32_FUNCTION(6, "SPI1_MOSI"),
+                STM32_FUNCTION(10, "TIM14_CH1"),
+                STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(8, "PA8"),
+                STM32_FUNCTION(0, "GPIOA8"),
+                STM32_FUNCTION(1, "MCO1"),
+                STM32_FUNCTION(2, "TIM1_CH1"),
+                STM32_FUNCTION(5, "I2C3_SCL"),
+                STM32_FUNCTION(8, "USART1_CK"),
+                STM32_FUNCTION(11, "OTG_FS_SOF"),
+                STM32_FUNCTION(15, "LCD_R6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(9, "PA9"),
+                STM32_FUNCTION(0, "GPIOA9"),
+                STM32_FUNCTION(2, "TIM1_CH2"),
+                STM32_FUNCTION(5, "I2C3_SMBA"),
+                STM32_FUNCTION(8, "USART1_TX"),
+                STM32_FUNCTION(14, "DCMI_D0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(10, "PA10"),
+                STM32_FUNCTION(0, "GPIOA10"),
+                STM32_FUNCTION(2, "TIM1_CH3"),
+                STM32_FUNCTION(8, "USART1_RX"),
+                STM32_FUNCTION(11, "OTG_FS_ID"),
+                STM32_FUNCTION(14, "DCMI_D1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(11, "PA11"),
+                STM32_FUNCTION(0, "GPIOA11"),
+                STM32_FUNCTION(2, "TIM1_CH4"),
+                STM32_FUNCTION(8, "USART1_CTS"),
+                STM32_FUNCTION(10, "CAN1_RX"),
+                STM32_FUNCTION(11, "OTG_FS_DM"),
+                STM32_FUNCTION(15, "LCD_R4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(12, "PA12"),
+                STM32_FUNCTION(0, "GPIOA12"),
+                STM32_FUNCTION(2, "TIM1_ETR"),
+                STM32_FUNCTION(8, "USART1_RTS"),
+                STM32_FUNCTION(10, "CAN1_TX"),
+                STM32_FUNCTION(11, "OTG_FS_DP"),
+                STM32_FUNCTION(15, "LCD_R5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(13, "PA13"),
+                STM32_FUNCTION(0, "GPIOA13"),
+                STM32_FUNCTION(1, "JTMS SWDIO"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(14, "PA14"),
+                STM32_FUNCTION(0, "GPIOA14"),
+                STM32_FUNCTION(1, "JTCK SWCLK"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(15, "PA15"),
+                STM32_FUNCTION(0, "GPIOA15"),
+                STM32_FUNCTION(1, "JTDI"),
+                STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+                STM32_FUNCTION(6, "SPI1_NSS"),
+                STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(16, "PB0"),
+                STM32_FUNCTION(0, "GPIOB0"),
+                STM32_FUNCTION(2, "TIM1_CH2N"),
+                STM32_FUNCTION(3, "TIM3_CH3"),
+                STM32_FUNCTION(4, "TIM8_CH2N"),
+                STM32_FUNCTION(10, "LCD_R3"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_D1"),
+                STM32_FUNCTION(12, "ETH_MII_RXD2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(17, "PB1"),
+                STM32_FUNCTION(0, "GPIOB1"),
+                STM32_FUNCTION(2, "TIM1_CH3N"),
+                STM32_FUNCTION(3, "TIM3_CH4"),
+                STM32_FUNCTION(4, "TIM8_CH3N"),
+                STM32_FUNCTION(10, "LCD_R6"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_D2"),
+                STM32_FUNCTION(12, "ETH_MII_RXD3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(18, "PB2"),
+                STM32_FUNCTION(0, "GPIOB2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(19, "PB3"),
+                STM32_FUNCTION(0, "GPIOB3"),
+                STM32_FUNCTION(1, "JTDO TRACESWO"),
+                STM32_FUNCTION(2, "TIM2_CH2"),
+                STM32_FUNCTION(6, "SPI1_SCK"),
+                STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(20, "PB4"),
+                STM32_FUNCTION(0, "GPIOB4"),
+                STM32_FUNCTION(1, "NJTRST"),
+                STM32_FUNCTION(3, "TIM3_CH1"),
+                STM32_FUNCTION(6, "SPI1_MISO"),
+                STM32_FUNCTION(7, "SPI3_MISO"),
+                STM32_FUNCTION(8, "I2S3EXT_SD"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(21, "PB5"),
+                STM32_FUNCTION(0, "GPIOB5"),
+                STM32_FUNCTION(3, "TIM3_CH2"),
+                STM32_FUNCTION(5, "I2C1_SMBA"),
+                STM32_FUNCTION(6, "SPI1_MOSI"),
+                STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
+                STM32_FUNCTION(10, "CAN2_RX"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_D7"),
+                STM32_FUNCTION(12, "ETH_PPS_OUT"),
+                STM32_FUNCTION(13, "FMC_SDCKE1"),
+                STM32_FUNCTION(14, "DCMI_D10"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(22, "PB6"),
+                STM32_FUNCTION(0, "GPIOB6"),
+                STM32_FUNCTION(3, "TIM4_CH1"),
+                STM32_FUNCTION(5, "I2C1_SCL"),
+                STM32_FUNCTION(8, "USART1_TX"),
+                STM32_FUNCTION(10, "CAN2_TX"),
+                STM32_FUNCTION(13, "FMC_SDNE1"),
+                STM32_FUNCTION(14, "DCMI_D5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(23, "PB7"),
+                STM32_FUNCTION(0, "GPIOB7"),
+                STM32_FUNCTION(3, "TIM4_CH2"),
+                STM32_FUNCTION(5, "I2C1_SDA"),
+                STM32_FUNCTION(8, "USART1_RX"),
+                STM32_FUNCTION(13, "FMC_NL"),
+                STM32_FUNCTION(14, "DCMI_VSYNC"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(24, "PB8"),
+                STM32_FUNCTION(0, "GPIOB8"),
+                STM32_FUNCTION(3, "TIM4_CH3"),
+                STM32_FUNCTION(4, "TIM10_CH1"),
+                STM32_FUNCTION(5, "I2C1_SCL"),
+                STM32_FUNCTION(10, "CAN1_RX"),
+                STM32_FUNCTION(12, "ETH_MII_TXD3"),
+                STM32_FUNCTION(13, "SDIO_D4"),
+                STM32_FUNCTION(14, "DCMI_D6"),
+                STM32_FUNCTION(15, "LCD_B6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(25, "PB9"),
+                STM32_FUNCTION(0, "GPIOB9"),
+                STM32_FUNCTION(3, "TIM4_CH4"),
+                STM32_FUNCTION(4, "TIM11_CH1"),
+                STM32_FUNCTION(5, "I2C1_SDA"),
+                STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
+                STM32_FUNCTION(10, "CAN1_TX"),
+                STM32_FUNCTION(13, "SDIO_D5"),
+                STM32_FUNCTION(14, "DCMI_D7"),
+                STM32_FUNCTION(15, "LCD_B7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(26, "PB10"),
+                STM32_FUNCTION(0, "GPIOB10"),
+                STM32_FUNCTION(2, "TIM2_CH3"),
+                STM32_FUNCTION(5, "I2C2_SCL"),
+                STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+                STM32_FUNCTION(8, "USART3_TX"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_D3"),
+                STM32_FUNCTION(12, "ETH_MII_RX_ER"),
+                STM32_FUNCTION(15, "LCD_G4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(27, "PB11"),
+                STM32_FUNCTION(0, "GPIOB11"),
+                STM32_FUNCTION(2, "TIM2_CH4"),
+                STM32_FUNCTION(5, "I2C2_SDA"),
+                STM32_FUNCTION(8, "USART3_RX"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_D4"),
+                STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
+                STM32_FUNCTION(15, "LCD_G5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(28, "PB12"),
+                STM32_FUNCTION(0, "GPIOB12"),
+                STM32_FUNCTION(2, "TIM1_BKIN"),
+                STM32_FUNCTION(5, "I2C2_SMBA"),
+                STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
+                STM32_FUNCTION(8, "USART3_CK"),
+                STM32_FUNCTION(10, "CAN2_RX"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_D5"),
+                STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
+                STM32_FUNCTION(13, "OTG_HS_ID"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(29, "PB13"),
+                STM32_FUNCTION(0, "GPIOB13"),
+                STM32_FUNCTION(2, "TIM1_CH1N"),
+                STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+                STM32_FUNCTION(8, "USART3_CTS"),
+                STM32_FUNCTION(10, "CAN2_TX"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_D6"),
+                STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(30, "PB14"),
+                STM32_FUNCTION(0, "GPIOB14"),
+                STM32_FUNCTION(2, "TIM1_CH2N"),
+                STM32_FUNCTION(4, "TIM8_CH2N"),
+                STM32_FUNCTION(6, "SPI2_MISO"),
+                STM32_FUNCTION(7, "I2S2EXT_SD"),
+                STM32_FUNCTION(8, "USART3_RTS"),
+                STM32_FUNCTION(10, "TIM12_CH1"),
+                STM32_FUNCTION(13, "OTG_HS_DM"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(31, "PB15"),
+                STM32_FUNCTION(0, "GPIOB15"),
+                STM32_FUNCTION(1, "RTC_REFIN"),
+                STM32_FUNCTION(2, "TIM1_CH3N"),
+                STM32_FUNCTION(4, "TIM8_CH3N"),
+                STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
+                STM32_FUNCTION(10, "TIM12_CH2"),
+                STM32_FUNCTION(13, "OTG_HS_DP"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(32, "PC0"),
+                STM32_FUNCTION(0, "GPIOC0"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_STP"),
+                STM32_FUNCTION(13, "FMC_SDNWE"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(33, "PC1"),
+                STM32_FUNCTION(0, "GPIOC1"),
+                STM32_FUNCTION(12, "ETH_MDC"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(34, "PC2"),
+                STM32_FUNCTION(0, "GPIOC2"),
+                STM32_FUNCTION(6, "SPI2_MISO"),
+                STM32_FUNCTION(7, "I2S2EXT_SD"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
+                STM32_FUNCTION(12, "ETH_MII_TXD2"),
+                STM32_FUNCTION(13, "FMC_SDNE0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(35, "PC3"),
+                STM32_FUNCTION(0, "GPIOC3"),
+                STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
+                STM32_FUNCTION(12, "ETH_MII_TX_CLK"),
+                STM32_FUNCTION(13, "FMC_SDCKE0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(36, "PC4"),
+                STM32_FUNCTION(0, "GPIOC4"),
+                STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(37, "PC5"),
+                STM32_FUNCTION(0, "GPIOC5"),
+                STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(38, "PC6"),
+                STM32_FUNCTION(0, "GPIOC6"),
+                STM32_FUNCTION(3, "TIM3_CH1"),
+                STM32_FUNCTION(4, "TIM8_CH1"),
+                STM32_FUNCTION(6, "I2S2_MCK"),
+                STM32_FUNCTION(9, "USART6_TX"),
+                STM32_FUNCTION(13, "SDIO_D6"),
+                STM32_FUNCTION(14, "DCMI_D0"),
+                STM32_FUNCTION(15, "LCD_HSYNC"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(39, "PC7"),
+                STM32_FUNCTION(0, "GPIOC7"),
+                STM32_FUNCTION(3, "TIM3_CH2"),
+                STM32_FUNCTION(4, "TIM8_CH2"),
+                STM32_FUNCTION(7, "I2S3_MCK"),
+                STM32_FUNCTION(9, "USART6_RX"),
+                STM32_FUNCTION(13, "SDIO_D7"),
+                STM32_FUNCTION(14, "DCMI_D1"),
+                STM32_FUNCTION(15, "LCD_G6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(40, "PC8"),
+                STM32_FUNCTION(0, "GPIOC8"),
+                STM32_FUNCTION(3, "TIM3_CH3"),
+                STM32_FUNCTION(4, "TIM8_CH3"),
+                STM32_FUNCTION(9, "USART6_CK"),
+                STM32_FUNCTION(13, "SDIO_D0"),
+                STM32_FUNCTION(14, "DCMI_D2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(41, "PC9"),
+                STM32_FUNCTION(0, "GPIOC9"),
+                STM32_FUNCTION(1, "MCO2"),
+                STM32_FUNCTION(3, "TIM3_CH4"),
+                STM32_FUNCTION(4, "TIM8_CH4"),
+                STM32_FUNCTION(5, "I2C3_SDA"),
+                STM32_FUNCTION(6, "I2S_CKIN"),
+                STM32_FUNCTION(13, "SDIO_D1"),
+                STM32_FUNCTION(14, "DCMI_D3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(42, "PC10"),
+                STM32_FUNCTION(0, "GPIOC10"),
+                STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
+                STM32_FUNCTION(8, "USART3_TX"),
+                STM32_FUNCTION(9, "UART4_TX"),
+                STM32_FUNCTION(13, "SDIO_D2"),
+                STM32_FUNCTION(14, "DCMI_D8"),
+                STM32_FUNCTION(15, "LCD_R2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(43, "PC11"),
+                STM32_FUNCTION(0, "GPIOC11"),
+                STM32_FUNCTION(6, "I2S3EXT_SD"),
+                STM32_FUNCTION(7, "SPI3_MISO"),
+                STM32_FUNCTION(8, "USART3_RX"),
+                STM32_FUNCTION(9, "UART4_RX"),
+                STM32_FUNCTION(13, "SDIO_D3"),
+                STM32_FUNCTION(14, "DCMI_D4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(44, "PC12"),
+                STM32_FUNCTION(0, "GPIOC12"),
+                STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
+                STM32_FUNCTION(8, "USART3_CK"),
+                STM32_FUNCTION(9, "UART5_TX"),
+                STM32_FUNCTION(13, "SDIO_CK"),
+                STM32_FUNCTION(14, "DCMI_D9"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(45, "PC13"),
+                STM32_FUNCTION(0, "GPIOC13"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(46, "PC14"),
+                STM32_FUNCTION(0, "GPIOC14"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(47, "PC15"),
+                STM32_FUNCTION(0, "GPIOC15"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(48, "PD0"),
+                STM32_FUNCTION(0, "GPIOD0"),
+                STM32_FUNCTION(10, "CAN1_RX"),
+                STM32_FUNCTION(13, "FMC_D2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(49, "PD1"),
+                STM32_FUNCTION(0, "GPIOD1"),
+                STM32_FUNCTION(10, "CAN1_TX"),
+                STM32_FUNCTION(13, "FMC_D3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(50, "PD2"),
+                STM32_FUNCTION(0, "GPIOD2"),
+                STM32_FUNCTION(3, "TIM3_ETR"),
+                STM32_FUNCTION(9, "UART5_RX"),
+                STM32_FUNCTION(13, "SDIO_CMD"),
+                STM32_FUNCTION(14, "DCMI_D11"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(51, "PD3"),
+                STM32_FUNCTION(0, "GPIOD3"),
+                STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+                STM32_FUNCTION(8, "USART2_CTS"),
+                STM32_FUNCTION(13, "FMC_CLK"),
+                STM32_FUNCTION(14, "DCMI_D5"),
+                STM32_FUNCTION(15, "LCD_G7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(52, "PD4"),
+                STM32_FUNCTION(0, "GPIOD4"),
+                STM32_FUNCTION(8, "USART2_RTS"),
+                STM32_FUNCTION(13, "FMC_NOE"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(53, "PD5"),
+                STM32_FUNCTION(0, "GPIOD5"),
+                STM32_FUNCTION(8, "USART2_TX"),
+                STM32_FUNCTION(13, "FMC_NWE"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(54, "PD6"),
+                STM32_FUNCTION(0, "GPIOD6"),
+                STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"),
+                STM32_FUNCTION(7, "SAI1_SD_A"),
+                STM32_FUNCTION(8, "USART2_RX"),
+                STM32_FUNCTION(13, "FMC_NWAIT"),
+                STM32_FUNCTION(14, "DCMI_D10"),
+                STM32_FUNCTION(15, "LCD_B2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(55, "PD7"),
+                STM32_FUNCTION(0, "GPIOD7"),
+                STM32_FUNCTION(8, "USART2_CK"),
+                STM32_FUNCTION(13, "FMC_NE1 FMC_NCE2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(56, "PD8"),
+                STM32_FUNCTION(0, "GPIOD8"),
+                STM32_FUNCTION(8, "USART3_TX"),
+                STM32_FUNCTION(13, "FMC_D13"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(57, "PD9"),
+                STM32_FUNCTION(0, "GPIOD9"),
+                STM32_FUNCTION(8, "USART3_RX"),
+                STM32_FUNCTION(13, "FMC_D14"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(58, "PD10"),
+                STM32_FUNCTION(0, "GPIOD10"),
+                STM32_FUNCTION(8, "USART3_CK"),
+                STM32_FUNCTION(13, "FMC_D15"),
+                STM32_FUNCTION(15, "LCD_B3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(59, "PD11"),
+                STM32_FUNCTION(0, "GPIOD11"),
+                STM32_FUNCTION(8, "USART3_CTS"),
+                STM32_FUNCTION(13, "FMC_A16"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(60, "PD12"),
+                STM32_FUNCTION(0, "GPIOD12"),
+                STM32_FUNCTION(3, "TIM4_CH1"),
+                STM32_FUNCTION(8, "USART3_RTS"),
+                STM32_FUNCTION(13, "FMC_A17"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(61, "PD13"),
+                STM32_FUNCTION(0, "GPIOD13"),
+                STM32_FUNCTION(3, "TIM4_CH2"),
+                STM32_FUNCTION(13, "FMC_A18"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(62, "PD14"),
+                STM32_FUNCTION(0, "GPIOD14"),
+                STM32_FUNCTION(3, "TIM4_CH3"),
+                STM32_FUNCTION(13, "FMC_D0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(63, "PD15"),
+                STM32_FUNCTION(0, "GPIOD15"),
+                STM32_FUNCTION(3, "TIM4_CH4"),
+                STM32_FUNCTION(13, "FMC_D1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(64, "PE0"),
+                STM32_FUNCTION(0, "GPIOE0"),
+                STM32_FUNCTION(3, "TIM4_ETR"),
+                STM32_FUNCTION(9, "UART8_RX"),
+                STM32_FUNCTION(13, "FMC_NBL0"),
+                STM32_FUNCTION(14, "DCMI_D2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(65, "PE1"),
+                STM32_FUNCTION(0, "GPIOE1"),
+                STM32_FUNCTION(9, "UART8_TX"),
+                STM32_FUNCTION(13, "FMC_NBL1"),
+                STM32_FUNCTION(14, "DCMI_D3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(66, "PE2"),
+                STM32_FUNCTION(0, "GPIOE2"),
+                STM32_FUNCTION(1, "TRACECLK"),
+                STM32_FUNCTION(6, "SPI4_SCK"),
+                STM32_FUNCTION(7, "SAI1_MCLK_A"),
+                STM32_FUNCTION(12, "ETH_MII_TXD3"),
+                STM32_FUNCTION(13, "FMC_A23"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(67, "PE3"),
+                STM32_FUNCTION(0, "GPIOE3"),
+                STM32_FUNCTION(1, "TRACED0"),
+                STM32_FUNCTION(7, "SAI1_SD_B"),
+                STM32_FUNCTION(13, "FMC_A19"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(68, "PE4"),
+                STM32_FUNCTION(0, "GPIOE4"),
+                STM32_FUNCTION(1, "TRACED1"),
+                STM32_FUNCTION(6, "SPI4_NSS"),
+                STM32_FUNCTION(7, "SAI1_FS_A"),
+                STM32_FUNCTION(13, "FMC_A20"),
+                STM32_FUNCTION(14, "DCMI_D4"),
+                STM32_FUNCTION(15, "LCD_B0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(69, "PE5"),
+                STM32_FUNCTION(0, "GPIOE5"),
+                STM32_FUNCTION(1, "TRACED2"),
+                STM32_FUNCTION(4, "TIM9_CH1"),
+                STM32_FUNCTION(6, "SPI4_MISO"),
+                STM32_FUNCTION(7, "SAI1_SCK_A"),
+                STM32_FUNCTION(13, "FMC_A21"),
+                STM32_FUNCTION(14, "DCMI_D6"),
+                STM32_FUNCTION(15, "LCD_G0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(70, "PE6"),
+                STM32_FUNCTION(0, "GPIOE6"),
+                STM32_FUNCTION(1, "TRACED3"),
+                STM32_FUNCTION(4, "TIM9_CH2"),
+                STM32_FUNCTION(6, "SPI4_MOSI"),
+                STM32_FUNCTION(7, "SAI1_SD_A"),
+                STM32_FUNCTION(13, "FMC_A22"),
+                STM32_FUNCTION(14, "DCMI_D7"),
+                STM32_FUNCTION(15, "LCD_G1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(71, "PE7"),
+                STM32_FUNCTION(0, "GPIOE7"),
+                STM32_FUNCTION(2, "TIM1_ETR"),
+                STM32_FUNCTION(9, "UART7_RX"),
+                STM32_FUNCTION(13, "FMC_D4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(72, "PE8"),
+                STM32_FUNCTION(0, "GPIOE8"),
+                STM32_FUNCTION(2, "TIM1_CH1N"),
+                STM32_FUNCTION(9, "UART7_TX"),
+                STM32_FUNCTION(13, "FMC_D5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(73, "PE9"),
+                STM32_FUNCTION(0, "GPIOE9"),
+                STM32_FUNCTION(2, "TIM1_CH1"),
+                STM32_FUNCTION(13, "FMC_D6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(74, "PE10"),
+                STM32_FUNCTION(0, "GPIOE10"),
+                STM32_FUNCTION(2, "TIM1_CH2N"),
+                STM32_FUNCTION(13, "FMC_D7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(75, "PE11"),
+                STM32_FUNCTION(0, "GPIOE11"),
+                STM32_FUNCTION(2, "TIM1_CH2"),
+                STM32_FUNCTION(6, "SPI4_NSS"),
+                STM32_FUNCTION(13, "FMC_D8"),
+                STM32_FUNCTION(15, "LCD_G3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(76, "PE12"),
+                STM32_FUNCTION(0, "GPIOE12"),
+                STM32_FUNCTION(2, "TIM1_CH3N"),
+                STM32_FUNCTION(6, "SPI4_SCK"),
+                STM32_FUNCTION(13, "FMC_D9"),
+                STM32_FUNCTION(15, "LCD_B4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(77, "PE13"),
+                STM32_FUNCTION(0, "GPIOE13"),
+                STM32_FUNCTION(2, "TIM1_CH3"),
+                STM32_FUNCTION(6, "SPI4_MISO"),
+                STM32_FUNCTION(13, "FMC_D10"),
+                STM32_FUNCTION(15, "LCD_DE"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(78, "PE14"),
+                STM32_FUNCTION(0, "GPIOE14"),
+                STM32_FUNCTION(2, "TIM1_CH4"),
+                STM32_FUNCTION(6, "SPI4_MOSI"),
+                STM32_FUNCTION(13, "FMC_D11"),
+                STM32_FUNCTION(15, "LCD_CLK"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(79, "PE15"),
+                STM32_FUNCTION(0, "GPIOE15"),
+                STM32_FUNCTION(2, "TIM1_BKIN"),
+                STM32_FUNCTION(13, "FMC_D12"),
+                STM32_FUNCTION(15, "LCD_R7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(80, "PF0"),
+                STM32_FUNCTION(0, "GPIOF0"),
+                STM32_FUNCTION(5, "I2C2_SDA"),
+                STM32_FUNCTION(13, "FMC_A0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(81, "PF1"),
+                STM32_FUNCTION(0, "GPIOF1"),
+                STM32_FUNCTION(5, "I2C2_SCL"),
+                STM32_FUNCTION(13, "FMC_A1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(82, "PF2"),
+                STM32_FUNCTION(0, "GPIOF2"),
+                STM32_FUNCTION(5, "I2C2_SMBA"),
+                STM32_FUNCTION(13, "FMC_A2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(83, "PF3"),
+                STM32_FUNCTION(0, "GPIOF3"),
+                STM32_FUNCTION(13, "FMC_A3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(84, "PF4"),
+                STM32_FUNCTION(0, "GPIOF4"),
+                STM32_FUNCTION(13, "FMC_A4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(85, "PF5"),
+                STM32_FUNCTION(0, "GPIOF5"),
+                STM32_FUNCTION(13, "FMC_A5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(86, "PF6"),
+                STM32_FUNCTION(0, "GPIOF6"),
+                STM32_FUNCTION(4, "TIM10_CH1"),
+                STM32_FUNCTION(6, "SPI5_NSS"),
+                STM32_FUNCTION(7, "SAI1_SD_B"),
+                STM32_FUNCTION(9, "UART7_RX"),
+                STM32_FUNCTION(13, "FMC_NIORD"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(87, "PF7"),
+                STM32_FUNCTION(0, "GPIOF7"),
+                STM32_FUNCTION(4, "TIM11_CH1"),
+                STM32_FUNCTION(6, "SPI5_SCK"),
+                STM32_FUNCTION(7, "SAI1_MCLK_B"),
+                STM32_FUNCTION(9, "UART7_TX"),
+                STM32_FUNCTION(13, "FMC_NREG"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(88, "PF8"),
+                STM32_FUNCTION(0, "GPIOF8"),
+                STM32_FUNCTION(6, "SPI5_MISO"),
+                STM32_FUNCTION(7, "SAI1_SCK_B"),
+                STM32_FUNCTION(10, "TIM13_CH1"),
+                STM32_FUNCTION(13, "FMC_NIOWR"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(89, "PF9"),
+                STM32_FUNCTION(0, "GPIOF9"),
+                STM32_FUNCTION(6, "SPI5_MOSI"),
+                STM32_FUNCTION(7, "SAI1_FS_B"),
+                STM32_FUNCTION(10, "TIM14_CH1"),
+                STM32_FUNCTION(13, "FMC_CD"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(90, "PF10"),
+                STM32_FUNCTION(0, "GPIOF10"),
+                STM32_FUNCTION(13, "FMC_INTR"),
+                STM32_FUNCTION(14, "DCMI_D11"),
+                STM32_FUNCTION(15, "LCD_DE"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(91, "PF11"),
+                STM32_FUNCTION(0, "GPIOF11"),
+                STM32_FUNCTION(6, "SPI5_MOSI"),
+                STM32_FUNCTION(13, "FMC_SDNRAS"),
+                STM32_FUNCTION(14, "DCMI_D12"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(92, "PF12"),
+                STM32_FUNCTION(0, "GPIOF12"),
+                STM32_FUNCTION(13, "FMC_A6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(93, "PF13"),
+                STM32_FUNCTION(0, "GPIOF13"),
+                STM32_FUNCTION(13, "FMC_A7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(94, "PF14"),
+                STM32_FUNCTION(0, "GPIOF14"),
+                STM32_FUNCTION(13, "FMC_A8"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(95, "PF15"),
+                STM32_FUNCTION(0, "GPIOF15"),
+                STM32_FUNCTION(13, "FMC_A9"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(96, "PG0"),
+                STM32_FUNCTION(0, "GPIOG0"),
+                STM32_FUNCTION(13, "FMC_A10"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(97, "PG1"),
+                STM32_FUNCTION(0, "GPIOG1"),
+                STM32_FUNCTION(13, "FMC_A11"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(98, "PG2"),
+                STM32_FUNCTION(0, "GPIOG2"),
+                STM32_FUNCTION(13, "FMC_A12"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(99, "PG3"),
+                STM32_FUNCTION(0, "GPIOG3"),
+                STM32_FUNCTION(13, "FMC_A13"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(100, "PG4"),
+                STM32_FUNCTION(0, "GPIOG4"),
+                STM32_FUNCTION(13, "FMC_A14 FMC_BA0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(101, "PG5"),
+                STM32_FUNCTION(0, "GPIOG5"),
+                STM32_FUNCTION(13, "FMC_A15 FMC_BA1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(102, "PG6"),
+                STM32_FUNCTION(0, "GPIOG6"),
+                STM32_FUNCTION(13, "FMC_INT2"),
+                STM32_FUNCTION(14, "DCMI_D12"),
+                STM32_FUNCTION(15, "LCD_R7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(103, "PG7"),
+                STM32_FUNCTION(0, "GPIOG7"),
+                STM32_FUNCTION(9, "USART6_CK"),
+                STM32_FUNCTION(13, "FMC_INT3"),
+                STM32_FUNCTION(14, "DCMI_D13"),
+                STM32_FUNCTION(15, "LCD_CLK"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(104, "PG8"),
+                STM32_FUNCTION(0, "GPIOG8"),
+                STM32_FUNCTION(6, "SPI6_NSS"),
+                STM32_FUNCTION(9, "USART6_RTS"),
+                STM32_FUNCTION(12, "ETH_PPS_OUT"),
+                STM32_FUNCTION(13, "FMC_SDCLK"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(105, "PG9"),
+                STM32_FUNCTION(0, "GPIOG9"),
+                STM32_FUNCTION(9, "USART6_RX"),
+                STM32_FUNCTION(13, "FMC_NE2 FMC_NCE3"),
+                STM32_FUNCTION(14, "DCMI_VSYNC"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(106, "PG10"),
+                STM32_FUNCTION(0, "GPIOG10"),
+                STM32_FUNCTION(10, "LCD_G3"),
+                STM32_FUNCTION(13, "FMC_NCE4_1 FMC_NE3"),
+                STM32_FUNCTION(14, "DCMI_D2"),
+                STM32_FUNCTION(15, "LCD_B2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(107, "PG11"),
+                STM32_FUNCTION(0, "GPIOG11"),
+                STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
+                STM32_FUNCTION(13, "FMC_NCE4_2"),
+                STM32_FUNCTION(14, "DCMI_D3"),
+                STM32_FUNCTION(15, "LCD_B3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(108, "PG12"),
+                STM32_FUNCTION(0, "GPIOG12"),
+                STM32_FUNCTION(6, "SPI6_MISO"),
+                STM32_FUNCTION(9, "USART6_RTS"),
+                STM32_FUNCTION(10, "LCD_B4"),
+                STM32_FUNCTION(13, "FMC_NE4"),
+                STM32_FUNCTION(15, "LCD_B1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(109, "PG13"),
+                STM32_FUNCTION(0, "GPIOG13"),
+                STM32_FUNCTION(6, "SPI6_SCK"),
+                STM32_FUNCTION(9, "USART6_CTS"),
+                STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
+                STM32_FUNCTION(13, "FMC_A24"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(110, "PG14"),
+                STM32_FUNCTION(0, "GPIOG14"),
+                STM32_FUNCTION(6, "SPI6_MOSI"),
+                STM32_FUNCTION(9, "USART6_TX"),
+                STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
+                STM32_FUNCTION(13, "FMC_A25"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(111, "PG15"),
+                STM32_FUNCTION(0, "GPIOG15"),
+                STM32_FUNCTION(9, "USART6_CTS"),
+                STM32_FUNCTION(13, "FMC_SDNCAS"),
+                STM32_FUNCTION(14, "DCMI_D13"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(112, "PH0"),
+                STM32_FUNCTION(0, "GPIOH0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(113, "PH1"),
+                STM32_FUNCTION(0, "GPIOH1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(114, "PH2"),
+                STM32_FUNCTION(0, "GPIOH2"),
+                STM32_FUNCTION(12, "ETH_MII_CRS"),
+                STM32_FUNCTION(13, "FMC_SDCKE0"),
+                STM32_FUNCTION(15, "LCD_R0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(115, "PH3"),
+                STM32_FUNCTION(0, "GPIOH3"),
+                STM32_FUNCTION(12, "ETH_MII_COL"),
+                STM32_FUNCTION(13, "FMC_SDNE0"),
+                STM32_FUNCTION(15, "LCD_R1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(116, "PH4"),
+                STM32_FUNCTION(0, "GPIOH4"),
+                STM32_FUNCTION(5, "I2C2_SCL"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(117, "PH5"),
+                STM32_FUNCTION(0, "GPIOH5"),
+                STM32_FUNCTION(5, "I2C2_SDA"),
+                STM32_FUNCTION(6, "SPI5_NSS"),
+                STM32_FUNCTION(13, "FMC_SDNWE"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(118, "PH6"),
+                STM32_FUNCTION(0, "GPIOH6"),
+                STM32_FUNCTION(5, "I2C2_SMBA"),
+                STM32_FUNCTION(6, "SPI5_SCK"),
+                STM32_FUNCTION(10, "TIM12_CH1"),
+                STM32_FUNCTION(12, "ETH_MII_RXD2"),
+                STM32_FUNCTION(13, "FMC_SDNE1"),
+                STM32_FUNCTION(14, "DCMI_D8"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(119, "PH7"),
+                STM32_FUNCTION(0, "GPIOH7"),
+                STM32_FUNCTION(5, "I2C3_SCL"),
+                STM32_FUNCTION(6, "SPI5_MISO"),
+                STM32_FUNCTION(12, "ETH_MII_RXD3"),
+                STM32_FUNCTION(13, "FMC_SDCKE1"),
+                STM32_FUNCTION(14, "DCMI_D9"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(120, "PH8"),
+                STM32_FUNCTION(0, "GPIOH8"),
+                STM32_FUNCTION(5, "I2C3_SDA"),
+                STM32_FUNCTION(13, "FMC_D16"),
+                STM32_FUNCTION(14, "DCMI_HSYNC"),
+                STM32_FUNCTION(15, "LCD_R2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(121, "PH9"),
+                STM32_FUNCTION(0, "GPIOH9"),
+                STM32_FUNCTION(5, "I2C3_SMBA"),
+                STM32_FUNCTION(10, "TIM12_CH2"),
+                STM32_FUNCTION(13, "FMC_D17"),
+                STM32_FUNCTION(14, "DCMI_D0"),
+                STM32_FUNCTION(15, "LCD_R3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(122, "PH10"),
+                STM32_FUNCTION(0, "GPIOH10"),
+                STM32_FUNCTION(3, "TIM5_CH1"),
+                STM32_FUNCTION(13, "FMC_D18"),
+                STM32_FUNCTION(14, "DCMI_D1"),
+                STM32_FUNCTION(15, "LCD_R4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(123, "PH11"),
+                STM32_FUNCTION(0, "GPIOH11"),
+                STM32_FUNCTION(3, "TIM5_CH2"),
+                STM32_FUNCTION(13, "FMC_D19"),
+                STM32_FUNCTION(14, "DCMI_D2"),
+                STM32_FUNCTION(15, "LCD_R5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(124, "PH12"),
+                STM32_FUNCTION(0, "GPIOH12"),
+                STM32_FUNCTION(3, "TIM5_CH3"),
+                STM32_FUNCTION(13, "FMC_D20"),
+                STM32_FUNCTION(14, "DCMI_D3"),
+                STM32_FUNCTION(15, "LCD_R6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(125, "PH13"),
+                STM32_FUNCTION(0, "GPIOH13"),
+                STM32_FUNCTION(4, "TIM8_CH1N"),
+                STM32_FUNCTION(10, "CAN1_TX"),
+                STM32_FUNCTION(13, "FMC_D21"),
+                STM32_FUNCTION(15, "LCD_G2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(126, "PH14"),
+                STM32_FUNCTION(0, "GPIOH14"),
+                STM32_FUNCTION(4, "TIM8_CH2N"),
+                STM32_FUNCTION(13, "FMC_D22"),
+                STM32_FUNCTION(14, "DCMI_D4"),
+                STM32_FUNCTION(15, "LCD_G3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(127, "PH15"),
+                STM32_FUNCTION(0, "GPIOH15"),
+                STM32_FUNCTION(4, "TIM8_CH3N"),
+                STM32_FUNCTION(13, "FMC_D23"),
+                STM32_FUNCTION(14, "DCMI_D11"),
+                STM32_FUNCTION(15, "LCD_G4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(128, "PI0"),
+                STM32_FUNCTION(0, "GPIOI0"),
+                STM32_FUNCTION(3, "TIM5_CH4"),
+                STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
+                STM32_FUNCTION(13, "FMC_D24"),
+                STM32_FUNCTION(14, "DCMI_D13"),
+                STM32_FUNCTION(15, "LCD_G5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(129, "PI1"),
+                STM32_FUNCTION(0, "GPIOI1"),
+                STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+                STM32_FUNCTION(13, "FMC_D25"),
+                STM32_FUNCTION(14, "DCMI_D8"),
+                STM32_FUNCTION(15, "LCD_G6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(130, "PI2"),
+                STM32_FUNCTION(0, "GPIOI2"),
+                STM32_FUNCTION(4, "TIM8_CH4"),
+                STM32_FUNCTION(6, "SPI2_MISO"),
+                STM32_FUNCTION(7, "I2S2EXT_SD"),
+                STM32_FUNCTION(13, "FMC_D26"),
+                STM32_FUNCTION(14, "DCMI_D9"),
+                STM32_FUNCTION(15, "LCD_G7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(131, "PI3"),
+                STM32_FUNCTION(0, "GPIOI3"),
+                STM32_FUNCTION(4, "TIM8_ETR"),
+                STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
+                STM32_FUNCTION(13, "FMC_D27"),
+                STM32_FUNCTION(14, "DCMI_D10"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(132, "PI4"),
+                STM32_FUNCTION(0, "GPIOI4"),
+                STM32_FUNCTION(4, "TIM8_BKIN"),
+                STM32_FUNCTION(13, "FMC_NBL2"),
+                STM32_FUNCTION(14, "DCMI_D5"),
+                STM32_FUNCTION(15, "LCD_B4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(133, "PI5"),
+                STM32_FUNCTION(0, "GPIOI5"),
+                STM32_FUNCTION(4, "TIM8_CH1"),
+                STM32_FUNCTION(13, "FMC_NBL3"),
+                STM32_FUNCTION(14, "DCMI_VSYNC"),
+                STM32_FUNCTION(15, "LCD_B5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(134, "PI6"),
+                STM32_FUNCTION(0, "GPIOI6"),
+                STM32_FUNCTION(4, "TIM8_CH2"),
+                STM32_FUNCTION(13, "FMC_D28"),
+                STM32_FUNCTION(14, "DCMI_D6"),
+                STM32_FUNCTION(15, "LCD_B6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(135, "PI7"),
+                STM32_FUNCTION(0, "GPIOI7"),
+                STM32_FUNCTION(4, "TIM8_CH3"),
+                STM32_FUNCTION(13, "FMC_D29"),
+                STM32_FUNCTION(14, "DCMI_D7"),
+                STM32_FUNCTION(15, "LCD_B7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(136, "PI8"),
+                STM32_FUNCTION(0, "GPIOI8"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(137, "PI9"),
+                STM32_FUNCTION(0, "GPIOI9"),
+                STM32_FUNCTION(10, "CAN1_RX"),
+                STM32_FUNCTION(13, "FMC_D30"),
+                STM32_FUNCTION(15, "LCD_VSYNC"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(138, "PI10"),
+                STM32_FUNCTION(0, "GPIOI10"),
+                STM32_FUNCTION(12, "ETH_MII_RX_ER"),
+                STM32_FUNCTION(13, "FMC_D31"),
+                STM32_FUNCTION(15, "LCD_HSYNC"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(139, "PI11"),
+                STM32_FUNCTION(0, "GPIOI11"),
+                STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(140, "PI12"),
+                STM32_FUNCTION(0, "GPIOI12"),
+                STM32_FUNCTION(15, "LCD_HSYNC"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(141, "PI13"),
+                STM32_FUNCTION(0, "GPIOI13"),
+                STM32_FUNCTION(15, "LCD_VSYNC"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(142, "PI14"),
+                STM32_FUNCTION(0, "GPIOI14"),
+                STM32_FUNCTION(15, "LCD_CLK"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(143, "PI15"),
+                STM32_FUNCTION(0, "GPIOI15"),
+                STM32_FUNCTION(15, "LCD_R0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(144, "PJ0"),
+                STM32_FUNCTION(0, "GPIOJ0"),
+                STM32_FUNCTION(15, "LCD_R1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(145, "PJ1"),
+                STM32_FUNCTION(0, "GPIOJ1"),
+                STM32_FUNCTION(15, "LCD_R2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(146, "PJ2"),
+                STM32_FUNCTION(0, "GPIOJ2"),
+                STM32_FUNCTION(15, "LCD_R3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(147, "PJ3"),
+                STM32_FUNCTION(0, "GPIOJ3"),
+                STM32_FUNCTION(15, "LCD_R4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(148, "PJ4"),
+                STM32_FUNCTION(0, "GPIOJ4"),
+                STM32_FUNCTION(15, "LCD_R5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(149, "PJ5"),
+                STM32_FUNCTION(0, "GPIOJ5"),
+                STM32_FUNCTION(15, "LCD_R6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(150, "PJ6"),
+                STM32_FUNCTION(0, "GPIOJ6"),
+                STM32_FUNCTION(15, "LCD_R7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(151, "PJ7"),
+                STM32_FUNCTION(0, "GPIOJ7"),
+                STM32_FUNCTION(15, "LCD_G0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(152, "PJ8"),
+                STM32_FUNCTION(0, "GPIOJ8"),
+                STM32_FUNCTION(15, "LCD_G1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(153, "PJ9"),
+                STM32_FUNCTION(0, "GPIOJ9"),
+                STM32_FUNCTION(15, "LCD_G2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(154, "PJ10"),
+                STM32_FUNCTION(0, "GPIOJ10"),
+                STM32_FUNCTION(15, "LCD_G3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(155, "PJ11"),
+                STM32_FUNCTION(0, "GPIOJ11"),
+                STM32_FUNCTION(15, "LCD_G4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(156, "PJ12"),
+                STM32_FUNCTION(0, "GPIOJ12"),
+                STM32_FUNCTION(15, "LCD_B0"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(157, "PJ13"),
+                STM32_FUNCTION(0, "GPIOJ13"),
+                STM32_FUNCTION(15, "LCD_B1"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(158, "PJ14"),
+                STM32_FUNCTION(0, "GPIOJ14"),
+                STM32_FUNCTION(15, "LCD_B2"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(159, "PJ15"),
+                STM32_FUNCTION(0, "GPIOJ15"),
+                STM32_FUNCTION(15, "LCD_B3"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(160, "PK0"),
+                STM32_FUNCTION(0, "GPIOK0"),
+                STM32_FUNCTION(15, "LCD_G5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(161, "PK1"),
+                STM32_FUNCTION(0, "GPIOK1"),
+                STM32_FUNCTION(15, "LCD_G6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(162, "PK2"),
+                STM32_FUNCTION(0, "GPIOK2"),
+                STM32_FUNCTION(15, "LCD_G7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(163, "PK3"),
+                STM32_FUNCTION(0, "GPIOK3"),
+                STM32_FUNCTION(15, "LCD_B4"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(164, "PK4"),
+                STM32_FUNCTION(0, "GPIOK4"),
+                STM32_FUNCTION(15, "LCD_B5"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(165, "PK5"),
+                STM32_FUNCTION(0, "GPIOK5"),
+                STM32_FUNCTION(15, "LCD_B6"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(166, "PK6"),
+                STM32_FUNCTION(0, "GPIOK6"),
+                STM32_FUNCTION(15, "LCD_B7"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+        STM32_PIN(
+                PINCTRL_PIN(167, "PK7"),
+                STM32_FUNCTION(0, "GPIOK7"),
+                STM32_FUNCTION(15, "LCD_DE"),
+                STM32_FUNCTION(16, "EVENTOUT"),
+                STM32_FUNCTION(17, "ANALOG")
+        ),
+};
+
+static struct stm32_pinctrl_match_data stm32f429_match_data = {
+        .pins = stm32f429_pins,
+        .npins = ARRAY_SIZE(stm32f429_pins),
+};
+
+static const struct of_device_id stm32f429_pctrl_match[] = {
+        {
+                .compatible = "st,stm32f429-pinctrl",
+                .data = &stm32f429_match_data,
+        },
+        { }
+};
+
+static struct platform_driver stm32f429_pinctrl_driver = {
+        .probe = stm32_pctl_probe,
+        .driver = {
+                .name = "stm32f429-pinctrl",
+                .of_match_table = stm32f429_pctrl_match,
+        },
+};
+
+static int __init stm32f429_pinctrl_init(void)
+{
+        return platform_driver_register(&stm32f429_pinctrl_driver);
+}
+device_initcall(stm32f429_pinctrl_init);
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f8dbc8bec0e1..aaf075b972f5 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -1,67 +1,75 @@
 if ARCH_SUNXI
 
-config PINCTRL_SUNXI_COMMON
+config PINCTRL_SUNXI
         bool
         select PINMUX
         select GENERIC_PINCONF
 
 config PINCTRL_SUN4I_A10
         def_bool MACH_SUN4I
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN5I_A10S
         def_bool MACH_SUN5I
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN5I_A13
         def_bool MACH_SUN5I
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN6I_A31
         def_bool MACH_SUN6I
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN6I_A31S
         def_bool MACH_SUN6I
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN6I_A31_R
         def_bool MACH_SUN6I
         depends on RESET_CONTROLLER
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN7I_A20
         def_bool MACH_SUN7I
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN8I_A23
         def_bool MACH_SUN8I
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN8I_A33
         def_bool MACH_SUN8I
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN8I_A83T
         def_bool MACH_SUN8I
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN8I_A23_R
         def_bool MACH_SUN8I
         depends on RESET_CONTROLLER
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN8I_H3
         def_bool MACH_SUN8I
+        select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_H3_R
+        def_bool MACH_SUN8I
         select PINCTRL_SUNXI_COMMON
 
 config PINCTRL_SUN9I_A80
         def_bool MACH_SUN9I
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
 
 config PINCTRL_SUN9I_A80_R
         def_bool MACH_SUN9I
         depends on RESET_CONTROLLER
-        select PINCTRL_SUNXI_COMMON
+        select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A64
+        bool
+        select PINCTRL_SUNXI
 
 endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index ef82f22bb9ef..2d8b64e222e0 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -1,5 +1,5 @@
 # Core
-obj-$(CONFIG_PINCTRL_SUNXI_COMMON)      += pinctrl-sunxi.o
+obj-y                                   += pinctrl-sunxi.o
 
 # SoC Drivers
 obj-$(CONFIG_PINCTRL_SUN4I_A10)         += pinctrl-sun4i-a10.o
@@ -12,7 +12,9 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20)		+= pinctrl-sun7i-a20.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23)         += pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)       += pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)         += pinctrl-sun8i-a33.o
+obj-$(CONFIG_PINCTRL_SUN50I_A64)        += pinctrl-sun50i-a64.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)        += pinctrl-sun8i-a83t.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3)          += pinctrl-sun8i-h3.o
+obj-$(CONFIG_PINCTRL_SUN8I_H3_R)        += pinctrl-sun8i-h3-r.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)         += pinctrl-sun9i-a80.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80_R)       += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
new file mode 100644
index 000000000000..4f2a726bbaeb
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
@@ -0,0 +1,601 @@
+/*
+ * Allwinner A64 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2016 - ARM Ltd.
+ * Author: Andre Przywara <andre.przywara@arm.com>
+ *
+ * Based on pinctrl-sun7i-a20.c, which is:
+ * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin a64_pins[] = {
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart2"),         /* TX */
+                  SUNXI_FUNCTION(0x4, "jtag"),          /* MS0 */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* EINT0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart2"),         /* RX */
+                  SUNXI_FUNCTION(0x4, "jtag"),          /* CK0 */
+                  SUNXI_FUNCTION(0x5, "sim"),           /* VCCEN */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),          /* EINT1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart2"),         /* RTS */
+                  SUNXI_FUNCTION(0x4, "jtag"),          /* DO0 */
+                  SUNXI_FUNCTION(0x5, "sim"),           /* VPPEN */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),          /* EINT2 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart2"),         /* CTS */
+                  SUNXI_FUNCTION(0x3, "i2s0"),          /* MCLK */
+                  SUNXI_FUNCTION(0x4, "jtag"),          /* DI0 */
+                  SUNXI_FUNCTION(0x5, "sim"),           /* VPPPP */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),          /* EINT3 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "aif2"),          /* SYNC */
+                  SUNXI_FUNCTION(0x3, "i2s0"),          /* SYNC */
+                  SUNXI_FUNCTION(0x5, "sim"),           /* CLK */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),          /* EINT4 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "aif2"),          /* BCLK */
+                  SUNXI_FUNCTION(0x3, "i2s0"),          /* BCLK */
+                  SUNXI_FUNCTION(0x5, "sim"),           /* DATA */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),          /* EINT5 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "aif2"),          /* DOUT */
+                  SUNXI_FUNCTION(0x3, "i2s0"),          /* DOUT */
+                  SUNXI_FUNCTION(0x5, "sim"),           /* RST */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),          /* EINT6 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "aif2"),          /* DIN */
+                  SUNXI_FUNCTION(0x3, "i2s0"),          /* DIN */
+                  SUNXI_FUNCTION(0x5, "sim"),           /* DET */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),          /* EINT7 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x4, "uart0"),         /* TX */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),          /* EINT8 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x4, "uart0"),         /* RX */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),          /* EINT9 */
+        /* Hole */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NWE */
+                  SUNXI_FUNCTION(0x4, "spi0")),         /* MOSI */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NALE */
+                  SUNXI_FUNCTION(0x3, "mmc2"),          /* DS */
+                  SUNXI_FUNCTION(0x4, "spi0")),         /* MISO */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCLE */
+                  SUNXI_FUNCTION(0x4, "spi0")),         /* SCK */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE1 */
+                  SUNXI_FUNCTION(0x4, "spi0")),         /* CS */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NRE# */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* CLK */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NRB0 */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* CMD */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0")),        /* NRB1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ0 */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ1 */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ2 */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D2 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ3 */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D3 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ4 */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D4 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ5 */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D5 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ6 */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D6 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ7 */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D7 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQS */
+                  SUNXI_FUNCTION(0x3, "mmc2")),         /* RST */
+        /* Hole */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D2 */
+                  SUNXI_FUNCTION(0x3, "uart3"),         /* TX */
+                  SUNXI_FUNCTION(0x4, "spi1"),          /* CS */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* CLK */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D3 */
+                  SUNXI_FUNCTION(0x3, "uart3"),         /* RX */
+                  SUNXI_FUNCTION(0x4, "spi1"),          /* CLK */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* DE */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D4 */
+                  SUNXI_FUNCTION(0x3, "uart4"),         /* TX */
+                  SUNXI_FUNCTION(0x4, "spi1"),          /* MOSI */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* HSYNC */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D5 */
+                  SUNXI_FUNCTION(0x3, "uart4"),         /* RX */
+                  SUNXI_FUNCTION(0x4, "spi1"),          /* MISO */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* VSYNC */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D6 */
+                  SUNXI_FUNCTION(0x3, "uart4"),         /* RTS */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* D0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D7 */
+                  SUNXI_FUNCTION(0x3, "uart4"),         /* CTS */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* D1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D10 */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* D2 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D11 */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* D3 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D12 */
+                  SUNXI_FUNCTION(0x4, "emac"),          /* ERXD3 */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* D4 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D13 */
+                  SUNXI_FUNCTION(0x4, "emac"),          /* ERXD2 */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* D5 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D14 */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* ERXD1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D15 */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* ERXD0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D18 */
+                  SUNXI_FUNCTION(0x3, "lvds0"),         /* VP0 */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* ERXCK */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D19 */
+                  SUNXI_FUNCTION(0x3, "lvds0"),         /* VN0 */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* ERXCTL */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D20 */
+                  SUNXI_FUNCTION(0x3, "lvds0"),         /* VP1 */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* ENULL */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D21 */
+                  SUNXI_FUNCTION(0x3, "lvds0"),         /* VN1 */
+                  SUNXI_FUNCTION(0x4, "emac"),          /* ETXD3 */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* D6 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D22 */
+                  SUNXI_FUNCTION(0x3, "lvds0"),         /* VP2 */
+                  SUNXI_FUNCTION(0x4, "emac"),          /* ETXD2 */
+                  SUNXI_FUNCTION(0x5, "ccir")),         /* D7 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D23 */
+                  SUNXI_FUNCTION(0x3, "lvds0"),         /* VN2 */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* ETXD1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* CLK */
+                  SUNXI_FUNCTION(0x3, "lvds0"),         /* VPC */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* ETXD0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* DE */
+                  SUNXI_FUNCTION(0x3, "lvds0"),         /* VNC */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* ETXCK */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* HSYNC */
+                  SUNXI_FUNCTION(0x3, "lvds0"),         /* VP3 */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* ETXCTL */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "lcd0"),          /* VSYNC */
+                  SUNXI_FUNCTION(0x3, "lvds0"),         /* VN3 */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* ECLKIN */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "pwm"),           /* PWM0 */
+                  SUNXI_FUNCTION(0x4, "emac")),         /* EMDC */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x4, "emac")),         /* EMDIO */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out")),
+        /* Hole */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* PCK */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* CLK */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* CK */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* ERR */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* HSYNC */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* SYNC */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* VSYNC */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* DVLD */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* D0 */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* D0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* D1 */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* D1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* D2 */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* D2 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* D3 */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* D3 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* D4 */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* D4 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* D5 */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* D5 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* D6 */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* D6 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0"),          /* D7 */
+                  SUNXI_FUNCTION(0x4, "ts0")),          /* D7 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0")),         /* SCK */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "csi0")),         /* SDA */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "pll"),           /* LOCK_DBG */
+                  SUNXI_FUNCTION(0x3, "i2c2")),         /* SCK */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x3, "i2c2")),         /* SDA */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out")),
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out")),
+        /* Hole */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D1 */
+                  SUNXI_FUNCTION(0x3, "jtag")),         /* MSI */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D0 */
+                  SUNXI_FUNCTION(0x3, "jtag")),         /* DI1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc0"),          /* CLK */
+                  SUNXI_FUNCTION(0x3, "uart0")),        /* TX */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc0"),          /* CMD */
+                  SUNXI_FUNCTION(0x3, "jtag")),         /* DO1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D3 */
+                  SUNXI_FUNCTION(0x4, "uart0")),        /* RX */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D2 */
+                  SUNXI_FUNCTION(0x3, "jtag")),         /* CK1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out")),
+        /* Hole */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc1"),          /* CLK */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* EINT0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc1"),          /* CMD */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* EINT1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc1"),          /* D0 */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),  /* EINT2 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc1"),          /* D1 */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* EINT3 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc1"),          /* D2 */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* EINT4 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mmc1"),          /* D3 */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),  /* EINT5 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart1"),         /* TX */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),  /* EINT6 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart1"),         /* RX */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),  /* EINT7 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart1"),         /* RTS */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),  /* EINT8 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart1"),         /* CTS */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),  /* EINT9 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "aif3"),          /* SYNC */
+                  SUNXI_FUNCTION(0x3, "i2s1"),          /* SYNC */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* EINT10 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "aif3"),          /* BCLK */
+                  SUNXI_FUNCTION(0x3, "i2s1"),          /* BCLK */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* EINT11 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "aif3"),          /* DOUT */
+                  SUNXI_FUNCTION(0x3, "i2s1"),          /* DOUT */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* EINT12 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "aif3"),          /* DIN */
+                  SUNXI_FUNCTION(0x3, "i2s1"),          /* DIN */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* EINT13 */
+        /* Hole */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "i2c0"),          /* SCK */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),  /* EINT0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "i2c0"),          /* SDA */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),  /* EINT1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "i2c1"),          /* SCK */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),  /* EINT2 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "i2c1"),          /* SDA */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),  /* EINT3 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart3"),         /* TX */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),  /* EINT4 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart3"),         /* RX */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),  /* EINT5 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart3"),         /* RTS */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),  /* EINT6 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "uart3"),         /* CTS */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),  /* EINT7 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "spdif"),         /* OUT */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),  /* EINT8 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),  /* EINT9 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mic"),           /* CLK */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* EINT10 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "mic"),           /* DATA */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* EINT11 */
+};
+
+static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
+        .pins = a64_pins,
+        .npins = ARRAY_SIZE(a64_pins),
+        .irq_banks = 3,
+};
+
+static int a64_pinctrl_probe(struct platform_device *pdev)
+{
+        return sunxi_pinctrl_init(pdev,
+                                  &a64_pinctrl_data);
+}
+
+static const struct of_device_id a64_pinctrl_match[] = {
+        { .compatible = "allwinner,sun50i-a64-pinctrl", },
+        {}
+};
+
+static struct platform_driver a64_pinctrl_driver = {
+        .probe  = a64_pinctrl_probe,
+        .driver = {
+                .name           = "sun50i-a64-pinctrl",
+                .of_match_table = a64_pinctrl_match,
+        },
+};
+builtin_platform_driver(a64_pinctrl_driver);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c02600..435ad30f45db 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "nand0"),         /* NCE4 */
-                  SUNXI_FUNCTION(0x3, "spi2"),          /* CS0 */
-                  SUNXI_FUNCTION_IRQ(0x6, 12)),         /* EINT12 */
+                  SUNXI_FUNCTION(0x3, "spi2")),         /* CS0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "nand0"),         /* NCE5 */
-                  SUNXI_FUNCTION(0x3, "spi2"),          /* CLK */
-                  SUNXI_FUNCTION_IRQ(0x6, 13)),         /* EINT13 */
+                  SUNXI_FUNCTION(0x3, "spi2")),         /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "nand0"),         /* NCE6 */
-                  SUNXI_FUNCTION(0x3, "spi2"),          /* MOSI */
-                  SUNXI_FUNCTION_IRQ(0x6, 14)),         /* EINT14 */
+                  SUNXI_FUNCTION(0x3, "spi2")),         /* MOSI */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "nand0"),         /* NCE7 */
-                  SUNXI_FUNCTION(0x3, "spi2"),          /* MISO */
-                  SUNXI_FUNCTION_IRQ(0x6, 15)),         /* EINT15 */
+                  SUNXI_FUNCTION(0x3, "spi2")),         /* MISO */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -960,65 +956,65 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "spi0"),          /* CS0 */
                   SUNXI_FUNCTION(0x3, "uart5"),         /* TX */
-                  SUNXI_FUNCTION_IRQ(0x5, 22)),         /* EINT22 */
+                  SUNXI_FUNCTION_IRQ(0x6, 22)),         /* EINT22 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "spi0"),          /* CLK */
                   SUNXI_FUNCTION(0x3, "uart5"),         /* RX */
-                  SUNXI_FUNCTION_IRQ(0x5, 23)),         /* EINT23 */
+                  SUNXI_FUNCTION_IRQ(0x6, 23)),         /* EINT23 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "spi0"),          /* MOSI */
                   SUNXI_FUNCTION(0x3, "uart6"),         /* TX */
                   SUNXI_FUNCTION(0x4, "clk_out_a"),     /* CLK_OUT_A */
-                  SUNXI_FUNCTION_IRQ(0x5, 24)),         /* EINT24 */
+                  SUNXI_FUNCTION_IRQ(0x6, 24)),         /* EINT24 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "spi0"),          /* MISO */
                   SUNXI_FUNCTION(0x3, "uart6"),         /* RX */
                   SUNXI_FUNCTION(0x4, "clk_out_b"),     /* CLK_OUT_B */
-                  SUNXI_FUNCTION_IRQ(0x5, 25)),         /* EINT25 */
+                  SUNXI_FUNCTION_IRQ(0x6, 25)),         /* EINT25 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "spi0"),          /* CS1 */
                   SUNXI_FUNCTION(0x3, "ps2"),           /* SCK1 */
                   SUNXI_FUNCTION(0x4, "timer4"),        /* TCLKIN0 */
-                  SUNXI_FUNCTION_IRQ(0x5, 26)),         /* EINT26 */
+                  SUNXI_FUNCTION_IRQ(0x6, 26)),         /* EINT26 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "spi1"),          /* CS1 */
                   SUNXI_FUNCTION(0x3, "ps2"),           /* SDA1 */
                   SUNXI_FUNCTION(0x4, "timer5"),        /* TCLKIN1 */
-                  SUNXI_FUNCTION_IRQ(0x5, 27)),         /* EINT27 */
+                  SUNXI_FUNCTION_IRQ(0x6, 27)),         /* EINT27 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "spi1"),          /* CS0 */
                   SUNXI_FUNCTION(0x3, "uart2"),         /* RTS */
-                  SUNXI_FUNCTION_IRQ(0x5, 28)),         /* EINT28 */
+                  SUNXI_FUNCTION_IRQ(0x6, 28)),         /* EINT28 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "spi1"),          /* CLK */
                   SUNXI_FUNCTION(0x3, "uart2"),         /* CTS */
-                  SUNXI_FUNCTION_IRQ(0x5, 29)),         /* EINT29 */
+                  SUNXI_FUNCTION_IRQ(0x6, 29)),         /* EINT29 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "spi1"),          /* MOSI */
                   SUNXI_FUNCTION(0x3, "uart2"),         /* TX */
-                  SUNXI_FUNCTION_IRQ(0x5, 30)),         /* EINT30 */
+                  SUNXI_FUNCTION_IRQ(0x6, 30)),         /* EINT30 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
                   SUNXI_FUNCTION(0x2, "spi1"),          /* MISO */
                   SUNXI_FUNCTION(0x3, "uart2"),         /* RX */
-                  SUNXI_FUNCTION_IRQ(0x5, 31)),         /* EINT31 */
+                  SUNXI_FUNCTION_IRQ(0x6, 31)),         /* EINT31 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
                   SUNXI_FUNCTION(0x0, "gpio_in"),
                   SUNXI_FUNCTION(0x1, "gpio_out"),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
new file mode 100644
index 000000000000..686ec212120b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
@@ -0,0 +1,106 @@
+/*
+ * Allwinner H3 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2016 Krzysztof Adamski <k@japko.eu>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_h3_r_pins[] = {
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_twi"),         /* SCK */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_twi"),         /* SDA */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_uart"),        /* TX */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_uart"),        /* RX */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_jtag"),        /* MS */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_jtag"),        /* CK */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PL_EINT5 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_jtag"),        /* DO */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PL_EINT6 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_jtag"),        /* DI */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PL_EINT7 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PL_EINT8 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PL_EINT9 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_pwm"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_cir_rx"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
+};
+
+static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = {
+        .pins = sun8i_h3_r_pins,
+        .npins = ARRAY_SIZE(sun8i_h3_r_pins),
+        .irq_banks = 1,
+        .pin_base = PL_BASE,
+        .irq_read_needs_mux = true
+};
+
+static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev)
+{
+        return sunxi_pinctrl_init(pdev,
+                                  &sun8i_h3_r_pinctrl_data);
+}
+
+static const struct of_device_id sun8i_h3_r_pinctrl_match[] = {
+        { .compatible = "allwinner,sun8i-h3-r-pinctrl", },
+        {}
+};
+
+static struct platform_driver sun8i_h3_r_pinctrl_driver = {
+        .probe  = sun8i_h3_r_pinctrl_probe,
+        .driver = {
+                .name           = "sun8i-h3-r-pinctrl",
+                .of_match_table = sun8i_h3_r_pinctrl_match,
+        },
+};
+builtin_platform_driver(sun8i_h3_r_pinctrl_driver);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
index 42547ffa20a8..92a873f73697 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
@@ -9,7 +9,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/module.h>
+#include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
@@ -164,7 +164,6 @@ static const struct of_device_id sun9i_a80_r_pinctrl_match[] = {
         { .compatible = "allwinner,sun9i-a80-r-pinctrl", },
         {}
 };
-MODULE_DEVICE_TABLE(of, sun9i_a80_r_pinctrl_match);
 
 static struct platform_driver sun9i_a80_r_pinctrl_driver = {
         .probe  = sun9i_a80_r_pinctrl_probe,
@@ -174,8 +173,4 @@ static struct platform_driver sun9i_a80_r_pinctrl_driver = {
                 .of_match_table = sun9i_a80_r_pinctrl_match,
         },
 };
-module_platform_driver(sun9i_a80_r_pinctrl_driver);
-
-MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
-MODULE_DESCRIPTION("Allwinner A80 R_PIO pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(sun9i_a80_r_pinctrl_driver);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 7a2465f5e71e..3a2f5619f87c 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -15,7 +15,7 @@
 #include <linux/gpio/driver.h>
 #include <linux/irqdomain.h>
 #include <linux/irqchip/chained_irq.h>
-#include <linux/module.h>
+#include <linux/export.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
@@ -459,15 +459,16 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
         u8 index = sunxi_data_offset(offset);
         u32 set_mux = pctl->desc->irq_read_needs_mux &&
                         test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags);
+        u32 pin = offset + chip->base;
         u32 val;
 
         if (set_mux)
-                sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT);
+                sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
 
         val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 
         if (set_mux)
-                sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ);
+                sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 
         return !!val;
 }
diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig
new file mode 100644
index 000000000000..24e20cc08d5b
--- /dev/null
+++ b/drivers/pinctrl/tegra/Kconfig
@@ -0,0 +1,30 @@
+config PINCTRL_TEGRA
+        bool
+        select PINMUX
+        select PINCONF
+
+config PINCTRL_TEGRA20
+        bool
+        select PINCTRL_TEGRA
+
+config PINCTRL_TEGRA30
+        bool
+        select PINCTRL_TEGRA
+
+config PINCTRL_TEGRA114
+        bool
+        select PINCTRL_TEGRA
+
+config PINCTRL_TEGRA124
+        bool
+        select PINCTRL_TEGRA
+
+config PINCTRL_TEGRA210
+        bool
+        select PINCTRL_TEGRA
+
+config PINCTRL_TEGRA_XUSB
+        def_bool y if ARCH_TEGRA
+        select GENERIC_PHY
+        select PINCONF
+        select PINMUX
diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile
new file mode 100644
index 000000000000..a927379b6794
--- /dev/null
+++ b/drivers/pinctrl/tegra/Makefile
@@ -0,0 +1,7 @@
+obj-y                                   += pinctrl-tegra.o
+obj-$(CONFIG_PINCTRL_TEGRA20)           += pinctrl-tegra20.o
+obj-$(CONFIG_PINCTRL_TEGRA30)           += pinctrl-tegra30.o
+obj-$(CONFIG_PINCTRL_TEGRA114)          += pinctrl-tegra114.o
+obj-$(CONFIG_PINCTRL_TEGRA124)          += pinctrl-tegra124.o
+obj-$(CONFIG_PINCTRL_TEGRA210)          += pinctrl-tegra210.o
+obj-$(CONFIG_PINCTRL_TEGRA_XUSB)        += pinctrl-tegra-xusb.o
diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
index bd3aa5a4fd6d..2f06029c9405 100644
--- a/drivers/pinctrl/pinctrl-tegra-xusb.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
@@ -24,8 +24,8 @@
 
 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 
-#include "core.h"
-#include "pinctrl-utils.h"
+#include "../core.h"
+#include "../pinctrl-utils.h"
 
 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 9da4da219a07..49388822c0e9 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -30,9 +30,9 @@
 #include <linux/pinctrl/pinconf.h>
 #include <linux/slab.h>
 
-#include "core.h"
+#include "../core.h"
+#include "../pinctrl-utils.h"
 #include "pinctrl-tegra.h"
-#include "pinctrl-utils.h"
 
 struct tegra_pmx {
         struct device *dev;
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index 1615db7e3a4b..1615db7e3a4b 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/tegra/pinctrl-tegra114.c
index 05e49d5137ab..05e49d5137ab 100644
--- a/drivers/pinctrl/pinctrl-tegra114.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra114.c
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/tegra/pinctrl-tegra124.c
index 7cd44c7c296d..7cd44c7c296d 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra124.c
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c
index 4833db4433d9..4833db4433d9 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c
diff --git a/drivers/pinctrl/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c
index 252b464901c0..252b464901c0 100644
--- a/drivers/pinctrl/pinctrl-tegra210.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/tegra/pinctrl-tegra30.c
index 47b2fd8bb2e9..47b2fd8bb2e9 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra30.c
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 7abd614dc383..0b40ded5738f 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -1,6 +1,6 @@
 menuconfig PINCTRL_UNIPHIER
         bool "UniPhier SoC pinctrl drivers"
-        depends on ARCH_UNIPHIER
+        depends on ARCH_UNIPHIER || COMPILE_TEST
         depends on OF && MFD_SYSCON
         default y
         select PINMUX
@@ -8,27 +8,27 @@ menuconfig PINCTRL_UNIPHIER
 
 if PINCTRL_UNIPHIER
 
-config PINCTRL_UNIPHIER_PH1_LD4
+config PINCTRL_UNIPHIER_LD4
         tristate "UniPhier PH1-LD4 SoC pinctrl driver"
         default y
 
-config PINCTRL_UNIPHIER_PH1_PRO4
+config PINCTRL_UNIPHIER_PRO4
         tristate "UniPhier PH1-Pro4 SoC pinctrl driver"
         default y
 
-config PINCTRL_UNIPHIER_PH1_SLD8
+config PINCTRL_UNIPHIER_SLD8
         tristate "UniPhier PH1-sLD8 SoC pinctrl driver"
         default y
 
-config PINCTRL_UNIPHIER_PH1_PRO5
+config PINCTRL_UNIPHIER_PRO5
         tristate "UniPhier PH1-Pro5 SoC pinctrl driver"
         default y
 
-config PINCTRL_UNIPHIER_PROXSTREAM2
+config PINCTRL_UNIPHIER_PXS2
         tristate "UniPhier ProXstream2 SoC pinctrl driver"
         default y
 
-config PINCTRL_UNIPHIER_PH1_LD6B
+config PINCTRL_UNIPHIER_LD6B
         tristate "UniPhier PH1-LD6b SoC pinctrl driver"
         default y
 
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index e7ce9670306c..3b8f9ee0bb6f 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -1,8 +1,8 @@
-obj-y                                           += pinctrl-uniphier-core.o
+obj-y                                   += pinctrl-uniphier-core.o
 
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4)          += pinctrl-ph1-ld4.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4)         += pinctrl-ph1-pro4.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8)         += pinctrl-ph1-sld8.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5)         += pinctrl-ph1-pro5.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2)      += pinctrl-proxstream2.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD6B)         += pinctrl-ph1-ld6b.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD4)      += pinctrl-uniphier-ld4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4)     += pinctrl-uniphier-pro4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8)     += pinctrl-uniphier-sld8.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PRO5)     += pinctrl-uniphier-pro5.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2)     += pinctrl-uniphier-pxs2.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B)     += pinctrl-uniphier-ld6b.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index a7056dccfa53..a7056dccfa53 100644
--- a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 1824831bb4da..1824831bb4da 100644
--- a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index ec8e92dfaf8c..ec8e92dfaf8c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index e3d648eae85a..e3d648eae85a 100644
--- a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
diff --git a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index bc00d7591c59..bc00d7591c59 100644
--- a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index c3700a33a5da..c3700a33a5da 100644
--- a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
new file mode 100644
index 000000000000..2f00bdc42442
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
@@ -0,0 +1,520 @@
+#ifndef __DTS_MT7623_PINFUNC_H
+#define __DTS_MT7623_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
+
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
+
+#define MT7623_PIN_2_PWRAP_INT_FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT7623_PIN_2_PWRAP_INT_FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
+
+#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
+
+#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
+
+#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
+
+#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
+
+#define MT7623_PIN_7_SPI1_CSN_FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
+
+#define MT7623_PIN_8_SPI1_MI_FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
+#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
+
+#define MT7623_PIN_9_SPI1_MO_FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
+#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
+
+#define MT7623_PIN_10_RTC32K_CK_FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT7623_PIN_10_RTC32K_CK_FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
+
+#define MT7623_PIN_11_WATCHDOG_FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT7623_PIN_11_WATCHDOG_FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
+
+#define MT7623_PIN_12_SRCLKENA_FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT7623_PIN_12_SRCLKENA_FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
+
+#define MT7623_PIN_13_SRCLKENAI_FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT7623_PIN_13_SRCLKENAI_FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
+
+#define MT7623_PIN_14_GPIO14_FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT7623_PIN_14_GPIO14_FUNC_URXD2 (MTK_PIN_NO(14) | 1)
+#define MT7623_PIN_14_GPIO14_FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
+
+#define MT7623_PIN_15_GPIO15_FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT7623_PIN_15_GPIO15_FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
+#define MT7623_PIN_15_GPIO15_FUNC_URXD2 (MTK_PIN_NO(15) | 2)
+
+#define MT7623_PIN_18_PCM_CLK_FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT7623_PIN_18_PCM_CLK_FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
+#define MT7623_PIN_18_PCM_CLK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(18) | 6)
+
+#define MT7623_PIN_19_PCM_SYNC_FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT7623_PIN_19_PCM_SYNC_FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
+#define MT7623_PIN_19_PCM_SYNC_FUNC_AP_PCM_SYNC (MTK_PIN_NO(19) | 6)
+
+#define MT7623_PIN_20_PCM_RX_FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT7623_PIN_20_PCM_RX_FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
+#define MT7623_PIN_20_PCM_RX_FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
+#define MT7623_PIN_20_PCM_RX_FUNC_AP_PCM_RX (MTK_PIN_NO(20) | 6)
+
+#define MT7623_PIN_21_PCM_TX_FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT7623_PIN_21_PCM_TX_FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
+#define MT7623_PIN_21_PCM_TX_FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
+#define MT7623_PIN_21_PCM_TX_FUNC_AP_PCM_TX (MTK_PIN_NO(21) | 6)
+
+#define MT7623_PIN_22_EINT0_FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT7623_PIN_22_EINT0_FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
+#define MT7623_PIN_22_EINT0_FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 2)
+
+#define MT7623_PIN_23_EINT1_FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT7623_PIN_23_EINT1_FUNC_URTS0 (MTK_PIN_NO(23) | 1)
+#define MT7623_PIN_23_EINT1_FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 2)
+
+#define MT7623_PIN_24_EINT2_FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT7623_PIN_24_EINT2_FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
+#define MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 2)
+
+#define MT7623_PIN_25_EINT3_FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT7623_PIN_25_EINT3_FUNC_URTS1 (MTK_PIN_NO(25) | 1)
+
+#define MT7623_PIN_26_EINT4_FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT7623_PIN_26_EINT4_FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
+#define MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
+
+#define MT7623_PIN_27_EINT5_FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT7623_PIN_27_EINT5_FUNC_URTS3 (MTK_PIN_NO(27) | 1)
+#define MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
+
+#define MT7623_PIN_28_EINT6_FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT7623_PIN_28_EINT6_FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
+#define MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
+
+#define MT7623_PIN_29_EINT7_FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT7623_PIN_29_EINT7_FUNC_IDDIG (MTK_PIN_NO(29) | 1)
+#define MT7623_PIN_29_EINT7_FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
+#define MT7623_PIN_29_EINT7_FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 6)
+
+#define MT7623_PIN_33_I2S1_DATA_FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_AP_PCM_TX (MTK_PIN_NO(33) | 6)
+
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_AP_PCM_RX (MTK_PIN_NO(34) | 6)
+
+#define MT7623_PIN_35_I2S1_BCK_FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(35) | 6)
+
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_AP_PCM_SYNC (MTK_PIN_NO(36) | 6)
+
+#define MT7623_PIN_37_I2S1_MCLK_FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
+
+#define MT7623_PIN_39_JTMS_FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT7623_PIN_39_JTMS_FUNC_JTMS (MTK_PIN_NO(39) | 1)
+
+#define MT7623_PIN_40_JTCK_FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT7623_PIN_40_JTCK_FUNC_JTCK (MTK_PIN_NO(40) | 1)
+
+#define MT7623_PIN_41_JTDI_FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT7623_PIN_41_JTDI_FUNC_JTDI (MTK_PIN_NO(41) | 1)
+
+#define MT7623_PIN_42_JTDO_FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT7623_PIN_42_JTDO_FUNC_JTDO (MTK_PIN_NO(42) | 1)
+
+#define MT7623_PIN_43_NCLE_FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT7623_PIN_43_NCLE_FUNC_NCLE (MTK_PIN_NO(43) | 1)
+#define MT7623_PIN_43_NCLE_FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
+
+#define MT7623_PIN_44_NCEB1_FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT7623_PIN_44_NCEB1_FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
+#define MT7623_PIN_44_NCEB1_FUNC_IDDIG (MTK_PIN_NO(44) | 2)
+
+#define MT7623_PIN_45_NCEB0_FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT7623_PIN_45_NCEB0_FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
+#define MT7623_PIN_45_NCEB0_FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
+
+#define MT7623_PIN_46_IR_FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT7623_PIN_46_IR_FUNC_IR (MTK_PIN_NO(46) | 1)
+
+#define MT7623_PIN_47_NREB_FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT7623_PIN_47_NREB_FUNC_NREB (MTK_PIN_NO(47) | 1)
+
+#define MT7623_PIN_48_NRNB_FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT7623_PIN_48_NRNB_FUNC_NRNB (MTK_PIN_NO(48) | 1)
+
+#define MT7623_PIN_49_I2S0_DATA_FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_AP_I2S_DO (MTK_PIN_NO(49) | 6)
+
+#define MT7623_PIN_53_SPI0_CSN_FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
+#define MT7623_PIN_53_SPI0_CSN_FUNC_PWM1 (MTK_PIN_NO(53) | 5)
+
+#define MT7623_PIN_54_SPI0_CK_FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
+
+#define MT7623_PIN_55_SPI0_MI_FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
+#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
+#define MT7623_PIN_55_SPI0_MI_FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
+#define MT7623_PIN_55_SPI0_MI_FUNC_PWM2 (MTK_PIN_NO(55) | 5)
+
+#define MT7623_PIN_56_SPI0_MO_FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
+#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
+
+#define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1)
+
+#define MT7623_PIN_61_GPIO61_FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT7623_PIN_61_GPIO61_FUNC_TEST_FD (MTK_PIN_NO(61) | 1)
+
+#define MT7623_PIN_62_GPIO62_FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT7623_PIN_62_GPIO62_FUNC_TEST_FC (MTK_PIN_NO(62) | 1)
+
+#define MT7623_PIN_63_WB_SCLK_FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT7623_PIN_63_WB_SCLK_FUNC_WB_SCLK (MTK_PIN_NO(63) | 1)
+
+#define MT7623_PIN_64_WB_SDATA_FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT7623_PIN_64_WB_SDATA_FUNC_WB_SDATA (MTK_PIN_NO(64) | 1)
+
+#define MT7623_PIN_65_WB_SEN_FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT7623_PIN_65_WB_SEN_FUNC_WB_SEN (MTK_PIN_NO(65) | 1)
+
+#define MT7623_PIN_66_WB_CRTL0_FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define MT7623_PIN_66_WB_CRTL0_FUNC_WB_CRTL0 (MTK_PIN_NO(66) | 1)
+
+#define MT7623_PIN_67_WB_CRTL1_FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define MT7623_PIN_67_WB_CRTL1_FUNC_WB_CRTL1 (MTK_PIN_NO(67) | 1)
+
+#define MT7623_PIN_68_WB_CRTL2_FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT7623_PIN_68_WB_CRTL2_FUNC_WB_CRTL2 (MTK_PIN_NO(68) | 1)
+
+#define MT7623_PIN_69_WB_CRTL3_FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT7623_PIN_69_WB_CRTL3_FUNC_WB_CRTL3 (MTK_PIN_NO(69) | 1)
+
+#define MT7623_PIN_70_WB_CRTL4_FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT7623_PIN_70_WB_CRTL4_FUNC_WB_CRTL4 (MTK_PIN_NO(70) | 1)
+
+#define MT7623_PIN_71_WB_CRTL5_FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT7623_PIN_71_WB_CRTL5_FUNC_WB_CRTL5 (MTK_PIN_NO(71) | 1)
+
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PWM0 (MTK_PIN_NO(72) | 4)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_AP_I2S_DI (MTK_PIN_NO(72) | 6)
+
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_AP_I2S_LRCK (MTK_PIN_NO(73) | 6)
+
+#define MT7623_PIN_74_I2S0_BCK_FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_AP_I2S_BCK (MTK_PIN_NO(74) | 6)
+
+#define MT7623_PIN_75_SDA0_FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT7623_PIN_75_SDA0_FUNC_SDA0 (MTK_PIN_NO(75) | 1)
+
+#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1)
+
+#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
+
+#define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
+
+#define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1)
+
+#define MT7623_PIN_96_MIPI_TCP_FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define MT7623_PIN_96_MIPI_TCP_FUNC_TCP (MTK_PIN_NO(96) | 1)
+
+#define MT7623_PIN_97_MIPI_TDN1_FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1 (MTK_PIN_NO(97) | 1)
+
+#define MT7623_PIN_98_MIPI_TDP1_FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1 (MTK_PIN_NO(98) | 1)
+
+#define MT7623_PIN_99_MIPI_TDN0_FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0 (MTK_PIN_NO(99) | 1)
+
+#define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1)
+
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
+
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_SCL1 (MTK_PIN_NO(106) | 3)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
+
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
+
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM0 (MTK_PIN_NO(108) | 3)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_URXD0 (MTK_PIN_NO(108) | 5)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM1 (MTK_PIN_NO(108) | 6)
+
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_SDA2 (MTK_PIN_NO(109) | 3)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_PWM2 (MTK_PIN_NO(109) | 6)
+
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_SCL2 (MTK_PIN_NO(110) | 3)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_URXD1 (MTK_PIN_NO(110) | 5)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_PWM3 (MTK_PIN_NO(110) | 6)
+
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7 (MTK_PIN_NO(111) | 4)
+
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6 (MTK_PIN_NO(112) | 4)
+
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5 (MTK_PIN_NO(113) | 4)
+
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4 (MTK_PIN_NO(114) | 4)
+
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8 (MTK_PIN_NO(115) | 4)
+
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_NALE (MTK_PIN_NO(116) | 4)
+
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB (MTK_PIN_NO(117) | 4)
+
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3 (MTK_PIN_NO(118) | 4)
+
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2 (MTK_PIN_NO(119) | 4)
+
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1 (MTK_PIN_NO(120) | 4)
+
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0 (MTK_PIN_NO(121) | 4)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
+
+#define MT7623_PIN_122_GPIO122_FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT7623_PIN_122_GPIO122_FUNC_TEST (MTK_PIN_NO(122) | 1)
+#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4)
+#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5)
+
+#define MT7623_PIN_123_GPIO123_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT7623_PIN_123_GPIO123_FUNC_TEST (MTK_PIN_NO(123) | 1)
+#define MT7623_PIN_123_GPIO123_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
+#define MT7623_PIN_123_GPIO123_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
+
+#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1)
+#define MT7623_PIN_124_GPIO124_FUNC_SDA1 (MTK_PIN_NO(124) | 4)
+#define MT7623_PIN_124_GPIO124_FUNC_PWM3 (MTK_PIN_NO(124) | 5)
+
+#define MT7623_PIN_125_GPIO125_FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT7623_PIN_125_GPIO125_FUNC_TEST (MTK_PIN_NO(125) | 1)
+#define MT7623_PIN_125_GPIO125_FUNC_SCL1 (MTK_PIN_NO(125) | 4)
+#define MT7623_PIN_125_GPIO125_FUNC_PWM4 (MTK_PIN_NO(125) | 5)
+
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_AP_I2S_MCLK (MTK_PIN_NO(126) | 6)
+
+#define MT7623_PIN_199_SPI1_CK_FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
+
+#define MT7623_PIN_200_URXD2_FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT7623_PIN_200_URXD2_FUNC_URXD2 (MTK_PIN_NO(200) | 6)
+
+#define MT7623_PIN_201_UTXD2_FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT7623_PIN_201_UTXD2_FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
+
+#define MT7623_PIN_203_PWM0_FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define MT7623_PIN_203_PWM0_FUNC_PWM0 (MTK_PIN_NO(203) | 1)
+#define MT7623_PIN_203_PWM0_FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
+
+#define MT7623_PIN_204_PWM1_FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+#define MT7623_PIN_204_PWM1_FUNC_PWM1 (MTK_PIN_NO(204) | 1)
+
+#define MT7623_PIN_205_PWM2_FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+#define MT7623_PIN_205_PWM2_FUNC_PWM2 (MTK_PIN_NO(205) | 1)
+
+#define MT7623_PIN_206_PWM3_FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+#define MT7623_PIN_206_PWM3_FUNC_PWM3 (MTK_PIN_NO(206) | 1)
+
+#define MT7623_PIN_207_PWM4_FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+#define MT7623_PIN_207_PWM4_FUNC_PWM4 (MTK_PIN_NO(207) | 1)
+
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PWM0 (MTK_PIN_NO(208) | 2)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 3)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
+
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 3)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PWM1 (MTK_PIN_NO(209) | 5)
+
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_IDDIG (MTK_PIN_NO(236) | 2)
+
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
+
+#define MT7623_PIN_238_EXT_SDIO1_FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
+#define MT7623_PIN_238_EXT_SDIO1_FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
+
+#define MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
+#define MT7623_PIN_239_EXT_SDIO0_FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
+
+#define MT7623_PIN_240_EXT_XCS_FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
+#define MT7623_PIN_240_EXT_XCS_FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
+
+#define MT7623_PIN_241_EXT_SCK_FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
+#define MT7623_PIN_241_EXT_SCK_FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
+
+#define MT7623_PIN_242_URTS2_FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
+#define MT7623_PIN_242_URTS2_FUNC_URTS2 (MTK_PIN_NO(242) | 1)
+#define MT7623_PIN_242_URTS2_FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
+#define MT7623_PIN_242_URTS2_FUNC_URXD3 (MTK_PIN_NO(242) | 3)
+#define MT7623_PIN_242_URTS2_FUNC_SCL1 (MTK_PIN_NO(242) | 4)
+
+#define MT7623_PIN_243_UCTS2_FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
+#define MT7623_PIN_243_UCTS2_FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
+#define MT7623_PIN_243_UCTS2_FUNC_URXD3 (MTK_PIN_NO(243) | 2)
+#define MT7623_PIN_243_UCTS2_FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
+#define MT7623_PIN_243_UCTS2_FUNC_SDA1 (MTK_PIN_NO(243) | 4)
+
+#define MT7623_PIN_250_GPIO250_FUNC_GPIO250 (MTK_PIN_NO(250) | 0)
+#define MT7623_PIN_250_GPIO250_FUNC_TEST_MD7 (MTK_PIN_NO(250) | 1)
+#define MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 6)
+
+#define MT7623_PIN_251_GPIO251_FUNC_GPIO251 (MTK_PIN_NO(251) | 0)
+#define MT7623_PIN_251_GPIO251_FUNC_TEST_MD6 (MTK_PIN_NO(251) | 1)
+#define MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 6)
+
+#define MT7623_PIN_252_GPIO252_FUNC_GPIO252 (MTK_PIN_NO(252) | 0)
+#define MT7623_PIN_252_GPIO252_FUNC_TEST_MD5 (MTK_PIN_NO(252) | 1)
+#define MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 6)
+
+#define MT7623_PIN_253_GPIO253_FUNC_GPIO253 (MTK_PIN_NO(253) | 0)
+#define MT7623_PIN_253_GPIO253_FUNC_TEST_MD4 (MTK_PIN_NO(253) | 1)
+#define MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 6)
+
+#define MT7623_PIN_254_GPIO254_FUNC_GPIO254 (MTK_PIN_NO(254) | 0)
+#define MT7623_PIN_254_GPIO254_FUNC_TEST_MD3 (MTK_PIN_NO(254) | 1)
+#define MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 6)
+
+#define MT7623_PIN_255_GPIO255_FUNC_GPIO255 (MTK_PIN_NO(255) | 0)
+#define MT7623_PIN_255_GPIO255_FUNC_TEST_MD2 (MTK_PIN_NO(255) | 1)
+#define MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 6)
+
+#define MT7623_PIN_256_GPIO256_FUNC_GPIO256 (MTK_PIN_NO(256) | 0)
+#define MT7623_PIN_256_GPIO256_FUNC_TEST_MD1 (MTK_PIN_NO(256) | 1)
+
+#define MT7623_PIN_257_GPIO257_FUNC_GPIO257 (MTK_PIN_NO(257) | 0)
+#define MT7623_PIN_257_GPIO257_FUNC_TEST_MD0 (MTK_PIN_NO(257) | 1)
+
+#define MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
+#define MT7623_PIN_261_MSDC1_INS_FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
+
+#define MT7623_PIN_262_G2_TXEN_FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
+#define MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
+
+#define MT7623_PIN_263_G2_TXD3_FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
+#define MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
+
+#define MT7623_PIN_264_G2_TXD2_FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
+#define MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
+
+#define MT7623_PIN_265_G2_TXD1_FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
+#define MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
+
+#define MT7623_PIN_266_G2_TXD0_FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
+#define MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
+
+#define MT7623_PIN_267_G2_TXCLK_FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
+#define MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
+
+#define MT7623_PIN_268_G2_RXCLK_FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
+#define MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
+
+#define MT7623_PIN_269_G2_RXD0_FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
+#define MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
+
+#define MT7623_PIN_270_G2_RXD1_FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
+#define MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
+
+#define MT7623_PIN_271_G2_RXD2_FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
+#define MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
+
+#define MT7623_PIN_272_G2_RXD3_FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
+#define MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
+
+#define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
+#define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
+
+#define MT7623_PIN_275_G2_MDC_FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
+#define MT7623_PIN_275_G2_MDC_FUNC_MDC (MTK_PIN_NO(275) | 1)
+
+#define MT7623_PIN_276_G2_MDIO_FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
+#define MT7623_PIN_276_G2_MDIO_FUNC_MDIO (MTK_PIN_NO(276) | 1)
+
+#define MT7623_PIN_278_JTAG_RESET_FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
+#define MT7623_PIN_278_JTAG_RESET_FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
+
+#endif /* __DTS_MT7623_PINFUNC_H */