diff options
author | Rex Zhu <Rex.Zhu@amd.com> | 2016-12-14 04:14:16 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-01-27 11:12:47 -0500 |
commit | 5c964221003d9a31ad56d4784773c91a291cba97 (patch) | |
tree | 407b959e5d549126127727a47315696e7b0cd07c | |
parent | f6f534e2af5b518f522b5df244accf945a6207ec (diff) |
drm/amdgpu: refine gfx_v8 pg code.
move en/disable GFX CP/SMU_HS PG to
function gfx_v8_0_set_powergating_state
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 373374164bd5..5ab53d7b4bad 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | |||
@@ -4024,17 +4024,6 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev) | |||
4024 | WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); | 4024 | WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); |
4025 | gfx_v8_0_init_power_gating(adev); | 4025 | gfx_v8_0_init_power_gating(adev); |
4026 | WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); | 4026 | WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); |
4027 | if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { | ||
4028 | cz_enable_sck_slow_down_on_power_up(adev, true); | ||
4029 | cz_enable_sck_slow_down_on_power_down(adev, true); | ||
4030 | } else { | ||
4031 | cz_enable_sck_slow_down_on_power_up(adev, false); | ||
4032 | cz_enable_sck_slow_down_on_power_down(adev, false); | ||
4033 | } | ||
4034 | if (adev->pg_flags & AMD_PG_SUPPORT_CP) | ||
4035 | cz_enable_cp_power_gating(adev, true); | ||
4036 | else | ||
4037 | cz_enable_cp_power_gating(adev, false); | ||
4038 | } else if ((adev->asic_type == CHIP_POLARIS11) || | 4027 | } else if ((adev->asic_type == CHIP_POLARIS11) || |
4039 | (adev->asic_type == CHIP_POLARIS12)) { | 4028 | (adev->asic_type == CHIP_POLARIS12)) { |
4040 | gfx_v8_0_init_csb(adev); | 4029 | gfx_v8_0_init_csb(adev); |
@@ -5360,6 +5349,18 @@ static int gfx_v8_0_set_powergating_state(void *handle, | |||
5360 | case CHIP_CARRIZO: | 5349 | case CHIP_CARRIZO: |
5361 | case CHIP_STONEY: | 5350 | case CHIP_STONEY: |
5362 | 5351 | ||
5352 | if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { | ||
5353 | cz_enable_sck_slow_down_on_power_up(adev, true); | ||
5354 | cz_enable_sck_slow_down_on_power_down(adev, true); | ||
5355 | } else { | ||
5356 | cz_enable_sck_slow_down_on_power_up(adev, false); | ||
5357 | cz_enable_sck_slow_down_on_power_down(adev, false); | ||
5358 | } | ||
5359 | if (adev->pg_flags & AMD_PG_SUPPORT_CP) | ||
5360 | cz_enable_cp_power_gating(adev, true); | ||
5361 | else | ||
5362 | cz_enable_cp_power_gating(adev, false); | ||
5363 | |||
5363 | cz_update_gfx_cg_power_gating(adev, enable); | 5364 | cz_update_gfx_cg_power_gating(adev, enable); |
5364 | 5365 | ||
5365 | if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) | 5366 | if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) |