diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-11-11 19:21:20 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-11-11 19:21:20 -0500 |
commit | 5c03b53cb7386a5a9ee16b50de4d77d5cd06a438 (patch) | |
tree | 97a39e3178b49adb3a892c9cdc713897fde2c709 | |
parent | 015ed9433be2b476ec7e2e6a9a411a56e3b5b035 (diff) | |
parent | a33547cc764ca994d27a8fcc5fc61fbf4b2f7361 (diff) |
Merge tag 'pinctrl-v4.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"All is about drivers, no core business going on.
- Fix a host of runtime problems with the Intel Cherryview driver:
suspend/resume needs to be marshalled properly, and strange effects
from BIOS interaction during suspend/resume need to be dealt with.
- A single bit was being set wrong in the Aspeed driver.
- Fix an iProc probe ordering fallout resulting from v4.9
refactorings for bus population.
- Do not specify a default trigger in the ST Micro cascaded GPIO IRQ
controller: the kernel will moan.
- Make IRQs optional altogether on the STM32 driver, it turns out not
all systems have them or want them.
- Fix a re-probe bug in the i.MX driver, it will eventually crash if
probed repeatedly, not good"
* tag 'pinctrl-v4.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl-aspeed-g5: Never set SCU90[6]
pinctrl: cherryview: Prevent possible interrupt storm on resume
pinctrl: cherryview: Serialize register access in suspend/resume
pinctrl: imx: reset group index on probe
pinctrl: stm32: move gpio irqs binding to optional
pinctrl: stm32: remove dependency with interrupt controller
pinctrl: st: don't specify default interrupt trigger
pinctrl: iproc: Fix iProc and NSP GPIO support
-rw-r--r-- | Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 10 | ||||
-rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 | ||||
-rw-r--r-- | drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 2 | ||||
-rw-r--r-- | drivers/pinctrl/bcm/pinctrl-nsp-gpio.c | 2 | ||||
-rw-r--r-- | drivers/pinctrl/freescale/pinctrl-imx.c | 1 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-cherryview.c | 17 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-st.c | 2 | ||||
-rw-r--r-- | drivers/pinctrl/stm32/pinctrl-stm32.c | 8 |
8 files changed, 29 insertions, 15 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index f9753c416974..b24583aa34c3 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | |||
@@ -14,11 +14,6 @@ Required properies: | |||
14 | - #size-cells : The value of this property must be 1 | 14 | - #size-cells : The value of this property must be 1 |
15 | - ranges : defines mapping between pin controller node (parent) to | 15 | - ranges : defines mapping between pin controller node (parent) to |
16 | gpio-bank node (children). | 16 | gpio-bank node (children). |
17 | - interrupt-parent: phandle of the interrupt parent to which the external | ||
18 | GPIO interrupts are forwarded to. | ||
19 | - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node | ||
20 | which includes IRQ mux selection register, and the offset of the IRQ mux | ||
21 | selection register. | ||
22 | - pins-are-numbered: Specify the subnodes are using numbered pinmux to | 17 | - pins-are-numbered: Specify the subnodes are using numbered pinmux to |
23 | specify pins. | 18 | specify pins. |
24 | 19 | ||
@@ -37,6 +32,11 @@ Required properties: | |||
37 | 32 | ||
38 | Optional properties: | 33 | Optional properties: |
39 | - reset: : Reference to the reset controller | 34 | - reset: : Reference to the reset controller |
35 | - interrupt-parent: phandle of the interrupt parent to which the external | ||
36 | GPIO interrupts are forwarded to. | ||
37 | - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node | ||
38 | which includes IRQ mux selection register, and the offset of the IRQ mux | ||
39 | selection register. | ||
40 | 40 | ||
41 | Example: | 41 | Example: |
42 | #include <dt-bindings/pinctrl/stm32f429-pinfunc.h> | 42 | #include <dt-bindings/pinctrl/stm32f429-pinfunc.h> |
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index c8c72e8259d3..87b46390b695 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | |||
@@ -26,7 +26,7 @@ | |||
26 | 26 | ||
27 | #define ASPEED_G5_NR_PINS 228 | 27 | #define ASPEED_G5_NR_PINS 228 |
28 | 28 | ||
29 | #define COND1 SIG_DESC_BIT(SCU90, 6, 0) | 29 | #define COND1 { SCU90, BIT(6), 0, 0 } |
30 | #define COND2 { SCU94, GENMASK(1, 0), 0, 0 } | 30 | #define COND2 { SCU94, GENMASK(1, 0), 0, 0 } |
31 | 31 | ||
32 | #define B14 0 | 32 | #define B14 0 |
diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index 7f7700716398..5d1e505c3c63 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | |||
@@ -844,6 +844,6 @@ static struct platform_driver iproc_gpio_driver = { | |||
844 | 844 | ||
845 | static int __init iproc_gpio_init(void) | 845 | static int __init iproc_gpio_init(void) |
846 | { | 846 | { |
847 | return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe); | 847 | return platform_driver_register(&iproc_gpio_driver); |
848 | } | 848 | } |
849 | arch_initcall_sync(iproc_gpio_init); | 849 | arch_initcall_sync(iproc_gpio_init); |
diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index 35783db1c10b..c8deb8be1da7 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c | |||
@@ -741,6 +741,6 @@ static struct platform_driver nsp_gpio_driver = { | |||
741 | 741 | ||
742 | static int __init nsp_gpio_init(void) | 742 | static int __init nsp_gpio_init(void) |
743 | { | 743 | { |
744 | return platform_driver_probe(&nsp_gpio_driver, nsp_gpio_probe); | 744 | return platform_driver_register(&nsp_gpio_driver); |
745 | } | 745 | } |
746 | arch_initcall_sync(nsp_gpio_init); | 746 | arch_initcall_sync(nsp_gpio_init); |
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 47613201269a..79c4e14a5a75 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c | |||
@@ -687,6 +687,7 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, | |||
687 | if (!info->functions) | 687 | if (!info->functions) |
688 | return -ENOMEM; | 688 | return -ENOMEM; |
689 | 689 | ||
690 | info->group_index = 0; | ||
690 | if (flat_funcs) { | 691 | if (flat_funcs) { |
691 | info->ngroups = of_get_child_count(np); | 692 | info->ngroups = of_get_child_count(np); |
692 | } else { | 693 | } else { |
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 30389f4ccab4..c43b1e9a06af 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c | |||
@@ -1652,12 +1652,15 @@ static int chv_pinctrl_probe(struct platform_device *pdev) | |||
1652 | } | 1652 | } |
1653 | 1653 | ||
1654 | #ifdef CONFIG_PM_SLEEP | 1654 | #ifdef CONFIG_PM_SLEEP |
1655 | static int chv_pinctrl_suspend(struct device *dev) | 1655 | static int chv_pinctrl_suspend_noirq(struct device *dev) |
1656 | { | 1656 | { |
1657 | struct platform_device *pdev = to_platform_device(dev); | 1657 | struct platform_device *pdev = to_platform_device(dev); |
1658 | struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); | 1658 | struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); |
1659 | unsigned long flags; | ||
1659 | int i; | 1660 | int i; |
1660 | 1661 | ||
1662 | raw_spin_lock_irqsave(&chv_lock, flags); | ||
1663 | |||
1661 | pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); | 1664 | pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); |
1662 | 1665 | ||
1663 | for (i = 0; i < pctrl->community->npins; i++) { | 1666 | for (i = 0; i < pctrl->community->npins; i++) { |
@@ -1678,15 +1681,20 @@ static int chv_pinctrl_suspend(struct device *dev) | |||
1678 | ctx->padctrl1 = readl(reg); | 1681 | ctx->padctrl1 = readl(reg); |
1679 | } | 1682 | } |
1680 | 1683 | ||
1684 | raw_spin_unlock_irqrestore(&chv_lock, flags); | ||
1685 | |||
1681 | return 0; | 1686 | return 0; |
1682 | } | 1687 | } |
1683 | 1688 | ||
1684 | static int chv_pinctrl_resume(struct device *dev) | 1689 | static int chv_pinctrl_resume_noirq(struct device *dev) |
1685 | { | 1690 | { |
1686 | struct platform_device *pdev = to_platform_device(dev); | 1691 | struct platform_device *pdev = to_platform_device(dev); |
1687 | struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); | 1692 | struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); |
1693 | unsigned long flags; | ||
1688 | int i; | 1694 | int i; |
1689 | 1695 | ||
1696 | raw_spin_lock_irqsave(&chv_lock, flags); | ||
1697 | |||
1690 | /* | 1698 | /* |
1691 | * Mask all interrupts before restoring per-pin configuration | 1699 | * Mask all interrupts before restoring per-pin configuration |
1692 | * registers because we don't know in which state BIOS left them | 1700 | * registers because we don't know in which state BIOS left them |
@@ -1731,12 +1739,15 @@ static int chv_pinctrl_resume(struct device *dev) | |||
1731 | chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); | 1739 | chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); |
1732 | chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); | 1740 | chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); |
1733 | 1741 | ||
1742 | raw_spin_unlock_irqrestore(&chv_lock, flags); | ||
1743 | |||
1734 | return 0; | 1744 | return 0; |
1735 | } | 1745 | } |
1736 | #endif | 1746 | #endif |
1737 | 1747 | ||
1738 | static const struct dev_pm_ops chv_pinctrl_pm_ops = { | 1748 | static const struct dev_pm_ops chv_pinctrl_pm_ops = { |
1739 | SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume) | 1749 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, |
1750 | chv_pinctrl_resume_noirq) | ||
1740 | }; | 1751 | }; |
1741 | 1752 | ||
1742 | static const struct acpi_device_id chv_pinctrl_acpi_match[] = { | 1753 | static const struct acpi_device_id chv_pinctrl_acpi_match[] = { |
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 99da4cf91031..b7bb37167969 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c | |||
@@ -1512,7 +1512,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, | |||
1512 | if (info->irqmux_base || gpio_irq > 0) { | 1512 | if (info->irqmux_base || gpio_irq > 0) { |
1513 | err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, | 1513 | err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, |
1514 | 0, handle_simple_irq, | 1514 | 0, handle_simple_irq, |
1515 | IRQ_TYPE_LEVEL_LOW); | 1515 | IRQ_TYPE_NONE); |
1516 | if (err) { | 1516 | if (err) { |
1517 | gpiochip_remove(&bank->gpio_chip); | 1517 | gpiochip_remove(&bank->gpio_chip); |
1518 | dev_info(dev, "could not add irqchip\n"); | 1518 | dev_info(dev, "could not add irqchip\n"); |
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 200667f08c37..efc43711ff5c 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c | |||
@@ -1092,9 +1092,11 @@ int stm32_pctl_probe(struct platform_device *pdev) | |||
1092 | return -EINVAL; | 1092 | return -EINVAL; |
1093 | } | 1093 | } |
1094 | 1094 | ||
1095 | ret = stm32_pctrl_dt_setup_irq(pdev, pctl); | 1095 | if (of_find_property(np, "interrupt-parent", NULL)) { |
1096 | if (ret) | 1096 | ret = stm32_pctrl_dt_setup_irq(pdev, pctl); |
1097 | return ret; | 1097 | if (ret) |
1098 | return ret; | ||
1099 | } | ||
1098 | 1100 | ||
1099 | for_each_child_of_node(np, child) | 1101 | for_each_child_of_node(np, child) |
1100 | if (of_property_read_bool(child, "gpio-controller")) | 1102 | if (of_property_read_bool(child, "gpio-controller")) |