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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2013-08-02 02:39:56 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-08-06 05:07:13 -0400
commit5b3859d7b2c10419e1cc7ce6c456995e757f4390 (patch)
treebc7589d62d1ca916fc80c2c94fef0bde6ed2776d
parent70e3f3d4f40fe5ecdb351acf33db06df077fb0c1 (diff)
ARM: shmobile: r8a7779: move r8a7779_init_irq_xxx() to setup
This patch moves r8a7779_init_irq_xxx() to setup code, and remove intc-r8a7779. Now, r8a7779_init_irq_extpin() uses platform_device_register_resndata() instead of platform_device_register() Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat
-rw-r--r--arch/arm/mach-shmobile/Makefile2
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7779.c116
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c80
3 files changed, 81 insertions, 117 deletions
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 74181314fded..969c3a9dde5b 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
11obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o 11obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o
12obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o 12obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o
13obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o 13obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o
14obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o 14obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o
15obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o 15obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o
16obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o 16obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
17 17
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
deleted file mode 100644
index e992a68b3bc7..000000000000
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * r8a7779 processor support - INTC hardware block
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/irqchip/arm-gic.h>
27#include <linux/platform_data/irq-renesas-intc-irqpin.h>
28#include <linux/irqchip.h>
29#include <mach/common.h>
30#include <mach/irqs.h>
31#include <mach/r8a7779.h>
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34
35#define INT2SMSKCR0 IOMEM(0xfe7822a0)
36#define INT2SMSKCR1 IOMEM(0xfe7822a4)
37#define INT2SMSKCR2 IOMEM(0xfe7822a8)
38#define INT2SMSKCR3 IOMEM(0xfe7822ac)
39#define INT2SMSKCR4 IOMEM(0xfe7822b0)
40
41#define INT2NTSR0 IOMEM(0xfe700060)
42#define INT2NTSR1 IOMEM(0xfe700064)
43
44static struct renesas_intc_irqpin_config irqpin0_platform_data = {
45 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
46 .sense_bitfield_width = 2,
47};
48
49static struct resource irqpin0_resources[] = {
50 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
51 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
52 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
53 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
54 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
55 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
56 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
57 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
58 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
59};
60
61static struct platform_device irqpin0_device = {
62 .name = "renesas_intc_irqpin",
63 .id = 0,
64 .resource = irqpin0_resources,
65 .num_resources = ARRAY_SIZE(irqpin0_resources),
66 .dev = {
67 .platform_data = &irqpin0_platform_data,
68 },
69};
70
71void __init r8a7779_init_irq_extpin(int irlm)
72{
73 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
74 unsigned long tmp;
75
76 if (icr0) {
77 tmp = ioread32(icr0);
78 if (irlm)
79 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
80 else
81 tmp &= ~(1 << 23); /* IRL mode - not supported */
82 tmp |= (1 << 21); /* LVLMODE = 1 */
83 iowrite32(tmp, icr0);
84 iounmap(icr0);
85
86 if (irlm)
87 platform_device_register(&irqpin0_device);
88 } else
89 pr_warn("r8a7779: unable to setup external irq pin mode\n");
90}
91
92#ifdef CONFIG_OF
93static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
94{
95 return 0; /* always allow wakeup */
96}
97
98void __init r8a7779_init_irq_dt(void)
99{
100 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
101
102 irqchip_init();
103
104 /* route all interrupts to ARM */
105 __raw_writel(0xffffffff, INT2NTSR0);
106 __raw_writel(0x3fffffff, INT2NTSR1);
107
108 /* unmask all known interrupts in INTCS2 */
109 __raw_writel(0xfffffff0, INT2SMSKCR0);
110 __raw_writel(0xfff7ffff, INT2SMSKCR1);
111 __raw_writel(0xfffbffdf, INT2SMSKCR2);
112 __raw_writel(0xbffffffc, INT2SMSKCR3);
113 __raw_writel(0x003fee3f, INT2SMSKCR4);
114
115}
116#endif
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index f0b6c7dea2f0..6a9933395434 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -22,8 +22,11 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/irqchip.h>
26#include <linux/irqchip/arm-gic.h>
25#include <linux/of_platform.h> 27#include <linux/of_platform.h>
26#include <linux/platform_data/gpio-rcar.h> 28#include <linux/platform_data/gpio-rcar.h>
29#include <linux/platform_data/irq-renesas-intc-irqpin.h>
27#include <linux/platform_device.h> 30#include <linux/platform_device.h>
28#include <linux/delay.h> 31#include <linux/delay.h>
29#include <linux/input.h> 32#include <linux/input.h>
@@ -67,6 +70,60 @@ void __init r8a7779_map_io(void)
67 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); 70 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
68} 71}
69 72
73/* IRQ */
74#define INT2SMSKCR0 IOMEM(0xfe7822a0)
75#define INT2SMSKCR1 IOMEM(0xfe7822a4)
76#define INT2SMSKCR2 IOMEM(0xfe7822a8)
77#define INT2SMSKCR3 IOMEM(0xfe7822ac)
78#define INT2SMSKCR4 IOMEM(0xfe7822b0)
79
80#define INT2NTSR0 IOMEM(0xfe700060)
81#define INT2NTSR1 IOMEM(0xfe700064)
82
83static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
84 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
85 .sense_bitfield_width = 2,
86};
87
88static struct resource irqpin0_resources[] __initdata = {
89 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
90 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
91 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
92 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
93 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
94 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
95 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
96 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
97 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
98};
99
100void __init r8a7779_init_irq_extpin(int irlm)
101{
102 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
103 u32 tmp;
104
105 if (!icr0) {
106 pr_warn("r8a7779: unable to setup external irq pin mode\n");
107 return;
108 }
109
110 tmp = ioread32(icr0);
111 if (irlm)
112 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
113 else
114 tmp &= ~(1 << 23); /* IRL mode - not supported */
115 tmp |= (1 << 21); /* LVLMODE = 1 */
116 iowrite32(tmp, icr0);
117 iounmap(icr0);
118
119 if (irlm)
120 platform_device_register_resndata(
121 &platform_bus, "renesas_intc_irqpin", -1,
122 irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
123 &irqpin0_platform_data, sizeof(irqpin0_platform_data));
124}
125
126/* PFC/GPIO */
70static struct resource r8a7779_pfc_resources[] = { 127static struct resource r8a7779_pfc_resources[] = {
71 DEFINE_RES_MEM(0xfffc0000, 0x023c), 128 DEFINE_RES_MEM(0xfffc0000, 0x023c),
72}; 129};
@@ -641,6 +698,29 @@ void __init r8a7779_init_late(void)
641} 698}
642 699
643#ifdef CONFIG_USE_OF 700#ifdef CONFIG_USE_OF
701static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
702{
703 return 0; /* always allow wakeup */
704}
705
706void __init r8a7779_init_irq_dt(void)
707{
708 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
709
710 irqchip_init();
711
712 /* route all interrupts to ARM */
713 __raw_writel(0xffffffff, INT2NTSR0);
714 __raw_writel(0x3fffffff, INT2NTSR1);
715
716 /* unmask all known interrupts in INTCS2 */
717 __raw_writel(0xfffffff0, INT2SMSKCR0);
718 __raw_writel(0xfff7ffff, INT2SMSKCR1);
719 __raw_writel(0xfffbffdf, INT2SMSKCR2);
720 __raw_writel(0xbffffffc, INT2SMSKCR3);
721 __raw_writel(0x003fee3f, INT2SMSKCR4);
722}
723
644void __init r8a7779_init_delay(void) 724void __init r8a7779_init_delay(void)
645{ 725{
646 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ 726 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 07:13:18 -0400