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authorAnson Huang <b20788@freescale.com>2015-08-04 11:54:58 -0400
committerShawn Guo <shawnguo@kernel.org>2015-08-11 11:15:27 -0400
commit5b032872c9c8a7abe3b19757f6873cc8b9864fc3 (patch)
tree795a84f6bf9847f5a1d86290a1adc70d93406256
parent18619ff55d613dc5c8276ae70e5ca4e48c609f44 (diff)
ARM: dts: imx6ul: add RTC support
Add RTC support for i.MX6UL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm/boot/dts/imx6ul.dtsi13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 70a11e395b9d..19fdaebfde5d 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -412,6 +412,19 @@
412 fsl,anatop = <&anatop>; 412 fsl,anatop = <&anatop>;
413 }; 413 };
414 414
415 snvs: snvs@020cc000 {
416 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
417 reg = <0x020cc000 0x4000>;
418
419 snvs_rtc: snvs-rtc-lp {
420 compatible = "fsl,sec-v4.0-mon-rtc-lp";
421 regmap = <&snvs>;
422 offset = <0x34>;
423 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
425 };
426 };
427
415 epit1: epit@020d0000 { 428 epit1: epit@020d0000 {
416 reg = <0x020d0000 0x4000>; 429 reg = <0x020d0000 0x4000>;
417 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 430 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;