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authorDavid S. Miller <davem@davemloft.net>2016-11-13 22:36:42 -0500
committerDavid S. Miller <davem@davemloft.net>2016-11-13 22:36:42 -0500
commit5aad5b42bd4b8c067cdac153636db56b00ac874c (patch)
tree9f6b2fedc17e9e8804dfefb5dded2b2307ed87fe
parent63fb571ee50320191a3cc2c4634c9c9f918a2c44 (diff)
parent94d66ae63151ab8db47fe468f5fe37a616f7bfeb (diff)
Merge branch 'dsa-mv88e6xxx-post-refactor-fixes'
Andrew Lunn says: ==================== dsa: mv88e6xxx: Fixes for port refactoring The patches which refactored setting up the switch MACs introduced a couple of regressions. The RGMII delays for a port can be set using other mechanism than just phy-mode. Don't overwrite the delays unless explicitly asked to. This broke my Armada 370 RD. Also, the mv88e6351 family supports setting RGMII delays, but is missing the necessary entries in the ops structures to allow this. These fixes are to patches currently in net-next. No need for stable etc. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/dsa/mv88e6xxx/chip.c4
-rw-r--r--drivers/net/dsa/mv88e6xxx/port.c5
2 files changed, 7 insertions, 2 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index c8f824d4ff26..d6d9d66b81ce 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3196,6 +3196,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
3196 .phy_write = mv88e6xxx_g2_smi_phy_write, 3196 .phy_write = mv88e6xxx_g2_smi_phy_write,
3197 .port_set_link = mv88e6xxx_port_set_link, 3197 .port_set_link = mv88e6xxx_port_set_link,
3198 .port_set_duplex = mv88e6xxx_port_set_duplex, 3198 .port_set_duplex = mv88e6xxx_port_set_duplex,
3199 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3199 .port_set_speed = mv88e6185_port_set_speed, 3200 .port_set_speed = mv88e6185_port_set_speed,
3200}; 3201};
3201 3202
@@ -3217,6 +3218,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
3217 .phy_write = mv88e6xxx_g2_smi_phy_write, 3218 .phy_write = mv88e6xxx_g2_smi_phy_write,
3218 .port_set_link = mv88e6xxx_port_set_link, 3219 .port_set_link = mv88e6xxx_port_set_link,
3219 .port_set_duplex = mv88e6xxx_port_set_duplex, 3220 .port_set_duplex = mv88e6xxx_port_set_duplex,
3221 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3220 .port_set_speed = mv88e6185_port_set_speed, 3222 .port_set_speed = mv88e6185_port_set_speed,
3221}; 3223};
3222 3224
@@ -3281,6 +3283,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
3281 .phy_write = mv88e6xxx_g2_smi_phy_write, 3283 .phy_write = mv88e6xxx_g2_smi_phy_write,
3282 .port_set_link = mv88e6xxx_port_set_link, 3284 .port_set_link = mv88e6xxx_port_set_link,
3283 .port_set_duplex = mv88e6xxx_port_set_duplex, 3285 .port_set_duplex = mv88e6xxx_port_set_duplex,
3286 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3284 .port_set_speed = mv88e6185_port_set_speed, 3287 .port_set_speed = mv88e6185_port_set_speed,
3285}; 3288};
3286 3289
@@ -3290,6 +3293,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
3290 .phy_write = mv88e6xxx_g2_smi_phy_write, 3293 .phy_write = mv88e6xxx_g2_smi_phy_write,
3291 .port_set_link = mv88e6xxx_port_set_link, 3294 .port_set_link = mv88e6xxx_port_set_link,
3292 .port_set_duplex = mv88e6xxx_port_set_duplex, 3295 .port_set_duplex = mv88e6xxx_port_set_duplex,
3296 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3293 .port_set_speed = mv88e6185_port_set_speed, 3297 .port_set_speed = mv88e6185_port_set_speed,
3294}; 3298};
3295 3299
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 18eeed083cbd..e4978f6367aa 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -63,9 +63,10 @@ static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
63 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK | 63 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
64 PORT_PCS_CTRL_RGMII_DELAY_TXCLK; 64 PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
65 break; 65 break;
66 default: 66 case PHY_INTERFACE_MODE_RGMII:
67 /* no delay */
68 break; 67 break;
68 default:
69 return 0;
69 } 70 }
70 71
71 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); 72 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);