diff options
author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-05-12 10:43:13 -0400 |
---|---|---|
committer | Jason Cooper <jason@lakedaemon.net> | 2016-06-22 14:44:54 -0400 |
commit | 5952884258e52ad695e281d7b8181d51384ee97c (patch) | |
tree | 9d8527ec945e399417ba06bb5b80dc521a137cde | |
parent | 50ad77db41fe3a08aeeae04088869142a1d9d007 (diff) |
irqchip/aspeed-vic: Add irq controller for Aspeed
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/1463064193-2178-3-git-send-email-joel@jms.id.au
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r-- | drivers/irqchip/Makefile | 1 | ||||
-rw-r--r-- | drivers/irqchip/irq-aspeed-vic.c | 230 |
2 files changed, 231 insertions, 0 deletions
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 38853a187607..bb5dc3dad8d1 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile | |||
@@ -69,3 +69,4 @@ obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o | |||
69 | obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o | 69 | obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o |
70 | obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o | 70 | obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o |
71 | obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o | 71 | obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o |
72 | obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o | ||
diff --git a/drivers/irqchip/irq-aspeed-vic.c b/drivers/irqchip/irq-aspeed-vic.c new file mode 100644 index 000000000000..d24451d5bf8a --- /dev/null +++ b/drivers/irqchip/irq-aspeed-vic.c | |||
@@ -0,0 +1,230 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp. | ||
3 | * | ||
4 | * Driver for Aspeed "new" VIC as found in SoC generation 3 and later | ||
5 | * | ||
6 | * Based on irq-vic.c: | ||
7 | * | ||
8 | * Copyright (C) 1999 - 2003 ARM Limited | ||
9 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License as published by | ||
13 | * the Free Software Foundation; either version 2 of the License, or | ||
14 | * (at your option) any later version. | ||
15 | * | ||
16 | * This program is distributed in the hope that it will be useful, | ||
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
19 | * GNU General Public License for more details. | ||
20 | * | ||
21 | */ | ||
22 | |||
23 | #include <linux/export.h> | ||
24 | #include <linux/init.h> | ||
25 | #include <linux/list.h> | ||
26 | #include <linux/io.h> | ||
27 | #include <linux/irq.h> | ||
28 | #include <linux/irqchip.h> | ||
29 | #include <linux/irqchip/chained_irq.h> | ||
30 | #include <linux/irqdomain.h> | ||
31 | #include <linux/of.h> | ||
32 | #include <linux/of_address.h> | ||
33 | #include <linux/of_irq.h> | ||
34 | #include <linux/syscore_ops.h> | ||
35 | #include <linux/device.h> | ||
36 | #include <linux/slab.h> | ||
37 | |||
38 | #include <asm/exception.h> | ||
39 | #include <asm/irq.h> | ||
40 | |||
41 | /* These definitions correspond to the "new mapping" of the | ||
42 | * register set that interleaves "high" and "low". The offsets | ||
43 | * below are for the "low" register, add 4 to get to the high one | ||
44 | */ | ||
45 | #define AVIC_IRQ_STATUS 0x00 | ||
46 | #define AVIC_FIQ_STATUS 0x08 | ||
47 | #define AVIC_RAW_STATUS 0x10 | ||
48 | #define AVIC_INT_SELECT 0x18 | ||
49 | #define AVIC_INT_ENABLE 0x20 | ||
50 | #define AVIC_INT_ENABLE_CLR 0x28 | ||
51 | #define AVIC_INT_TRIGGER 0x30 | ||
52 | #define AVIC_INT_TRIGGER_CLR 0x38 | ||
53 | #define AVIC_INT_SENSE 0x40 | ||
54 | #define AVIC_INT_DUAL_EDGE 0x48 | ||
55 | #define AVIC_INT_EVENT 0x50 | ||
56 | #define AVIC_EDGE_CLR 0x58 | ||
57 | #define AVIC_EDGE_STATUS 0x60 | ||
58 | |||
59 | #define NUM_IRQS 64 | ||
60 | |||
61 | struct aspeed_vic { | ||
62 | void __iomem *base; | ||
63 | u32 edge_sources[2]; | ||
64 | struct irq_domain *dom; | ||
65 | }; | ||
66 | static struct aspeed_vic *system_avic; | ||
67 | |||
68 | static void vic_init_hw(struct aspeed_vic *vic) | ||
69 | { | ||
70 | u32 sense; | ||
71 | |||
72 | /* Disable all interrupts */ | ||
73 | writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); | ||
74 | writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); | ||
75 | |||
76 | /* Make sure no soft trigger is on */ | ||
77 | writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); | ||
78 | writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); | ||
79 | |||
80 | /* Set everything to be IRQ */ | ||
81 | writel(0, vic->base + AVIC_INT_SELECT); | ||
82 | writel(0, vic->base + AVIC_INT_SELECT + 4); | ||
83 | |||
84 | /* Some interrupts have a programable high/low level trigger | ||
85 | * (4 GPIO direct inputs), for now we assume this was configured | ||
86 | * by firmware. We read which ones are edge now. | ||
87 | */ | ||
88 | sense = readl(vic->base + AVIC_INT_SENSE); | ||
89 | vic->edge_sources[0] = ~sense; | ||
90 | sense = readl(vic->base + AVIC_INT_SENSE + 4); | ||
91 | vic->edge_sources[1] = ~sense; | ||
92 | |||
93 | /* Clear edge detection latches */ | ||
94 | writel(0xffffffff, vic->base + AVIC_EDGE_CLR); | ||
95 | writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4); | ||
96 | } | ||
97 | |||
98 | static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) | ||
99 | { | ||
100 | struct aspeed_vic *vic = system_avic; | ||
101 | u32 stat, irq; | ||
102 | |||
103 | for (;;) { | ||
104 | irq = 0; | ||
105 | stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS); | ||
106 | if (!stat) { | ||
107 | stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4); | ||
108 | irq = 32; | ||
109 | } | ||
110 | if (stat == 0) | ||
111 | break; | ||
112 | irq += ffs(stat) - 1; | ||
113 | handle_domain_irq(vic->dom, irq, regs); | ||
114 | } | ||
115 | } | ||
116 | |||
117 | static void avic_ack_irq(struct irq_data *d) | ||
118 | { | ||
119 | struct aspeed_vic *vic = irq_data_get_irq_chip_data(d); | ||
120 | unsigned int sidx = d->hwirq >> 5; | ||
121 | unsigned int sbit = 1u << (d->hwirq & 0x1f); | ||
122 | |||
123 | /* Clear edge latch for edge interrupts, nop for level */ | ||
124 | if (vic->edge_sources[sidx] & sbit) | ||
125 | writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4); | ||
126 | } | ||
127 | |||
128 | static void avic_mask_irq(struct irq_data *d) | ||
129 | { | ||
130 | struct aspeed_vic *vic = irq_data_get_irq_chip_data(d); | ||
131 | unsigned int sidx = d->hwirq >> 5; | ||
132 | unsigned int sbit = 1u << (d->hwirq & 0x1f); | ||
133 | |||
134 | writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4); | ||
135 | } | ||
136 | |||
137 | static void avic_unmask_irq(struct irq_data *d) | ||
138 | { | ||
139 | struct aspeed_vic *vic = irq_data_get_irq_chip_data(d); | ||
140 | unsigned int sidx = d->hwirq >> 5; | ||
141 | unsigned int sbit = 1u << (d->hwirq & 0x1f); | ||
142 | |||
143 | writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4); | ||
144 | } | ||
145 | |||
146 | /* For level irq, faster than going through a nop "ack" and mask */ | ||
147 | static void avic_mask_ack_irq(struct irq_data *d) | ||
148 | { | ||
149 | struct aspeed_vic *vic = irq_data_get_irq_chip_data(d); | ||
150 | unsigned int sidx = d->hwirq >> 5; | ||
151 | unsigned int sbit = 1u << (d->hwirq & 0x1f); | ||
152 | |||
153 | /* First mask */ | ||
154 | writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4); | ||
155 | |||
156 | /* Then clear edge latch for edge interrupts */ | ||
157 | if (vic->edge_sources[sidx] & sbit) | ||
158 | writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4); | ||
159 | } | ||
160 | |||
161 | static struct irq_chip avic_chip = { | ||
162 | .name = "AVIC", | ||
163 | .irq_ack = avic_ack_irq, | ||
164 | .irq_mask = avic_mask_irq, | ||
165 | .irq_unmask = avic_unmask_irq, | ||
166 | .irq_mask_ack = avic_mask_ack_irq, | ||
167 | }; | ||
168 | |||
169 | static int avic_map(struct irq_domain *d, unsigned int irq, | ||
170 | irq_hw_number_t hwirq) | ||
171 | { | ||
172 | struct aspeed_vic *vic = d->host_data; | ||
173 | unsigned int sidx = hwirq >> 5; | ||
174 | unsigned int sbit = 1u << (hwirq & 0x1f); | ||
175 | |||
176 | /* Check if interrupt exists */ | ||
177 | if (sidx > 1) | ||
178 | return -EPERM; | ||
179 | |||
180 | if (vic->edge_sources[sidx] & sbit) | ||
181 | irq_set_chip_and_handler(irq, &avic_chip, handle_edge_irq); | ||
182 | else | ||
183 | irq_set_chip_and_handler(irq, &avic_chip, handle_level_irq); | ||
184 | irq_set_chip_data(irq, vic); | ||
185 | irq_set_probe(irq); | ||
186 | return 0; | ||
187 | } | ||
188 | |||
189 | static struct irq_domain_ops avic_dom_ops = { | ||
190 | .map = avic_map, | ||
191 | .xlate = irq_domain_xlate_onetwocell, | ||
192 | }; | ||
193 | |||
194 | static int __init avic_of_init(struct device_node *node, | ||
195 | struct device_node *parent) | ||
196 | { | ||
197 | void __iomem *regs; | ||
198 | struct aspeed_vic *vic; | ||
199 | |||
200 | if (WARN(parent, "non-root Aspeed VIC not supported")) | ||
201 | return -EINVAL; | ||
202 | if (WARN(system_avic, "duplicate Aspeed VIC not supported")) | ||
203 | return -EINVAL; | ||
204 | |||
205 | regs = of_iomap(node, 0); | ||
206 | if (WARN_ON(!regs)) | ||
207 | return -EIO; | ||
208 | |||
209 | vic = kzalloc(sizeof(struct aspeed_vic), GFP_KERNEL); | ||
210 | if (WARN_ON(!vic)) { | ||
211 | iounmap(regs); | ||
212 | return -ENOMEM; | ||
213 | } | ||
214 | vic->base = regs; | ||
215 | |||
216 | /* Initialize soures, all masked */ | ||
217 | vic_init_hw(vic); | ||
218 | |||
219 | /* Ready to receive interrupts */ | ||
220 | system_avic = vic; | ||
221 | set_handle_irq(avic_handle_irq); | ||
222 | |||
223 | /* Register our domain */ | ||
224 | vic->dom = irq_domain_add_simple(node, NUM_IRQS, 0, | ||
225 | &avic_dom_ops, vic); | ||
226 | |||
227 | return 0; | ||
228 | } | ||
229 | |||
230 | IRQCHIP_DECLARE(aspeed_new_vic, "aspeed,ast2400-vic", avic_of_init); | ||