Merge tag 'pci-v4.19-fixes-3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Bjorn writes:
  "PCI fixes for v4.19:

   - Reprogram bridge prefetch registers to fix NVIDIA and Radeon issues
     after suspend/resume (Daniel Drake)

   - Fix mvebu I/O mapping creation sequence (Thomas Petazzoni)

   - Fix minor MAINTAINERS file match issue (Bjorn Helgaas)"

* tag 'pci-v4.19-fixes-3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: mvebu: Fix PCI I/O mapping creation sequence
  MAINTAINERS: Remove obsolete drivers/pci pattern from ACPI section
  PCI: Reprogram bridge prefetch registers on resume

3 files changed, 67 insertions, 13 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index e2d974963359..48a65c3a4189 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -324,7 +324,6 @@ F:	Documentation/ABI/testing/sysfs-bus-acpi
 F:      Documentation/ABI/testing/configfs-acpi
 F:      drivers/pci/*acpi*
 F:      drivers/pci/*/*acpi*
-F:      drivers/pci/*/*/*acpi*
 F:      tools/power/acpi/
 
 ACPI APEI
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index 50eb0729385b..a41d79b8d46a 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -1145,7 +1145,6 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
 {
         struct device *dev = &pcie->pdev->dev;
         struct device_node *np = dev->of_node;
-        unsigned int i;
         int ret;
 
         INIT_LIST_HEAD(&pcie->resources);
@@ -1179,13 +1178,58 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
                                          resource_size(&pcie->io) - 1);
                 pcie->realio.name = "PCI I/O";
 
+                pci_add_resource(&pcie->resources, &pcie->realio);
+        }
+
+        return devm_request_pci_bus_resources(dev, &pcie->resources);
+}
+
+/*
+ * This is a copy of pci_host_probe(), except that it does the I/O
+ * remap as the last step, once we are sure we won't fail.
+ *
+ * It should be removed once the I/O remap error handling issue has
+ * been sorted out.
+ */
+static int mvebu_pci_host_probe(struct pci_host_bridge *bridge)
+{
+        struct mvebu_pcie *pcie;
+        struct pci_bus *bus, *child;
+        int ret;
+
+        ret = pci_scan_root_bus_bridge(bridge);
+        if (ret < 0) {
+                dev_err(bridge->dev.parent, "Scanning root bridge failed");
+                return ret;
+        }
+
+        pcie = pci_host_bridge_priv(bridge);
+        if (resource_size(&pcie->io) != 0) {
+                unsigned int i;
+
                 for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K)
                         pci_ioremap_io(i, pcie->io.start + i);
+        }
 
-                pci_add_resource(&pcie->resources, &pcie->realio);
+        bus = bridge->bus;
+
+        /*
+         * We insert PCI resources into the iomem_resource and
+         * ioport_resource trees in either pci_bus_claim_resources()
+         * or pci_bus_assign_resources().
+         */
+        if (pci_has_flag(PCI_PROBE_ONLY)) {
+                pci_bus_claim_resources(bus);
+        } else {
+                pci_bus_size_bridges(bus);
+                pci_bus_assign_resources(bus);
+
+                list_for_each_entry(child, &bus->children, node)
+                        pcie_bus_configure_settings(child);
         }
 
-        return devm_request_pci_bus_resources(dev, &pcie->resources);
+        pci_bus_add_devices(bus);
+        return 0;
 }
 
 static int mvebu_pcie_probe(struct platform_device *pdev)
@@ -1268,7 +1312,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
         bridge->align_resource = mvebu_pcie_align_resource;
         bridge->msi = pcie->msi;
 
-        return pci_host_probe(bridge);
+        return mvebu_pci_host_probe(bridge);
 }
 
 static const struct of_device_id mvebu_pcie_of_match_table[] = {
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 1835f3a7aa8d..51b6c81671c1 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1289,12 +1289,12 @@ int pci_save_state(struct pci_dev *dev)
 EXPORT_SYMBOL(pci_save_state);
 
 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
-                                     u32 saved_val, int retry)
+                                     u32 saved_val, int retry, bool force)
 {
         u32 val;
 
         pci_read_config_dword(pdev, offset, &val);
-        if (val == saved_val)
+        if (!force && val == saved_val)
                 return;
 
         for (;;) {
@@ -1313,25 +1313,36 @@ static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
 }
 
 static void pci_restore_config_space_range(struct pci_dev *pdev,
-                                           int start, int end, int retry)
+                                           int start, int end, int retry,
+                                           bool force)
 {
         int index;
 
         for (index = end; index >= start; index--)
                 pci_restore_config_dword(pdev, 4 * index,
                                          pdev->saved_config_space[index],
-                                         retry);
+                                         retry, force);
 }
 
 static void pci_restore_config_space(struct pci_dev *pdev)
 {
         if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
-                pci_restore_config_space_range(pdev, 10, 15, 0);
+                pci_restore_config_space_range(pdev, 10, 15, 0, false);
                 /* Restore BARs before the command register. */
-                pci_restore_config_space_range(pdev, 4, 9, 10);
-                pci_restore_config_space_range(pdev, 0, 3, 0);
+                pci_restore_config_space_range(pdev, 4, 9, 10, false);
+                pci_restore_config_space_range(pdev, 0, 3, 0, false);
+        } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
+                pci_restore_config_space_range(pdev, 12, 15, 0, false);
+
+                /*
+                 * Force rewriting of prefetch registers to avoid S3 resume
+                 * issues on Intel PCI bridges that occur when these
+                 * registers are not explicitly written.
+                 */
+                pci_restore_config_space_range(pdev, 9, 11, 0, true);
+                pci_restore_config_space_range(pdev, 0, 8, 0, false);
         } else {
-                pci_restore_config_space_range(pdev, 0, 15, 0);
+                pci_restore_config_space_range(pdev, 0, 15, 0, false);
         }
 }