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authorSohil Mehta <sohil.mehta@intel.com>2017-12-20 14:59:25 -0500
committerJoerg Roedel <jroedel@suse.de>2018-01-17 09:02:50 -0500
commit59103caa6839592788e7ad58b35863aac034631a (patch)
treeb645989c4381eb78047b628f04be37a602c08538
parent5e3b4a15dd8da6bded2092694c8db3b505cbf711 (diff)
iommu/vt-d: Add a check for 1GB page support
Add a check to verify IOMMU 1GB page support. If the CPU supports 1GB pages but the IOMMU does not support it then disable SVM by not allocating PASID tables. Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
-rw-r--r--drivers/iommu/intel-svm.c4
-rw-r--r--include/linux/intel-iommu.h1
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index 6643277e321e..e9a56ad09a76 100644
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -41,6 +41,10 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
41 struct page *pages; 41 struct page *pages;
42 int order; 42 int order;
43 43
44 if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
45 !cap_fl1gp_support(iommu->cap))
46 return -EINVAL;
47
44 /* Start at 2 because it's defined as 2^(1+PSS) */ 48 /* Start at 2 because it's defined as 2^(1+PSS) */
45 iommu->pasid_max = 2 << ecap_pss(iommu->ecap); 49 iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
46 50
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index f3274d9f46a2..a56bab114f39 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -84,6 +84,7 @@
84 * Decoding Capability Register 84 * Decoding Capability Register
85 */ 85 */
86#define cap_pi_support(c) (((c) >> 59) & 1) 86#define cap_pi_support(c) (((c) >> 59) & 1)
87#define cap_fl1gp_support(c) (((c) >> 56) & 1)
87#define cap_read_drain(c) (((c) >> 55) & 1) 88#define cap_read_drain(c) (((c) >> 55) & 1)
88#define cap_write_drain(c) (((c) >> 54) & 1) 89#define cap_write_drain(c) (((c) >> 54) & 1)
89#define cap_max_amask_val(c) (((c) >> 48) & 0x3f) 90#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)