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authorArnd Bergmann <arnd@arndb.de>2015-05-15 05:24:22 -0400
committerKevin Hilman <khilman@linaro.org>2015-06-24 20:30:39 -0400
commit58c179674329b4d03a9d22df55d95cb0a8da5d85 (patch)
tree6aeb4bff2efa7eac9bd6c9594ed0d6e503e4164a
parent1647e3c73ce54fc32536bb3a834eccad39b23572 (diff)
ARM: hisi: revert changes from hisi/hip04-dt branch
This backs out all changes that were added in the hip04-dt branch after various boot problems were discovered in UEFI booting. Reported-by: Tyler Baker <tyler.baker@linaro.org> Cc: Wei Xu <xuwei5@hisilicon.com> [khilman: minor changelog updates] Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Kevin Hilman <khilman@linaro.org>
-rw-r--r--arch/arm/boot/dts/hip04-d01.dts27
-rw-r--r--arch/arm/boot/dts/hip04.dtsi133
2 files changed, 0 insertions, 160 deletions
diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts
index ba04dd5fba8b..40a9e33c2654 100644
--- a/arch/arm/boot/dts/hip04-d01.dts
+++ b/arch/arm/boot/dts/hip04-d01.dts
@@ -28,32 +28,5 @@
28 uart0: uart@4007000 { 28 uart0: uart@4007000 {
29 status = "ok"; 29 status = "ok";
30 }; 30 };
31
32 nand: nand@4020000 {
33 nand-bus-width = <8>;
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
37
38 partition@0 {
39 label = "nand_text";
40 reg = <0x00000000 0x00400000>;
41 };
42
43 partition@00400000 {
44 label = "nand_monitor";
45 reg = <0x00400000 0x00400000>;
46 };
47
48 partition@00800000 {
49 label = "nand_kernel";
50 reg = <0x00800000 0x00800000>;
51 };
52
53 partition@01000000 {
54 label = "nand_fs";
55 reg = <0x01000000 0x1f000000>;
56 };
57 };
58 }; 31 };
59}; 32};
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 6434b7f91329..44044f275115 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -269,139 +269,6 @@
269 interrupts = <0 372 4>; 269 interrupts = <0 372 4>;
270 }; 270 };
271 271
272 gpio@4003000 {
273 #address-cells = <1>;
274 #size-cells = <0>;
275 compatible = "snps,dw-apb-gpio";
276 reg = <0x4003000 0x1000>;
277
278 gpio3: gpio-controller@0 {
279 compatible = "snps,dw-apb-gpio-port";
280 gpio-controller;
281 #gpio-cells = <2>;
282 snps,nr-gpios = <32>;
283 reg = <0>;
284 interrupt-parent = <&gic>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
287 interrupts = <0 392 4>;
288 };
289 };
290
291 gpio@4002000 {
292 #address-cells = <1>;
293 #size-cells = <0>;
294 compatible = "snps,dw-apb-gpio";
295 reg = <0x4002000 0x1000>;
296
297 gpio2: gpio-controller@0 {
298 compatible = "snps,dw-apb-gpio-port";
299 gpio-controller;
300 #gpio-cells = <2>;
301 snps,nr-gpios = <32>;
302 reg = <0>;
303 interrupt-parent = <&gic>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 interrupts = <0 391 4>;
307 };
308 };
309
310 gpio@4001000 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 compatible = "snps,dw-apb-gpio";
314 reg = <0x4001000 0x1000>;
315
316 gpio1: gpio-controller@0 {
317 compatible = "snps,dw-apb-gpio-port";
318 gpio-controller;
319 #gpio-cells = <2>;
320 snps,nr-gpios = <32>;
321 reg = <0>;
322 interrupt-parent = <&gic>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 interrupts = <0 390 4>;
326 };
327 };
328
329 gpio@4000000 {
330 #address-cells = <1>;
331 #size-cells = <0>;
332 compatible = "snps,dw-apb-gpio";
333 reg = <0x4000000 0x1000>;
334
335 gpio0: gpio-controller@0 {
336 compatible = "snps,dw-apb-gpio-port";
337 gpio-controller;
338 #gpio-cells = <2>;
339 snps,nr-gpios = <32>;
340 reg = <0>;
341 interrupt-parent = <&gic>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 interrupts = <0 389 4>;
345 };
346 };
347
348 nand: nand@4020000 {
349 compatible = "hisilicon,504-nfc";
350 reg = <0x4020000 0x10000>, <0x5000000 0x1000>;
351 interrupts = <0 379 4>;
352 #address-cells = <1>;
353 #size-cells = <1>;
354 };
355
356 mdio {
357 compatible = "hisilicon,hip04-mdio";
358 reg = <0x28f1000 0x1000>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361
362 phy0: ethernet-phy@0 {
363 compatible = "ethernet-phy-ieee802.3-c22";
364 reg = <0>;
365 marvell,reg-init = <18 0x14 0 0x8001>;
366 };
367
368 phy1: ethernet-phy@1 {
369 compatible = "ethernet-phy-ieee802.3-c22";
370 reg = <1>;
371 marvell,reg-init = <18 0x14 0 0x8001>;
372 };
373 };
374
375 ppe: ppe@28c0000 {
376 compatible = "hisilicon,hip04-ppe", "syscon";
377 reg = <0x28c0000 0x10000>;
378 };
379
380 fe: ethernet@28b0000 {
381 compatible = "hisilicon,hip04-mac";
382 reg = <0x28b0000 0x10000>;
383 interrupts = <0 413 4>;
384 phy-mode = "mii";
385 port-handle = <&ppe 31 0>;
386 };
387
388 ge0: ethernet@2800000 {
389 compatible = "hisilicon,hip04-mac";
390 reg = <0x2800000 0x10000>;
391 interrupts = <0 402 4>;
392 phy-mode = "sgmii";
393 port-handle = <&ppe 0 1>;
394 phy-handle = <&phy0>;
395 };
396
397 ge8: ethernet@2880000 {
398 compatible = "hisilicon,hip04-mac";
399 reg = <0x2880000 0x10000>;
400 interrupts = <0 410 4>;
401 phy-mode = "sgmii";
402 port-handle = <&ppe 8 2>;
403 phy-handle = <&phy1>;
404 };
405 }; 272 };
406 273
407 etb@0,e3c42000 { 274 etb@0,e3c42000 {