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authorOlof Johansson <olof@lixom.net>2015-01-12 17:32:47 -0500
committerOlof Johansson <olof@lixom.net>2015-01-12 17:32:47 -0500
commit58bdda1b571ffeab50874ca851d7473b3d10d03c (patch)
tree484be483fa78ccb7a77fc145421a5ec05cd02114
parenteaa27f34e91a14cdceed26ed6c6793ec1d186115 (diff)
parent09bd745b555c262d1e2c851777317f3adf3cf3d4 (diff)
Merge tag 'renesas-sh73a0-ccf-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Merge "Renesas ARM Based SoC sh73a0 CCF Updates for v3.20" from Simon Horman: * Add sh73a0 CCF support * tag 'renesas-sh73a0-ccf-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: sh73a0: disable legacy clock initialization ARM: shmobile: sh73a0: add MSTP clock assignments to DT ARM: shmobile: kzm9g-reference: Common clock framework DT description ARM: shmobile: sh73a0: Common clock framework DT description ARM: shmobile: sh73a0: Add CPG register bits header clk: shmobile: sh73a0 common clock framework implementation Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt35
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts4
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi358
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c5
-rw-r--r--drivers/clk/shmobile/Makefile1
-rw-r--r--drivers/clk/shmobile/clk-sh73a0.c218
-rw-r--r--include/dt-bindings/clock/sh73a0-clock.h79
7 files changed, 699 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt
new file mode 100644
index 000000000000..a8978ec94831
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt
@@ -0,0 +1,35 @@
1These bindings should be considered EXPERIMENTAL for now.
2
3* Renesas SH73A0 Clock Pulse Generator (CPG)
4
5The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
6and several fixed ratio dividers.
7
8Required Properties:
9
10 - compatible: Must be "renesas,sh73a0-cpg-clocks"
11
12 - reg: Base address and length of the memory resource used by the CPG
13
14 - clocks: Reference to the parent clocks ("extal1" and "extal2")
15
16 - #clock-cells: Must be 1
17
18 - clock-output-names: The names of the clocks. Supported clocks are "main",
19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
20 "m1", "m2", "z", "zx", and "hp".
21
22
23Example
24-------
25
26 cpg_clocks: cpg_clocks@e6150000 {
27 compatible = "renesas,sh73a0-cpg-clocks";
28 reg = <0 0xe6150000 0 0x10000>;
29 clocks = <&extal1_clk>, <&extal2_clk>;
30 #clock-cells = <1>;
31 clock-output-names = "main", "pll0", "pll1", "pll2",
32 "pll3", "dsi0phy", "dsi1phy",
33 "zg", "m3", "b", "m1", "m2",
34 "z", "zx", "hp";
35 };
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 939be1299ca6..3d912ea8fef4 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -182,6 +182,10 @@
182 status = "ok"; 182 status = "ok";
183}; 183};
184 184
185&extal2_clk {
186 clock-frequency = <48000000>;
187};
188
185&i2c0 { 189&i2c0 {
186 status = "okay"; 190 status = "okay";
187 as3711@40 { 191 as3711@40 {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index d8def5a529da..cca22ec59a2e 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -10,6 +10,7 @@
10 10
11/include/ "skeleton.dtsi" 11/include/ "skeleton.dtsi"
12 12
13#include <dt-bindings/clock/sh73a0-clock.h>
13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
14 15
15/ { 16/ {
@@ -55,6 +56,8 @@
55 56
56 renesas,channels-mask = <0x3f>; 57 renesas,channels-mask = <0x3f>;
57 58
59 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
60 clock-names = "fck";
58 status = "disabled"; 61 status = "disabled";
59 }; 62 };
60 63
@@ -144,6 +147,7 @@
144 0 168 IRQ_TYPE_LEVEL_HIGH 147 0 168 IRQ_TYPE_LEVEL_HIGH
145 0 169 IRQ_TYPE_LEVEL_HIGH 148 0 169 IRQ_TYPE_LEVEL_HIGH
146 0 170 IRQ_TYPE_LEVEL_HIGH>; 149 0 170 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
147 status = "disabled"; 151 status = "disabled";
148 }; 152 };
149 153
@@ -156,6 +160,7 @@
156 0 52 IRQ_TYPE_LEVEL_HIGH 160 0 52 IRQ_TYPE_LEVEL_HIGH
157 0 53 IRQ_TYPE_LEVEL_HIGH 161 0 53 IRQ_TYPE_LEVEL_HIGH
158 0 54 IRQ_TYPE_LEVEL_HIGH>; 162 0 54 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
159 status = "disabled"; 164 status = "disabled";
160 }; 165 };
161 166
@@ -168,6 +173,7 @@
168 0 172 IRQ_TYPE_LEVEL_HIGH 173 0 172 IRQ_TYPE_LEVEL_HIGH
169 0 173 IRQ_TYPE_LEVEL_HIGH 174 0 173 IRQ_TYPE_LEVEL_HIGH
170 0 174 IRQ_TYPE_LEVEL_HIGH>; 175 0 174 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
171 status = "disabled"; 177 status = "disabled";
172 }; 178 };
173 179
@@ -180,6 +186,7 @@
180 0 184 IRQ_TYPE_LEVEL_HIGH 186 0 184 IRQ_TYPE_LEVEL_HIGH
181 0 185 IRQ_TYPE_LEVEL_HIGH 187 0 185 IRQ_TYPE_LEVEL_HIGH
182 0 186 IRQ_TYPE_LEVEL_HIGH>; 188 0 186 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
183 status = "disabled"; 190 status = "disabled";
184 }; 191 };
185 192
@@ -192,6 +199,7 @@
192 0 188 IRQ_TYPE_LEVEL_HIGH 199 0 188 IRQ_TYPE_LEVEL_HIGH
193 0 189 IRQ_TYPE_LEVEL_HIGH 200 0 189 IRQ_TYPE_LEVEL_HIGH
194 0 190 IRQ_TYPE_LEVEL_HIGH>; 201 0 190 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
195 status = "disabled"; 203 status = "disabled";
196 }; 204 };
197 205
@@ -200,6 +208,7 @@
200 reg = <0xe6bd0000 0x100>; 208 reg = <0xe6bd0000 0x100>;
201 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 209 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
202 0 141 IRQ_TYPE_LEVEL_HIGH>; 210 0 141 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
203 reg-io-width = <4>; 212 reg-io-width = <4>;
204 status = "disabled"; 213 status = "disabled";
205 }; 214 };
@@ -210,6 +219,7 @@
210 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH 219 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
211 0 84 IRQ_TYPE_LEVEL_HIGH 220 0 84 IRQ_TYPE_LEVEL_HIGH
212 0 85 IRQ_TYPE_LEVEL_HIGH>; 221 0 85 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
213 cap-sd-highspeed; 223 cap-sd-highspeed;
214 status = "disabled"; 224 status = "disabled";
215 }; 225 };
@@ -220,6 +230,7 @@
220 reg = <0xee120000 0x100>; 230 reg = <0xee120000 0x100>;
221 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 231 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
222 0 89 IRQ_TYPE_LEVEL_HIGH>; 232 0 89 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
223 toshiba,mmc-wrprotect-disable; 234 toshiba,mmc-wrprotect-disable;
224 cap-sd-highspeed; 235 cap-sd-highspeed;
225 status = "disabled"; 236 status = "disabled";
@@ -230,6 +241,7 @@
230 reg = <0xee140000 0x100>; 241 reg = <0xee140000 0x100>;
231 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 242 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
232 0 105 IRQ_TYPE_LEVEL_HIGH>; 243 0 105 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
233 toshiba,mmc-wrprotect-disable; 245 toshiba,mmc-wrprotect-disable;
234 cap-sd-highspeed; 246 cap-sd-highspeed;
235 status = "disabled"; 247 status = "disabled";
@@ -239,6 +251,8 @@
239 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 251 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
240 reg = <0xe6c40000 0x100>; 252 reg = <0xe6c40000 0x100>;
241 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 253 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
255 clock-names = "sci_ick";
242 status = "disabled"; 256 status = "disabled";
243 }; 257 };
244 258
@@ -246,6 +260,8 @@
246 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 260 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
247 reg = <0xe6c50000 0x100>; 261 reg = <0xe6c50000 0x100>;
248 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
264 clock-names = "sci_ick";
249 status = "disabled"; 265 status = "disabled";
250 }; 266 };
251 267
@@ -253,6 +269,8 @@
253 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 269 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
254 reg = <0xe6c60000 0x100>; 270 reg = <0xe6c60000 0x100>;
255 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 271 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
273 clock-names = "sci_ick";
256 status = "disabled"; 274 status = "disabled";
257 }; 275 };
258 276
@@ -260,6 +278,8 @@
260 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 278 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
261 reg = <0xe6c70000 0x100>; 279 reg = <0xe6c70000 0x100>;
262 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 280 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
282 clock-names = "sci_ick";
263 status = "disabled"; 283 status = "disabled";
264 }; 284 };
265 285
@@ -267,6 +287,8 @@
267 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 287 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
268 reg = <0xe6c80000 0x100>; 288 reg = <0xe6c80000 0x100>;
269 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 289 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
291 clock-names = "sci_ick";
270 status = "disabled"; 292 status = "disabled";
271 }; 293 };
272 294
@@ -274,6 +296,8 @@
274 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 296 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
275 reg = <0xe6cb0000 0x100>; 297 reg = <0xe6cb0000 0x100>;
276 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 298 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
300 clock-names = "sci_ick";
277 status = "disabled"; 301 status = "disabled";
278 }; 302 };
279 303
@@ -281,6 +305,8 @@
281 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 305 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
282 reg = <0xe6cc0000 0x100>; 306 reg = <0xe6cc0000 0x100>;
283 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
309 clock-names = "sci_ick";
284 status = "disabled"; 310 status = "disabled";
285 }; 311 };
286 312
@@ -288,6 +314,8 @@
288 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 314 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
289 reg = <0xe6cd0000 0x100>; 315 reg = <0xe6cd0000 0x100>;
290 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 316 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
318 clock-names = "sci_ick";
291 status = "disabled"; 319 status = "disabled";
292 }; 320 };
293 321
@@ -295,6 +323,8 @@
295 compatible = "renesas,scifb-sh73a0", "renesas,scifb"; 323 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
296 reg = <0xe6c30000 0x100>; 324 reg = <0xe6c30000 0x100>;
297 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 325 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
327 clock-names = "sci_ick";
298 status = "disabled"; 328 status = "disabled";
299 }; 329 };
300 330
@@ -322,4 +352,332 @@
322 interrupts = <0 146 0x4>; 352 interrupts = <0 146 0x4>;
323 status = "disabled"; 353 status = "disabled";
324 }; 354 };
355
356 clocks {
357 #address-cells = <1>;
358 #size-cells = <1>;
359 ranges;
360
361 /* External root clocks */
362 extalr_clk: extalr_clk {
363 compatible = "fixed-clock";
364 #clock-cells = <0>;
365 clock-frequency = <32768>;
366 clock-output-names = "extalr";
367 };
368 extal1_clk: extal1_clk {
369 compatible = "fixed-clock";
370 #clock-cells = <0>;
371 clock-frequency = <26000000>;
372 clock-output-names = "extal1";
373 };
374 extal2_clk: extal2_clk {
375 compatible = "fixed-clock";
376 #clock-cells = <0>;
377 clock-output-names = "extal2";
378 };
379 extcki_clk: extcki_clk {
380 compatible = "fixed-clock";
381 #clock-cells = <0>;
382 clock-output-names = "extcki";
383 };
384 fsiack_clk: fsiack_clk {
385 compatible = "fixed-clock";
386 #clock-cells = <0>;
387 clock-frequency = <0>;
388 clock-output-names = "fsiack";
389 };
390 fsibck_clk: fsibck_clk {
391 compatible = "fixed-clock";
392 #clock-cells = <0>;
393 clock-frequency = <0>;
394 clock-output-names = "fsibck";
395 };
396
397 /* Special CPG clocks */
398 cpg_clocks: cpg_clocks@e6150000 {
399 compatible = "renesas,sh73a0-cpg-clocks";
400 reg = <0xe6150000 0x10000>;
401 clocks = <&extal1_clk>, <&extal2_clk>;
402 #clock-cells = <1>;
403 clock-output-names = "main", "pll0", "pll1", "pll2",
404 "pll3", "dsi0phy", "dsi1phy",
405 "zg", "m3", "b", "m1", "m2",
406 "z", "zx", "hp";
407 };
408
409 /* Variable factor clocks (DIV6) */
410 vclk1_clk: vclk1_clk@e6150008 {
411 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
412 reg = <0xe6150008 4>;
413 clocks = <&pll1_div2_clk>;
414 #clock-cells = <0>;
415 clock-output-names = "vclk1";
416 };
417 vclk2_clk: vclk2_clk@e615000c {
418 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
419 reg = <0xe615000c 4>;
420 clocks = <&pll1_div2_clk>;
421 #clock-cells = <0>;
422 clock-output-names = "vclk2";
423 };
424 vclk3_clk: vclk3_clk@e615001c {
425 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
426 reg = <0xe615001c 4>;
427 clocks = <&pll1_div2_clk>;
428 #clock-cells = <0>;
429 clock-output-names = "vclk3";
430 };
431 zb_clk: zb_clk@e6150010 {
432 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
433 reg = <0xe6150010 4>;
434 clocks = <&pll1_div2_clk>;
435 #clock-cells = <0>;
436 clock-output-names = "zb";
437 };
438 flctl_clk: flctl_clk@e6150014 {
439 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
440 reg = <0xe6150014 4>;
441 clocks = <&pll1_div2_clk>;
442 #clock-cells = <0>;
443 clock-output-names = "flctlck";
444 };
445 sdhi0_clk: sdhi0_clk@e6150074 {
446 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
447 reg = <0xe6150074 4>;
448 clocks = <&pll1_div2_clk>;
449 #clock-cells = <0>;
450 clock-output-names = "sdhi0ck";
451 };
452 sdhi1_clk: sdhi1_clk@e6150078 {
453 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
454 reg = <0xe6150078 4>;
455 clocks = <&pll1_div2_clk>;
456 #clock-cells = <0>;
457 clock-output-names = "sdhi1ck";
458 };
459 sdhi2_clk: sdhi2_clk@e615007c {
460 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
461 reg = <0xe615007c 4>;
462 clocks = <&pll1_div2_clk>;
463 #clock-cells = <0>;
464 clock-output-names = "sdhi2ck";
465 };
466 fsia_clk: fsia_clk@e6150018 {
467 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
468 reg = <0xe6150018 4>;
469 clocks = <&pll1_div2_clk>;
470 #clock-cells = <0>;
471 clock-output-names = "fsia";
472 };
473 fsib_clk: fsib_clk@e6150090 {
474 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
475 reg = <0xe6150090 4>;
476 clocks = <&pll1_div2_clk>;
477 #clock-cells = <0>;
478 clock-output-names = "fsib";
479 };
480 sub_clk: sub_clk@e6150080 {
481 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
482 reg = <0xe6150080 4>;
483 clocks = <&extal2_clk>;
484 #clock-cells = <0>;
485 clock-output-names = "sub";
486 };
487 spua_clk: spua_clk@e6150084 {
488 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
489 reg = <0xe6150084 4>;
490 clocks = <&pll1_div2_clk>;
491 #clock-cells = <0>;
492 clock-output-names = "spua";
493 };
494 spuv_clk: spuv_clk@e6150094 {
495 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
496 reg = <0xe6150094 4>;
497 clocks = <&pll1_div2_clk>;
498 #clock-cells = <0>;
499 clock-output-names = "spuv";
500 };
501 msu_clk: msu_clk@e6150088 {
502 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
503 reg = <0xe6150088 4>;
504 clocks = <&pll1_div2_clk>;
505 #clock-cells = <0>;
506 clock-output-names = "msu";
507 };
508 hsi_clk: hsi_clk@e615008c {
509 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
510 reg = <0xe615008c 4>;
511 clocks = <&pll1_div2_clk>;
512 #clock-cells = <0>;
513 clock-output-names = "hsi";
514 };
515 mfg1_clk: mfg1_clk@e6150098 {
516 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
517 reg = <0xe6150098 4>;
518 clocks = <&pll1_div2_clk>;
519 #clock-cells = <0>;
520 clock-output-names = "mfg1";
521 };
522 mfg2_clk: mfg2_clk@e615009c {
523 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
524 reg = <0xe615009c 4>;
525 clocks = <&pll1_div2_clk>;
526 #clock-cells = <0>;
527 clock-output-names = "mfg2";
528 };
529 dsit_clk: dsit_clk@e6150060 {
530 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
531 reg = <0xe6150060 4>;
532 clocks = <&pll1_div2_clk>;
533 #clock-cells = <0>;
534 clock-output-names = "dsit";
535 };
536 dsi0p_clk: dsi0p_clk@e6150064 {
537 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
538 reg = <0xe6150064 4>;
539 clocks = <&pll1_div2_clk>;
540 #clock-cells = <0>;
541 clock-output-names = "dsi0pck";
542 };
543
544 /* Fixed factor clocks */
545 main_div2_clk: main_div2_clk {
546 compatible = "fixed-factor-clock";
547 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
548 #clock-cells = <0>;
549 clock-div = <2>;
550 clock-mult = <1>;
551 clock-output-names = "main_div2";
552 };
553 pll1_div2_clk: pll1_div2_clk {
554 compatible = "fixed-factor-clock";
555 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
556 #clock-cells = <0>;
557 clock-div = <2>;
558 clock-mult = <1>;
559 clock-output-names = "pll1_div2";
560 };
561 pll1_div7_clk: pll1_div7_clk {
562 compatible = "fixed-factor-clock";
563 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
564 #clock-cells = <0>;
565 clock-div = <7>;
566 clock-mult = <1>;
567 clock-output-names = "pll1_div7";
568 };
569 pll1_div13_clk: pll1_div13_clk {
570 compatible = "fixed-factor-clock";
571 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
572 #clock-cells = <0>;
573 clock-div = <13>;
574 clock-mult = <1>;
575 clock-output-names = "pll1_div13";
576 };
577 twd_clk: twd_clk {
578 compatible = "fixed-factor-clock";
579 clocks = <&cpg_clocks SH73A0_CLK_Z>;
580 #clock-cells = <0>;
581 clock-div = <4>;
582 clock-mult = <1>;
583 clock-output-names = "twd";
584 };
585
586 /* Gate clocks */
587 mstp0_clks: mstp0_clks@e6150130 {
588 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
589 reg = <0xe6150130 4>, <0xe6150030 4>;
590 clocks = <&cpg_clocks SH73A0_CLK_HP>;
591 #clock-cells = <1>;
592 clock-indices = <
593 SH73A0_CLK_IIC2
594 >;
595 clock-output-names =
596 "iic2";
597 };
598 mstp1_clks: mstp1_clks@e6150134 {
599 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
600 reg = <0xe6150134 4>, <0xe6150038 4>;
601 clocks = <&cpg_clocks SH73A0_CLK_B>,
602 <&cpg_clocks SH73A0_CLK_B>,
603 <&cpg_clocks SH73A0_CLK_B>,
604 <&cpg_clocks SH73A0_CLK_B>,
605 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
606 <&cpg_clocks SH73A0_CLK_HP>,
607 <&cpg_clocks SH73A0_CLK_ZG>,
608 <&cpg_clocks SH73A0_CLK_B>;
609 #clock-cells = <1>;
610 clock-indices = <
611 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
612 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
613 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
614 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
615 SH73A0_CLK_LCDC0
616 >;
617 clock-output-names =
618 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
619 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
620 };
621 mstp2_clks: mstp2_clks@e6150138 {
622 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
623 reg = <0xe6150138 4>, <0xe6150040 4>;
624 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
625 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
626 <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
627 <&sub_clk>, <&sub_clk>;
628 #clock-cells = <1>;
629 clock-indices = <
630 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
631 SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
632 SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
633 SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
634 SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
635 >;
636 clock-output-names =
637 "scifa7", "sy_dmac", "mp_dmac", "scifa5",
638 "scifb", "scifa0", "scifa1", "scifa2",
639 "scifa3", "scifa4";
640 };
641 mstp3_clks: mstp3_clks@e615013c {
642 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
643 reg = <0xe615013c 4>, <0xe6150048 4>;
644 clocks = <&sub_clk>, <&extalr_clk>,
645 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
646 <&cpg_clocks SH73A0_CLK_HP>,
647 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
648 <&sdhi0_clk>, <&sdhi1_clk>,
649 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
650 <&main_div2_clk>, <&main_div2_clk>,
651 <&main_div2_clk>, <&main_div2_clk>,
652 <&main_div2_clk>;
653 #clock-cells = <1>;
654 clock-indices = <
655 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
656 SH73A0_CLK_FSI SH73A0_CLK_IRDA
657 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
658 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
659 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
660 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
661 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
662 SH73A0_CLK_TPU4
663 >;
664 clock-output-names =
665 "scifa6", "cmt1", "fsi", "irda", "iic1",
666 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
667 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
668 };
669 mstp4_clks: mstp4_clks@e6150140 {
670 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
671 reg = <0xe6150140 4>, <0xe615004c 4>;
672 clocks = <&cpg_clocks SH73A0_CLK_HP>,
673 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
674 #clock-cells = <1>;
675 clock-indices = <
676 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
677 SH73A0_CLK_KEYSC
678 >;
679 clock-output-names =
680 "iic3", "iic4", "keysc";
681 };
682 };
325}; 683};
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 93ebe3430bfe..354cab111bf1 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -763,7 +763,9 @@ void __init __weak sh73a0_register_twd(void) { }
763void __init sh73a0_earlytimer_init(void) 763void __init sh73a0_earlytimer_init(void)
764{ 764{
765 shmobile_init_delay(); 765 shmobile_init_delay();
766#ifndef CONFIG_COMMON_CLK
766 sh73a0_clock_init(); 767 sh73a0_clock_init();
768#endif
767 shmobile_earlytimer_init(); 769 shmobile_earlytimer_init();
768 sh73a0_register_twd(); 770 sh73a0_register_twd();
769} 771}
@@ -782,8 +784,9 @@ void __init sh73a0_add_early_devices(void)
782void __init sh73a0_add_standard_devices_dt(void) 784void __init sh73a0_add_standard_devices_dt(void)
783{ 785{
784 /* clocks are setup late during boot in the case of DT */ 786 /* clocks are setup late during boot in the case of DT */
787#ifndef CONFIG_COMMON_CLK
785 sh73a0_clock_init(); 788 sh73a0_clock_init();
786 789#endif
787 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 790 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
788} 791}
789 792
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 960bf22d42ae..f83980f2b956 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -5,5 +5,6 @@ obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
5obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o 5obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
6obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o 6obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
7obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o 7obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o
8obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o
8obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o 9obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o
9obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o 10obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o
diff --git a/drivers/clk/shmobile/clk-sh73a0.c b/drivers/clk/shmobile/clk-sh73a0.c
new file mode 100644
index 000000000000..8574a6d91b20
--- /dev/null
+++ b/drivers/clk/shmobile/clk-sh73a0.c
@@ -0,0 +1,218 @@
1/*
2 * sh73a0 Core CPG Clocks
3 *
4 * Copyright (C) 2014 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/shmobile.h>
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/spinlock.h>
19
20struct sh73a0_cpg {
21 struct clk_onecell_data data;
22 spinlock_t lock;
23 void __iomem *reg;
24};
25
26#define CPG_FRQCRA 0x00
27#define CPG_FRQCRB 0x04
28#define CPG_SD0CKCR 0x74
29#define CPG_SD1CKCR 0x78
30#define CPG_SD2CKCR 0x7c
31#define CPG_PLLECR 0xd0
32#define CPG_PLL0CR 0xd8
33#define CPG_PLL1CR 0x28
34#define CPG_PLL2CR 0x2c
35#define CPG_PLL3CR 0xdc
36#define CPG_CKSCR 0xc0
37#define CPG_DSI0PHYCR 0x6c
38#define CPG_DSI1PHYCR 0x70
39
40#define CLK_ENABLE_ON_INIT BIT(0)
41
42struct div4_clk {
43 const char *name;
44 const char *parent;
45 unsigned int reg;
46 unsigned int shift;
47};
48
49static struct div4_clk div4_clks[] = {
50 { "zg", "pll0", CPG_FRQCRA, 16 },
51 { "m3", "pll1", CPG_FRQCRA, 12 },
52 { "b", "pll1", CPG_FRQCRA, 8 },
53 { "m1", "pll1", CPG_FRQCRA, 4 },
54 { "m2", "pll1", CPG_FRQCRA, 0 },
55 { "zx", "pll1", CPG_FRQCRB, 12 },
56 { "hp", "pll1", CPG_FRQCRB, 4 },
57 { NULL, 0, 0, 0 },
58};
59
60static const struct clk_div_table div4_div_table[] = {
61 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
62 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
63 { 12, 7 }, { 0, 0 }
64};
65
66static const struct clk_div_table z_div_table[] = {
67 /* ZSEL == 0 */
68 { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },
69 { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 },
70 { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 },
71 /* ZSEL == 1 */
72 { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 },
73 { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }
74};
75
76static struct clk * __init
77sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
78 const char *name)
79{
80 const struct clk_div_table *table = NULL;
81 unsigned int shift, reg, width;
82 const char *parent_name;
83 unsigned int mult = 1;
84 unsigned int div = 1;
85
86 if (!strcmp(name, "main")) {
87 /* extal1, extal1_div2, extal2, extal2_div2 */
88 u32 parent_idx = (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
89
90 parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
91 div = (parent_idx & 1) + 1;
92 } else if (!strncmp(name, "pll", 3)) {
93 void __iomem *enable_reg = cpg->reg;
94 u32 enable_bit = name[3] - '0';
95
96 parent_name = "main";
97 switch (enable_bit) {
98 case 0:
99 enable_reg += CPG_PLL0CR;
100 break;
101 case 1:
102 enable_reg += CPG_PLL1CR;
103 break;
104 case 2:
105 enable_reg += CPG_PLL2CR;
106 break;
107 case 3:
108 enable_reg += CPG_PLL3CR;
109 break;
110 default:
111 return ERR_PTR(-EINVAL);
112 }
113 if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
114 mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1;
115 /* handle CFG bit for PLL1 and PLL2 */
116 if (enable_bit == 1 || enable_bit == 2)
117 if (clk_readl(enable_reg) & BIT(20))
118 mult *= 2;
119 }
120 } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
121 u32 phy_no = name[3] - '0';
122 void __iomem *dsi_reg = cpg->reg +
123 (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
124
125 parent_name = phy_no ? "dsi1pck" : "dsi0pck";
126 mult = __raw_readl(dsi_reg);
127 if (!(mult & 0x8000))
128 mult = 1;
129 else
130 mult = (mult & 0x3f) + 1;
131 } else if (!strcmp(name, "z")) {
132 parent_name = "pll0";
133 table = z_div_table;
134 reg = CPG_FRQCRB;
135 shift = 24;
136 width = 5;
137 } else {
138 struct div4_clk *c;
139
140 for (c = div4_clks; c->name; c++) {
141 if (!strcmp(name, c->name)) {
142 parent_name = c->parent;
143 table = div4_div_table;
144 reg = c->reg;
145 shift = c->shift;
146 width = 4;
147 break;
148 }
149 }
150 if (!c->name)
151 return ERR_PTR(-EINVAL);
152 }
153
154 if (!table) {
155 return clk_register_fixed_factor(NULL, name, parent_name, 0,
156 mult, div);
157 } else {
158 return clk_register_divider_table(NULL, name, parent_name, 0,
159 cpg->reg + reg, shift, width, 0,
160 table, &cpg->lock);
161 }
162}
163
164static void __init sh73a0_cpg_clocks_init(struct device_node *np)
165{
166 struct sh73a0_cpg *cpg;
167 struct clk **clks;
168 unsigned int i;
169 int num_clks;
170
171 num_clks = of_property_count_strings(np, "clock-output-names");
172 if (num_clks < 0) {
173 pr_err("%s: failed to count clocks\n", __func__);
174 return;
175 }
176
177 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
178 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
179 if (cpg == NULL || clks == NULL) {
180 /* We're leaking memory on purpose, there's no point in cleaning
181 * up as the system won't boot anyway.
182 */
183 return;
184 }
185
186 spin_lock_init(&cpg->lock);
187
188 cpg->data.clks = clks;
189 cpg->data.clk_num = num_clks;
190
191 cpg->reg = of_iomap(np, 0);
192 if (WARN_ON(cpg->reg == NULL))
193 return;
194
195 /* Set SDHI clocks to a known state */
196 clk_writel(0x108, cpg->reg + CPG_SD0CKCR);
197 clk_writel(0x108, cpg->reg + CPG_SD1CKCR);
198 clk_writel(0x108, cpg->reg + CPG_SD2CKCR);
199
200 for (i = 0; i < num_clks; ++i) {
201 const char *name;
202 struct clk *clk;
203
204 of_property_read_string_index(np, "clock-output-names", i,
205 &name);
206
207 clk = sh73a0_cpg_register_clock(np, cpg, name);
208 if (IS_ERR(clk))
209 pr_err("%s: failed to register %s %s clock (%ld)\n",
210 __func__, np->name, name, PTR_ERR(clk));
211 else
212 cpg->data.clks[i] = clk;
213 }
214
215 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
216}
217CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",
218 sh73a0_cpg_clocks_init);
diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h
new file mode 100644
index 000000000000..1dd3eb2b7d90
--- /dev/null
+++ b/include/dt-bindings/clock/sh73a0-clock.h
@@ -0,0 +1,79 @@
1/*
2 * Copyright 2014 Ulrich Hecht
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_SH73A0_H__
11#define __DT_BINDINGS_CLOCK_SH73A0_H__
12
13/* CPG */
14#define SH73A0_CLK_MAIN 0
15#define SH73A0_CLK_PLL0 1
16#define SH73A0_CLK_PLL1 2
17#define SH73A0_CLK_PLL2 3
18#define SH73A0_CLK_PLL3 4
19#define SH73A0_CLK_DSI0PHY 5
20#define SH73A0_CLK_DSI1PHY 6
21#define SH73A0_CLK_ZG 7
22#define SH73A0_CLK_M3 8
23#define SH73A0_CLK_B 9
24#define SH73A0_CLK_M1 10
25#define SH73A0_CLK_M2 11
26#define SH73A0_CLK_Z 12
27#define SH73A0_CLK_ZX 13
28#define SH73A0_CLK_HP 14
29
30/* MSTP0 */
31#define SH73A0_CLK_IIC2 1
32
33/* MSTP1 */
34#define SH73A0_CLK_CEU1 29
35#define SH73A0_CLK_CSI2_RX1 28
36#define SH73A0_CLK_CEU0 27
37#define SH73A0_CLK_CSI2_RX0 26
38#define SH73A0_CLK_TMU0 25
39#define SH73A0_CLK_DSITX0 18
40#define SH73A0_CLK_IIC0 16
41#define SH73A0_CLK_SGX 12
42#define SH73A0_CLK_LCDC0 0
43
44/* MSTP2 */
45#define SH73A0_CLK_SCIFA7 19
46#define SH73A0_CLK_SY_DMAC 18
47#define SH73A0_CLK_MP_DMAC 17
48#define SH73A0_CLK_SCIFA5 7
49#define SH73A0_CLK_SCIFB 6
50#define SH73A0_CLK_SCIFA0 4
51#define SH73A0_CLK_SCIFA1 3
52#define SH73A0_CLK_SCIFA2 2
53#define SH73A0_CLK_SCIFA3 1
54#define SH73A0_CLK_SCIFA4 0
55
56/* MSTP3 */
57#define SH73A0_CLK_SCIFA6 31
58#define SH73A0_CLK_CMT1 29
59#define SH73A0_CLK_FSI 28
60#define SH73A0_CLK_IRDA 25
61#define SH73A0_CLK_IIC1 23
62#define SH73A0_CLK_USB 22
63#define SH73A0_CLK_FLCTL 15
64#define SH73A0_CLK_SDHI0 14
65#define SH73A0_CLK_SDHI1 13
66#define SH73A0_CLK_MMCIF0 12
67#define SH73A0_CLK_SDHI2 11
68#define SH73A0_CLK_TPU0 4
69#define SH73A0_CLK_TPU1 3
70#define SH73A0_CLK_TPU2 2
71#define SH73A0_CLK_TPU3 1
72#define SH73A0_CLK_TPU4 0
73
74/* MSTP4 */
75#define SH73A0_CLK_IIC3 11
76#define SH73A0_CLK_IIC4 10
77#define SH73A0_CLK_KEYSC 3
78
79#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 11:04:16 -0400