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authorAndi Kleen <ak@linux.intel.com>2017-11-08 19:07:18 -0500
committerThomas Gleixner <tglx@linutronix.de>2017-11-13 11:03:38 -0500
commit58ba4d5a25579e5c7e312bd359c95f3a9a0a242c (patch)
tree7f684a26e11191d570f1b072138f3cee48ca4423
parent516fb7f2e73dcc303fb97fc3593209fcacf2d982 (diff)
perf/x86/intel: Hide TSX events when RTM is not supported
0day testing reported a perf test regression on Haswell systems without RTM. Commit a5df70c35 hides the in_tx/in_tx_cp attributes when RTM is not available, but the TSX events are still available in sysfs. Due to the missing attributes the event parser fails on those files. Don't show the TSX events in sysfs when RTM is not available on Haswell/Broadwell/Skylake. Fixes: a5df70c354c2 (perf/x86: Only show format attributes when supported) Reported-by: kernel test robot <xiaolong.ye@intel.com> Tested-by: Jin Yao <yao.jin@linux.intel.com> Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra <peterz@infradead.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20171109000718.14137-1-andi@firstfloor.org
-rw-r--r--arch/x86/events/intel/core.c35
1 files changed, 23 insertions, 12 deletions
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9fb9a1f1e47b..f94855000d4e 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3730,6 +3730,19 @@ EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3730EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 3730EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
3731 3731
3732static struct attribute *hsw_events_attrs[] = { 3732static struct attribute *hsw_events_attrs[] = {
3733 EVENT_PTR(mem_ld_hsw),
3734 EVENT_PTR(mem_st_hsw),
3735 EVENT_PTR(td_slots_issued),
3736 EVENT_PTR(td_slots_retired),
3737 EVENT_PTR(td_fetch_bubbles),
3738 EVENT_PTR(td_total_slots),
3739 EVENT_PTR(td_total_slots_scale),
3740 EVENT_PTR(td_recovery_bubbles),
3741 EVENT_PTR(td_recovery_bubbles_scale),
3742 NULL
3743};
3744
3745static struct attribute *hsw_tsx_events_attrs[] = {
3733 EVENT_PTR(tx_start), 3746 EVENT_PTR(tx_start),
3734 EVENT_PTR(tx_commit), 3747 EVENT_PTR(tx_commit),
3735 EVENT_PTR(tx_abort), 3748 EVENT_PTR(tx_abort),
@@ -3742,18 +3755,16 @@ static struct attribute *hsw_events_attrs[] = {
3742 EVENT_PTR(el_conflict), 3755 EVENT_PTR(el_conflict),
3743 EVENT_PTR(cycles_t), 3756 EVENT_PTR(cycles_t),
3744 EVENT_PTR(cycles_ct), 3757 EVENT_PTR(cycles_ct),
3745 EVENT_PTR(mem_ld_hsw),
3746 EVENT_PTR(mem_st_hsw),
3747 EVENT_PTR(td_slots_issued),
3748 EVENT_PTR(td_slots_retired),
3749 EVENT_PTR(td_fetch_bubbles),
3750 EVENT_PTR(td_total_slots),
3751 EVENT_PTR(td_total_slots_scale),
3752 EVENT_PTR(td_recovery_bubbles),
3753 EVENT_PTR(td_recovery_bubbles_scale),
3754 NULL 3758 NULL
3755}; 3759};
3756 3760
3761static __init struct attribute **get_hsw_events_attrs(void)
3762{
3763 return boot_cpu_has(X86_FEATURE_RTM) ?
3764 merge_attr(hsw_events_attrs, hsw_tsx_events_attrs) :
3765 hsw_events_attrs;
3766}
3767
3757static ssize_t freeze_on_smi_show(struct device *cdev, 3768static ssize_t freeze_on_smi_show(struct device *cdev,
3758 struct device_attribute *attr, 3769 struct device_attribute *attr,
3759 char *buf) 3770 char *buf)
@@ -4182,7 +4193,7 @@ __init int intel_pmu_init(void)
4182 4193
4183 x86_pmu.hw_config = hsw_hw_config; 4194 x86_pmu.hw_config = hsw_hw_config;
4184 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4195 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4185 x86_pmu.cpu_events = hsw_events_attrs; 4196 x86_pmu.cpu_events = get_hsw_events_attrs();
4186 x86_pmu.lbr_double_abort = true; 4197 x86_pmu.lbr_double_abort = true;
4187 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4198 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4188 hsw_format_attr : nhm_format_attr; 4199 hsw_format_attr : nhm_format_attr;
@@ -4221,7 +4232,7 @@ __init int intel_pmu_init(void)
4221 4232
4222 x86_pmu.hw_config = hsw_hw_config; 4233 x86_pmu.hw_config = hsw_hw_config;
4223 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4234 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4224 x86_pmu.cpu_events = hsw_events_attrs; 4235 x86_pmu.cpu_events = get_hsw_events_attrs();
4225 x86_pmu.limit_period = bdw_limit_period; 4236 x86_pmu.limit_period = bdw_limit_period;
4226 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4237 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4227 hsw_format_attr : nhm_format_attr; 4238 hsw_format_attr : nhm_format_attr;
@@ -4279,7 +4290,7 @@ __init int intel_pmu_init(void)
4279 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4290 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4280 hsw_format_attr : nhm_format_attr; 4291 hsw_format_attr : nhm_format_attr;
4281 extra_attr = merge_attr(extra_attr, skl_format_attr); 4292 extra_attr = merge_attr(extra_attr, skl_format_attr);
4282 x86_pmu.cpu_events = hsw_events_attrs; 4293 x86_pmu.cpu_events = get_hsw_events_attrs();
4283 intel_pmu_pebs_data_source_skl( 4294 intel_pmu_pebs_data_source_skl(
4284 boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X); 4295 boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X);
4285 pr_cont("Skylake events, "); 4296 pr_cont("Skylake events, ");