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authorGeert Uytterhoeven <geert+renesas@glider.be>2017-04-03 05:54:14 -0400
committerSimon Horman <horms+renesas@verge.net.au>2017-04-03 06:34:24 -0400
commit57ff9d736e05bede56fdb47599fdddb3408d4651 (patch)
treeda27211724cbe327aad6edccbaaf1f18d8f92df3
parent7b39e985cfc18bba43646240b10a830046382abf (diff)
ARM: dts: r8a7794: Add Z2 clock
Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider, and link the first CPU node to it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 2f6e94fd408c..a19b884fb258 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -43,6 +43,7 @@
43 compatible = "arm,cortex-a7"; 43 compatible = "arm,cortex-a7";
44 reg = <0>; 44 reg = <0>;
45 clock-frequency = <1000000000>; 45 clock-frequency = <1000000000>;
46 clocks = <&z2_clk>;
46 power-domains = <&sysc R8A7794_PD_CA7_CPU0>; 47 power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
47 next-level-cache = <&L2_CA7>; 48 next-level-cache = <&L2_CA7>;
48 }; 49 };
@@ -1064,6 +1065,13 @@
1064 clock-div = <2>; 1065 clock-div = <2>;
1065 clock-mult = <1>; 1066 clock-mult = <1>;
1066 }; 1067 };
1068 z2_clk: z2 {
1069 compatible = "fixed-factor-clock";
1070 clocks = <&cpg_clocks R8A7794_CLK_PLL0>;
1071 #clock-cells = <0>;
1072 clock-div = <1>;
1073 clock-mult = <1>;
1074 };
1067 zg_clk: zg { 1075 zg_clk: zg {
1068 compatible = "fixed-factor-clock"; 1076 compatible = "fixed-factor-clock";
1069 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1077 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;