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authorLinus Torvalds <torvalds@linux-foundation.org>2016-11-22 16:20:34 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2016-11-22 16:20:34 -0500
commit57527ed10b3bc2abf50844f6995371fa9ac503df (patch)
tree094556a872ff036a44b13f0ebee671ef7feba8d1
parent000b8949e903fc8bf78b99ac8568347251986ebf (diff)
parentc8616671af913ed2c5fb5b45f09c28599458ba1a (diff)
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "A handful of driver fixes. The sunxi fixes are for an incorrect clk tree configuration and a bad frequency calculation. The other two are fixes for passing the wrong pointer in drivers recently converted to clk_hw style registration" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: efm32gg: Pass correct type to hw provider registration clk: berlin: Pass correct type to hw provider registration clk: sunxi: Fix M factor computation for APB1 clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent
-rw-r--r--drivers/clk/berlin/bg2.c2
-rw-r--r--drivers/clk/berlin/bg2q.c2
-rw-r--r--drivers/clk/clk-efm32gg.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun6i-a31.c12
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c2
5 files changed, 16 insertions, 4 deletions
diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c
index edf3b96b3b73..1d99292e2039 100644
--- a/drivers/clk/berlin/bg2.c
+++ b/drivers/clk/berlin/bg2.c
@@ -685,7 +685,7 @@ static void __init berlin2_clock_setup(struct device_node *np)
685 } 685 }
686 686
687 /* register clk-provider */ 687 /* register clk-provider */
688 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data); 688 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
689 689
690 return; 690 return;
691 691
diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
index 0718e831475f..3b784b593afd 100644
--- a/drivers/clk/berlin/bg2q.c
+++ b/drivers/clk/berlin/bg2q.c
@@ -382,7 +382,7 @@ static void __init berlin2q_clock_setup(struct device_node *np)
382 } 382 }
383 383
384 /* register clk-provider */ 384 /* register clk-provider */
385 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data); 385 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
386 386
387 return; 387 return;
388 388
diff --git a/drivers/clk/clk-efm32gg.c b/drivers/clk/clk-efm32gg.c
index 8802a2dd56ac..f674778fb3ac 100644
--- a/drivers/clk/clk-efm32gg.c
+++ b/drivers/clk/clk-efm32gg.c
@@ -82,6 +82,6 @@ static void __init efm32gg_cmu_init(struct device_node *np)
82 hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0", 82 hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0",
83 "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL); 83 "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
84 84
85 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data); 85 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
86} 86}
87CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init); 87CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 79596463e0d9..4a82a49cff5e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -191,6 +191,8 @@ static struct clk_div_table axi_div_table[] = {
191static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu", 191static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
192 0x050, 0, 3, axi_div_table, 0); 192 0x050, 0, 3, axi_div_table, 0);
193 193
194#define SUN6I_A31_AHB1_REG 0x054
195
194static const char * const ahb1_parents[] = { "osc32k", "osc24M", 196static const char * const ahb1_parents[] = { "osc32k", "osc24M",
195 "axi", "pll-periph" }; 197 "axi", "pll-periph" };
196 198
@@ -1230,6 +1232,16 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node)
1230 val &= BIT(16); 1232 val &= BIT(16);
1231 writel(val, reg + SUN6I_A31_PLL_MIPI_REG); 1233 writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
1232 1234
1235 /* Force AHB1 to PLL6 / 3 */
1236 val = readl(reg + SUN6I_A31_AHB1_REG);
1237 /* set PLL6 pre-div = 3 */
1238 val &= ~GENMASK(7, 6);
1239 val |= 0x2 << 6;
1240 /* select PLL6 / pre-div */
1241 val &= ~GENMASK(13, 12);
1242 val |= 0x3 << 12;
1243 writel(val, reg + SUN6I_A31_AHB1_REG);
1244
1233 sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc); 1245 sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
1234 1246
1235 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, 1247 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 838b22aa8b67..f2c9274b8bd5 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -373,7 +373,7 @@ static void sun4i_get_apb1_factors(struct factors_request *req)
373 else 373 else
374 calcp = 3; 374 calcp = 3;
375 375
376 calcm = (req->parent_rate >> calcp) - 1; 376 calcm = (div >> calcp) - 1;
377 377
378 req->rate = (req->parent_rate >> calcp) / (calcm + 1); 378 req->rate = (req->parent_rate >> calcp) / (calcm + 1);
379 req->m = calcm; 379 req->m = calcm;