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authorXiaofei Tan <tanxiaofei@huawei.com>2018-01-17 11:46:52 -0500
committerMartin K. Petersen <martin.petersen@oracle.com>2018-01-22 20:03:58 -0500
commit56ad7fcd4f058f74db8f4b08dd4e61a52bd8feba (patch)
treeb382ac43c0c10c189b9f2328cdf004ea7e5cfa8c
parentf870bcbe9a991264f424ad937916695b2f3de133 (diff)
scsi: hisi_sas: devicetree: bindings: add LED feature for v2 hw
Add directly attached disk LED feature for v2 hw. Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
-rw-r--r--Documentation/devicetree/bindings/scsi/hisilicon-sas.txt5
1 files changed, 4 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
index b6a869f97715..df3bef7998fa 100644
--- a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
+++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
@@ -8,7 +8,10 @@ Main node required properties:
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset 8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset 9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address 10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Address and length of the SAS register 11 - reg : Contains two regions. The first is the address and length of the SAS
12 register. The second is the address and length of CPLD register for
13 SGPIO control. The second is optional, and should be set only when
14 we use a CPLD for directly attached disk LED control.
12 - hisilicon,sas-syscon: phandle of syscon used for sas control 15 - hisilicon,sas-syscon: phandle of syscon used for sas control
13 - ctrl-reset-reg : offset to controller reset register in ctrl reg 16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
14 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg 17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg