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authorJean Delvare <jdelvare@suse.de>2017-07-30 04:18:25 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-08-02 14:29:42 -0400
commit5694785cf09bf0e7bd8e5f62361ea34fa162a4a0 (patch)
tree3b89f0cf1ba1c94dc0441fa3cdc36cfb7310e105
parentc471e70b187e62efc77bcdf6f58795907f8f4851 (diff)
drm/amdgpu: Fix undue fallthroughs in golden registers initialization
As I was staring at the si_init_golden_registers code, I noticed that the Pitcairn initialization silently falls through the Cape Verde initialization, and the Oland initialization falls through the Hainan initialization. However there is no comment stating that this is intentional, and the radeon driver doesn't have any such fallthrough, so I suspect this is not supposed to happen. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Cc: Ken Wang <Qingqing.Wang@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Marek Olšák" <maraeo@gmail.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index f45fb0f022b3..4267fa417997 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1385,6 +1385,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
1385 amdgpu_program_register_sequence(adev, 1385 amdgpu_program_register_sequence(adev,
1386 pitcairn_mgcg_cgcg_init, 1386 pitcairn_mgcg_cgcg_init,
1387 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); 1387 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1388 break;
1388 case CHIP_VERDE: 1389 case CHIP_VERDE:
1389 amdgpu_program_register_sequence(adev, 1390 amdgpu_program_register_sequence(adev,
1390 verde_golden_registers, 1391 verde_golden_registers,
@@ -1409,6 +1410,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
1409 amdgpu_program_register_sequence(adev, 1410 amdgpu_program_register_sequence(adev,
1410 oland_mgcg_cgcg_init, 1411 oland_mgcg_cgcg_init,
1411 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); 1412 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1413 break;
1412 case CHIP_HAINAN: 1414 case CHIP_HAINAN:
1413 amdgpu_program_register_sequence(adev, 1415 amdgpu_program_register_sequence(adev,
1414 hainan_golden_registers, 1416 hainan_golden_registers,