Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle: "Boston platform support: - Document DT bindings - Add CLK driver for board clocks CM: - Avoid per-core locking with CM3 & higher - WARN on attempt to lock invalid VP, not BUG CPS: - Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6 - Prevent multi-core with dcache aliasing - Handle cores not powering down more gracefully - Handle spurious VP starts more gracefully DSP: - Add lwx & lhx missaligned access support eBPF: - Add MIPS support along with many supporting change to add the required infrastructure Generic arch code: - Misc sysmips MIPS_ATOMIC_SET fixes - Drop duplicate HAVE_SYSCALL_TRACEPOINTS - Negate error syscall return in trace - Correct forced syscall errors - Traced negative syscalls should return -ENOSYS - Allow samples/bpf/tracex5 to access syscall arguments for sane traces - Cleanup from old Kconfig options in defconfigs - Fix PREF instruction usage by memcpy for MIPS R6 - Fix various special cases in the FPU eulation - Fix some special cases in MIPS16e2 support - Fix MIPS I ISA /proc/cpuinfo reporting - Sort MIPS Kconfig alphabetically - Fix minimum alignment requirement of IRQ stack as required by ABI / GCC - Fix special cases in the module loader - Perform post-DMA cache flushes on systems with MAARs - Probe the I6500 CPU - Cleanup cmpxchg and add support for 1 and 2 byte operations - Use queued read/write locks (qrwlock) - Use queued spinlocks (qspinlock) - Add CPU shared FTLB feature detection - Handle tlbex-tlbp race condition - Allow storing pgd in C0_CONTEXT for MIPSr6 - Use current_cpu_type() in m4kc_tlbp_war() - Support Boston in the generic kernel Generic platform: - yamon-dt: Pull YAMON DT shim code out of SEAD-3 board - yamon-dt: Support > 256MB of RAM - yamon-dt: Use serial* rather than uart* aliases - Abstract FDT fixup application - Set RTC_ALWAYS_BCD to 0 - Add a MAINTAINERS entry core kernel: - qspinlock.c: include linux/prefetch.h Loongson 3: - Add support Perf: - Add I6500 support SEAD-3: - Remove GIC timer from DT - Set interrupt-parent per-device, not at root node - Fix GIC interrupt specifiers SMP: - Skip IPI setup if we only have a single CPU VDSO: - Make comment match reality - Improvements to time code in VDSO" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits) locking/qspinlock: Include linux/prefetch.h MIPS: Fix MIPS I ISA /proc/cpuinfo reporting MIPS: Fix minimum alignment requirement of IRQ stack MIPS: generic: Support MIPS Boston development boards MIPS: DTS: img: Don't attempt to build-in all .dtb files clk: boston: Add a driver for MIPS Boston board clocks dt-bindings: Document img,boston-clock binding MIPS: Traced negative syscalls should return -ENOSYS MIPS: Correct forced syscall errors MIPS: Negate error syscall return in trace MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select MIPS16e2: Provide feature overrides for non-MIPS16 systems MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions MIPS: MIPS16e2: Identify ASE presence MIPS: VDSO: Fix a mismatch between comment and preprocessor constant MIPS: VDSO: Add implementation of gettimeofday() fallback MIPS: VDSO: Add implementation of clock_gettime() fallback MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse() MIPS: Use current_cpu_type() in m4kc_tlbp_war() ...
author: Linus Torvalds <torvalds@linux-foundation.org> 2017-07-15 13:59:54 -0400
committer: Linus Torvalds <torvalds@linux-foundation.org> 2017-07-15 13:59:54 -0400
commit: 568d135d337d3114688fef9fdbce7fb6dbbd04c7 (patch)
tree: b9355b94182a51eec5cfc69dd335e39a2e97ac7d
parent: 4ecd4ff55ac5c7fe9e232f34a41c4d54f2d825c1 (diff)
parent: d40e0d4fb5613099a58c95a9403f51b03e40e861 (diff)
136 files changed, 2453 insertions, 1836 deletions
diff --git a/Documentation/devicetree/bindings/clock/img,boston-clock.txt b/Documentation/devicetree/bindings/clock/img,boston-clock.txt
new file mode 100644
index 000000000000..7bc5e9ffb624
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/img,boston-clock.txt
@@ -0,0 +1,31 @@
+Binding for Imagination Technologies MIPS Boston clock sources.
+This binding uses the common clock binding[1].
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+The device node must be a child node of the syscon node corresponding to the
+Boston system's platform registers.
+Required properties:
+- compatible : Should be "img,boston-clock".
+- #clock-cells : Should be set to 1.
+  Values available for clock consumers can be found in the header file:
+    <dt-bindings/clock/boston-clock.h>
+Example:
+        system-controller@17ffd000 {
+                compatible = "img,boston-platform-regs", "syscon";
+                reg = <0x17ffd000 0x1000>;
+                clk_boston: clock {
+                        compatible = "img,boston-clock";
+                        #clock-cells = <1>;
+                };
+        };
+        uart0: uart@17ffe000 {
+                /* ... */
+                clocks = <&clk_boston BOSTON_CLK_SYS>;
+        };
diff --git a/MAINTAINERS b/MAINTAINERS
index 428e042dcd21..205d3977ac46 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8732,6 +8732,12 @@ F:	Documentation/devicetree/bindings/mips/
 F:      Documentation/mips/
 F:      arch/mips/
+MIPS GENERIC PLATFORM
+M:      Paul Burton <paul.burton@imgtec.com>
+L:      linux-mips@linux-mips.org
+S:      Supported
+F:      arch/mips/generic/
 MIPS/LOONGSON1 ARCHITECTURE
 M:      Keguang Zhang <keguang.zhang@gmail.com>
 L:      linux-mips@linux-mips.org
@@ -8741,6 +8747,16 @@ F:	arch/mips/include/asm/mach-loongson32/
 F:      drivers/*/*loongson1*
 F:      drivers/*/*/*loongson1*
+MIPS BOSTON DEVELOPMENT BOARD
+M:      Paul Burton <paul.burton@imgtec.com>
+L:      linux-mips@linux-mips.org
+S:      Maintained
+F:      Documentation/devicetree/bindings/clock/img,boston-clock.txt
+F:      arch/mips/boot/dts/img/boston.dts
+F:      arch/mips/configs/generic/board-boston.config
+F:      drivers/clk/imgtec/clk-boston.c
+F:      include/dt-bindings/clock/boston-clock.h
 MIROSOUND PCM20 FM RADIO RECEIVER DRIVER
 M:      Hans Verkuil <hverkuil@xs4all.nl>
 L:      linux-media@vger.kernel.org
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 45bcd1cfcec0..8dd20358464f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1,75 +1,77 @@
 config MIPS
        bool
        default y
-        select ARCH_SUPPORTS_UPROBES
+        select ARCH_BINFMT_ELF_STATE
+        select ARCH_CLOCKSOURCE_DATA
+        select ARCH_DISCARD_MEMBLOCK
+        select ARCH_HAS_ELF_RANDOMIZE
+        select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
        select ARCH_MIGHT_HAVE_PC_PARPORT
        select ARCH_MIGHT_HAVE_PC_SERIO
-        select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
+        select ARCH_SUPPORTS_UPROBES
        select ARCH_USE_BUILTIN_BSWAP
-        select HAVE_CONTEXT_TRACKING
+        select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
-        select HAVE_GENERIC_DMA_COHERENT
+        select ARCH_USE_QUEUED_RWLOCKS
-        select HAVE_IDE
+        select ARCH_USE_QUEUED_SPINLOCKS
-        select HAVE_IRQ_EXIT_ON_IRQ_STACK
+        select ARCH_WANT_IPC_PARSE_VERSION
-        select HAVE_OPROFILE
+        select BUILDTIME_EXTABLE_SORT
-        select HAVE_PERF_EVENTS
+        select CLONE_BACKWARDS
-        select PERF_USE_VMALLOC
+        select CPU_PM if CPU_IDLE
+        select GENERIC_ATOMIC64 if !64BIT
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_CMOS_UPDATE
+        select GENERIC_CPU_AUTOPROBE
+        select GENERIC_IRQ_PROBE
+        select GENERIC_IRQ_SHOW
+        select GENERIC_PCI_IOMAP
+        select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
+        select GENERIC_SMP_IDLE_THREAD
+        select GENERIC_TIME_VSYSCALL
+        select HANDLE_DOMAIN_IRQ
+        select HAVE_ARCH_JUMP_LABEL
        select HAVE_ARCH_KGDB
        select HAVE_ARCH_MMAP_RND_BITS if MMU
        select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
        select HAVE_ARCH_SECCOMP_FILTER
        select HAVE_ARCH_TRACEHOOK
-        select HAVE_CBPF_JIT if !CPU_MICROMIPS
+        select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
-        select HAVE_FUNCTION_TRACER
+        select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
+        select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
+        select HAVE_CC_STACKPROTECTOR
+        select HAVE_CONTEXT_TRACKING
+        select HAVE_COPY_THREAD_TLS
+        select HAVE_C_RECORDMCOUNT
+        select HAVE_DEBUG_KMEMLEAK
+        select HAVE_DEBUG_STACKOVERFLOW
+        select HAVE_DMA_API_DEBUG
+        select HAVE_DMA_CONTIGUOUS
        select HAVE_DYNAMIC_FTRACE
+        select HAVE_EXIT_THREAD
        select HAVE_FTRACE_MCOUNT_RECORD
-        select HAVE_C_RECORDMCOUNT
        select HAVE_FUNCTION_GRAPH_TRACER
+        select HAVE_FUNCTION_TRACER
+        select HAVE_GENERIC_DMA_COHERENT
+        select HAVE_IDE
+        select HAVE_IRQ_EXIT_ON_IRQ_STACK
+        select HAVE_IRQ_TIME_ACCOUNTING
        select HAVE_KPROBES
        select HAVE_KRETPROBES
-        select HAVE_SYSCALL_TRACEPOINTS
-        select HAVE_DEBUG_KMEMLEAK
-        select HAVE_SYSCALL_TRACEPOINTS
-        select ARCH_HAS_ELF_RANDOMIZE
-        select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
-        select RTC_LIB if !MACH_LOONGSON64
-        select GENERIC_ATOMIC64 if !64BIT
-        select HAVE_DMA_CONTIGUOUS
-        select HAVE_DMA_API_DEBUG
-        select GENERIC_IRQ_PROBE
-        select GENERIC_IRQ_SHOW
-        select GENERIC_PCI_IOMAP
-        select HAVE_ARCH_JUMP_LABEL
-        select ARCH_WANT_IPC_PARSE_VERSION
-        select IRQ_FORCED_THREADING
        select HAVE_MEMBLOCK
        select HAVE_MEMBLOCK_NODE_MAP
-        select ARCH_DISCARD_MEMBLOCK
-        select GENERIC_SMP_IDLE_THREAD
-        select BUILDTIME_EXTABLE_SORT
-        select GENERIC_CPU_AUTOPROBE
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
-        select GENERIC_CMOS_UPDATE
        select HAVE_MOD_ARCH_SPECIFIC
        select HAVE_NMI
-        select VIRT_TO_BUS
+        select HAVE_OPROFILE
-        select MODULES_USE_ELF_REL if MODULES
+        select HAVE_PERF_EVENTS
+        select HAVE_REGS_AND_STACK_ACCESS_API
+        select HAVE_SYSCALL_TRACEPOINTS
+        select HAVE_VIRT_CPU_ACCOUNTING_GEN
+        select IRQ_FORCED_THREADING
        select MODULES_USE_ELF_RELA if MODULES && 64BIT
-        select CLONE_BACKWARDS
+        select MODULES_USE_ELF_REL if MODULES
-        select HAVE_DEBUG_STACKOVERFLOW
+        select PERF_USE_VMALLOC
-        select HAVE_CC_STACKPROTECTOR
+        select RTC_LIB if !MACH_LOONGSON64
-        select CPU_PM if CPU_IDLE
-        select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
-        select ARCH_BINFMT_ELF_STATE
        select SYSCTL_EXCEPTION_TRACE
-        select HAVE_VIRT_CPU_ACCOUNTING_GEN
+        select VIRT_TO_BUS
-        select HAVE_IRQ_TIME_ACCOUNTING
-        select GENERIC_TIME_VSYSCALL
-        select ARCH_CLOCKSOURCE_DATA
-        select HANDLE_DOMAIN_IRQ
-        select HAVE_EXIT_THREAD
-        select HAVE_REGS_AND_STACK_ACCESS_API
-        select HAVE_COPY_THREAD_TLS
 menu "Machine selection"
@@ -1179,6 +1181,15 @@ config SYS_SUPPORTS_RELOCATABLE
         The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
         to allow access to command line and entropy sources.
+config MIPS_CBPF_JIT
+        def_bool y
+        depends on BPF_JIT && HAVE_CBPF_JIT
+config MIPS_EBPF_JIT
+        def_bool y
+        depends on BPF_JIT && HAVE_EBPF_JIT
 #
 # Endianness selection.  Sufficiently obscure so many users don't know what to
 # answer,so we try hard to limit the available choices.  Also the use of a
@@ -2062,7 +2073,7 @@ config CPU_SUPPORTS_UNCACHED_ACCELERATED
        bool
 config MIPS_PGD_C0_CONTEXT
        bool
-        default y if 64BIT && CPU_MIPSR2 && !CPU_XLP
+        default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
 #
 # Set to y for ptrace access to watch registers.
@@ -2370,6 +2381,7 @@ config MIPS_CPS
        select SMP
        select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
        select SYS_SUPPORTS_HOTPLUG_CPU
+        select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
        select SYS_SUPPORTS_SMP
        select WEAK_ORDERING
        help
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 02a1787c888c..04343625b929 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -160,7 +160,7 @@ cflags-$(CONFIG_CPU_MIPS32_R1)	+= $(call cc-option,-march=mips32,-mips32 -U_MIPS
                        -Wa,-mips32 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R2)  += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
                        -Wa,-mips32r2 -Wa,--trap
-cflags-$(CONFIG_CPU_MIPS32_R6)  += -march=mips32r6 -Wa,--trap
+cflags-$(CONFIG_CPU_MIPS32_R6)  += -march=mips32r6 -Wa,--trap -modd-spreg
 cflags-$(CONFIG_CPU_MIPS64_R1)  += $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
                        -Wa,-mips64 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R2)  += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
diff --git a/arch/mips/boot/dts/img/Makefile b/arch/mips/boot/dts/img/Makefile
index 69a65f0f82d2..3d70958d0f5a 100644
--- a/arch/mips/boot/dts/img/Makefile
+++ b/arch/mips/boot/dts/img/Makefile
@@ -1,6 +1,7 @@
-dtb-$(CONFIG_MACH_PISTACHIO)    += pistachio_marduk.dtb
+dtb-$(CONFIG_FIT_IMAGE_FDT_BOSTON)      += boston.dtb
-obj-y                           += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+dtb-$(CONFIG_MACH_PISTACHIO)    += pistachio_marduk.dtb
+obj-$(CONFIG_MACH_PISTACHIO)    += pistachio_marduk.dtb.o
 # Force kbuild to make empty built-in.o if necessary
 obj-                            += dummy.o
diff --git a/arch/mips/boot/dts/img/boston.dts b/arch/mips/boot/dts/img/boston.dts
new file mode 100644
index 000000000000..53bfa29a7093
--- /dev/null
+++ b/arch/mips/boot/dts/img/boston.dts
@@ -0,0 +1,224 @@
+/dts-v1/;
+#include <dt-bindings/clock/boston-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "img,boston";
+        chosen {
+                stdout-path = "uart0:115200";
+        };
+        aliases {
+                uart0 = &uart0;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "img,mips";
+                        reg = <0>;
+                        clocks = <&clk_boston BOSTON_CLK_CPU>;
+                };
+        };
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+        pci0: pci@10000000 {
+                compatible = "xlnx,axi-pcie-host-1.00.a";
+                device_type = "pci";
+                reg = <0x10000000 0x2000000>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
+                ranges = <0x02000000 0 0x40000000
+                          0x40000000 0 0x40000000>;
+                interrupt-map-mask = <0 0 0 7>;
+                interrupt-map = <0 0 0 1 &pci0_intc 1>,
+                                <0 0 0 2 &pci0_intc 2>,
+                                <0 0 0 3 &pci0_intc 3>,
+                                <0 0 0 4 &pci0_intc 4>;
+                pci0_intc: interrupt-controller {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                };
+        };
+        pci1: pci@12000000 {
+                compatible = "xlnx,axi-pcie-host-1.00.a";
+                device_type = "pci";
+                reg = <0x12000000 0x2000000>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
+                ranges = <0x02000000 0 0x20000000
+                          0x20000000 0 0x20000000>;
+                interrupt-map-mask = <0 0 0 7>;
+                interrupt-map = <0 0 0 1 &pci1_intc 1>,
+                                <0 0 0 2 &pci1_intc 2>,
+                                <0 0 0 3 &pci1_intc 3>,
+                                <0 0 0 4 &pci1_intc 4>;
+                pci1_intc: interrupt-controller {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                };
+        };
+        pci2: pci@14000000 {
+                compatible = "xlnx,axi-pcie-host-1.00.a";
+                device_type = "pci";
+                reg = <0x14000000 0x2000000>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
+                ranges = <0x02000000 0 0x16000000
+                          0x16000000 0 0x100000>;
+                interrupt-map-mask = <0 0 0 7>;
+                interrupt-map = <0 0 0 1 &pci2_intc 1>,
+                                <0 0 0 2 &pci2_intc 2>,
+                                <0 0 0 3 &pci2_intc 3>,
+                                <0 0 0 4 &pci2_intc 4>;
+                pci2_intc: interrupt-controller {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                };
+                pci2_root@0,0,0 {
+                        compatible = "pci10ee,7021";
+                        reg = <0x00000000 0 0 0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        eg20t_bridge@1,0,0 {
+                                compatible = "pci8086,8800";
+                                reg = <0x00010000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                eg20t_mac@2,0,1 {
+                                        compatible = "pci8086,8802";
+                                        reg = <0x00020100 0 0 0 0>;
+                                        phy-reset-gpios = <&eg20t_gpio 6
+                                                           GPIO_ACTIVE_LOW>;
+                                };
+                                eg20t_gpio: eg20t_gpio@2,0,2 {
+                                        compatible = "pci8086,8803";
+                                        reg = <0x00020200 0 0 0 0>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+                                eg20t_i2c@2,12,2 {
+                                        compatible = "pci8086,8817";
+                                        reg = <0x00026200 0 0 0 0>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        rtc@0x68 {
+                                                compatible = "st,m41t81s";
+                                                reg = <0x68>;
+                                        };
+                                };
+                        };
+                };
+        };
+        gic: interrupt-controller@16120000 {
+                compatible = "mti,gic";
+                reg = <0x16120000 0x20000>;
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                timer {
+                        compatible = "mti,gic-timer";
+                        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+                        clocks = <&clk_boston BOSTON_CLK_CPU>;
+                };
+        };
+        cdmm@16140000 {
+                compatible = "mti,mips-cdmm";
+                reg = <0x16140000 0x8000>;
+        };
+        cpc@16200000 {
+                compatible = "mti,mips-cpc";
+                reg = <0x16200000 0x8000>;
+        };
+        plat_regs: system-controller@17ffd000 {
+                compatible = "img,boston-platform-regs", "syscon";
+                reg = <0x17ffd000 0x1000>;
+                clk_boston: clock {
+                        compatible = "img,boston-clock";
+                        #clock-cells = <1>;
+                };
+        };
+        reboot: syscon-reboot {
+                compatible = "syscon-reboot";
+                regmap = <&plat_regs>;
+                offset = <0x10>;
+                mask = <0x10>;
+        };
+        uart0: uart@17ffe000 {
+                compatible = "ns16550a";
+                reg = <0x17ffe000 0x1000>;
+                reg-shift = <2>;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_boston BOSTON_CLK_SYS>;
+        };
+        lcd: lcd@17fff000 {
+                compatible = "img,boston-lcd";
+                reg = <0x17fff000 0x8>;
+        };
+};
diff --git a/arch/mips/boot/dts/mti/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts
index b112879a5d9d..4f8bc83c2960 100644
--- a/arch/mips/boot/dts/mti/sead3.dts
+++ b/arch/mips/boot/dts/mti/sead3.dts
@@ -11,15 +11,14 @@
        #size-cells = <1>;
        compatible = "mti,sead-3";
        model = "MIPS SEAD-3";
-        interrupt-parent = <&gic>;
        chosen {
-                stdout-path = "uart1:115200";
+                stdout-path = "serial1:115200";
        };
        aliases {
-                uart0 = &uart0;
+                serial0 = &uart0;
-                uart1 = &uart1;
+                serial1 = &uart1;
        };
        cpus {
@@ -54,18 +53,14 @@
                 * controller & should be probed first.
                 */
                interrupt-parent = <&cpu_intc>;
-                timer {
-                        compatible = "mti,gic-timer";
-                        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-                };
        };
        ehci@1b200000 {
                compatible = "generic-ehci";
                reg = <0x1b200000 0x1000>;
-                interrupts = <0>; /* GIC 0 or CPU 6 */
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
                has-transaction-translator;
        };
@@ -227,7 +222,8 @@
                clock-frequency = <14745600>;
-                interrupts = <3>; /* GIC 3 or CPU 4 */
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
                no-loopback-test;
        };
@@ -241,7 +237,8 @@
                clock-frequency = <14745600>;
-                interrupts = <2>; /* GIC 2 or CPU 4 */
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
                no-loopback-test;
        };
@@ -251,7 +248,8 @@
                reg = <0x1f010000 0x10000>;
                reg-io-width = <4>;
-                interrupts = <0>; /* GIC 0 or CPU 6 */
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
                phy-mode = "mii";
                smsc,irq-push-pull;
diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig
index 320772caf054..92fca3c42eac 100644
--- a/arch/mips/configs/ar7_defconfig
+++ b/arch/mips/configs/ar7_defconfig
@@ -3,7 +3,6 @@ CONFIG_HIGH_RES_TIMERS=y
 CONFIG_HZ_100=y
 CONFIG_KEXEC=y
 # CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
@@ -41,7 +40,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_TCP_CONG_ADVANCED=y
 # CONFIG_TCP_CONG_BIC is not set
@@ -86,7 +84,6 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
@@ -99,8 +96,6 @@ CONFIG_FIXED_PHY=y
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_CPMAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_PPP=m
 CONFIG_PPP_MULTILINK=y
 CONFIG_PPP_FILTER=y
@@ -142,7 +137,6 @@ CONFIG_BSD_DISKLABEL=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
 CONFIG_CRYPTO=y
diff --git a/arch/mips/configs/ath79_defconfig b/arch/mips/configs/ath79_defconfig
index 134879c1310a..25ed914933e5 100644
--- a/arch/mips/configs/ath79_defconfig
+++ b/arch/mips/configs/ath79_defconfig
@@ -7,7 +7,6 @@ CONFIG_ATH79_MACH_PB44=y
 CONFIG_ATH79_MACH_UBNT_XM=y
 CONFIG_HZ_100=y
 # CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -35,7 +34,6 @@ CONFIG_IP_ADVANCED_ROUTER=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_CFG80211=m
 CONFIG_MAC80211=m
diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig
index 5599a9f1e3c6..131b350f014f 100644
--- a/arch/mips/configs/bcm63xx_defconfig
+++ b/arch/mips/configs/bcm63xx_defconfig
@@ -5,7 +5,6 @@ CONFIG_BCM63XX_CPU_6348=y
 CONFIG_BCM63XX_CPU_6358=y
 CONFIG_NO_HZ=y
 # CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_TINY_RCU=y
@@ -33,7 +32,6 @@ CONFIG_INET=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_CFG80211=y
@@ -50,13 +48,10 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_BCM63XX_PHY=y
 CONFIG_NET_ETHERNET=y
 CONFIG_BCM63XX_ENET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_B43=y
 # CONFIG_B43_PHY_LP is not set
 # CONFIG_INPUT is not set
@@ -70,7 +65,6 @@ CONFIG_SERIAL_BCM63XX_CONSOLE=y
 # CONFIG_HWMON is not set
 # CONFIG_VGA_ARB is not set
 CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
 CONFIG_USB_OHCI_HCD=y
@@ -84,7 +78,6 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_PROC_KCORE=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0,115200"
 # CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index d20b09d77b53..a55009edbb29 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -4,7 +4,6 @@ CONFIG_SMP=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_HZ_1000=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
@@ -60,7 +59,6 @@ CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
-# CONFIG_INET_LRO is not set
 CONFIG_TCP_MD5SIG=y
 CONFIG_IPV6_ROUTER_PREF=y
 CONFIG_IPV6_ROUTE_INFO=y
@@ -182,7 +180,6 @@ CONFIG_QUOTA=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
 CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
 CONFIG_ISO9660_FS=m
@@ -284,7 +281,6 @@ CONFIG_CRYPTO_SEED=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 CONFIG_CRC_T10DIF=m
 CONFIG_CRC7=m
diff --git a/arch/mips/configs/bmips_be_defconfig b/arch/mips/configs/bmips_be_defconfig
index acf7785c4cdb..a7072a14d396 100644
--- a/arch/mips/configs/bmips_be_defconfig
+++ b/arch/mips/configs/bmips_be_defconfig
@@ -23,7 +23,6 @@ CONFIG_INET=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_CFG80211=y
 CONFIG_NL80211_TESTMODE=y
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 2924ba34a01b..bd80b5c852dd 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -1,6 +1,5 @@
 CONFIG_MACH_VR41XX=y
 CONFIG_ZAO_CAPCELLA=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -46,8 +45,6 @@ CONFIG_SMSC_PHY=m
 CONFIG_NET_ETHERNET=y
 CONFIG_NET_PCI=y
 CONFIG_8139TOO=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
@@ -59,7 +56,6 @@ CONFIG_SERIAL_VR41XX_CONSOLE=y
 CONFIG_GPIO_VR41XX=y
 # CONFIG_HWMON is not set
 # CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_VR41XX=y
diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig
index d4fda41f00ba..e5b18f1a31a0 100644
--- a/arch/mips/configs/cavium_octeon_defconfig
+++ b/arch/mips/configs/cavium_octeon_defconfig
@@ -42,7 +42,6 @@ CONFIG_IP_MROUTE=y
 CONFIG_IP_PIMSM_V1=y
 CONFIG_IP_PIMSM_V2=y
 CONFIG_SYN_COOKIES=y
-# CONFIG_INET_LRO is not set
 CONFIG_IPV6=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index 43e0ba24470c..b42cfa7865f9 100644
--- a/arch/mips/configs/ci20_defconfig
+++ b/arch/mips/configs/ci20_defconfig
@@ -41,7 +41,6 @@ CONFIG_INET=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 23b66934e18d..a9066f300665 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -1,5 +1,4 @@
 CONFIG_MIPS_COBALT=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_RELAY=y
@@ -15,17 +14,14 @@ CONFIG_XFRM_USER=y
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
-# CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_JEDECPROBE=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_RAID_ATTRS=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
@@ -36,8 +32,6 @@ CONFIG_NET_ETHERNET=y
 CONFIG_NET_TULIP=y
 CONFIG_DE2104X=y
 CONFIG_TULIP=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
@@ -56,7 +50,6 @@ CONFIG_FB_COBALT=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_HID=m
 CONFIG_USB=m
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=m
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
 CONFIG_USB_OHCI_HCD=m
@@ -84,6 +77,5 @@ CONFIG_NFS_V3_ACL=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
 CONFIG_NFSD_V3_ACL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_CRC16=y
 CONFIG_LIBCRC32C=y
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 2b6cb41d5715..e149f78901f8 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -1,6 +1,5 @@
 CONFIG_MACH_DECSTATION=y
 CONFIG_CPU_R3000=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index e94d266c4b97..c3ac0209457c 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -1,6 +1,5 @@
 CONFIG_MACH_VR41XX=y
 CONFIG_CASIO_E55=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -28,7 +27,6 @@ CONFIG_SERIAL_VR41XX_CONSOLE=y
 CONFIG_GPIO_VR41XX=y
 # CONFIG_HWMON is not set
 # CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_VR41XX=y
diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig
index 87435897fd50..499f51498ecb 100644
--- a/arch/mips/configs/fuloong2e_defconfig
+++ b/arch/mips/configs/fuloong2e_defconfig
@@ -3,7 +3,6 @@ CONFIG_64BIT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-fuloong2e"
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
@@ -47,7 +46,6 @@ CONFIG_NET_IPGRE=m
 CONFIG_NET_IPGRE_BROADCAST=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_NETFILTER=y
@@ -79,7 +77,6 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
@@ -88,7 +85,6 @@ CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_ECN=m
 CONFIG_IP_NF_TARGET_TTL=m
@@ -101,7 +97,6 @@ CONFIG_NET_9P=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_FW_LOADER=m
 CONFIG_MTD=m
-CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=m
 CONFIG_MTD_CFI=m
 CONFIG_MTD_JEDECPROBE=m
@@ -163,7 +158,6 @@ CONFIG_I2C=m
 CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_VIAPRO=m
 # CONFIG_HWMON is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=m
 CONFIG_FB=y
 CONFIG_FB_RADEON=y
 # CONFIG_FB_RADEON_I2C is not set
@@ -184,7 +178,6 @@ CONFIG_USB_KBD=y
 CONFIG_USB_MOUSE=y
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_OTG_WHITELIST=y
 CONFIG_USB_WUSB_CBAF=m
 CONFIG_USB_C67X00_HCD=m
@@ -201,7 +194,6 @@ CONFIG_USB_TMC=m
 CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_ONETOUCH=y
 CONFIG_USB_STORAGE_CYPRESS_ATACB=y
-CONFIG_USB_LIBUSUAL=y
 CONFIG_USB_SEVSEG=m
 CONFIG_USB_ISIGHTFW=m
 CONFIG_UIO=m
@@ -215,7 +207,6 @@ CONFIG_EXT4_FS=m
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
 CONFIG_REISERFS_FS=m
-CONFIG_AUTOFS_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_FUSE_FS=y
 CONFIG_ISO9660_FS=m
@@ -256,8 +247,6 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_CRYPTO_FIPS=y
 CONFIG_CRYPTO_AUTHENC=m
 CONFIG_CRYPTO_CCM=m
diff --git a/arch/mips/configs/generic/board-boston.config b/arch/mips/configs/generic/board-boston.config
new file mode 100644
index 000000000000..19560a45b683
--- /dev/null
+++ b/arch/mips/configs/generic/board-boston.config
@@ -0,0 +1,48 @@
+CONFIG_FIT_IMAGE_FDT_BOSTON=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_AUXDISPLAY=y
+CONFIG_IMG_ASCII_LCD=y
+CONFIG_COMMON_CLK_BOSTON=y
+CONFIG_DMADEVICES=y
+CONFIG_PCH_DMA=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PCH=y
+CONFIG_I2C=y
+CONFIG_I2C_EG20T=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PCI=y
+CONFIG_NETDEVICES=y
+CONFIG_PCH_GBE=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCH_PHUB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_M41T80=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_TOPCLIFF_PCH=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig
index e24feb0633aa..b1911816337c 100644
--- a/arch/mips/configs/gpr_defconfig
+++ b/arch/mips/configs/gpr_defconfig
@@ -2,7 +2,6 @@ CONFIG_MIPS_ALCHEMY=y
 CONFIG_MIPS_GPR=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -59,7 +58,6 @@ CONFIG_NETFILTER_XT_MATCH_REALM=m
 CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
@@ -68,7 +66,6 @@ CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_ECN=m
 CONFIG_IP_NF_TARGET_TTL=m
@@ -166,7 +163,6 @@ CONFIG_YAM=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
@@ -200,8 +196,6 @@ CONFIG_SMSC_PHY=m
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_MIPS_AU1X00_ENET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_ATH_COMMON=y
 CONFIG_ATH_DEBUG=y
 CONFIG_ATH5K=y
@@ -286,14 +280,12 @@ CONFIG_USB_HIDDEV=y
 CONFIG_USB_KBD=m
 CONFIG_USB_MOUSE=m
 CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_MON=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=m
-CONFIG_USB_LIBUSUAL=y
 CONFIG_USB_SERIAL=y
 CONFIG_USB_EZUSB=y
 CONFIG_USB_SERIAL_GENERIC=y
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index ec8e9684296d..83e8fe2064aa 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -4,7 +4,6 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_HZ_1000=y
 CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
@@ -46,7 +45,6 @@ CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
-# CONFIG_INET_LRO is not set
 CONFIG_TCP_MD5SIG=y
 CONFIG_IPV6_ROUTER_PREF=y
 CONFIG_IPV6_ROUTE_INFO=y
@@ -139,7 +137,6 @@ CONFIG_IP_VS_SED=m
 CONFIG_IP_VS_NQ=m
 CONFIG_IP_VS_FTP=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
@@ -148,7 +145,6 @@ CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_NF_NAT=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
@@ -163,7 +159,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -174,7 +169,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
@@ -215,7 +209,6 @@ CONFIG_RFKILL=m
 CONFIG_CONNECTOR=m
 CONFIG_CDROM_PKTCDVD=m
 CONFIG_ATA_OVER_ETH=m
-# CONFIG_MISC_DEVICES is not set
 CONFIG_RAID_ATTRS=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
@@ -245,8 +238,6 @@ CONFIG_MDIO_BITBANG=m
 CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=m
 CONFIG_SGISEEQ=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_HOSTAP=m
 CONFIG_INPUT_MOUSEDEV=m
 CONFIG_MOUSE_PS2=m
@@ -286,7 +277,6 @@ CONFIG_QUOTA=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
 CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
 CONFIG_ISO9660_FS=m
@@ -355,7 +345,6 @@ CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
 CONFIG_DLM=m
 CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_KEYS=y
 CONFIG_CRYPTO_FIPS=y
 CONFIG_CRYPTO_NULL=m
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index e582069b44fd..a0d593248668 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -5,7 +5,6 @@ CONFIG_SMP=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_HZ_1000=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_IKCONFIG=y
@@ -104,7 +103,6 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_OSD=m
 CONFIG_CDROM_PKTCDVD=m
 CONFIG_ATA_OVER_ETH=m
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=y
@@ -325,7 +323,6 @@ CONFIG_XFS_POSIX_ACL=y
 CONFIG_BTRFS_FS=m
 CONFIG_BTRFS_FS_POSIX_ACL=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
-CONFIG_AUTOFS_FS=m
 CONFIG_FUSE_FS=m
 CONFIG_CUSE=m
 CONFIG_FSCACHE=m
@@ -342,7 +339,6 @@ CONFIG_NFS_V3=y
 CONFIG_RPCSEC_GSS_KRB5=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_DLM=m
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_KEYS=y
 CONFIG_SECURITYFS=y
 CONFIG_CRYPTO_FIPS=y
@@ -378,7 +374,6 @@ CONFIG_CRYPTO_SEED=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 CONFIG_CRYPTO_DEV_HIFN_795X=m
 CONFIG_CRC_T10DIF=m
diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig
index 4dbf6269b3f9..d0a4c2cfacf8 100644
--- a/arch/mips/configs/ip28_defconfig
+++ b/arch/mips/configs/ip28_defconfig
@@ -1,7 +1,6 @@
 CONFIG_SGI_IP28=y
 CONFIG_ARC_CONSOLE=y
 CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
@@ -35,10 +34,8 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 CONFIG_TCP_MD5SIG=y
 # CONFIG_IPV6 is not set
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
@@ -48,8 +45,6 @@ CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
 CONFIG_NET_ETHERNET=y
 CONFIG_SGISEEQ=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_MOUSE_PS2_ALPS is not set
 # CONFIG_MOUSE_PS2_SYNAPTICS is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index f9af98f63cff..1e26e58b9dc3 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -1,6 +1,5 @@
 CONFIG_SGI_IP32=y
 # CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
@@ -38,7 +37,6 @@ CONFIG_NET_IPGRE=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
-# CONFIG_INET_LRO is not set
 CONFIG_TCP_CONG_ADVANCED=y
 CONFIG_TCP_MD5SIG=y
 CONFIG_INET6_AH=m
@@ -76,8 +74,6 @@ CONFIG_NET_TULIP=y
 CONFIG_DE2104X=m
 CONFIG_TULIP=m
 CONFIG_TULIP_MMIO=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_INPUT_EVDEV=m
 # CONFIG_SERIO_I8042 is not set
 CONFIG_SERIO_MACEPS2=y
@@ -87,7 +83,6 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_WATCHDOG=y
-CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_GBE=y
@@ -117,7 +112,6 @@ CONFIG_EXT3_FS_SECURITY=y
 CONFIG_QUOTA=y
 CONFIG_QFMT_V1=m
 CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
 CONFIG_ISO9660_FS=m
@@ -178,8 +172,6 @@ CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KEYS=y
 CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_CBC=y
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index 3019fce63cd3..9ad1c94376c8 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -1,7 +1,6 @@
 CONFIG_MACH_JAZZ=y
 CONFIG_OLIVETTI_M700=y
 CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
@@ -85,7 +84,6 @@ CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
@@ -94,7 +92,6 @@ CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_NF_NAT=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
@@ -109,7 +106,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -120,7 +116,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
@@ -276,7 +271,6 @@ CONFIG_REISERFS_FS_POSIX_ACL=y
 CONFIG_REISERFS_FS_SECURITY=y
 CONFIG_XFS_FS=m
 CONFIG_XFS_QUOTA=y
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
 CONFIG_ISO9660_FS=m
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 9bc08f275120..af12281a5c33 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -18,23 +18,18 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_NET_PCI=y
 CONFIG_TC35815=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
@@ -58,5 +53,3 @@ CONFIG_PROC_KCORE=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
index e620a2c3eba4..947a35c7c46c 100644
--- a/arch/mips/configs/lasat_defconfig
+++ b/arch/mips/configs/lasat_defconfig
@@ -5,7 +5,6 @@ CONFIG_DS1603=y
 CONFIG_LASAT_SYSCTL=y
 CONFIG_HZ_1000=y
 # CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_EXPERT=y
@@ -31,7 +30,6 @@ CONFIG_INET=y
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
@@ -44,8 +42,6 @@ CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_NET_PCI=y
 CONFIG_PCNET32=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
@@ -56,7 +52,6 @@ CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_SERIAL_8250_PCI is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig
index 8df80c6383f2..1ec8ed8d05d1 100644
--- a/arch/mips/configs/lemote2f_defconfig
+++ b/arch/mips/configs/lemote2f_defconfig
@@ -7,7 +7,6 @@ CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_KEXEC=y
 # CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
@@ -83,8 +82,6 @@ CONFIG_NET_SCHED=y
 CONFIG_NET_EMATCH=y
 CONFIG_NET_CLS_ACT=y
 CONFIG_BT=m
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
 CONFIG_BT_RFCOMM=m
 CONFIG_BT_RFCOMM_TTY=y
 CONFIG_BT_BNEP=m
@@ -142,7 +139,6 @@ CONFIG_8139TOO=y
 # CONFIG_8139TOO_PIO is not set
 CONFIG_R8169=y
 CONFIG_R8169_VLAN=y
-# CONFIG_NETDEV_10000 is not set
 CONFIG_USB_USBNET=m
 CONFIG_USB_NET_CDC_EEM=m
 CONFIG_NETCONSOLE=m
@@ -205,7 +201,6 @@ CONFIG_USB_ZR364XX=m
 CONFIG_USB_STKWEBCAM=m
 CONFIG_USB_S2255=m
 # CONFIG_RADIO_ADAPTERS is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_MODE_HELPERS=y
@@ -290,7 +285,6 @@ CONFIG_HID_WACOM=m
 CONFIG_HID_ZEROPLUS=m
 CONFIG_ZEROPLUS_FF=y
 CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_DYNAMIC_MINORS=y
 CONFIG_USB_OTG_WHITELIST=y
 CONFIG_USB_MON=y
@@ -313,10 +307,8 @@ CONFIG_USB_STORAGE_SDDR09=m
 CONFIG_USB_STORAGE_SDDR55=m
 CONFIG_USB_STORAGE_JUMPSHOT=m
 CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_LIBUSUAL=y
 CONFIG_USB_SERIAL=m
 CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_LED=m
 CONFIG_USB_GADGET=m
 CONFIG_USB_GADGET_M66592=y
 CONFIG_MMC=m
@@ -341,7 +333,6 @@ CONFIG_XFS_POSIX_ACL=y
 CONFIG_BTRFS_FS=m
 CONFIG_QUOTA=y
 CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FSCACHE=m
 CONFIG_CACHEFILES=m
@@ -407,8 +398,6 @@ CONFIG_PRINTK_TIME=y
 CONFIG_FRAME_WARN=1024
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KEYS=y
 CONFIG_CRYPTO_FIPS=y
 CONFIG_CRYPTO_NULL=m
@@ -446,6 +435,5 @@ CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 CONFIG_CRC_T10DIF=y
diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig
index 7f95c4b3ab2c..324dfee23dfb 100644
--- a/arch/mips/configs/loongson3_defconfig
+++ b/arch/mips/configs/loongson3_defconfig
@@ -95,7 +95,6 @@ CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_ECN=m
 CONFIG_IP_NF_TARGET_TTL=m
@@ -252,7 +251,6 @@ CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=m
 CONFIG_DRM=y
 CONFIG_DRM_RADEON=y
-CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB_RADEON=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_PLATFORM=m
@@ -335,7 +333,6 @@ CONFIG_STRIP_ASM_SYMS=y
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_RCU_CPU_STALL_VERBOSE is not set
 # CONFIG_FTRACE is not set
 CONFIG_SECURITY=y
 CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/malta_kvm_defconfig b/arch/mips/configs/malta_kvm_defconfig
index e233f878afef..80ecd94ed126 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -133,7 +133,6 @@ CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig b/arch/mips/configs/malta_kvm_guest_defconfig
index fbe085c328ab..35ad1f8d1a79 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -132,7 +132,6 @@ CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
diff --git a/arch/mips/configs/malta_qemu_32r6_defconfig b/arch/mips/configs/malta_qemu_32r6_defconfig
index cbf37dd0c490..77145ecaa23b 100644
--- a/arch/mips/configs/malta_qemu_32r6_defconfig
+++ b/arch/mips/configs/malta_qemu_32r6_defconfig
@@ -42,7 +42,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
-# CONFIG_INET_LRO is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
diff --git a/arch/mips/configs/maltaaprp_defconfig b/arch/mips/configs/maltaaprp_defconfig
index 35f6ba260df8..cc2687cfdc13 100644
--- a/arch/mips/configs/maltaaprp_defconfig
+++ b/arch/mips/configs/maltaaprp_defconfig
@@ -43,7 +43,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
-# CONFIG_INET_LRO is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
@@ -135,7 +134,6 @@ CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=m
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_MATROX=y
diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig
index 900f14543eeb..55b68b981b05 100644
--- a/arch/mips/configs/maltasmvp_defconfig
+++ b/arch/mips/configs/maltasmvp_defconfig
@@ -46,7 +46,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
-# CONFIG_INET_LRO is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
diff --git a/arch/mips/configs/maltasmvp_eva_defconfig b/arch/mips/configs/maltasmvp_eva_defconfig
index 8e2738b5e180..5ca590cf1635 100644
--- a/arch/mips/configs/maltasmvp_eva_defconfig
+++ b/arch/mips/configs/maltasmvp_eva_defconfig
@@ -47,7 +47,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
-# CONFIG_INET_LRO is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
@@ -140,7 +139,6 @@ CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=m
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_MATROX=y
diff --git a/arch/mips/configs/maltaup_defconfig b/arch/mips/configs/maltaup_defconfig
index 6dc4e309a691..7ea7c0ba2666 100644
--- a/arch/mips/configs/maltaup_defconfig
+++ b/arch/mips/configs/maltaup_defconfig
@@ -42,7 +42,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
-# CONFIG_INET_LRO is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
@@ -134,7 +133,6 @@ CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=m
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_MATROX=y
diff --git a/arch/mips/configs/markeins_defconfig b/arch/mips/configs/markeins_defconfig
index 0f08e4623ee4..43ce6576ab1c 100644
--- a/arch/mips/configs/markeins_defconfig
+++ b/arch/mips/configs/markeins_defconfig
@@ -1,7 +1,6 @@
 CONFIG_NEC_MARKEINS=y
 CONFIG_HZ_1000=y
 CONFIG_PREEMPT=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
@@ -92,7 +91,6 @@ CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_NF_NAT=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
@@ -117,7 +115,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
@@ -125,7 +122,6 @@ CONFIG_IP6_NF_RAW=m
 CONFIG_FW_LOADER=m
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
diff --git a/arch/mips/configs/mips_paravirt_defconfig b/arch/mips/configs/mips_paravirt_defconfig
index 84cfcb4bf2ea..accf0db1dc6f 100644
--- a/arch/mips/configs/mips_paravirt_defconfig
+++ b/arch/mips/configs/mips_paravirt_defconfig
@@ -39,7 +39,6 @@ CONFIG_IP_MROUTE=y
 CONFIG_IP_PIMSM_V1=y
 CONFIG_IP_PIMSM_V2=y
 CONFIG_SYN_COOKIES=y
-# CONFIG_INET_LRO is not set
 CONFIG_IPV6=y
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index a2c045fab6c5..3486b034f726 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -1,6 +1,5 @@
 CONFIG_MACH_VR41XX=y
 CONFIG_VICTOR_MPC30X=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_RELAY=y
@@ -31,8 +30,6 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_PATA_LEGACY=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_USB_PEGASUS=m
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
@@ -45,13 +42,11 @@ CONFIG_SERIAL_VR41XX_CONSOLE=y
 CONFIG_GPIO_VR41XX=y
 # CONFIG_HWMON is not set
 # CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB=m
 CONFIG_USB_OHCI_HCD=m
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_VR41XX=y
 CONFIG_EXT2_FS=y
-CONFIG_AUTOFS_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_CONFIGFS_FS=m
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index 201edfb2637d..3c8c16b10732 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -2,7 +2,6 @@ CONFIG_PMC_MSP=y
 CONFIG_PMC_MSP7120_GW=y
 CONFIG_CPU_MIPS32_R2=y
 CONFIG_PREEMPT=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-pmc"
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -38,7 +37,6 @@ CONFIG_BRIDGE=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index f3f60056bc27..4011f1869e72 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -1,7 +1,6 @@
 CONFIG_MIPS_ALCHEMY=y
 CONFIG_MIPS_MTX1=y
 CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -81,7 +80,6 @@ CONFIG_NETFILTER_XT_MATCH_REALM=m
 CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
@@ -90,7 +88,6 @@ CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_ECN=m
 CONFIG_IP_NF_TARGET_TTL=m
@@ -98,7 +95,6 @@ CONFIG_IP_NF_RAW=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -108,7 +104,6 @@ CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
@@ -225,8 +220,6 @@ CONFIG_TOSHIBA_FIR=m
 CONFIG_VLSI_FIR=m
 CONFIG_MCS_FIR=m
 CONFIG_BT=m
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
 CONFIG_BT_RFCOMM=m
 CONFIG_BT_RFCOMM_TTY=y
 CONFIG_BT_BNEP=m
@@ -246,7 +239,6 @@ CONFIG_BT_HCIBTUART=m
 CONFIG_BT_HCIVHCI=m
 CONFIG_CONNECTOR=m
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
@@ -257,7 +249,6 @@ CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=m
 CONFIG_BLK_DEV_SD=m
 CONFIG_CHR_DEV_SG=m
@@ -596,7 +587,6 @@ CONFIG_USB_STORAGE_SDDR55=m
 CONFIG_USB_STORAGE_JUMPSHOT=m
 CONFIG_USB_STORAGE_ALAUDA=m
 CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_LIBUSUAL=y
 CONFIG_USB_MDC800=m
 CONFIG_USB_MICROTEK=m
 CONFIG_USB_SERIAL=m
@@ -640,7 +630,6 @@ CONFIG_USB_ADUTUX=m
 CONFIG_USB_RIO500=m
 CONFIG_USB_LEGOTOWER=m
 CONFIG_USB_LCD=m
-CONFIG_USB_LED=m
 CONFIG_USB_CYPRESS_CY7C63=m
 CONFIG_USB_CYTHERM=m
 CONFIG_USB_IDMOUSE=m
diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig
index 07d01827a973..5720ce23e9aa 100644
--- a/arch/mips/configs/nlm_xlp_defconfig
+++ b/arch/mips/configs/nlm_xlp_defconfig
@@ -6,7 +6,6 @@ CONFIG_KSM=y
 CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
 CONFIG_SMP=y
 # CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -183,14 +182,12 @@ CONFIG_IP_VS_SED=m
 CONFIG_IP_VS_NQ=m
 CONFIG_IP_VS_FTP=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_NF_NAT=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
@@ -317,7 +314,6 @@ CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
@@ -607,7 +603,6 @@ CONFIG_CRYPTO_SEED=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 CONFIG_CRC_CCITT=m
 CONFIG_CRC7=m
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
index f59969acb724..fea56c535d92 100644
--- a/arch/mips/configs/nlm_xlr_defconfig
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -7,7 +7,6 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_KEXEC=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_CROSS_COMPILE=""
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
@@ -163,7 +162,6 @@ CONFIG_IP_VS_SED=m
 CONFIG_IP_VS_NQ=m
 CONFIG_IP_VS_FTP=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
@@ -171,7 +169,6 @@ CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_NF_NAT=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
@@ -186,7 +183,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -197,7 +193,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
@@ -308,7 +303,6 @@ CONFIG_BLK_DEV_OSD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
 CONFIG_CDROM_PKTCDVD=y
-CONFIG_MISC_DEVICES=y
 CONFIG_RAID_ATTRS=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
@@ -369,7 +363,6 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1374=y
 # CONFIG_HWMON is not set
 # CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_UIO=y
 CONFIG_UIO_PDRV=m
@@ -522,7 +515,6 @@ CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_SCHED_TRACER=y
 CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_KGDB=y
@@ -568,7 +560,6 @@ CONFIG_CRYPTO_SEED=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 CONFIG_CRC_CCITT=m
 CONFIG_CRC7=m
diff --git a/arch/mips/configs/pnx8335_stb225_defconfig b/arch/mips/configs/pnx8335_stb225_defconfig
index c887066ecc2a..81b5eb89446c 100644
--- a/arch/mips/configs/pnx8335_stb225_defconfig
+++ b/arch/mips/configs/pnx8335_stb225_defconfig
@@ -5,7 +5,6 @@ CONFIG_HIGH_RES_TIMERS=y
 CONFIG_HZ_128=y
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -27,12 +26,10 @@ CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_INET_AH=y
-# CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
@@ -41,15 +38,12 @@ CONFIG_MTD_CFI_GEOMETRY=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_ATA=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=m
 CONFIG_INPUT_EVBUG=m
@@ -94,4 +88,3 @@ CONFIG_NLS_ASCII=m
 CONFIG_NLS_ISO8859_1=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_UTF8=m
-CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/mips/configs/qi_lb60_defconfig b/arch/mips/configs/qi_lb60_defconfig
index d7bb8cce1068..3f1333517405 100644
--- a/arch/mips/configs/qi_lb60_defconfig
+++ b/arch/mips/configs/qi_lb60_defconfig
@@ -34,7 +34,6 @@ CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_TCP_CONG_ADVANCED=y
 # CONFIG_TCP_CONG_BIC is not set
@@ -109,7 +108,6 @@ CONFIG_USB_GADGET_DEBUG=y
 CONFIG_USB_ETH=y
 # CONFIG_USB_ETH_RNDIS is not set
 CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_JZ4740=y
 CONFIG_RTC_CLASS=y
@@ -183,7 +181,6 @@ CONFIG_PANIC_ON_OOPS=y
 # CONFIG_FTRACE is not set
 CONFIG_KGDB=y
 CONFIG_RUNTIME_DEBUG=y
-CONFIG_CRYPTO_ZLIB=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_FONTS=y
 CONFIG_FONT_SUN8x16=y
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
index 5d9d708e12e5..6fa56c6e53f5 100644
--- a/arch/mips/configs/rb532_defconfig
+++ b/arch/mips/configs/rb532_defconfig
@@ -3,7 +3,6 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_HZ_100=y
 # CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
@@ -39,7 +38,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
 CONFIG_TCP_CONG_ADVANCED=y
 CONFIG_TCP_CONG_CUBIC=m
@@ -114,7 +112,6 @@ CONFIG_NET_CLS_IND=y
 CONFIG_HAMRADIO=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_BLOCK2MTD=y
 CONFIG_MTD_NAND=y
@@ -129,8 +126,6 @@ CONFIG_NET_ETHERNET=y
 CONFIG_KORINA=y
 CONFIG_NET_PCI=y
 CONFIG_VIA_RHINE=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_ATMEL=m
 CONFIG_PPP=m
 CONFIG_PPP_MULTILINK=y
@@ -183,7 +178,6 @@ CONFIG_BSD_DISKLABEL=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_CRYPTO=y
 CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_ZLIB=y
 # CONFIG_CRYPTO_HW is not set
 CONFIG_CRC16=m
 CONFIG_LIBCRC32C=m
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index 43d55e5abacb..fb195e29e449 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -31,12 +31,10 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=m
 CONFIG_MTD_BLOCK_RO=m
 CONFIG_MTD_CFI=y
@@ -50,7 +48,6 @@ CONFIG_MTD_NAND_TXX9NDFMC=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDE_TX4938=y
 CONFIG_BLK_DEV_IDE_TX4939=y
@@ -60,8 +57,6 @@ CONFIG_SMC91X=y
 CONFIG_NE2000=y
 CONFIG_NET_PCI=y
 CONFIG_TC35815=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_WLAN is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
@@ -108,5 +103,3 @@ CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index c2b4e3f33a73..99679e514042 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -3,7 +3,6 @@ CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_ARC_CONSOLE=y
 CONFIG_HZ_1000=y
 CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
@@ -94,7 +93,6 @@ CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
@@ -103,7 +101,6 @@ CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_NF_NAT=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
@@ -118,7 +115,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -129,7 +125,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
@@ -214,7 +209,6 @@ CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_UB=m
 CONFIG_BLK_DEV_RAM=m
 CONFIG_CDROM_PKTCDVD=m
 CONFIG_ATA_OVER_ETH=m
@@ -353,7 +347,6 @@ CONFIG_USB_SERIAL_OMNINET=m
 CONFIG_USB_RIO500=m
 CONFIG_USB_LEGOTOWER=m
 CONFIG_USB_LCD=m
-CONFIG_USB_LED=m
 CONFIG_USB_CYTHERM=m
 CONFIG_USB_SISUSBVGA=m
 CONFIG_USB_LD=m
@@ -366,7 +359,6 @@ CONFIG_REISERFS_FS_POSIX_ACL=y
 CONFIG_REISERFS_FS_SECURITY=y
 CONFIG_XFS_FS=m
 CONFIG_XFS_QUOTA=y
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
 CONFIG_ISO9660_FS=m
diff --git a/arch/mips/configs/rt305x_defconfig b/arch/mips/configs/rt305x_defconfig
index d14ae2fa7d13..c695b7b1c4ae 100644
--- a/arch/mips/configs/rt305x_defconfig
+++ b/arch/mips/configs/rt305x_defconfig
@@ -5,7 +5,6 @@ CONFIG_CPU_MIPS32_R2=y
 # CONFIG_CROSS_MEMORY_ATTACH is not set
 CONFIG_HZ_100=y
 # CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -44,7 +43,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_TCP_CONG_ADVANCED=y
 # CONFIG_TCP_CONG_BIC is not set
diff --git a/arch/mips/configs/sb1250_swarm_defconfig b/arch/mips/configs/sb1250_swarm_defconfig
index 7fca09fedb59..c724bdd6a7e6 100644
--- a/arch/mips/configs/sb1250_swarm_defconfig
+++ b/arch/mips/configs/sb1250_swarm_defconfig
@@ -4,7 +4,6 @@ CONFIG_64BIT=y
 CONFIG_SMP=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_HZ_1000=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=15
 CONFIG_CGROUPS=y
diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig
index 11f51505d562..4041597e3170 100644
--- a/arch/mips/configs/tb0219_defconfig
+++ b/arch/mips/configs/tb0219_defconfig
@@ -1,6 +1,5 @@
 CONFIG_MACH_VR41XX=y
 CONFIG_TANBAC_TB0219=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -31,7 +30,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_NETWORK_SECMARK=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -40,7 +38,6 @@ CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_XIP=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_PHYLIB=m
 CONFIG_MARVELL_PHY=m
@@ -57,7 +54,6 @@ CONFIG_VIA_RHINE=y
 CONFIG_VIA_RHINE_MMIO=y
 CONFIG_R8169=y
 CONFIG_VIA_VELOCITY=y
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
@@ -70,7 +66,6 @@ CONFIG_SERIAL_VR41XX_CONSOLE=y
 CONFIG_GPIO_TB0219=y
 # CONFIG_HWMON is not set
 # CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB=m
 CONFIG_USB_MON=m
 CONFIG_USB_EHCI_HCD=m
@@ -91,6 +86,5 @@ CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index 9327b3af32cd..565f0441c50d 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -1,6 +1,5 @@
 CONFIG_MACH_VR41XX=y
 CONFIG_TANBAC_TB0226=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -29,7 +28,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_NETWORK_SECMARK=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -37,7 +35,6 @@ CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_XIP=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -49,8 +46,6 @@ CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_NET_PCI=y
 CONFIG_E100=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_USB_CATC=m
 CONFIG_USB_KAWETH=m
 CONFIG_USB_PEGASUS=m
@@ -66,7 +61,6 @@ CONFIG_SERIAL_VR41XX_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
 # CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
@@ -87,7 +81,6 @@ CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200"
 CONFIG_CRC32=m
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index a967289b7970..a702be602fb9 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -1,5 +1,4 @@
 CONFIG_MACH_VR41XX=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -31,7 +30,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
 CONFIG_TCP_CONG_ADVANCED=y
 CONFIG_TCP_CONG_BIC=y
 CONFIG_TCP_CONG_CUBIC=m
@@ -43,7 +41,6 @@ CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_XIP=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_SCAN_ASYNC=y
 # CONFIG_SCSI_LOWLEVEL is not set
@@ -64,7 +61,6 @@ CONFIG_VIA_RHINE=y
 CONFIG_VIA_RHINE_MMIO=y
 CONFIG_R8169=y
 CONFIG_VIA_VELOCITY=y
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
@@ -76,7 +72,6 @@ CONFIG_SERIAL_VR41XX_CONSOLE=y
 CONFIG_GPIO_VR41XX=y
 # CONFIG_HWMON is not set
 CONFIG_MFD_SM501=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
 CONFIG_FB=y
 CONFIG_FB_SM501=y
 # CONFIG_VGA_CONSOLE is not set
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index ee4b2be43c44..a84eac409c9c 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -1,6 +1,5 @@
 CONFIG_MACH_VR41XX=y
 CONFIG_IBM_WORKPAD=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -28,13 +27,10 @@ CONFIG_IP_MULTICAST=y
 # CONFIG_IPV6 is not set
 CONFIG_NETWORK_SECMARK=y
 CONFIG_BLK_DEV_RAM=m
-# CONFIG_MISC_DEVICES is not set
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDECS=m
 CONFIG_IDE_GENERIC=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_NET_PCMCIA=y
 CONFIG_PCMCIA_3C589=m
 CONFIG_PCMCIA_3C574=m
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index a606b3f9196c..51ffbbaddee2 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -9,11 +9,31 @@ config LEGACY_BOARDS
          kernel is booted without being provided with an FDT via the UHI
          boot protocol.
+config YAMON_DT_SHIM
+        bool
+        help
+          Select this from your board if the board uses the YAMON bootloader
+          and you wish to include code which helps translate various
+          YAMON-provided environment variables into a device tree properties.
+comment "Legacy (non-UHI/non-FIT) Boards"
 config LEGACY_BOARD_SEAD3
        bool "Support MIPS SEAD-3 boards"
        select LEGACY_BOARDS
+        select YAMON_DT_SHIM
        help
          Enable this to include support for booting on MIPS SEAD-3 FPGA-based
          development boards, which boot using a legacy boot protocol.
+comment "FIT/UHI Boards"
+config FIT_IMAGE_FDT_BOSTON
+        bool "Include FDT for MIPS Boston boards"
+        help
+          Enable this to include the FDT for the MIPS Boston development board
+          from Imagination Technologies in the FIT kernel image. You should
+          enable this if you wish to boot on a MIPS Boston board, as it is
+          expected by the bootloader.
 endif
diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile
index acb9b6d62b16..56b3ea565ed9 100644
--- a/arch/mips/generic/Makefile
+++ b/arch/mips/generic/Makefile
@@ -12,5 +12,6 @@ obj-y += init.o
 obj-y += irq.o
 obj-y += proc.o
+obj-$(CONFIG_YAMON_DT_SHIM)             += yamon-dt.o
 obj-$(CONFIG_LEGACY_BOARD_SEAD3)        += board-sead3.o
 obj-$(CONFIG_KEXEC)                     += kexec.o
diff --git a/arch/mips/generic/board-sead3.c b/arch/mips/generic/board-sead3.c
index f4ae0584a33b..f109a6b9fdd0 100644
--- a/arch/mips/generic/board-sead3.c
+++ b/arch/mips/generic/board-sead3.c
@@ -13,10 +13,12 @@
 #include <linux/errno.h>
 #include <linux/libfdt.h>
 #include <linux/printk.h>
+#include <linux/sizes.h>
 #include <asm/fw/fw.h>
 #include <asm/io.h>
 #include <asm/machine.h>
+#include <asm/yamon-dt.h>
 #define SEAD_CONFIG                     CKSEG1ADDR(0x1b100110)
 #define SEAD_CONFIG_GIC_PRESENT         BIT(1)
@@ -25,6 +27,15 @@
 #define MIPS_REVISION_MACHINE           (0xf << 4)
 #define MIPS_REVISION_MACHINE_SEAD3     (0x4 << 4)
+/*
+ * Maximum 384MB RAM at physical address 0, preceding any I/O.
+ */
+static struct yamon_mem_region mem_regions[] __initdata = {
+        /* start        size */
+        { 0,            SZ_256M + SZ_128M },
+        {}
+};
 static __init bool sead3_detect(void)
 {
        uint32_t rev;
@@ -33,96 +44,9 @@ static __init bool sead3_detect(void)
        return (rev & MIPS_REVISION_MACHINE) == MIPS_REVISION_MACHINE_SEAD3;
 }
-static __init int append_cmdline(void *fdt)
-{
-        int err, chosen_off;
-        /* find or add chosen node */
-        chosen_off = fdt_path_offset(fdt, "/chosen");
-        if (chosen_off == -FDT_ERR_NOTFOUND)
-                chosen_off = fdt_path_offset(fdt, "/chosen@0");
-        if (chosen_off == -FDT_ERR_NOTFOUND)
-                chosen_off = fdt_add_subnode(fdt, 0, "chosen");
-        if (chosen_off < 0) {
-                pr_err("Unable to find or add DT chosen node: %d\n",
-                       chosen_off);
-                return chosen_off;
-        }
-        err = fdt_setprop_string(fdt, chosen_off, "bootargs", fw_getcmdline());
-        if (err) {
-                pr_err("Unable to set bootargs property: %d\n", err);
-                return err;
-        }
-        return 0;
-}
 static __init int append_memory(void *fdt)
 {
-        unsigned long phys_memsize, memsize;
+        return yamon_dt_append_memory(fdt, mem_regions);
-        __be32 mem_array[2];
-        int err, mem_off;
-        char *var;
-        /* find memory size from the bootloader environment */
-        var = fw_getenv("memsize");
-        if (var) {
-                err = kstrtoul(var, 0, &phys_memsize);
-                if (err) {
-                        pr_err("Failed to read memsize env variable '%s'\n",
-                               var);
-                        return -EINVAL;
-                }
-        } else {
-                pr_warn("The bootloader didn't provide memsize: defaulting to 32MB\n");
-                phys_memsize = 32 << 20;
-        }
-        /* default to using all available RAM */
-        memsize = phys_memsize;
-        /* allow the user to override the usable memory */
-        var = strstr(arcs_cmdline, "memsize=");
-        if (var)
-                memsize = memparse(var + strlen("memsize="), NULL);
-        /* if the user says there's more RAM than we thought, believe them */
-        phys_memsize = max_t(unsigned long, phys_memsize, memsize);
-        /* find or add a memory node */
-        mem_off = fdt_path_offset(fdt, "/memory");
-        if (mem_off == -FDT_ERR_NOTFOUND)
-                mem_off = fdt_add_subnode(fdt, 0, "memory");
-        if (mem_off < 0) {
-                pr_err("Unable to find or add memory DT node: %d\n", mem_off);
-                return mem_off;
-        }
-        err = fdt_setprop_string(fdt, mem_off, "device_type", "memory");
-        if (err) {
-                pr_err("Unable to set memory node device_type: %d\n", err);
-                return err;
-        }
-        mem_array[0] = 0;
-        mem_array[1] = cpu_to_be32(phys_memsize);
-        err = fdt_setprop(fdt, mem_off, "reg", mem_array, sizeof(mem_array));
-        if (err) {
-                pr_err("Unable to set memory regs property: %d\n", err);
-                return err;
-        }
-        mem_array[0] = 0;
-        mem_array[1] = cpu_to_be32(memsize);
-        err = fdt_setprop(fdt, mem_off, "linux,usable-memory",
-                          mem_array, sizeof(mem_array));
-        if (err) {
-                pr_err("Unable to set linux,usable-memory property: %d\n", err);
-                return err;
-        }
-        return 0;
 }
 static __init int remove_gic(void *fdt)
@@ -163,14 +87,16 @@ static __init int remove_gic(void *fdt)
                return -EINVAL;
        }
-        err = fdt_setprop_u32(fdt, 0, "interrupt-parent", cpu_phandle);
-        if (err) {
-                pr_err("unable to set root interrupt-parent: %d\n", err);
-                return err;
-        }
        uart_off = fdt_node_offset_by_compatible(fdt, -1, "ns16550a");
        while (uart_off >= 0) {
+                err = fdt_setprop_u32(fdt, uart_off, "interrupt-parent",
+                                      cpu_phandle);
+                if (err) {
+                        pr_warn("unable to set UART interrupt-parent: %d\n",
+                                err);
+                        return err;
+                }
                err = fdt_setprop_u32(fdt, uart_off, "interrupts",
                                      cpu_uart_int);
                if (err) {
@@ -193,6 +119,12 @@ static __init int remove_gic(void *fdt)
                return eth_off;
        }
+        err = fdt_setprop_u32(fdt, eth_off, "interrupt-parent", cpu_phandle);
+        if (err) {
+                pr_err("unable to set ethernet interrupt-parent: %d\n", err);
+                return err;
+        }
        err = fdt_setprop_u32(fdt, eth_off, "interrupts", cpu_eth_int);
        if (err) {
                pr_err("unable to set ethernet interrupts property: %d\n", err);
@@ -205,94 +137,29 @@ static __init int remove_gic(void *fdt)
                return ehci_off;
        }
-        err = fdt_setprop_u32(fdt, ehci_off, "interrupts", cpu_ehci_int);
+        err = fdt_setprop_u32(fdt, ehci_off, "interrupt-parent", cpu_phandle);
        if (err) {
-                pr_err("unable to set EHCI interrupts property: %d\n", err);
+                pr_err("unable to set EHCI interrupt-parent: %d\n", err);
                return err;
        }
-        return 0;
+        err = fdt_setprop_u32(fdt, ehci_off, "interrupts", cpu_ehci_int);
-}
-static __init int serial_config(void *fdt)
-{
-        const char *yamontty, *mode_var;
-        char mode_var_name[9], path[18], parity;
-        unsigned int uart, baud, stop_bits;
-        bool hw_flow;
-        int chosen_off, err;
-        yamontty = fw_getenv("yamontty");
-        if (!yamontty || !strcmp(yamontty, "tty0")) {
-                uart = 0;
-        } else if (!strcmp(yamontty, "tty1")) {
-                uart = 1;
-        } else {
-                pr_warn("yamontty environment variable '%s' invalid\n",
-                        yamontty);
-                uart = 0;
-        }
-        baud = stop_bits = 0;
-        parity = 0;
-        hw_flow = false;
-        snprintf(mode_var_name, sizeof(mode_var_name), "modetty%u", uart);
-        mode_var = fw_getenv(mode_var_name);
-        if (mode_var) {
-                while (mode_var[0] >= '0' && mode_var[0] <= '9') {
-                        baud *= 10;
-                        baud += mode_var[0] - '0';
-                        mode_var++;
-                }
-                if (mode_var[0] == ',')
-                        mode_var++;
-                if (mode_var[0])
-                        parity = mode_var[0];
-                if (mode_var[0] == ',')
-                        mode_var++;
-                if (mode_var[0])
-                        stop_bits = mode_var[0] - '0';
-                if (mode_var[0] == ',')
-                        mode_var++;
-                if (!strcmp(mode_var, "hw"))
-                        hw_flow = true;
-        }
-        if (!baud)
-                baud = 38400;
-        if (parity != 'e' && parity != 'n' && parity != 'o')
-                parity = 'n';
-        if (stop_bits != 7 && stop_bits != 8)
-                stop_bits = 8;
-        WARN_ON(snprintf(path, sizeof(path), "uart%u:%u%c%u%s",
-                         uart, baud, parity, stop_bits,
-                         hw_flow ? "r" : "") >= sizeof(path));
-        /* find or add chosen node */
-        chosen_off = fdt_path_offset(fdt, "/chosen");
-        if (chosen_off == -FDT_ERR_NOTFOUND)
-                chosen_off = fdt_path_offset(fdt, "/chosen@0");
-        if (chosen_off == -FDT_ERR_NOTFOUND)
-                chosen_off = fdt_add_subnode(fdt, 0, "chosen");
-        if (chosen_off < 0) {
-                pr_err("Unable to find or add DT chosen node: %d\n",
-                       chosen_off);
-                return chosen_off;
-        }
-        err = fdt_setprop_string(fdt, chosen_off, "stdout-path", path);
        if (err) {
-                pr_err("Unable to set stdout-path property: %d\n", err);
+                pr_err("unable to set EHCI interrupts property: %d\n", err);
                return err;
        }
        return 0;
 }
+static const struct mips_fdt_fixup sead3_fdt_fixups[] __initconst = {
+        { yamon_dt_append_cmdline, "append command line" },
+        { append_memory, "append memory" },
+        { remove_gic, "remove GIC when not present" },
+        { yamon_dt_serial_config, "append serial configuration" },
+        { },
+};
 static __init const void *sead3_fixup_fdt(const void *fdt,
                                          const void *match_data)
 {
@@ -307,29 +174,10 @@ static __init const void *sead3_fixup_fdt(const void *fdt,
        fw_init_cmdline();
-        err = fdt_open_into(fdt, fdt_buf, sizeof(fdt_buf));
+        err = apply_mips_fdt_fixups(fdt_buf, sizeof(fdt_buf),
-        if (err)
+                                    fdt, sead3_fdt_fixups);
-                panic("Unable to open FDT: %d", err);
-        err = append_cmdline(fdt_buf);
-        if (err)
-                panic("Unable to patch FDT: %d", err);
-        err = append_memory(fdt_buf);
-        if (err)
-                panic("Unable to patch FDT: %d", err);
-        err = remove_gic(fdt_buf);
-        if (err)
-                panic("Unable to patch FDT: %d", err);
-        err = serial_config(fdt_buf);
-        if (err)
-                panic("Unable to patch FDT: %d", err);
-        err = fdt_pack(fdt_buf);
        if (err)
-                panic("Unable to pack FDT: %d\n", err);
+                panic("Unable to fixup FDT: %d", err);
        return fdt_buf;
 }
diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c
index 1231b5a17b37..3f32b376d30e 100644
--- a/arch/mips/generic/init.c
+++ b/arch/mips/generic/init.c
@@ -122,6 +122,33 @@ void __init device_tree_init(void)
                err = register_up_smp_ops();
 }
+int __init apply_mips_fdt_fixups(void *fdt_out, size_t fdt_out_size,
+                                 const void *fdt_in,
+                                 const struct mips_fdt_fixup *fixups)
+{
+        int err;
+        err = fdt_open_into(fdt_in, fdt_out, fdt_out_size);
+        if (err) {
+                pr_err("Failed to open FDT\n");
+                return err;
+        }
+        for (; fixups->apply; fixups++) {
+                err = fixups->apply(fdt_out);
+                if (err) {
+                        pr_err("Failed to apply FDT fixup \"%s\"\n",
+                               fixups->description);
+                        return err;
+                }
+        }
+        err = fdt_pack(fdt_out);
+        if (err)
+                pr_err("Failed to pack FDT\n");
+        return err;
+}
 void __init plat_time_init(void)
 {
        struct device_node *np;
diff --git a/arch/mips/generic/vmlinux.its.S b/arch/mips/generic/vmlinux.its.S
index f67fbf1c8541..3390e2f80b80 100644
--- a/arch/mips/generic/vmlinux.its.S
+++ b/arch/mips/generic/vmlinux.its.S
@@ -29,3 +29,28 @@
                };
        };
 };
+#ifdef CONFIG_FIT_IMAGE_FDT_BOSTON
+/ {
+        images {
+                fdt@boston {
+                        description = "img,boston Device Tree";
+                        data = /incbin/("boot/dts/img/boston.dtb");
+                        type = "flat_dt";
+                        arch = "mips";
+                        compression = "none";
+                        hash@0 {
+                                algo = "sha1";
+                        };
+                };
+        };
+        configurations {
+                conf@boston {
+                        description = "Boston Linux kernel";
+                        kernel = "kernel@0";
+                        fdt = "fdt@boston";
+                };
+        };
+};
+#endif /* CONFIG_FIT_IMAGE_FDT_BOSTON */
diff --git a/arch/mips/generic/yamon-dt.c b/arch/mips/generic/yamon-dt.c
new file mode 100644
index 000000000000..6077bca9b364
--- /dev/null
+++ b/arch/mips/generic/yamon-dt.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#define pr_fmt(fmt) "yamon-dt: " fmt
+#include <linux/bug.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/libfdt.h>
+#include <linux/printk.h>
+#include <asm/fw/fw.h>
+#include <asm/yamon-dt.h>
+#define MAX_MEM_ARRAY_ENTRIES   2
+__init int yamon_dt_append_cmdline(void *fdt)
+{
+        int err, chosen_off;
+        /* find or add chosen node */
+        chosen_off = fdt_path_offset(fdt, "/chosen");
+        if (chosen_off == -FDT_ERR_NOTFOUND)
+                chosen_off = fdt_path_offset(fdt, "/chosen@0");
+        if (chosen_off == -FDT_ERR_NOTFOUND)
+                chosen_off = fdt_add_subnode(fdt, 0, "chosen");
+        if (chosen_off < 0) {
+                pr_err("Unable to find or add DT chosen node: %d\n",
+                       chosen_off);
+                return chosen_off;
+        }
+        err = fdt_setprop_string(fdt, chosen_off, "bootargs", fw_getcmdline());
+        if (err) {
+                pr_err("Unable to set bootargs property: %d\n", err);
+                return err;
+        }
+        return 0;
+}
+static unsigned int __init gen_fdt_mem_array(
+                                        const struct yamon_mem_region *regions,
+                                        __be32 *mem_array,
+                                        unsigned int max_entries,
+                                        unsigned long memsize)
+{
+        const struct yamon_mem_region *mr;
+        unsigned long size;
+        unsigned int entries = 0;
+        for (mr = regions; mr->size && memsize; ++mr) {
+                if (entries >= max_entries) {
+                        pr_warn("Number of regions exceeds max %u\n",
+                                max_entries);
+                        break;
+                }
+                /* How much of the remaining RAM fits in the next region? */
+                size = min_t(unsigned long, memsize, mr->size);
+                memsize -= size;
+                /* Emit a memory region */
+                *(mem_array++) = cpu_to_be32(mr->start);
+                *(mem_array++) = cpu_to_be32(size);
+                ++entries;
+                /* Discard the next mr->discard bytes */
+                memsize -= min_t(unsigned long, memsize, mr->discard);
+        }
+        return entries;
+}
+__init int yamon_dt_append_memory(void *fdt,
+                                  const struct yamon_mem_region *regions)
+{
+        unsigned long phys_memsize, memsize;
+        __be32 mem_array[2 * MAX_MEM_ARRAY_ENTRIES];
+        unsigned int mem_entries;
+        int i, err, mem_off;
+        char *var, param_name[10], *var_names[] = {
+                "ememsize", "memsize",
+        };
+        /* find memory size from the bootloader environment */
+        for (i = 0; i < ARRAY_SIZE(var_names); i++) {
+                var = fw_getenv(var_names[i]);
+                if (!var)
+                        continue;
+                err = kstrtoul(var, 0, &phys_memsize);
+                if (!err)
+                        break;
+                pr_warn("Failed to read the '%s' env variable '%s'\n",
+                        var_names[i], var);
+        }
+        if (!phys_memsize) {
+                pr_warn("The bootloader didn't provide memsize: defaulting to 32MB\n");
+                phys_memsize = 32 << 20;
+        }
+        /* default to using all available RAM */
+        memsize = phys_memsize;
+        /* allow the user to override the usable memory */
+        for (i = 0; i < ARRAY_SIZE(var_names); i++) {
+                snprintf(param_name, sizeof(param_name), "%s=", var_names[i]);
+                var = strstr(arcs_cmdline, param_name);
+                if (!var)
+                        continue;
+                memsize = memparse(var + strlen(param_name), NULL);
+        }
+        /* if the user says there's more RAM than we thought, believe them */
+        phys_memsize = max_t(unsigned long, phys_memsize, memsize);
+        /* find or add a memory node */
+        mem_off = fdt_path_offset(fdt, "/memory");
+        if (mem_off == -FDT_ERR_NOTFOUND)
+                mem_off = fdt_add_subnode(fdt, 0, "memory");
+        if (mem_off < 0) {
+                pr_err("Unable to find or add memory DT node: %d\n", mem_off);
+                return mem_off;
+        }
+        err = fdt_setprop_string(fdt, mem_off, "device_type", "memory");
+        if (err) {
+                pr_err("Unable to set memory node device_type: %d\n", err);
+                return err;
+        }
+        mem_entries = gen_fdt_mem_array(regions, mem_array,
+                                        MAX_MEM_ARRAY_ENTRIES, phys_memsize);
+        err = fdt_setprop(fdt, mem_off, "reg",
+                          mem_array, mem_entries * 2 * sizeof(mem_array[0]));
+        if (err) {
+                pr_err("Unable to set memory regs property: %d\n", err);
+                return err;
+        }
+        mem_entries = gen_fdt_mem_array(regions, mem_array,
+                                        MAX_MEM_ARRAY_ENTRIES, memsize);
+        err = fdt_setprop(fdt, mem_off, "linux,usable-memory",
+                          mem_array, mem_entries * 2 * sizeof(mem_array[0]));
+        if (err) {
+                pr_err("Unable to set linux,usable-memory property: %d\n", err);
+                return err;
+        }
+        return 0;
+}
+__init int yamon_dt_serial_config(void *fdt)
+{
+        const char *yamontty, *mode_var;
+        char mode_var_name[9], path[20], parity;
+        unsigned int uart, baud, stop_bits;
+        bool hw_flow;
+        int chosen_off, err;
+        yamontty = fw_getenv("yamontty");
+        if (!yamontty || !strcmp(yamontty, "tty0")) {
+                uart = 0;
+        } else if (!strcmp(yamontty, "tty1")) {
+                uart = 1;
+        } else {
+                pr_warn("yamontty environment variable '%s' invalid\n",
+                        yamontty);
+                uart = 0;
+        }
+        baud = stop_bits = 0;
+        parity = 0;
+        hw_flow = false;
+        snprintf(mode_var_name, sizeof(mode_var_name), "modetty%u", uart);
+        mode_var = fw_getenv(mode_var_name);
+        if (mode_var) {
+                while (mode_var[0] >= '0' && mode_var[0] <= '9') {
+                        baud *= 10;
+                        baud += mode_var[0] - '0';
+                        mode_var++;
+                }
+                if (mode_var[0] == ',')
+                        mode_var++;
+                if (mode_var[0])
+                        parity = mode_var[0];
+                if (mode_var[0] == ',')
+                        mode_var++;
+                if (mode_var[0])
+                        stop_bits = mode_var[0] - '0';
+                if (mode_var[0] == ',')
+                        mode_var++;
+                if (!strcmp(mode_var, "hw"))
+                        hw_flow = true;
+        }
+        if (!baud)
+                baud = 38400;
+        if (parity != 'e' && parity != 'n' && parity != 'o')
+                parity = 'n';
+        if (stop_bits != 7 && stop_bits != 8)
+                stop_bits = 8;
+        WARN_ON(snprintf(path, sizeof(path), "serial%u:%u%c%u%s",
+                         uart, baud, parity, stop_bits,
+                         hw_flow ? "r" : "") >= sizeof(path));
+        /* find or add chosen node */
+        chosen_off = fdt_path_offset(fdt, "/chosen");
+        if (chosen_off == -FDT_ERR_NOTFOUND)
+                chosen_off = fdt_path_offset(fdt, "/chosen@0");
+        if (chosen_off == -FDT_ERR_NOTFOUND)
+                chosen_off = fdt_add_subnode(fdt, 0, "chosen");
+        if (chosen_off < 0) {
+                pr_err("Unable to find or add DT chosen node: %d\n",
+                       chosen_off);
+                return chosen_off;
+        }
+        err = fdt_setprop_string(fdt, chosen_off, "stdout-path", path);
+        if (err) {
+                pr_err("Unable to set stdout-path property: %d\n", err);
+                return err;
+        }
+        return 0;
+}
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 2535c7b4c482..7c8aab23bce8 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -12,6 +12,8 @@ generic-y += mm-arch-hooks.h
 generic-y += parport.h
 generic-y += percpu.h
 generic-y += preempt.h
+generic-y += qrwlock.h
+generic-y += qspinlock.h
 generic-y += sections.h
 generic-y += segment.h
 generic-y += serial.h
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index de781cf54bc7..da80878f2c0d 100644
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -74,10 +74,7 @@ static inline int compute_return_epc(struct pt_regs *regs)
                        return __microMIPS_compute_return_epc(regs);
                if (cpu_has_mips16)
                        return __MIPS16e_compute_return_epc(regs);
-                return regs->cp0_epc;
+        } else if (!delay_slot(regs)) {
-        }
-        if (!delay_slot(regs)) {
                regs->cp0_epc += 4;
                return 0;
        }
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index b71ab4a5fd50..903f3bf48419 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -13,153 +13,107 @@
 #include <asm/compiler.h>
 #include <asm/war.h>
-static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
+/*
-{
+ * Using a branch-likely instruction to check the result of an sc instruction
-        __u32 retval;
+ * works around a bug present in R10000 CPUs prior to revision 3.0 that could
+ * cause ll-sc sequences to execute non-atomically.
-        smp_mb__before_llsc();
+ */
+#if R10000_LLSC_WAR
-        if (kernel_uses_llsc && R10000_LLSC_WAR) {
+# define __scbeqz "beqzl"
-                unsigned long dummy;
+#else
+# define __scbeqz "beqz"
-                __asm__ __volatile__(
+#endif
-                "       .set    arch=r4000                              \n"
-                "1:     ll      %0, %3                  # xchg_u32      \n"
-                "       .set    mips0                                   \n"
-                "       move    %2, %z4                                 \n"
-                "       .set    arch=r4000                              \n"
-                "       sc      %2, %1                                  \n"
-                "       beqzl   %2, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
-                : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
-                : "memory");
-        } else if (kernel_uses_llsc) {
-                unsigned long dummy;
-                do {
-                        __asm__ __volatile__(
-                        "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
-                        "       ll      %0, %3          # xchg_u32      \n"
-                        "       .set    mips0                           \n"
-                        "       move    %2, %z4                         \n"
-                        "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
-                        "       sc      %2, %1                          \n"
-                        "       .set    mips0                           \n"
-                        : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
-                          "=&r" (dummy)
-                        : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
-                        : "memory");
-                } while (unlikely(!dummy));
-        } else {
-                unsigned long flags;
-                raw_local_irq_save(flags);
-                retval = *m;
-                *m = val;
-                raw_local_irq_restore(flags);   /* implies memory barrier  */
-        }
-        smp_llsc_mb();
-        return retval;
-}
-#ifdef CONFIG_64BIT
+/*
-static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
+ * These functions doesn't exist, so if they are called you'll either:
-{
+ *
-        __u64 retval;
+ * - Get an error at compile-time due to __compiletime_error, if supported by
+ *   your compiler.
-        smp_mb__before_llsc();
+ *
+ * or:
-        if (kernel_uses_llsc && R10000_LLSC_WAR) {
+ *
-                unsigned long dummy;
+ * - Get an error at link-time due to the call to the missing function.
+ */
-                __asm__ __volatile__(
+extern unsigned long __cmpxchg_called_with_bad_pointer(void)
-                "       .set    arch=r4000                              \n"
+        __compiletime_error("Bad argument size for cmpxchg");
-                "1:     lld     %0, %3                  # xchg_u64      \n"
+extern unsigned long __xchg_called_with_bad_pointer(void)
-                "       move    %2, %z4                                 \n"
+        __compiletime_error("Bad argument size for xchg");
-                "       scd     %2, %1                                  \n"
-                "       beqzl   %2, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
-                : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
-                : "memory");
-        } else if (kernel_uses_llsc) {
-                unsigned long dummy;
-                do {
-                        __asm__ __volatile__(
-                        "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
-                        "       lld     %0, %3          # xchg_u64      \n"
-                        "       move    %2, %z4                         \n"
-                        "       scd     %2, %1                          \n"
-                        "       .set    mips0                           \n"
-                        : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
-                          "=&r" (dummy)
-                        : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
-                        : "memory");
-                } while (unlikely(!dummy));
-        } else {
-                unsigned long flags;
-                raw_local_irq_save(flags);
-                retval = *m;
-                *m = val;
-                raw_local_irq_restore(flags);   /* implies memory barrier  */
-        }
-        smp_llsc_mb();
+#define __xchg_asm(ld, st, m, val)                                      \
+({                                                                      \
+        __typeof(*(m)) __ret;                                           \
+                                                                        \
+        if (kernel_uses_llsc) {                                         \
+                __asm__ __volatile__(                                   \
+                "       .set    push                            \n"     \
+                "       .set    noat                            \n"     \
+                "       .set    " MIPS_ISA_ARCH_LEVEL "         \n"     \
+                "1:     " ld "  %0, %2          # __xchg_asm    \n"     \
+                "       .set    mips0                           \n"     \
+                "       move    $1, %z3                         \n"     \
+                "       .set    " MIPS_ISA_ARCH_LEVEL "         \n"     \
+                "       " st "  $1, %1                          \n"     \
+                "\t" __scbeqz " $1, 1b                          \n"     \
+                "       .set    pop                             \n"     \
+                : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m)           \
+                : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)                  \
+                : "memory");                                            \
+        } else {                                                        \
+                unsigned long __flags;                                  \
+                                                                        \
+                raw_local_irq_save(__flags);                            \
+                __ret = *m;                                             \
+                *m = val;                                               \
+                raw_local_irq_restore(__flags);                         \
+        }                                                               \
+                                                                        \
+        __ret;                                                          \
+})
-        return retval;
+extern unsigned long __xchg_small(volatile void *ptr, unsigned long val,
-}
+                                  unsigned int size);
-#else
-extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
-#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
-#endif
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+static inline unsigned long __xchg(volatile void *ptr, unsigned long x,
+                                   int size)
 {
        switch (size) {
+        case 1:
+        case 2:
+                return __xchg_small(ptr, x, size);
        case 4:
-                return __xchg_u32(ptr, x);
+                return __xchg_asm("ll", "sc", (volatile u32 *)ptr, x);
        case 8:
-                return __xchg_u64(ptr, x);
+                if (!IS_ENABLED(CONFIG_64BIT))
-        }
+                        return __xchg_called_with_bad_pointer();
+                return __xchg_asm("lld", "scd", (volatile u64 *)ptr, x);
-        return x;
+        default:
+                return __xchg_called_with_bad_pointer();
+        }
 }
 #define xchg(ptr, x)                                                    \
 ({                                                                      \
-        BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc);                            \
+        __typeof__(*(ptr)) __res;                                       \
                                                                        \
-        ((__typeof__(*(ptr)))                                           \
+        smp_mb__before_llsc();                                          \
-                __xchg((unsigned long)(x), (ptr), sizeof(*(ptr))));     \
+                                                                        \
+        __res = (__typeof__(*(ptr)))                                    \
+                __xchg((ptr), (unsigned long)(x), sizeof(*(ptr)));      \
+                                                                        \
+        smp_llsc_mb();                                                  \
+                                                                        \
+        __res;                                                          \
 })
 #define __cmpxchg_asm(ld, st, m, old, new)                              \
 ({                                                                      \
        __typeof(*(m)) __ret;                                           \
                                                                        \
-        if (kernel_uses_llsc && R10000_LLSC_WAR) {                      \
+        if (kernel_uses_llsc) {                                         \
-                __asm__ __volatile__(                                   \
-                "       .set    push                            \n"     \
-                "       .set    noat                            \n"     \
-                "       .set    arch=r4000                      \n"     \
-                "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \
-                "       bne     %0, %z3, 2f                     \n"     \
-                "       .set    mips0                           \n"     \
-                "       move    $1, %z4                         \n"     \
-                "       .set    arch=r4000                      \n"     \
-                "       " st "  $1, %1                          \n"     \
-                "       beqzl   $1, 1b                          \n"     \
-                "2:                                             \n"     \
-                "       .set    pop                             \n"     \
-                : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m)           \
-                : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new)              \
-                : "memory");                                            \
-        } else if (kernel_uses_llsc) {                                  \
                __asm__ __volatile__(                                   \
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
@@ -170,7 +124,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
                "       move    $1, %z4                         \n"     \
                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"     \
                "       " st "  $1, %1                          \n"     \
-                "       beqz    $1, 1b                          \n"     \
+                "\t" __scbeqz " $1, 1b                          \n"     \
                "       .set    pop                             \n"     \
                "2:                                             \n"     \
                : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m)           \
@@ -189,44 +143,50 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
        __ret;                                                          \
 })
-/*
+extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
- * This function doesn't exist, so you'll get a linker error
+                                     unsigned long new, unsigned int size);
- * if something tries to do an invalid cmpxchg().
- */
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
-extern void __cmpxchg_called_with_bad_pointer(void);
+                                      unsigned long new, unsigned int size)
+{
+        switch (size) {
+        case 1:
+        case 2:
+                return __cmpxchg_small(ptr, old, new, size);
+        case 4:
+                return __cmpxchg_asm("ll", "sc", (volatile u32 *)ptr, old, new);
+        case 8:
+                /* lld/scd are only available for MIPS64 */
+                if (!IS_ENABLED(CONFIG_64BIT))
+                        return __cmpxchg_called_with_bad_pointer();
+                return __cmpxchg_asm("lld", "scd", (volatile u64 *)ptr, old, new);
-#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier)             \
+        default:
+                return __cmpxchg_called_with_bad_pointer();
+        }
+}
+#define cmpxchg_local(ptr, old, new)                                    \
+        ((__typeof__(*(ptr)))                                           \
+                __cmpxchg((ptr),                                        \
+                          (unsigned long)(__typeof__(*(ptr)))(old),     \
+                          (unsigned long)(__typeof__(*(ptr)))(new),     \
+                          sizeof(*(ptr))))
+#define cmpxchg(ptr, old, new)                                          \
 ({                                                                      \
-        __typeof__(ptr) __ptr = (ptr);                                  \
+        __typeof__(*(ptr)) __res;                                       \
-        __typeof__(*(ptr)) __old = (old);                               \
-        __typeof__(*(ptr)) __new = (new);                               \
-        __typeof__(*(ptr)) __res = 0;                                   \
                                                                        \
-        pre_barrier;                                                    \
+        smp_mb__before_llsc();                                          \
-                                                                        \
+        __res = cmpxchg_local((ptr), (old), (new));                     \
-        switch (sizeof(*(__ptr))) {                                     \
+        smp_llsc_mb();                                                  \
-        case 4:                                                         \
-                __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \
-                break;                                                  \
-        case 8:                                                         \
-                if (sizeof(long) == 8) {                                \
-                        __res = __cmpxchg_asm("lld", "scd", __ptr,      \
-                                           __old, __new);               \
-                        break;                                          \
-                }                                                       \
-        default:                                                        \
-                __cmpxchg_called_with_bad_pointer();                    \
-                break;                                                  \
-        }                                                               \
-                                                                        \
-        post_barrier;                                                   \
                                                                        \
        __res;                                                          \
 })
-#define cmpxchg(ptr, old, new)          __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
-#define cmpxchg_local(ptr, old, new)    __cmpxchg(ptr, old, new, , )
 #ifdef CONFIG_64BIT
 #define cmpxchg64_local(ptr, o, n)                                      \
  ({                                                                    \
@@ -245,4 +205,6 @@ extern void __cmpxchg_called_with_bad_pointer(void);
 #define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
 #endif
+#undef __scbeqz
 #endif /* __ASM_CMPXCHG_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 494d38274142..8baa9033b181 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -138,6 +138,9 @@
 #ifndef cpu_has_mips16
 #define cpu_has_mips16          (cpu_data[0].ases & MIPS_ASE_MIPS16)
 #endif
+#ifndef cpu_has_mips16e2
+#define cpu_has_mips16e2        (cpu_data[0].ases & MIPS_ASE_MIPS16E2)
+#endif
 #ifndef cpu_has_mdmx
 #define cpu_has_mdmx            (cpu_data[0].ases & MIPS_ASE_MDMX)
 #endif
@@ -487,6 +490,47 @@
 # define cpu_has_perf           (cpu_data[0].options & MIPS_CPU_PERF)
 #endif
+#if defined(CONFIG_SMP) && defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
+/*
+ * Some systems share FTLB RAMs between threads within a core (siblings in
+ * kernel parlance). This means that FTLB entries may become invalid at almost
+ * any point when an entry is evicted due to a sibling thread writing an entry
+ * to the shared FTLB RAM.
+ *
+ * This is only relevant to SMP systems, and the only systems that exhibit this
+ * property implement MIPSr6 or higher so we constrain support for this to
+ * kernels that will run on such systems.
+ */
+# ifndef cpu_has_shared_ftlb_ram
+#  define cpu_has_shared_ftlb_ram \
+        (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_RAM)
+# endif
+/*
+ * Some systems take this a step further & share FTLB entries between siblings.
+ * This is implemented as TLB writes happening as usual, but if an entry
+ * written by a sibling exists in the shared FTLB for a translation which would
+ * otherwise cause a TLB refill exception then the CPU will use the entry
+ * written by its sibling rather than triggering a refill & writing a matching
+ * TLB entry for itself.
+ *
+ * This is naturally only valid if a TLB entry is known to be suitable for use
+ * on all siblings in a CPU, and so it only takes effect when MMIDs are in use
+ * rather than ASIDs or when a TLB entry is marked global.
+ */
+# ifndef cpu_has_shared_ftlb_entries
+#  define cpu_has_shared_ftlb_entries \
+        (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES)
+# endif
+#endif /* SMP && __mips_isa_rev >= 6 */
+#ifndef cpu_has_shared_ftlb_ram
+# define cpu_has_shared_ftlb_ram 0
+#endif
+#ifndef cpu_has_shared_ftlb_entries
+# define cpu_has_shared_ftlb_entries 0
+#endif
 /*
 * Guest capabilities
 */
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index bdd6dc18e65c..175fe565f4e1 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -84,6 +84,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
        case CPU_I6400:
+        case CPU_I6500:
        case CPU_P6600:
 #endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 98f59307e6a3..d0c152b989f8 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -124,6 +124,7 @@
 #define PRID_IMP_P5600          0xa800
 #define PRID_IMP_I6400          0xa900
 #define PRID_IMP_M6250          0xab00
+#define PRID_IMP_I6500          0xb000
 /*
 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -247,6 +248,7 @@
 #define PRID_REV_LOONGSON3B_R1  0x0006
 #define PRID_REV_LOONGSON3B_R2  0x0007
 #define PRID_REV_LOONGSON3A_R2  0x0008
+#define PRID_REV_LOONGSON3A_R3  0x0009
 /*
 * Older processors used to encode processor version and revision in two
@@ -322,7 +324,7 @@ enum cpu_type_enum {
         */
        CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
        CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
-        CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
+        CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
        CPU_QEMU_GENERIC,
@@ -416,6 +418,10 @@ enum cpu_type_enum {
 #define MIPS_CPU_GUESTID        MBIT_ULL(51)    /* CPU uses VZ ASE GuestID feature */
 #define MIPS_CPU_DRG            MBIT_ULL(52)    /* CPU has VZ Direct Root to Guest (DRG) */
 #define MIPS_CPU_UFR            MBIT_ULL(53)    /* CPU supports User mode FR switching */
+#define MIPS_CPU_SHARED_FTLB_RAM \
+                                MBIT_ULL(54)    /* CPU shares FTLB RAM with another */
+#define MIPS_CPU_SHARED_FTLB_ENTRIES \
+                                MBIT_ULL(55)    /* CPU shares FTLB entries with another */
 /*
 * CPU ASE encodings
@@ -430,5 +436,6 @@ enum cpu_type_enum {
 #define MIPS_ASE_VZ             0x00000080 /* Virtualization ASE */
 #define MIPS_ASE_MSA            0x00000100 /* MIPS SIMD Architecture */
 #define MIPS_ASE_DSP3           0x00000200 /* Signal Processing ASE Rev 3*/
+#define MIPS_ASE_MIPS16E2       0x00000400 /* MIPS16e2 */
 #endif /* _ASM_CPU_H */
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index ddd1c918103b..c5d351786416 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -18,7 +18,7 @@
 #include <irq.h>
 #define IRQ_STACK_SIZE                  THREAD_SIZE
-#define IRQ_STACK_START                 (IRQ_STACK_SIZE - sizeof(unsigned long))
+#define IRQ_STACK_START                 (IRQ_STACK_SIZE - 16)
 extern void *irq_stack[NR_CPUS];
diff --git a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
index ade0356df257..e6a8108cde4e 100644
--- a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
@@ -40,6 +40,7 @@
 #endif
 #define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
 #define cpu_has_mdmx                    0
 #define cpu_has_mips3d                  0
 #define cpu_has_smartmips               0
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index c5b6eef0efa7..bace5b9ae4df 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -31,6 +31,7 @@
 #define cpu_has_ejtag                   1
 #define cpu_has_llsc                    1
 #define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
 #define cpu_has_mdmx                    0
 #define cpu_has_mips3d                  0
 #define cpu_has_smartmips               0
diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
index bc1167dbd4e3..b56cf10b91d3 100644
--- a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
@@ -19,6 +19,7 @@
 #define cpu_has_ejtag                   1
 #define cpu_has_llsc                    1
 #define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
 #define cpu_has_mdmx                    0
 #define cpu_has_mips3d                  0
 #define cpu_has_smartmips               0
diff --git a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
index 30c5cd9fd973..291fe90aafa5 100644
--- a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
@@ -37,6 +37,7 @@
 #endif
 #define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
 #define cpu_has_mdmx            0
 #define cpu_has_mips3d          0
 #define cpu_has_smartmips       0
diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
index 21eae03d752a..2ec10237688c 100644
--- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
@@ -27,6 +27,7 @@
 #define cpu_has_mcheck                  0
 #define cpu_has_ejtag                   0
 #define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
 #define cpu_has_mdmx                    0
 #define cpu_has_mips3d                  0
 #define cpu_has_smartmips               0
diff --git a/arch/mips/include/asm/mach-generic/mc146818rtc.h b/arch/mips/include/asm/mach-generic/mc146818rtc.h
index 0b9a942f079d..9c72e540ff56 100644
--- a/arch/mips/include/asm/mach-generic/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-generic/mc146818rtc.h
@@ -27,7 +27,7 @@ static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
        outb_p(data, RTC_PORT(1));
 }
-#define RTC_ALWAYS_BCD  1
+#define RTC_ALWAYS_BCD  0
 #ifndef mc146818_decode_year
 #define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
index 9b19b72dba56..b80d5eafc9db 100644
--- a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
@@ -19,6 +19,7 @@
 #define cpu_has_32fpr           1
 #define cpu_has_counter         1
 #define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
 #define cpu_has_divec           0
 #define cpu_has_cache_cdex_p    1
 #define cpu_has_prefetch        0
diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
index 7449794eade6..136d6d464e32 100644
--- a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
@@ -43,6 +43,7 @@
 #define cpu_has_ejtag                   0
 #define cpu_has_llsc                    1
 #define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
 #define cpu_has_mdmx                    0
 #define cpu_has_mips3d                  0
 #define cpu_has_smartmips               0
diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
index 4cec06d133db..ba8b4e30b3e2 100644
--- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
@@ -16,6 +16,7 @@
 */
 #define cpu_has_watch           1
 #define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
 #define cpu_has_divec           0
 #define cpu_has_vce             0
 #define cpu_has_cache_cdex_p    0
diff --git a/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
index 241409b78ff1..63b4c889094b 100644
--- a/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
@@ -29,6 +29,7 @@
 #define cpu_has_32fpr           1
 #define cpu_has_counter         1
 #define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
 #define cpu_has_vce             0
 #define cpu_has_cache_cdex_s    0
 #define cpu_has_mcheck          0
diff --git a/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
index 0933f94a1e69..7c5e576f9d96 100644
--- a/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
@@ -23,6 +23,7 @@
 #define cpu_has_ejtag 1
 #define cpu_has_llsc            1
 #define cpu_has_mips16 0
+#define cpu_has_mips16e2        0
 #define cpu_has_mdmx 0
 #define cpu_has_mips3d 0
 #define cpu_has_smartmips 0
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index d3f3258b7cd4..9f9bb9c53785 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -27,12 +27,22 @@ struct efi_memory_map_loongson {
 } __packed;
 enum loongson_cpu_type {
-        Loongson_2E = 0,
+        Legacy_2E = 0x0,
-        Loongson_2F = 1,
+        Legacy_2F = 0x1,
-        Loongson_3A = 2,
+        Legacy_3A = 0x2,
-        Loongson_3B = 3,
+        Legacy_3B = 0x3,
-        Loongson_1A = 4,
+        Legacy_1A = 0x4,
-        Loongson_1B = 5
+        Legacy_1B = 0x5,
+        Legacy_2G = 0x6,
+        Legacy_2H = 0x7,
+        Loongson_1A = 0x100,
+        Loongson_1B = 0x101,
+        Loongson_2E = 0x200,
+        Loongson_2F = 0x201,
+        Loongson_2G = 0x202,
+        Loongson_2H = 0x203,
+        Loongson_3A = 0x300,
+        Loongson_3B = 0x301
 };
 /*
diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
index 89328a3d44d8..581915ce231c 100644
--- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -32,6 +32,7 @@
 #define cpu_has_mcheck          0
 #define cpu_has_mdmx            0
 #define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
 #define cpu_has_mips3d          0
 #define cpu_has_mipsmt          0
 #define cpu_has_smartmips       0
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 091deb1700e5..0c29ff820bb9 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -13,6 +13,7 @@
 #define cpu_has_4k_cache        1
 #define cpu_has_watch           1
 #define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
 #define cpu_has_counter         1
 #define cpu_has_divec           1
 #define cpu_has_vce             0
diff --git a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
index b15307597ee3..6a1087ee8c6e 100644
--- a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
@@ -48,6 +48,7 @@
 #define cpu_has_llsc                    1
 #define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
 #define cpu_has_mdmx                    0
 #define cpu_has_mips3d                  0
 #define cpu_has_smartmips               0
diff --git a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
index d38be668e338..e1e182300fea 100644
--- a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
@@ -17,6 +17,7 @@
 #define cpu_has_counter         1
 #define cpu_has_watch           0
 #define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
 #define cpu_has_divec           0
 #define cpu_has_cache_cdex_p    1
 #define cpu_has_prefetch        0
diff --git a/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
index 92927b62b5a0..7022358057fd 100644
--- a/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
@@ -13,6 +13,7 @@
 */
 #define cpu_has_watch           1
 #define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
 #define cpu_has_divec           1
 #define cpu_has_vce             0
 #define cpu_has_cache_cdex_p    0
diff --git a/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
index 7f5144c6ce2d..b9d39dc45420 100644
--- a/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
@@ -6,6 +6,7 @@
 #define cpu_has_inclusive_pcaches       0
 #define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
 #define cpu_has_mdmx            0
 #define cpu_has_mips3d          0
 #define cpu_has_smartmips       0
diff --git a/arch/mips/include/asm/machine.h b/arch/mips/include/asm/machine.h
index 6b444cd9526f..ecb6c7335484 100644
--- a/arch/mips/include/asm/machine.h
+++ b/arch/mips/include/asm/machine.h
@@ -60,4 +60,35 @@ mips_machine_is_compatible(const struct mips_machine *mach, const void *fdt)
        return NULL;
 }
+/**
+ * struct mips_fdt_fixup - Describe a fixup to apply to an FDT
+ * @apply: applies the fixup to @fdt, returns zero on success else -errno
+ * @description: a short description of the fixup
+ *
+ * Describes a fixup applied to an FDT blob by the @apply function. The
+ * @description field provides a short description of the fixup intended for
+ * use in error messages if the @apply function returns non-zero.
+ */
+struct mips_fdt_fixup {
+        int (*apply)(void *fdt);
+        const char *description;
+};
+/**
+ * apply_mips_fdt_fixups() - apply fixups to an FDT blob
+ * @fdt_out: buffer in which to place the fixed-up FDT
+ * @fdt_out_size: the size of the @fdt_out buffer
+ * @fdt_in: the FDT blob
+ * @fixups: pointer to an array of fixups to be applied
+ *
+ * Loop through the array of fixups pointed to by @fixups, calling the apply
+ * function on each until either one returns an error or we reach the end of
+ * the list as indicated by an entry with a NULL apply field.
+ *
+ * Return: zero on success, else -errno
+ */
+extern int __init apply_mips_fdt_fixups(void *fdt_out, size_t fdt_out_size,
+                                        const void *fdt_in,
+                                        const struct mips_fdt_fixup *fixups);
 #endif /* __MIPS_ASM_MACHINE_H__ */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 6875b69f59f7..dbb0eceda2c6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -652,6 +652,7 @@
 #define MIPS_CONF5_SBRI         (_ULCAST_(1) << 6)
 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
+#define MIPS_CONF5_CA2          (_ULCAST_(1) << 14)
 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 702c273e67a9..e51add184717 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -47,8 +47,8 @@ typedef struct {
 #define Elf_Mips_Rel    Elf32_Rel
 #define Elf_Mips_Rela   Elf32_Rela
-#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM(rel.r_info)
+#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM((rel).r_info)
-#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE(rel.r_info)
+#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE((rel).r_info)
 #endif
@@ -65,8 +65,8 @@ typedef struct {
 #define Elf_Mips_Rel    Elf64_Mips_Rel
 #define Elf_Mips_Rela   Elf64_Mips_Rela
-#define ELF_MIPS_R_SYM(rel) (rel.r_sym)
+#define ELF_MIPS_R_SYM(rel) ((rel).r_sym)
-#define ELF_MIPS_R_TYPE(rel) (rel.r_type)
+#define ELF_MIPS_R_TYPE(rel) ((rel).r_type)
 #endif
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index a8df44d60607..a7d21da16b6a 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -9,431 +9,9 @@
 #ifndef _ASM_SPINLOCK_H
 #define _ASM_SPINLOCK_H
-#include <linux/compiler.h>
-#include <asm/barrier.h>
 #include <asm/processor.h>
-#include <asm/compiler.h>
+#include <asm/qrwlock.h>
-#include <asm/war.h>
+#include <asm/qspinlock.h>
-/*
- * Your basic SMP spinlocks, allowing only a single CPU anywhere
- *
- * Simple spin lock operations.  There are two variants, one clears IRQ's
- * on the local processor, one does not.
- *
- * These are fair FIFO ticket locks
- *
- * (the type definitions are in asm/spinlock_types.h)
- */
-/*
- * Ticket locks are conceptually two parts, one indicating the current head of
- * the queue, and the other indicating the current tail. The lock is acquired
- * by atomically noting the tail and incrementing it by one (thus adding
- * ourself to the queue and noting our position), then waiting until the head
- * becomes equal to the the initial value of the tail.
- */
-static inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
-        u32 counters = ACCESS_ONCE(lock->lock);
-        return ((counters >> 16) ^ counters) & 0xffff;
-}
-static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
-{
-        return lock.h.serving_now == lock.h.ticket;
-}
-#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
-static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
-{
-        u16 owner = READ_ONCE(lock->h.serving_now);
-        smp_rmb();
-        for (;;) {
-                arch_spinlock_t tmp = READ_ONCE(*lock);
-                if (tmp.h.serving_now == tmp.h.ticket ||
-                    tmp.h.serving_now != owner)
-                        break;
-                cpu_relax();
-        }
-        smp_acquire__after_ctrl_dep();
-}
-static inline int arch_spin_is_contended(arch_spinlock_t *lock)
-{
-        u32 counters = ACCESS_ONCE(lock->lock);
-        return (((counters >> 16) - counters) & 0xffff) > 1;
-}
-#define arch_spin_is_contended  arch_spin_is_contended
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
-        int my_ticket;
-        int tmp;
-        int inc = 0x10000;
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__ (
-                "       .set push               # arch_spin_lock        \n"
-                "       .set noreorder                                  \n"
-                "                                                       \n"
-                "1:     ll      %[ticket], %[ticket_ptr]                \n"
-                "       addu    %[my_ticket], %[ticket], %[inc]         \n"
-                "       sc      %[my_ticket], %[ticket_ptr]             \n"
-                "       beqzl   %[my_ticket], 1b                        \n"
-                "        nop                                            \n"
-                "       srl     %[my_ticket], %[ticket], 16             \n"
-                "       andi    %[ticket], %[ticket], 0xffff            \n"
-                "       bne     %[ticket], %[my_ticket], 4f             \n"
-                "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
-                "2:                                                     \n"
-                "       .subsection 2                                   \n"
-                "4:     andi    %[ticket], %[ticket], 0xffff            \n"
-                "       sll     %[ticket], 5                            \n"
-                "                                                       \n"
-                "6:     bnez    %[ticket], 6b                           \n"
-                "        subu   %[ticket], 1                            \n"
-                "                                                       \n"
-                "       lhu     %[ticket], %[serving_now_ptr]           \n"
-                "       beq     %[ticket], %[my_ticket], 2b             \n"
-                "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
-                "       b       4b                                      \n"
-                "        subu   %[ticket], %[ticket], 1                 \n"
-                "       .previous                                       \n"
-                "       .set pop                                        \n"
-                : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
-                  [serving_now_ptr] "+m" (lock->h.serving_now),
-                  [ticket] "=&r" (tmp),
-                  [my_ticket] "=&r" (my_ticket)
-                : [inc] "r" (inc));
-        } else {
-                __asm__ __volatile__ (
-                "       .set push               # arch_spin_lock        \n"
-                "       .set noreorder                                  \n"
-                "                                                       \n"
-                "1:     ll      %[ticket], %[ticket_ptr]                \n"
-                "       addu    %[my_ticket], %[ticket], %[inc]         \n"
-                "       sc      %[my_ticket], %[ticket_ptr]             \n"
-                "       beqz    %[my_ticket], 1b                        \n"
-                "        srl    %[my_ticket], %[ticket], 16             \n"
-                "       andi    %[ticket], %[ticket], 0xffff            \n"
-                "       bne     %[ticket], %[my_ticket], 4f             \n"
-                "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
-                "2:     .insn                                           \n"
-                "       .subsection 2                                   \n"
-                "4:     andi    %[ticket], %[ticket], 0xffff            \n"
-                "       sll     %[ticket], 5                            \n"
-                "                                                       \n"
-                "6:     bnez    %[ticket], 6b                           \n"
-                "        subu   %[ticket], 1                            \n"
-                "                                                       \n"
-                "       lhu     %[ticket], %[serving_now_ptr]           \n"
-                "       beq     %[ticket], %[my_ticket], 2b             \n"
-                "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
-                "       b       4b                                      \n"
-                "        subu   %[ticket], %[ticket], 1                 \n"
-                "       .previous                                       \n"
-                "       .set pop                                        \n"
-                : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
-                  [serving_now_ptr] "+m" (lock->h.serving_now),
-                  [ticket] "=&r" (tmp),
-                  [my_ticket] "=&r" (my_ticket)
-                : [inc] "r" (inc));
-        }
-        smp_llsc_mb();
-}
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
-        unsigned int serving_now = lock->h.serving_now + 1;
-        wmb();
-        lock->h.serving_now = (u16)serving_now;
-        nudge_writes();
-}
-static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
-{
-        int tmp, tmp2, tmp3;
-        int inc = 0x10000;
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__ (
-                "       .set push               # arch_spin_trylock     \n"
-                "       .set noreorder                                  \n"
-                "                                                       \n"
-                "1:     ll      %[ticket], %[ticket_ptr]                \n"
-                "       srl     %[my_ticket], %[ticket], 16             \n"
-                "       andi    %[now_serving], %[ticket], 0xffff       \n"
-                "       bne     %[my_ticket], %[now_serving], 3f        \n"
-                "        addu   %[ticket], %[ticket], %[inc]            \n"
-                "       sc      %[ticket], %[ticket_ptr]                \n"
-                "       beqzl   %[ticket], 1b                           \n"
-                "        li     %[ticket], 1                            \n"
-                "2:                                                     \n"
-                "       .subsection 2                                   \n"
-                "3:     b       2b                                      \n"
-                "        li     %[ticket], 0                            \n"
-                "       .previous                                       \n"
-                "       .set pop                                        \n"
-                : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
-                  [ticket] "=&r" (tmp),
-                  [my_ticket] "=&r" (tmp2),
-                  [now_serving] "=&r" (tmp3)
-                : [inc] "r" (inc));
-        } else {
-                __asm__ __volatile__ (
-                "       .set push               # arch_spin_trylock     \n"
-                "       .set noreorder                                  \n"
-                "                                                       \n"
-                "1:     ll      %[ticket], %[ticket_ptr]                \n"
-                "       srl     %[my_ticket], %[ticket], 16             \n"
-                "       andi    %[now_serving], %[ticket], 0xffff       \n"
-                "       bne     %[my_ticket], %[now_serving], 3f        \n"
-                "        addu   %[ticket], %[ticket], %[inc]            \n"
-                "       sc      %[ticket], %[ticket_ptr]                \n"
-                "       beqz    %[ticket], 1b                           \n"
-                "        li     %[ticket], 1                            \n"
-                "2:     .insn                                           \n"
-                "       .subsection 2                                   \n"
-                "3:     b       2b                                      \n"
-                "        li     %[ticket], 0                            \n"
-                "       .previous                                       \n"
-                "       .set pop                                        \n"
-                : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
-                  [ticket] "=&r" (tmp),
-                  [my_ticket] "=&r" (tmp2),
-                  [now_serving] "=&r" (tmp3)
-                : [inc] "r" (inc));
-        }
-        smp_llsc_mb();
-        return tmp;
-}
-/*
- * Read-write spinlocks, allowing multiple readers but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts but no interrupt
- * writers. For those circumstances we can "mix" irq-safe locks - any writer
- * needs to get a irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- */
-/*
- * read_can_lock - would read_trylock() succeed?
- * @lock: the rwlock in question.
- */
-#define arch_read_can_lock(rw)  ((rw)->lock >= 0)
-/*
- * write_can_lock - would write_trylock() succeed?
- * @lock: the rwlock in question.
- */
-#define arch_write_can_lock(rw) (!(rw)->lock)
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
-        unsigned int tmp;
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    noreorder       # arch_read_lock        \n"
-                "1:     ll      %1, %2                                  \n"
-                "       bltz    %1, 1b                                  \n"
-                "        addu   %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       .set    reorder                                 \n"
-                : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
-                : GCC_OFF_SMALL_ASM() (rw->lock)
-                : "memory");
-        } else {
-                do {
-                        __asm__ __volatile__(
-                        "1:     ll      %1, %2  # arch_read_lock        \n"
-                        "       bltz    %1, 1b                          \n"
-                        "        addu   %1, 1                           \n"
-                        "2:     sc      %1, %0                          \n"
-                        : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
-                        : GCC_OFF_SMALL_ASM() (rw->lock)
-                        : "memory");
-                } while (unlikely(!tmp));
-        }
-        smp_llsc_mb();
-}
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
-        unsigned int tmp;
-        smp_mb__before_llsc();
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "1:     ll      %1, %2          # arch_read_unlock      \n"
-                "       addiu   %1, -1                                  \n"
-                "       sc      %1, %0                                  \n"
-                "       beqzl   %1, 1b                                  \n"
-                : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
-                : GCC_OFF_SMALL_ASM() (rw->lock)
-                : "memory");
-        } else {
-                do {
-                        __asm__ __volatile__(
-                        "1:     ll      %1, %2  # arch_read_unlock      \n"
-                        "       addiu   %1, -1                          \n"
-                        "       sc      %1, %0                          \n"
-                        : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
-                        : GCC_OFF_SMALL_ASM() (rw->lock)
-                        : "memory");
-                } while (unlikely(!tmp));
-        }
-}
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
-        unsigned int tmp;
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    noreorder       # arch_write_lock       \n"
-                "1:     ll      %1, %2                                  \n"
-                "       bnez    %1, 1b                                  \n"
-                "        lui    %1, 0x8000                              \n"
-                "       sc      %1, %0                                  \n"
-                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       .set    reorder                                 \n"
-                : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
-                : GCC_OFF_SMALL_ASM() (rw->lock)
-                : "memory");
-        } else {
-                do {
-                        __asm__ __volatile__(
-                        "1:     ll      %1, %2  # arch_write_lock       \n"
-                        "       bnez    %1, 1b                          \n"
-                        "        lui    %1, 0x8000                      \n"
-                        "2:     sc      %1, %0                          \n"
-                        : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
-                        : GCC_OFF_SMALL_ASM() (rw->lock)
-                        : "memory");
-                } while (unlikely(!tmp));
-        }
-        smp_llsc_mb();
-}
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
-        smp_mb__before_llsc();
-        __asm__ __volatile__(
-        "                               # arch_write_unlock     \n"
-        "       sw      $0, %0                                  \n"
-        : "=m" (rw->lock)
-        : "m" (rw->lock)
-        : "memory");
-}
-static inline int arch_read_trylock(arch_rwlock_t *rw)
-{
-        unsigned int tmp;
-        int ret;
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    noreorder       # arch_read_trylock     \n"
-                "       li      %2, 0                                   \n"
-                "1:     ll      %1, %3                                  \n"
-                "       bltz    %1, 2f                                  \n"
-                "        addu   %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       .set    reorder                                 \n"
-                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                __WEAK_LLSC_MB
-                "       li      %2, 1                                   \n"
-                "2:                                                     \n"
-                : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
-                : GCC_OFF_SMALL_ASM() (rw->lock)
-                : "memory");
-        } else {
-                __asm__ __volatile__(
-                "       .set    noreorder       # arch_read_trylock     \n"
-                "       li      %2, 0                                   \n"
-                "1:     ll      %1, %3                                  \n"
-                "       bltz    %1, 2f                                  \n"
-                "        addu   %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       beqz    %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       .set    reorder                                 \n"
-                __WEAK_LLSC_MB
-                "       li      %2, 1                                   \n"
-                "2:     .insn                                           \n"
-                : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
-                : GCC_OFF_SMALL_ASM() (rw->lock)
-                : "memory");
-        }
-        return ret;
-}
-static inline int arch_write_trylock(arch_rwlock_t *rw)
-{
-        unsigned int tmp;
-        int ret;
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    noreorder       # arch_write_trylock    \n"
-                "       li      %2, 0                                   \n"
-                "1:     ll      %1, %3                                  \n"
-                "       bnez    %1, 2f                                  \n"
-                "        lui    %1, 0x8000                              \n"
-                "       sc      %1, %0                                  \n"
-                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                __WEAK_LLSC_MB
-                "       li      %2, 1                                   \n"
-                "       .set    reorder                                 \n"
-                "2:                                                     \n"
-                : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
-                : GCC_OFF_SMALL_ASM() (rw->lock)
-                : "memory");
-        } else {
-                do {
-                        __asm__ __volatile__(
-                        "       ll      %1, %3  # arch_write_trylock    \n"
-                        "       li      %2, 0                           \n"
-                        "       bnez    %1, 2f                          \n"
-                        "       lui     %1, 0x8000                      \n"
-                        "       sc      %1, %0                          \n"
-                        "       li      %2, 1                           \n"
-                        "2:     .insn                                   \n"
-                        : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp),
-                          "=&r" (ret)
-                        : GCC_OFF_SMALL_ASM() (rw->lock)
-                        : "memory");
-                } while (unlikely(!tmp));
-                smp_llsc_mb();
-        }
-        return ret;
-}
 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h
index 9b2528e612c0..177e722eb96c 100644
--- a/arch/mips/include/asm/spinlock_types.h
+++ b/arch/mips/include/asm/spinlock_types.h
@@ -1,37 +1,7 @@
 #ifndef _ASM_SPINLOCK_TYPES_H
 #define _ASM_SPINLOCK_TYPES_H
-#ifndef __LINUX_SPINLOCK_TYPES_H
+#include <asm-generic/qspinlock_types.h>
-# error "please don't include this file directly"
+#include <asm-generic/qrwlock_types.h>
-#endif
-#include <linux/types.h>
-#include <asm/byteorder.h>
-typedef union {
-        /*
-         * bits  0..15 : serving_now
-         * bits 16..31 : ticket
-         */
-        u32 lock;
-        struct {
-#ifdef __BIG_ENDIAN
-                u16 ticket;
-                u16 serving_now;
-#else
-                u16 serving_now;
-                u16 ticket;
-#endif
-        } h;
-} arch_spinlock_t;
-#define __ARCH_SPIN_LOCK_UNLOCKED       { .lock = 0 }
-typedef struct {
-        volatile unsigned int lock;
-} arch_rwlock_t;
-#define __ARCH_RW_LOCK_UNLOCKED         { 0 }
 #endif
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index d87882513ee3..7c713025b23f 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -85,7 +85,7 @@ static inline void syscall_set_return_value(struct task_struct *task,
 {
        if (error) {
                regs->regs[2] = -error;
-                regs->regs[7] = -1;
+                regs->regs[7] = 1;
        } else {
                regs->regs[2] = val;
                regs->regs[7] = 0;
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 3748f4d120a5..59dae37f6b8d 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -72,9 +72,12 @@ Ip_u1u2s3(_beq);
 Ip_u1u2s3(_beql);
 Ip_u1s2(_bgez);
 Ip_u1s2(_bgezl);
+Ip_u1s2(_bgtz);
+Ip_u1s2(_blez);
 Ip_u1s2(_bltz);
 Ip_u1s2(_bltzl);
 Ip_u1u2s3(_bne);
+Ip_u1(_break);
 Ip_u2s3u1(_cache);
 Ip_u1u2(_cfc1);
 Ip_u2u1(_cfcmsa);
@@ -82,19 +85,28 @@ Ip_u1u2(_ctc1);
 Ip_u2u1(_ctcmsa);
 Ip_u2u1s3(_daddiu);
 Ip_u3u1u2(_daddu);
+Ip_u1u2(_ddivu);
 Ip_u1(_di);
 Ip_u2u1msbu3(_dins);
 Ip_u2u1msbu3(_dinsm);
+Ip_u2u1msbu3(_dinsu);
 Ip_u1u2(_divu);
 Ip_u1u2u3(_dmfc0);
 Ip_u1u2u3(_dmtc0);
+Ip_u1u2(_dmultu);
 Ip_u2u1u3(_drotr);
 Ip_u2u1u3(_drotr32);
+Ip_u2u1(_dsbh);
+Ip_u2u1(_dshd);
 Ip_u2u1u3(_dsll);
 Ip_u2u1u3(_dsll32);
+Ip_u3u2u1(_dsllv);
 Ip_u2u1u3(_dsra);
+Ip_u2u1u3(_dsra32);
+Ip_u3u2u1(_dsrav);
 Ip_u2u1u3(_dsrl);
 Ip_u2u1u3(_dsrl32);
+Ip_u3u2u1(_dsrlv);
 Ip_u3u1u2(_dsubu);
 Ip_0(_eret);
 Ip_u2u1msbu3(_ext);
@@ -104,6 +116,7 @@ Ip_u1(_jal);
 Ip_u2u1(_jalr);
 Ip_u1(_jr);
 Ip_u2s3u1(_lb);
+Ip_u2s3u1(_lbu);
 Ip_u2s3u1(_ld);
 Ip_u3u1u2(_ldx);
 Ip_u2s3u1(_lh);
@@ -112,27 +125,35 @@ Ip_u2s3u1(_ll);
 Ip_u2s3u1(_lld);
 Ip_u1s2(_lui);
 Ip_u2s3u1(_lw);
+Ip_u2s3u1(_lwu);
 Ip_u3u1u2(_lwx);
 Ip_u1u2u3(_mfc0);
 Ip_u1u2u3(_mfhc0);
 Ip_u1(_mfhi);
 Ip_u1(_mflo);
+Ip_u3u1u2(_movn);
+Ip_u3u1u2(_movz);
 Ip_u1u2u3(_mtc0);
 Ip_u1u2u3(_mthc0);
 Ip_u1(_mthi);
 Ip_u1(_mtlo);
 Ip_u3u1u2(_mul);
+Ip_u1u2(_multu);
+Ip_u3u1u2(_nor);
 Ip_u3u1u2(_or);
 Ip_u2u1u3(_ori);
 Ip_u2s3u1(_pref);
 Ip_0(_rfe);
 Ip_u2u1u3(_rotr);
+Ip_u2s3u1(_sb);
 Ip_u2s3u1(_sc);
 Ip_u2s3u1(_scd);
 Ip_u2s3u1(_sd);
+Ip_u2s3u1(_sh);
 Ip_u2u1u3(_sll);
 Ip_u3u2u1(_sllv);
 Ip_s3s1s2(_slt);
+Ip_u2u1s3(_slti);
 Ip_u2u1s3(_sltiu);
 Ip_u3u1u2(_sltu);
 Ip_u2u1u3(_sra);
@@ -248,6 +269,15 @@ static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
                uasm_i_dsrl32(p, a1, a2, a3 - 32);
 }
+static inline void uasm_i_dsra_safe(u32 **p, unsigned int a1,
+                                    unsigned int a2, unsigned int a3)
+{
+        if (a3 < 32)
+                uasm_i_dsra(p, a1, a2, a3);
+        else
+                uasm_i_dsra32(p, a1, a2, a3 - 32);
+}
 /* Handle relocations. */
 struct uasm_reloc {
        u32 *addr;
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
index 8f4ca5dd992b..b7cd6cf77b83 100644
--- a/arch/mips/include/asm/vdso.h
+++ b/arch/mips/include/asm/vdso.h
@@ -79,8 +79,8 @@ union mips_vdso_data {
        struct {
                u64 xtime_sec;
                u64 xtime_nsec;
-                u32 wall_to_mono_sec;
+                u64 wall_to_mono_sec;
-                u32 wall_to_mono_nsec;
+                u64 wall_to_mono_nsec;
                u32 seq_count;
                u32 cs_shift;
                u8 clock_mode;
diff --git a/arch/mips/include/asm/yamon-dt.h b/arch/mips/include/asm/yamon-dt.h
new file mode 100644
index 000000000000..485cfe3e45e1
--- /dev/null
+++ b/arch/mips/include/asm/yamon-dt.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __MIPS_ASM_YAMON_DT_H__
+#define __MIPS_ASM_YAMON_DT_H__
+#include <linux/types.h>
+/**
+ * struct yamon_mem_region - Represents a contiguous range of physical RAM.
+ * @start:      Start physical address.
+ * @size:       Maximum size of region.
+ * @discard:    Length of additional memory to discard after the region.
+ */
+struct yamon_mem_region {
+        phys_addr_t     start;
+        phys_addr_t     size;
+        phys_addr_t     discard;
+};
+/**
+ * yamon_dt_append_cmdline() - Append YAMON-provided command line to /chosen
+ * @fdt: the FDT blob
+ *
+ * Write the YAMON-provided command line to the bootargs property of the
+ * /chosen node in @fdt.
+ *
+ * Return: 0 on success, else -errno
+ */
+extern __init int yamon_dt_append_cmdline(void *fdt);
+/**
+ * yamon_dt_append_memory() - Append YAMON-provided memory info to /memory
+ * @fdt:        the FDT blob
+ * @regions:    zero size terminated array of physical memory regions
+ *
+ * Generate a /memory node in @fdt based upon memory size information provided
+ * by YAMON in its environment and the @regions array.
+ *
+ * Return: 0 on success, else -errno
+ */
+extern __init int yamon_dt_append_memory(void *fdt,
+                                        const struct yamon_mem_region *regions);
+/**
+ * yamon_dt_serial_config() - Append YAMON-provided serial config to /chosen
+ * @fdt: the FDT blob
+ *
+ * Generate a stdout-path property in the /chosen node of @fdt, based upon
+ * information provided in the YAMON environment about the UART configuration
+ * of the system.
+ *
+ * Return: 0 on success, else -errno
+ */
+extern __init int yamon_dt_serial_config(void *fdt);
+#endif /* __MIPS_ASM_YAMON_DT_H__ */
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index b5e46ae872d3..d61897535926 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -276,12 +276,19 @@ enum lx_func {
 */
 enum bshfl_func {
        wsbh_op = 0x2,
-        dshd_op = 0x5,
        seb_op  = 0x10,
        seh_op  = 0x18,
 };
 /*
+ * DBSHFL opcodes
+ */
+enum dbshfl_func {
+        dsbh_op = 0x2,
+        dshd_op = 0x5,
+};
+/*
 * MSA minor opcodes.
 */
 enum msa_func {
@@ -755,6 +762,16 @@ struct msa_mi10_format {		/* MSA MI10 */
        ;))))))
 };
+struct dsp_format {             /* SPEC3 DSP format instructions */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int base : 5,
+        __BITFIELD_FIELD(unsigned int index : 5,
+        __BITFIELD_FIELD(unsigned int rd : 5,
+        __BITFIELD_FIELD(unsigned int op : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
 struct spec3_format {   /* SPEC3 */
        __BITFIELD_FIELD(unsigned int opcode:6,
        __BITFIELD_FIELD(unsigned int rs:5,
@@ -1046,6 +1063,7 @@ union mips_instruction {
        struct b_format b_format;
        struct ps_format ps_format;
        struct v_format v_format;
+        struct dsp_format dsp_format;
        struct spec3_format spec3_format;
        struct fb_format fb_format;
        struct fp0_format fp0_format;
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 9a0e37b92ce0..46c0581256f1 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -4,7 +4,7 @@
 extra-y         := head.o vmlinux.lds
-obj-y           += cpu-probe.o branch.o elf.o entry.o genex.o idle.o irq.o \
+obj-y           += cmpxchg.o cpu-probe.o branch.o elf.o entry.o genex.o idle.o irq.o \
                   process.o prom.o ptrace.o reset.o setup.o signal.o \
                   syscall.o time.o topology.o traps.o unaligned.o watch.o \
                   vdso.o cacheinfo.o
@@ -31,7 +31,6 @@ obj-$(CONFIG_SYNC_R4K)		+= sync-r4k.o
 obj-$(CONFIG_DEBUG_FS)          += segment.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-$(CONFIG_MODULES)           += module.o
-obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o
 obj-$(CONFIG_FTRACE_SYSCALLS)   += ftrace.o
 obj-$(CONFIG_FUNCTION_TRACER)   += mcount.o ftrace.o
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index f702a459a830..b79ed9af9886 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -399,7 +399,7 @@ int __MIPS16e_compute_return_epc(struct pt_regs *regs)
 *
 * @regs:       Pointer to pt_regs
 * @insn:       branch instruction to decode
- * @returns:    -EFAULT on error and forces SIGBUS, and on success
+ * @returns:    -EFAULT on error and forces SIGILL, and on success
 *              returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
 *              evaluating the branch.
 *
@@ -431,7 +431,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                        /* Fall through */
                case jr_op:
                        if (NO_R6EMU && insn.r_format.func == jr_op)
-                                goto sigill_r6;
+                                goto sigill_r2r6;
                        regs->cp0_epc = regs->regs[insn.r_format.rs];
                        break;
                }
@@ -446,7 +446,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                switch (insn.i_format.rt) {
                case bltzl_op:
                        if (NO_R6EMU)
-                                goto sigill_r6;
+                                goto sigill_r2r6;
                case bltz_op:
                        if ((long)regs->regs[insn.i_format.rs] < 0) {
                                epc = epc + 4 + (insn.i_format.simmediate << 2);
@@ -459,7 +459,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                case bgezl_op:
                        if (NO_R6EMU)
-                                goto sigill_r6;
+                                goto sigill_r2r6;
                case bgez_op:
                        if ((long)regs->regs[insn.i_format.rs] >= 0) {
                                epc = epc + 4 + (insn.i_format.simmediate << 2);
@@ -473,10 +473,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                case bltzal_op:
                case bltzall_op:
                        if (NO_R6EMU && (insn.i_format.rs ||
-                            insn.i_format.rt == bltzall_op)) {
+                            insn.i_format.rt == bltzall_op))
-                                ret = -SIGILL;
+                                goto sigill_r2r6;
-                                break;
-                        }
                        regs->regs[31] = epc + 8;
                        /*
                         * OK we are here either because we hit a NAL
@@ -507,10 +505,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                case bgezal_op:
                case bgezall_op:
                        if (NO_R6EMU && (insn.i_format.rs ||
-                            insn.i_format.rt == bgezall_op)) {
+                            insn.i_format.rt == bgezall_op))
-                                ret = -SIGILL;
+                                goto sigill_r2r6;
-                                break;
-                        }
                        regs->regs[31] = epc + 8;
                        /*
                         * OK we are here either because we hit a BAL
@@ -556,6 +552,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        /*
         * These are unconditional and in j_format.
         */
+        case jalx_op:
        case jal_op:
                regs->regs[31] = regs->cp0_epc + 8;
        case j_op:
@@ -573,7 +570,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
         */
        case beql_op:
                if (NO_R6EMU)
-                        goto sigill_r6;
+                        goto sigill_r2r6;
        case beq_op:
                if (regs->regs[insn.i_format.rs] ==
                    regs->regs[insn.i_format.rt]) {
@@ -587,7 +584,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        case bnel_op:
                if (NO_R6EMU)
-                        goto sigill_r6;
+                        goto sigill_r2r6;
        case bne_op:
                if (regs->regs[insn.i_format.rs] !=
                    regs->regs[insn.i_format.rt]) {
@@ -601,7 +598,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        case blezl_op: /* not really i_format */
                if (!insn.i_format.rt && NO_R6EMU)
-                        goto sigill_r6;
+                        goto sigill_r2r6;
        case blez_op:
                /*
                 * Compact branches for R6 for the
@@ -636,7 +633,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        case bgtzl_op:
                if (!insn.i_format.rt && NO_R6EMU)
-                        goto sigill_r6;
+                        goto sigill_r2r6;
        case bgtz_op:
                /*
                 * Compact branches for R6 for the
@@ -774,35 +771,27 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
 #else
        case bc6_op:
                /* Only valid for MIPS R6 */
-                if (!cpu_has_mips_r6) {
+                if (!cpu_has_mips_r6)
-                        ret = -SIGILL;
+                        goto sigill_r6;
-                        break;
-                }
                regs->cp0_epc += 8;
                break;
        case balc6_op:
-                if (!cpu_has_mips_r6) {
+                if (!cpu_has_mips_r6)
-                        ret = -SIGILL;
+                        goto sigill_r6;
-                        break;
-                }
                /* Compact branch: BALC */
                regs->regs[31] = epc + 4;
                epc += 4 + (insn.i_format.simmediate << 2);
                regs->cp0_epc = epc;
                break;
        case pop66_op:
-                if (!cpu_has_mips_r6) {
+                if (!cpu_has_mips_r6)
-                        ret = -SIGILL;
+                        goto sigill_r6;
-                        break;
-                }
                /* Compact branch: BEQZC || JIC */
                regs->cp0_epc += 8;
                break;
        case pop76_op:
-                if (!cpu_has_mips_r6) {
+                if (!cpu_has_mips_r6)
-                        ret = -SIGILL;
+                        goto sigill_r6;
-                        break;
-                }
                /* Compact branch: BNEZC || JIALC */
                if (!insn.i_format.rs) {
                        /* JIALC: set $31/ra */
@@ -814,10 +803,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        case pop10_op:
        case pop30_op:
                /* Only valid for MIPS R6 */
-                if (!cpu_has_mips_r6) {
+                if (!cpu_has_mips_r6)
-                        ret = -SIGILL;
+                        goto sigill_r6;
-                        break;
-                }
                /*
                 * Compact branches:
                 * bovc, beqc, beqzalc, bnvc, bnec, bnezlac
@@ -831,12 +818,18 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        return ret;
 sigill_dsp:
-        printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
+        pr_debug("%s: DSP branch but not DSP ASE - sending SIGILL.\n",
-        force_sig(SIGBUS, current);
+                 current->comm);
+        force_sig(SIGILL, current);
+        return -EFAULT;
+sigill_r2r6:
+        pr_debug("%s: R2 branch but r2-to-r6 emulator is not present - sending SIGILL.\n",
+                 current->comm);
+        force_sig(SIGILL, current);
        return -EFAULT;
 sigill_r6:
-        pr_info("%s: R2 branch but r2-to-r6 emulator is not preset - sending SIGILL.\n",
+        pr_debug("%s: R6 branch but no MIPSr6 ISA support - sending SIGILL.\n",
-                current->comm);
+                 current->comm);
        force_sig(SIGILL, current);
        return -EFAULT;
 }
diff --git a/arch/mips/kernel/cmpxchg.c b/arch/mips/kernel/cmpxchg.c
new file mode 100644
index 000000000000..7730f1d3434f
--- /dev/null
+++ b/arch/mips/kernel/cmpxchg.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2017 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/bitops.h>
+#include <asm/cmpxchg.h>
+unsigned long __xchg_small(volatile void *ptr, unsigned long val, unsigned int size)
+{
+        u32 old32, new32, load32, mask;
+        volatile u32 *ptr32;
+        unsigned int shift;
+        /* Check that ptr is naturally aligned */
+        WARN_ON((unsigned long)ptr & (size - 1));
+        /* Mask value to the correct size. */
+        mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
+        val &= mask;
+        /*
+         * Calculate a shift & mask that correspond to the value we wish to
+         * exchange within the naturally aligned 4 byte integerthat includes
+         * it.
+         */
+        shift = (unsigned long)ptr & 0x3;
+        if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+                shift ^= sizeof(u32) - size;
+        shift *= BITS_PER_BYTE;
+        mask <<= shift;
+        /*
+         * Calculate a pointer to the naturally aligned 4 byte integer that
+         * includes our byte of interest, and load its value.
+         */
+        ptr32 = (volatile u32 *)((unsigned long)ptr & ~0x3);
+        load32 = *ptr32;
+        do {
+                old32 = load32;
+                new32 = (load32 & ~mask) | (val << shift);
+                load32 = cmpxchg(ptr32, old32, new32);
+        } while (load32 != old32);
+        return (load32 & mask) >> shift;
+}
+unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
+                              unsigned long new, unsigned int size)
+{
+        u32 mask, old32, new32, load32;
+        volatile u32 *ptr32;
+        unsigned int shift;
+        u8 load;
+        /* Check that ptr is naturally aligned */
+        WARN_ON((unsigned long)ptr & (size - 1));
+        /* Mask inputs to the correct size. */
+        mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
+        old &= mask;
+        new &= mask;
+        /*
+         * Calculate a shift & mask that correspond to the value we wish to
+         * compare & exchange within the naturally aligned 4 byte integer
+         * that includes it.
+         */
+        shift = (unsigned long)ptr & 0x3;
+        if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+                shift ^= sizeof(u32) - size;
+        shift *= BITS_PER_BYTE;
+        mask <<= shift;
+        /*
+         * Calculate a pointer to the naturally aligned 4 byte integer that
+         * includes our byte of interest, and load its value.
+         */
+        ptr32 = (volatile u32 *)((unsigned long)ptr & ~0x3);
+        load32 = *ptr32;
+        while (true) {
+                /*
+                 * Ensure the byte we want to exchange matches the expected
+                 * old value, and if not then bail.
+                 */
+                load = (load32 & mask) >> shift;
+                if (load != old)
+                        return load;
+                /*
+                 * Calculate the old & new values of the naturally aligned
+                 * 4 byte integer that include the byte we want to exchange.
+                 * Attempt to exchange the old value for the new value, and
+                 * return if we succeed.
+                 */
+                old32 = (load32 & ~mask) | (old << shift);
+                new32 = (load32 & ~mask) | (new << shift);
+                load32 = cmpxchg(ptr32, old32, new32);
+                if (load32 == old32)
+                        return old;
+        }
+}
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index a00e87b0256d..b849fe6aad94 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -22,6 +22,7 @@
 #define GCR_CL_COHERENCE_OFS    0x2008
 #define GCR_CL_ID_OFS           0x2028
+#define CPC_CL_VC_STOP_OFS      0x2020
 #define CPC_CL_VC_RUN_OFS       0x2028
 .extern mips_cm_base
@@ -376,8 +377,12 @@ LEAF(mips_cps_boot_vpes)
        PTR_LI  t2, UNCAC_BASE
        PTR_ADD t1, t1, t2
-        /* Set VC_RUN to the VPE mask */
+        /* Start any other VPs that ought to be running */
        PTR_S   ta2, CPC_CL_VC_RUN_OFS(t1)
+        /* Ensure this VP stops running if it shouldn't be */
+        not     ta2
+        PTR_S   ta2, CPC_CL_VC_STOP_OFS(t1)
        ehb
 #elif defined(CONFIG_MIPS_MT)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 1aba27786bd5..d08afc7dc507 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -564,6 +564,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
                back_to_back_c0_hazard();
                break;
        case CPU_I6400:
+        case CPU_I6500:
                /* There's no way to disable the FTLB */
                if (!(flags & FTLB_EN))
                        return 1;
@@ -844,6 +845,8 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
                c->options |= MIPS_CPU_MVH;
        if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
                c->options |= MIPS_CPU_VP;
+        if (config5 & MIPS_CONF5_CA2)
+                c->ases |= MIPS_ASE_MIPS16E2;
        return config5 & MIPS_CONF_M;
 }
@@ -1635,6 +1638,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                c->cputype = CPU_I6400;
                __cpu_name[cpu] = "MIPS I6400";
                break;
+        case PRID_IMP_I6500:
+                c->cputype = CPU_I6500;
+                __cpu_name[cpu] = "MIPS I6500";
+                break;
        case PRID_IMP_M5150:
                c->cputype = CPU_M5150;
                __cpu_name[cpu] = "MIPS M5150";
@@ -1648,6 +1655,17 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
        decode_configs(c);
        spram_config();
+        switch (__get_cpu_type(c->cputype)) {
+        case CPU_I6500:
+                c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
+                /* fall-through */
+        case CPU_I6400:
+                c->options |= MIPS_CPU_SHARED_FTLB_RAM;
+                /* fall-through */
+        default:
+                break;
+        }
 }
 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
@@ -1831,6 +1849,12 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
                        set_elf_platform(cpu, "loongson3a");
                        set_isa(c, MIPS_CPU_ISA_M64R2);
                        break;
+                case PRID_REV_LOONGSON3A_R3:
+                        c->cputype = CPU_LOONGSON3;
+                        __cpu_name[cpu] = "ICT Loongson-3";
+                        set_elf_platform(cpu, "loongson3a");
+                        set_isa(c, MIPS_CPU_ISA_M64R2);
+                        break;
                }
                decode_configs(c);
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
index 659e6d3ae335..cb0c57f860d4 100644
--- a/arch/mips/kernel/mips-cm.c
+++ b/arch/mips/kernel/mips-cm.c
@@ -265,15 +265,34 @@ void mips_cm_lock_other(unsigned int core, unsigned int vp)
        u32 val;
        preempt_disable();
-        curr_core = current_cpu_data.core;
-        spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
-                          per_cpu(cm_core_lock_flags, curr_core));
        if (mips_cm_revision() >= CM_REV_CM3) {
                val = core << CM3_GCR_Cx_OTHER_CORE_SHF;
                val |= vp << CM3_GCR_Cx_OTHER_VP_SHF;
+                /*
+                 * We need to disable interrupts in SMP systems in order to
+                 * ensure that we don't interrupt the caller with code which
+                 * may modify the redirect register. We do so here in a
+                 * slightly obscure way by using a spin lock, since this has
+                 * the neat property of also catching any nested uses of
+                 * mips_cm_lock_other() leading to a deadlock or a nice warning
+                 * with lockdep enabled.
+                 */
+                spin_lock_irqsave(this_cpu_ptr(&cm_core_lock),
+                                  *this_cpu_ptr(&cm_core_lock_flags));
        } else {
-                BUG_ON(vp != 0);
+                WARN_ON(vp != 0);
+                /*
+                 * We only have a GCR_CL_OTHER per core in systems with
+                 * CM 2.5 & older, so have to ensure other VP(E)s don't
+                 * race with us.
+                 */
+                curr_core = current_cpu_data.core;
+                spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
+                                  per_cpu(cm_core_lock_flags, curr_core));
                val = core << CM_GCR_Cx_OTHER_CORENUM_SHF;
        }
@@ -288,10 +307,17 @@ void mips_cm_lock_other(unsigned int core, unsigned int vp)
 void mips_cm_unlock_other(void)
 {
-        unsigned curr_core = current_cpu_data.core;
+        unsigned int curr_core;
+        if (mips_cm_revision() < CM_REV_CM3) {
+                curr_core = current_cpu_data.core;
+                spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
+                                       per_cpu(cm_core_lock_flags, curr_core));
+        } else {
+                spin_unlock_irqrestore(this_cpu_ptr(&cm_core_lock),
+                                       *this_cpu_ptr(&cm_core_lock_flags));
+        }
-        spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
-                               per_cpu(cm_core_lock_flags, curr_core));
        preempt_enable();
 }
diff --git a/arch/mips/kernel/module-rela.c b/arch/mips/kernel/module-rela.c
deleted file mode 100644
index 781168834456..000000000000
--- a/arch/mips/kernel/module-rela.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- *  Copyright (C) 2001 Rusty Russell.
- *  Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
- *  Copyright (C) 2005 Thiemo Seufer
- *  Copyright (C) 2015 Imagination Technologies Ltd.
- */
-#include <linux/elf.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/moduleloader.h>
-extern int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v);
-static int apply_r_mips_32_rela(struct module *me, u32 *location, Elf_Addr v)
-{
-        *location = v;
-        return 0;
-}
-static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v)
-{
-        if (v % 4) {
-                pr_err("module %s: dangerous R_MIPS_26 RELA relocation\n",
-                       me->name);
-                return -ENOEXEC;
-        }
-        if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
-                pr_err("module %s: relocation overflow\n", me->name);
-                return -ENOEXEC;
-        }
-        *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff);
-        return 0;
-}
-static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v)
-{
-        *location = (*location & 0xffff0000) |
-                    ((((long long) v + 0x8000LL) >> 16) & 0xffff);
-        return 0;
-}
-static int apply_r_mips_lo16_rela(struct module *me, u32 *location, Elf_Addr v)
-{
-        *location = (*location & 0xffff0000) | (v & 0xffff);
-        return 0;
-}
-static int apply_r_mips_pc_rela(struct module *me, u32 *location, Elf_Addr v,
-                                unsigned bits)
-{
-        unsigned long mask = GENMASK(bits - 1, 0);
-        unsigned long se_bits;
-        long offset;
-        if (v % 4) {
-                pr_err("module %s: dangerous R_MIPS_PC%u RELA relocation\n",
-                       me->name, bits);
-                return -ENOEXEC;
-        }
-        offset = ((long)v - (long)location) >> 2;
-        /* check the sign bit onwards are identical - ie. we didn't overflow */
-        se_bits = (offset & BIT(bits - 1)) ? ~0ul : 0;
-        if ((offset & ~mask) != (se_bits & ~mask)) {
-                pr_err("module %s: relocation overflow\n", me->name);
-                return -ENOEXEC;
-        }
-        *location = (*location & ~mask) | (offset & mask);
-        return 0;
-}
-static int apply_r_mips_pc16_rela(struct module *me, u32 *location, Elf_Addr v)
-{
-        return apply_r_mips_pc_rela(me, location, v, 16);
-}
-static int apply_r_mips_pc21_rela(struct module *me, u32 *location, Elf_Addr v)
-{
-        return apply_r_mips_pc_rela(me, location, v, 21);
-}
-static int apply_r_mips_pc26_rela(struct module *me, u32 *location, Elf_Addr v)
-{
-        return apply_r_mips_pc_rela(me, location, v, 26);
-}
-static int apply_r_mips_64_rela(struct module *me, u32 *location, Elf_Addr v)
-{
-        *(Elf_Addr *)location = v;
-        return 0;
-}
-static int apply_r_mips_higher_rela(struct module *me, u32 *location,
-                                    Elf_Addr v)
-{
-        *location = (*location & 0xffff0000) |
-                    ((((long long) v + 0x80008000LL) >> 32) & 0xffff);
-        return 0;
-}
-static int apply_r_mips_highest_rela(struct module *me, u32 *location,
-                                     Elf_Addr v)
-{
-        *location = (*location & 0xffff0000) |
-                    ((((long long) v + 0x800080008000LL) >> 48) & 0xffff);
-        return 0;
-}
-static int (*reloc_handlers_rela[]) (struct module *me, u32 *location,
-                                Elf_Addr v) = {
-        [R_MIPS_NONE]           = apply_r_mips_none,
-        [R_MIPS_32]             = apply_r_mips_32_rela,
-        [R_MIPS_26]             = apply_r_mips_26_rela,
-        [R_MIPS_HI16]           = apply_r_mips_hi16_rela,
-        [R_MIPS_LO16]           = apply_r_mips_lo16_rela,
-        [R_MIPS_PC16]           = apply_r_mips_pc16_rela,
-        [R_MIPS_64]             = apply_r_mips_64_rela,
-        [R_MIPS_HIGHER]         = apply_r_mips_higher_rela,
-        [R_MIPS_HIGHEST]        = apply_r_mips_highest_rela,
-        [R_MIPS_PC21_S2]        = apply_r_mips_pc21_rela,
-        [R_MIPS_PC26_S2]        = apply_r_mips_pc26_rela,
-};
-int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
-                       unsigned int symindex, unsigned int relsec,
-                       struct module *me)
-{
-        Elf_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr;
-        int (*handler)(struct module *me, u32 *location, Elf_Addr v);
-        Elf_Sym *sym;
-        u32 *location;
-        unsigned int i, type;
-        Elf_Addr v;
-        int res;
-        pr_debug("Applying relocate section %u to %u\n", relsec,
-               sechdrs[relsec].sh_info);
-        for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
-                /* This is where to make the change */
-                location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
-                        + rel[i].r_offset;
-                /* This is the symbol it is referring to */
-                sym = (Elf_Sym *)sechdrs[symindex].sh_addr
-                        + ELF_MIPS_R_SYM(rel[i]);
-                if (sym->st_value >= -MAX_ERRNO) {
-                        /* Ignore unresolved weak symbol */
-                        if (ELF_ST_BIND(sym->st_info) == STB_WEAK)
-                                continue;
-                        pr_warn("%s: Unknown symbol %s\n",
-                               me->name, strtab + sym->st_name);
-                        return -ENOENT;
-                }
-                type = ELF_MIPS_R_TYPE(rel[i]);
-                if (type < ARRAY_SIZE(reloc_handlers_rela))
-                        handler = reloc_handlers_rela[type];
-                else
-                        handler = NULL;
-                if (!handler) {
-                        pr_err("%s: Unknown relocation type %u\n",
-                               me->name, type);
-                        return -EINVAL;
-                }
-                v = sym->st_value + rel[i].r_addend;
-                res = handler(me, location, v);
-                if (res)
-                        return res;
-        }
-        return 0;
-}
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index 50c020c47e54..491605137b03 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -53,22 +53,25 @@ void *module_alloc(unsigned long size)
 }
 #endif
-int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v)
+static int apply_r_mips_none(struct module *me, u32 *location,
+                             u32 base, Elf_Addr v, bool rela)
 {
        return 0;
 }
-static int apply_r_mips_32_rel(struct module *me, u32 *location, Elf_Addr v)
+static int apply_r_mips_32(struct module *me, u32 *location,
+                           u32 base, Elf_Addr v, bool rela)
 {
-        *location += v;
+        *location = base + v;
        return 0;
 }
-static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
+static int apply_r_mips_26(struct module *me, u32 *location,
+                           u32 base, Elf_Addr v, bool rela)
 {
        if (v % 4) {
-                pr_err("module %s: dangerous R_MIPS_26 REL relocation\n",
+                pr_err("module %s: dangerous R_MIPS_26 relocation\n",
                       me->name);
                return -ENOEXEC;
        }
@@ -80,15 +83,22 @@ static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
        }
        *location = (*location & ~0x03ffffff) |
-                    ((*location + (v >> 2)) & 0x03ffffff);
+                    ((base + (v >> 2)) & 0x03ffffff);
        return 0;
 }
-static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v)
+static int apply_r_mips_hi16(struct module *me, u32 *location,
+                             u32 base, Elf_Addr v, bool rela)
 {
        struct mips_hi16 *n;
+        if (rela) {
+                *location = (*location & 0xffff0000) |
+                            ((((long long) v + 0x8000LL) >> 16) & 0xffff);
+                return 0;
+        }
        /*
         * We cannot relocate this one now because we don't know the value of
         * the carry we need to add.  Save the information, and let LO16 do the
@@ -117,12 +127,18 @@ static void free_relocation_chain(struct mips_hi16 *l)
        }
 }
-static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
+static int apply_r_mips_lo16(struct module *me, u32 *location,
+                             u32 base, Elf_Addr v, bool rela)
 {
-        unsigned long insnlo = *location;
+        unsigned long insnlo = base;
        struct mips_hi16 *l;
        Elf_Addr val, vallo;
+        if (rela) {
+                *location = (*location & 0xffff0000) | (v & 0xffff);
+                return 0;
+        }
        /* Sign extend the addend we extract from the lo insn.  */
        vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
@@ -178,26 +194,26 @@ out_danger:
        free_relocation_chain(l);
        me->arch.r_mips_hi16_list = NULL;
-        pr_err("module %s: dangerous R_MIPS_LO16 REL relocation\n", me->name);
+        pr_err("module %s: dangerous R_MIPS_LO16 relocation\n", me->name);
        return -ENOEXEC;
 }
-static int apply_r_mips_pc_rel(struct module *me, u32 *location, Elf_Addr v,
+static int apply_r_mips_pc(struct module *me, u32 *location, u32 base,
-                               unsigned bits)
+                           Elf_Addr v, unsigned int bits)
 {
        unsigned long mask = GENMASK(bits - 1, 0);
        unsigned long se_bits;
        long offset;
        if (v % 4) {
-                pr_err("module %s: dangerous R_MIPS_PC%u REL relocation\n",
+                pr_err("module %s: dangerous R_MIPS_PC%u relocation\n",
                       me->name, bits);
                return -ENOEXEC;
        }
-        /* retrieve & sign extend implicit addend */
+        /* retrieve & sign extend implicit addend if any */
-        offset = *location & mask;
+        offset = base & mask;
        offset |= (offset & BIT(bits - 1)) ? ~mask : 0;
        offset += ((long)v - (long)location) >> 2;
@@ -214,99 +230,192 @@ static int apply_r_mips_pc_rel(struct module *me, u32 *location, Elf_Addr v,
        return 0;
 }
-static int apply_r_mips_pc16_rel(struct module *me, u32 *location, Elf_Addr v)
+static int apply_r_mips_pc16(struct module *me, u32 *location,
+                             u32 base, Elf_Addr v, bool rela)
+{
+        return apply_r_mips_pc(me, location, base, v, 16);
+}
+static int apply_r_mips_pc21(struct module *me, u32 *location,
+                             u32 base, Elf_Addr v, bool rela)
+{
+        return apply_r_mips_pc(me, location, base, v, 21);
+}
+static int apply_r_mips_pc26(struct module *me, u32 *location,
+                             u32 base, Elf_Addr v, bool rela)
+{
+        return apply_r_mips_pc(me, location, base, v, 26);
+}
+static int apply_r_mips_64(struct module *me, u32 *location,
+                           u32 base, Elf_Addr v, bool rela)
 {
-        return apply_r_mips_pc_rel(me, location, v, 16);
+        if (WARN_ON(!rela))
+                return -EINVAL;
+        *(Elf_Addr *)location = v;
+        return 0;
 }
-static int apply_r_mips_pc21_rel(struct module *me, u32 *location, Elf_Addr v)
+static int apply_r_mips_higher(struct module *me, u32 *location,
+                               u32 base, Elf_Addr v, bool rela)
 {
-        return apply_r_mips_pc_rel(me, location, v, 21);
+        if (WARN_ON(!rela))
+                return -EINVAL;
+        *location = (*location & 0xffff0000) |
+                    ((((long long)v + 0x80008000LL) >> 32) & 0xffff);
+        return 0;
 }
-static int apply_r_mips_pc26_rel(struct module *me, u32 *location, Elf_Addr v)
+static int apply_r_mips_highest(struct module *me, u32 *location,
+                                u32 base, Elf_Addr v, bool rela)
 {
-        return apply_r_mips_pc_rel(me, location, v, 26);
+        if (WARN_ON(!rela))
+                return -EINVAL;
+        *location = (*location & 0xffff0000) |
+                    ((((long long)v + 0x800080008000LL) >> 48) & 0xffff);
+        return 0;
 }
-static int (*reloc_handlers_rel[]) (struct module *me, u32 *location,
+/**
-                                Elf_Addr v) = {
+ * reloc_handler() - Apply a particular relocation to a module
+ * @me: the module to apply the reloc to
+ * @location: the address at which the reloc is to be applied
+ * @base: the existing value at location for REL-style; 0 for RELA-style
+ * @v: the value of the reloc, with addend for RELA-style
+ *
+ * Each implemented reloc_handler function applies a particular type of
+ * relocation to the module @me. Relocs that may be found in either REL or RELA
+ * variants can be handled by making use of the @base & @v parameters which are
+ * set to values which abstract the difference away from the particular reloc
+ * implementations.
+ *
+ * Return: 0 upon success, else -ERRNO
+ */
+typedef int (*reloc_handler)(struct module *me, u32 *location,
+                             u32 base, Elf_Addr v, bool rela);
+/* The handlers for known reloc types */
+static reloc_handler reloc_handlers[] = {
        [R_MIPS_NONE]           = apply_r_mips_none,
-        [R_MIPS_32]             = apply_r_mips_32_rel,
+        [R_MIPS_32]             = apply_r_mips_32,
-        [R_MIPS_26]             = apply_r_mips_26_rel,
+        [R_MIPS_26]             = apply_r_mips_26,
-        [R_MIPS_HI16]           = apply_r_mips_hi16_rel,
+        [R_MIPS_HI16]           = apply_r_mips_hi16,
-        [R_MIPS_LO16]           = apply_r_mips_lo16_rel,
+        [R_MIPS_LO16]           = apply_r_mips_lo16,
-        [R_MIPS_PC16]           = apply_r_mips_pc16_rel,
+        [R_MIPS_PC16]           = apply_r_mips_pc16,
-        [R_MIPS_PC21_S2]        = apply_r_mips_pc21_rel,
+        [R_MIPS_64]             = apply_r_mips_64,
-        [R_MIPS_PC26_S2]        = apply_r_mips_pc26_rel,
+        [R_MIPS_HIGHER]         = apply_r_mips_higher,
+        [R_MIPS_HIGHEST]        = apply_r_mips_highest,
+        [R_MIPS_PC21_S2]        = apply_r_mips_pc21,
+        [R_MIPS_PC26_S2]        = apply_r_mips_pc26,
 };
-int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
+static int __apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
-                   unsigned int symindex, unsigned int relsec,
+                            unsigned int symindex, unsigned int relsec,
-                   struct module *me)
+                            struct module *me, bool rela)
 {
-        Elf_Mips_Rel *rel = (void *) sechdrs[relsec].sh_addr;
+        union {
-        int (*handler)(struct module *me, u32 *location, Elf_Addr v);
+                Elf_Mips_Rel *rel;
+                Elf_Mips_Rela *rela;
+        } r;
+        reloc_handler handler;
        Elf_Sym *sym;
-        u32 *location;
+        u32 *location, base;
        unsigned int i, type;
        Elf_Addr v;
-        int res;
+        int err = 0;
+        size_t reloc_sz;
        pr_debug("Applying relocate section %u to %u\n", relsec,
               sechdrs[relsec].sh_info);
+        r.rel = (void *)sechdrs[relsec].sh_addr;
+        reloc_sz = rela ? sizeof(*r.rela) : sizeof(*r.rel);
        me->arch.r_mips_hi16_list = NULL;
-        for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
+        for (i = 0; i < sechdrs[relsec].sh_size / reloc_sz; i++) {
                /* This is where to make the change */
                location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
-                        + rel[i].r_offset;
+                        + r.rel->r_offset;
                /* This is the symbol it is referring to */
                sym = (Elf_Sym *)sechdrs[symindex].sh_addr
-                        + ELF_MIPS_R_SYM(rel[i]);
+                        + ELF_MIPS_R_SYM(*r.rel);
                if (sym->st_value >= -MAX_ERRNO) {
                        /* Ignore unresolved weak symbol */
                        if (ELF_ST_BIND(sym->st_info) == STB_WEAK)
                                continue;
                        pr_warn("%s: Unknown symbol %s\n",
                                me->name, strtab + sym->st_name);
-                        return -ENOENT;
+                        err = -ENOENT;
+                        goto out;
                }
-                type = ELF_MIPS_R_TYPE(rel[i]);
+                type = ELF_MIPS_R_TYPE(*r.rel);
+                if (type < ARRAY_SIZE(reloc_handlers))
-                if (type < ARRAY_SIZE(reloc_handlers_rel))
+                        handler = reloc_handlers[type];
-                        handler = reloc_handlers_rel[type];
                else
                        handler = NULL;
                if (!handler) {
                        pr_err("%s: Unknown relocation type %u\n",
                               me->name, type);
-                        return -EINVAL;
+                        err = -EINVAL;
+                        goto out;
                }
-                v = sym->st_value;
+                if (rela) {
-                res = handler(me, location, v);
+                        v = sym->st_value + r.rela->r_addend;
-                if (res)
+                        base = 0;
-                        return res;
+                        r.rela = &r.rela[1];
+                } else {
+                        v = sym->st_value;
+                        base = *location;
+                        r.rel = &r.rel[1];
+                }
+                err = handler(me, location, base, v, rela);
+                if (err)
+                        goto out;
        }
+out:
        /*
-         * Normally the hi16 list should be deallocated at this point.  A
+         * Normally the hi16 list should be deallocated at this point. A
         * malformed binary however could contain a series of R_MIPS_HI16
-         * relocations not followed by a R_MIPS_LO16 relocation.  In that
+         * relocations not followed by a R_MIPS_LO16 relocation, or if we hit
-         * case, free up the list and return an error.
+         * an error processing a reloc we might have gotten here before
+         * reaching the R_MIPS_LO16. In either case, free up the list and
+         * return an error.
         */
        if (me->arch.r_mips_hi16_list) {
                free_relocation_chain(me->arch.r_mips_hi16_list);
                me->arch.r_mips_hi16_list = NULL;
+                err = err ?: -ENOEXEC;
-                return -ENOEXEC;
        }
-        return 0;
+        return err;
+}
+int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
+                   unsigned int symindex, unsigned int relsec,
+                   struct module *me)
+{
+        return __apply_relocate(sechdrs, strtab, symindex, relsec, me, false);
+}
+#ifdef CONFIG_MODULES_USE_ELF_RELA
+int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
+                       unsigned int symindex, unsigned int relsec,
+                       struct module *me)
+{
+        return __apply_relocate(sechdrs, strtab, symindex, relsec, me, true);
 }
+#endif /* CONFIG_MODULES_USE_ELF_RELA */
 /* Given an address, look for it in the module exception tables. */
 const struct exception_table_entry *search_module_dbetables(unsigned long addr)
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index f3e301f95aef..9e6c74bf66c4 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -814,7 +814,7 @@ static const struct mips_perf_event mipsxxcore_event_map2
        [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
 };
-static const struct mips_perf_event i6400_event_map[PERF_COUNT_HW_MAX] = {
+static const struct mips_perf_event i6x00_event_map[PERF_COUNT_HW_MAX] = {
        [PERF_COUNT_HW_CPU_CYCLES]          = { 0x00, CNTR_EVEN | CNTR_ODD },
        [PERF_COUNT_HW_INSTRUCTIONS]        = { 0x01, CNTR_EVEN | CNTR_ODD },
        /* These only count dcache, not icache */
@@ -1014,7 +1014,7 @@ static const struct mips_perf_event mipsxxcore_cache_map2
 },
 };
-static const struct mips_perf_event i6400_cache_map
+static const struct mips_perf_event i6x00_cache_map
                                [PERF_COUNT_HW_CACHE_MAX]
                                [PERF_COUNT_HW_CACHE_OP_MAX]
                                [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -1610,6 +1610,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
 #endif
                break;
        case CPU_I6400:
+        case CPU_I6500:
                /* 8-bit event numbers */
                base_id = config & 0xff;
                raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
@@ -1770,8 +1771,13 @@ init_hw_perf_events(void)
                break;
        case CPU_I6400:
                mipspmu.name = "mips/I6400";
-                mipspmu.general_event_map = &i6400_event_map;
+                mipspmu.general_event_map = &i6x00_event_map;
-                mipspmu.cache_event_map = &i6400_cache_map;
+                mipspmu.cache_event_map = &i6x00_cache_map;
+                break;
+        case CPU_I6500:
+                mipspmu.name = "mips/I6500";
+                mipspmu.general_event_map = &i6x00_event_map;
+                mipspmu.cache_event_map = &i6x00_cache_map;
                break;
        case CPU_1004K:
                mipspmu.name = "mips/1004K";
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 4eff2aed7360..70604c753aa4 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -83,7 +83,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
        }
        seq_printf(m, "isa\t\t\t:"); 
-        if (cpu_has_mips_r1)
+        if (cpu_has_mips_1)
                seq_printf(m, " mips1");
        if (cpu_has_mips_2)
                seq_printf(m, "%s", " mips2");
@@ -109,6 +109,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
        seq_printf(m, "ASEs implemented\t:");
        if (cpu_has_mips16)     seq_printf(m, "%s", " mips16");
+        if (cpu_has_mips16e2)   seq_printf(m, "%s", " mips16e2");
        if (cpu_has_mdmx)       seq_printf(m, "%s", " mdmx");
        if (cpu_has_mips3d)     seq_printf(m, "%s", " mips3d");
        if (cpu_has_smartmips)  seq_printf(m, "%s", " smartmips");
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 6931fe722a0b..6dd13641a418 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -868,14 +868,39 @@ asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
            tracehook_report_syscall_entry(regs))
                return -1;
-        if (secure_computing(NULL) == -1)
+#ifdef CONFIG_SECCOMP
-                return -1;
+        if (unlikely(test_thread_flag(TIF_SECCOMP))) {
+                int ret, i;
+                struct seccomp_data sd;
+                sd.nr = syscall;
+                sd.arch = syscall_get_arch();
+                for (i = 0; i < 6; i++) {
+                        unsigned long v, r;
+                        r = mips_get_syscall_arg(&v, current, regs, i);
+                        sd.args[i] = r ? 0 : v;
+                }
+                sd.instruction_pointer = KSTK_EIP(current);
+                ret = __secure_computing(&sd);
+                if (ret == -1)
+                        return ret;
+        }
+#endif
        if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
                trace_sys_enter(regs, regs->regs[2]);
        audit_syscall_entry(syscall, regs->regs[4], regs->regs[5],
                            regs->regs[6], regs->regs[7]);
+        /*
+         * Negative syscall numbers are mistaken for rejected syscalls, but
+         * won't have had the return value set appropriately, so we do so now.
+         */
+        if (syscall < 0)
+                syscall_set_return_value(current, regs, -ENOSYS, 0);
        return syscall;
 }
@@ -895,7 +920,7 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs)
        audit_syscall_exit(regs);
        if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
-                trace_sys_exit(regs, regs->regs[2]);
+                trace_sys_exit(regs, regs_return_value(regs));
        if (test_thread_flag(TIF_SYSCALL_TRACE))
                tracehook_report_syscall_exit(regs, 0);
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 80ed68b2c95e..27c2f90eeb21 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -371,7 +371,7 @@ EXPORT(sys_call_table)
        PTR     sys_writev
        PTR     sys_cacheflush
        PTR     sys_cachectl
-        PTR     sys_sysmips
+        PTR     __sys_sysmips
        PTR     sys_ni_syscall                  /* 4150 */
        PTR     sys_getsid
        PTR     sys_fdatasync
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 49765b44aa9b..65d5aeeb9bdb 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -311,7 +311,7 @@ EXPORT(sys_call_table)
        PTR     sys_sched_getaffinity
        PTR     sys_cacheflush
        PTR     sys_cachectl
-        PTR     sys_sysmips
+        PTR     __sys_sysmips
        PTR     sys_io_setup                    /* 5200 */
        PTR     sys_io_destroy
        PTR     sys_io_getevents
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 90bad2d1b2d3..cbf190ef9e8a 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -302,7 +302,7 @@ EXPORT(sysn32_call_table)
        PTR     compat_sys_sched_getaffinity
        PTR     sys_cacheflush
        PTR     sys_cachectl
-        PTR     sys_sysmips
+        PTR     __sys_sysmips
        PTR     compat_sys_io_setup                     /* 6200 */
        PTR     sys_io_destroy
        PTR     compat_sys_io_getevents
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 2dd70bd104e1..c30bc520885f 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -371,7 +371,7 @@ EXPORT(sys32_call_table)
        PTR     compat_sys_writev
        PTR     sys_cacheflush
        PTR     sys_cachectl
-        PTR     sys_sysmips
+        PTR     __sys_sysmips
        PTR     sys_ni_syscall                  /* 4150 */
        PTR     sys_getsid
        PTR     sys_fdatasync
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 01d1dbde5fbf..fe3939726765 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -670,6 +670,46 @@ static int __init early_parse_mem(char *p)
 }
 early_param("mem", early_parse_mem);
+static int __init early_parse_memmap(char *p)
+{
+        char *oldp;
+        u64 start_at, mem_size;
+        if (!p)
+                return -EINVAL;
+        if (!strncmp(p, "exactmap", 8)) {
+                pr_err("\"memmap=exactmap\" invalid on MIPS\n");
+                return 0;
+        }
+        oldp = p;
+        mem_size = memparse(p, &p);
+        if (p == oldp)
+                return -EINVAL;
+        if (*p == '@') {
+                start_at = memparse(p+1, &p);
+                add_memory_region(start_at, mem_size, BOOT_MEM_RAM);
+        } else if (*p == '#') {
+                pr_err("\"memmap=nn#ss\" (force ACPI data) invalid on MIPS\n");
+                return -EINVAL;
+        } else if (*p == '$') {
+                start_at = memparse(p+1, &p);
+                add_memory_region(start_at, mem_size, BOOT_MEM_RESERVED);
+        } else {
+                pr_err("\"memmap\" invalid format!\n");
+                return -EINVAL;
+        }
+        if (*p == '\0') {
+                usermem = 1;
+                return 0;
+        } else
+                return -EINVAL;
+}
+early_param("memmap", early_parse_memmap);
 #ifdef CONFIG_PROC_VMCORE
 unsigned long setup_elfcorehdr, setup_elfcorehdr_size;
 static int __init early_parse_elfcorehdr(char *p)
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 36954ddd0b9f..f832e99ad4c3 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -142,9 +142,11 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
        /* Warn the user if the CCA prevents multi-core */
        ncores = mips_cm_numcores();
-        if (cca_unsuitable && ncores > 1) {
+        if ((cca_unsuitable || cpu_has_dc_aliases) && ncores > 1) {
-                pr_warn("Using only one core due to unsuitable CCA 0x%x\n",
+                pr_warn("Using only one core due to %s%s%s\n",
-                        cca);
+                        cca_unsuitable ? "unsuitable CCA" : "",
+                        (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
+                        cpu_has_dc_aliases ? "dcache aliasing" : "");
                for_each_present_cpu(c) {
                        if (cpu_data[c].core)
@@ -488,6 +490,7 @@ static void cps_cpu_die(unsigned int cpu)
 {
        unsigned core = cpu_data[cpu].core;
        unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+        ktime_t fail_time;
        unsigned stat;
        int err;
@@ -514,6 +517,7 @@ static void cps_cpu_die(unsigned int cpu)
                 * state, the latter happening when a JTAG probe is connected
                 * in which case the CPC will refuse to power down the core.
                 */
+                fail_time = ktime_add_ms(ktime_get(), 2000);
                do {
                        mips_cm_lock_other(core, 0);
                        mips_cpc_lock_other(core);
@@ -521,9 +525,28 @@ static void cps_cpu_die(unsigned int cpu)
                        stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
                        mips_cpc_unlock_other();
                        mips_cm_unlock_other();
-                } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
-                         stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
+                        if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
-                         stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
+                            stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
+                            stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
+                                break;
+                        /*
+                         * The core ought to have powered down, but didn't &
+                         * now we don't really know what state it's in. It's
+                         * likely that its _pwr_up pin has been wired to logic
+                         * 1 & it powered back up as soon as we powered it
+                         * down...
+                         *
+                         * The best we can do is warn the user & continue in
+                         * the hope that the core is doing nothing harmful &
+                         * might behave properly if we online it later.
+                         */
+                        if (WARN(ktime_after(ktime_get(), fail_time),
+                                 "CPU%u hasn't powered down, seq. state %u\n",
+                                 cpu, stat >> CPC_Cx_STAT_CONF_SEQSTATE_SHF))
+                                break;
+                } while (1);
                /* Indicate the core is powered off */
                bitmap_clear(core_power, core, 1);
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index aba1afb64b62..770d4d1516cb 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -335,6 +335,9 @@ int mips_smp_ipi_free(const struct cpumask *mask)
 static int __init mips_smp_ipi_init(void)
 {
+        if (num_possible_cpus() == 1)
+                return 0;
        mips_smp_ipi_allocate(cpu_possible_mask);
        call_desc = irq_to_desc(call_virq);
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 1dfa7f5796c7..58c6f634b550 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -29,6 +29,7 @@
 #include <linux/sched/task_stack.h>
 #include <asm/asm.h>
+#include <asm/asm-eva.h>
 #include <asm/branch.h>
 #include <asm/cachectl.h>
 #include <asm/cacheflush.h>
@@ -131,16 +132,14 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new)
                __asm__ __volatile__ (
                "       .set    "MIPS_ISA_ARCH_LEVEL"                   \n"
                "       li      %[err], 0                               \n"
-                "1:     ll      %[old], (%[addr])                       \n"
+                "1:                                                     \n"
+                user_ll("%[old]", "(%[addr])")
                "       move    %[tmp], %[new]                          \n"
-                "2:     sc      %[tmp], (%[addr])                       \n"
+                "2:                                                     \n"
-                "       bnez    %[tmp], 4f                              \n"
+                user_sc("%[tmp]", "(%[addr])")
+                "       beqz    %[tmp], 1b                              \n"
                "3:                                                     \n"
                "       .insn                                           \n"
-                "       .subsection 2                                   \n"
-                "4:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "                                                       \n"
                "       .section .fixup,\"ax\"                          \n"
                "5:     li      %[err], %[efault]                       \n"
                "       j       3b                                      \n"
@@ -192,6 +191,12 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new)
        unreachable();
 }
+/*
+ * mips_atomic_set() normally returns directly via syscall_exit potentially
+ * clobbering static registers, so be sure to preserve them.
+ */
+save_static_function(sys_sysmips);
 SYSCALL_DEFINE3(sysmips, long, cmd, long, arg1, long, arg2)
 {
        switch (cmd) {
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index f806ee56e639..5eaf2578ac04 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -939,88 +939,114 @@ static void emulate_load_store_insn(struct pt_regs *regs,
                 * The remaining opcodes are the ones that are really of
                 * interest.
                 */
-#ifdef CONFIG_EVA
        case spec3_op:
-                /*
+                if (insn.dsp_format.func == lx_op) {
-                 * we can land here only from kernel accessing user memory,
+                        switch (insn.dsp_format.op) {
-                 * so we need to "switch" the address limit to user space, so
+                        case lwx_op:
-                 * address check can work properly.
+                                if (!access_ok(VERIFY_READ, addr, 4))
-                 */
+                                        goto sigbus;
-                seg = get_fs();
+                                LoadW(addr, value, res);
-                set_fs(USER_DS);
+                                if (res)
-                switch (insn.spec3_format.func) {
+                                        goto fault;
-                case lhe_op:
+                                compute_return_epc(regs);
-                        if (!access_ok(VERIFY_READ, addr, 2)) {
+                                regs->regs[insn.dsp_format.rd] = value;
-                                set_fs(seg);
+                                break;
-                                goto sigbus;
+                        case lhx_op:
-                        }
+                                if (!access_ok(VERIFY_READ, addr, 2))
-                        LoadHWE(addr, value, res);
+                                        goto sigbus;
-                        if (res) {
+                                LoadHW(addr, value, res);
-                                set_fs(seg);
+                                if (res)
-                                goto fault;
+                                        goto fault;
-                        }
+                                compute_return_epc(regs);
-                        compute_return_epc(regs);
+                                regs->regs[insn.dsp_format.rd] = value;
-                        regs->regs[insn.spec3_format.rt] = value;
+                                break;
-                        break;
+                        default:
-                case lwe_op:
+                                goto sigill;
-                        if (!access_ok(VERIFY_READ, addr, 4)) {
-                                set_fs(seg);
-                                goto sigbus;
                        }
+                }
+#ifdef CONFIG_EVA
+                else {
+                        /*
+                         * we can land here only from kernel accessing user
+                         * memory, so we need to "switch" the address limit to
+                         * user space, so that address check can work properly.
+                         */
+                        seg = get_fs();
+                        set_fs(USER_DS);
+                        switch (insn.spec3_format.func) {
+                        case lhe_op:
+                                if (!access_ok(VERIFY_READ, addr, 2)) {
+                                        set_fs(seg);
+                                        goto sigbus;
+                                }
+                                LoadHWE(addr, value, res);
+                                if (res) {
+                                        set_fs(seg);
+                                        goto fault;
+                                }
+                                compute_return_epc(regs);
+                                regs->regs[insn.spec3_format.rt] = value;
+                                break;
+                        case lwe_op:
+                                if (!access_ok(VERIFY_READ, addr, 4)) {
+                                        set_fs(seg);
+                                        goto sigbus;
+                                }
                                LoadWE(addr, value, res);
-                        if (res) {
+                                if (res) {
-                                set_fs(seg);
+                                        set_fs(seg);
-                                goto fault;
+                                        goto fault;
-                        }
+                                }
-                        compute_return_epc(regs);
+                                compute_return_epc(regs);
-                        regs->regs[insn.spec3_format.rt] = value;
+                                regs->regs[insn.spec3_format.rt] = value;
-                        break;
+                                break;
-                case lhue_op:
+                        case lhue_op:
-                        if (!access_ok(VERIFY_READ, addr, 2)) {
+                                if (!access_ok(VERIFY_READ, addr, 2)) {
-                                set_fs(seg);
+                                        set_fs(seg);
-                                goto sigbus;
+                                        goto sigbus;
-                        }
+                                }
-                        LoadHWUE(addr, value, res);
+                                LoadHWUE(addr, value, res);
-                        if (res) {
+                                if (res) {
-                                set_fs(seg);
+                                        set_fs(seg);
-                                goto fault;
+                                        goto fault;
-                        }
+                                }
-                        compute_return_epc(regs);
+                                compute_return_epc(regs);
-                        regs->regs[insn.spec3_format.rt] = value;
+                                regs->regs[insn.spec3_format.rt] = value;
-                        break;
+                                break;
-                case she_op:
+                        case she_op:
-                        if (!access_ok(VERIFY_WRITE, addr, 2)) {
+                                if (!access_ok(VERIFY_WRITE, addr, 2)) {
-                                set_fs(seg);
+                                        set_fs(seg);
-                                goto sigbus;
+                                        goto sigbus;
-                        }
+                                }
-                        compute_return_epc(regs);
+                                compute_return_epc(regs);
-                        value = regs->regs[insn.spec3_format.rt];
+                                value = regs->regs[insn.spec3_format.rt];
-                        StoreHWE(addr, value, res);
+                                StoreHWE(addr, value, res);
-                        if (res) {
+                                if (res) {
-                                set_fs(seg);
+                                        set_fs(seg);
-                                goto fault;
+                                        goto fault;
-                        }
+                                }
-                        break;
+                                break;
-                case swe_op:
+                        case swe_op:
-                        if (!access_ok(VERIFY_WRITE, addr, 4)) {
+                                if (!access_ok(VERIFY_WRITE, addr, 4)) {
-                                set_fs(seg);
+                                        set_fs(seg);
-                                goto sigbus;
+                                        goto sigbus;
-                        }
+                                }
-                        compute_return_epc(regs);
+                                compute_return_epc(regs);
-                        value = regs->regs[insn.spec3_format.rt];
+                                value = regs->regs[insn.spec3_format.rt];
-                        StoreWE(addr, value, res);
+                                StoreWE(addr, value, res);
-                        if (res) {
+                                if (res) {
+                                        set_fs(seg);
+                                        goto fault;
+                                }
+                                break;
+                        default:
                                set_fs(seg);
-                                goto fault;
+                                goto sigill;
                        }
-                        break;
-                default:
                        set_fs(seg);
-                        goto sigill;
                }
-                set_fs(seg);
-                break;
 #endif
+                break;
        case lh_op:
                if (!access_ok(VERIFY_READ, addr, 2))
                        goto sigbus;
@@ -1984,6 +2010,8 @@ static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
        u16 __user *pc16;
        unsigned long origpc;
        union mips16e_instruction mips16inst, oldinst;
+        unsigned int opcode;
+        int extended = 0;
        origpc = regs->cp0_epc;
        orig31 = regs->regs[31];
@@ -1996,6 +2024,7 @@ static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
        /* skip EXTEND instruction */
        if (mips16inst.ri.opcode == MIPS16e_extend_op) {
+                extended = 1;
                pc16++;
                __get_user(mips16inst.full, pc16);
        } else if (delay_slot(regs)) {
@@ -2008,7 +2037,8 @@ static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
                        goto sigbus;
        }
-        switch (mips16inst.ri.opcode) {
+        opcode = mips16inst.ri.opcode;
+        switch (opcode) {
        case MIPS16e_i64_op:    /* I64 or RI64 instruction */
                switch (mips16inst.i64.func) {  /* I64/RI64 func field check */
                case MIPS16e_ldpc_func:
@@ -2028,9 +2058,40 @@ static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
                goto sigbus;
        case MIPS16e_swsp_op:
+                reg = reg16to32[mips16inst.ri.rx];
+                if (extended && cpu_has_mips16e2)
+                        switch (mips16inst.ri.imm >> 5) {
+                        case 0:         /* SWSP */
+                        case 1:         /* SWGP */
+                                break;
+                        case 2:         /* SHGP */
+                                opcode = MIPS16e_sh_op;
+                                break;
+                        default:
+                                goto sigbus;
+                        }
+                break;
        case MIPS16e_lwpc_op:
+                reg = reg16to32[mips16inst.ri.rx];
+                break;
        case MIPS16e_lwsp_op:
                reg = reg16to32[mips16inst.ri.rx];
+                if (extended && cpu_has_mips16e2)
+                        switch (mips16inst.ri.imm >> 5) {
+                        case 0:         /* LWSP */
+                        case 1:         /* LWGP */
+                                break;
+                        case 2:         /* LHGP */
+                                opcode = MIPS16e_lh_op;
+                                break;
+                        case 4:         /* LHUGP */
+                                opcode = MIPS16e_lhu_op;
+                                break;
+                        default:
+                                goto sigbus;
+                        }
                break;
        case MIPS16e_i8_op:
@@ -2044,7 +2105,7 @@ static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
                break;
        }
-        switch (mips16inst.ri.opcode) {
+        switch (opcode) {
        case MIPS16e_lb_op:
        case MIPS16e_lbu_op:
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index 3114a2ed1f4e..03e3304d6ae5 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -28,6 +28,9 @@
 #ifdef CONFIG_MIPS_MALTA
 #undef CONFIG_CPU_HAS_PREFETCH
 #endif
+#ifdef CONFIG_CPU_MIPSR6
+#undef CONFIG_CPU_HAS_PREFETCH
+#endif
 #include <asm/asm.h>
 #include <asm/asm-offsets.h>
diff --git a/arch/mips/loongson64/common/env.c b/arch/mips/loongson64/common/env.c
index 6afa21850267..1e8a955ae5a8 100644
--- a/arch/mips/loongson64/common/env.c
+++ b/arch/mips/loongson64/common/env.c
@@ -90,7 +90,9 @@ void __init prom_init_env(void)
        cpu_clock_freq = ecpu->cpu_clock_freq;
        loongson_sysconf.cputype = ecpu->cputype;
-        if (ecpu->cputype == Loongson_3A) {
+        switch (ecpu->cputype) {
+        case Legacy_3A:
+        case Loongson_3A:
                loongson_sysconf.cores_per_node = 4;
                loongson_sysconf.cores_per_package = 4;
                smp_group[0] = 0x900000003ff01000;
@@ -111,7 +113,9 @@ void __init prom_init_env(void)
                loongson_freqctrl[3] = 0x900030001fe001d0;
                loongson_sysconf.ht_control_base = 0x90000EFDFB000000;
                loongson_sysconf.workarounds = WORKAROUND_CPUFREQ;
-        } else if (ecpu->cputype == Loongson_3B) {
+                break;
+        case Legacy_3B:
+        case Loongson_3B:
                loongson_sysconf.cores_per_node = 4; /* One chip has 2 nodes */
                loongson_sysconf.cores_per_package = 8;
                smp_group[0] = 0x900000003ff01000;
@@ -132,7 +136,8 @@ void __init prom_init_env(void)
                loongson_freqctrl[3] = 0x900060001fe001d0;
                loongson_sysconf.ht_control_base = 0x90001EFDFB000000;
                loongson_sysconf.workarounds = WORKAROUND_CPUHOTPLUG;
-        } else {
+                break;
+        default:
                loongson_sysconf.cores_per_node = 1;
                loongson_sysconf.cores_per_package = 1;
                loongson_chipcfg[0] = 0x900000001fe00180;
@@ -193,6 +198,7 @@ void __init prom_init_env(void)
                        break;
                case PRID_REV_LOONGSON3A_R1:
                case PRID_REV_LOONGSON3A_R2:
+                case PRID_REV_LOONGSON3A_R3:
                        cpu_clock_freq = 900000000;
                        break;
                case PRID_REV_LOONGSON3B_R1:
diff --git a/arch/mips/loongson64/common/init.c b/arch/mips/loongson64/common/init.c
index 9b987fe98b5b..6ef17120722f 100644
--- a/arch/mips/loongson64/common/init.c
+++ b/arch/mips/loongson64/common/init.c
@@ -10,13 +10,25 @@
 #include <linux/bootmem.h>
 #include <asm/bootinfo.h>
+#include <asm/traps.h>
 #include <asm/smp-ops.h>
+#include <asm/cacheflush.h>
 #include <loongson.h>
 /* Loongson CPU address windows config space base address */
 unsigned long __maybe_unused _loongson_addrwincfg_base;
+static void __init mips_nmi_setup(void)
+{
+        void *base;
+        extern char except_vec_nmi;
+        base = (void *)(CAC_BASE + 0x380);
+        memcpy(base, &except_vec_nmi, 0x80);
+        flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
+}
 void __init prom_init(void)
 {
 #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
@@ -40,6 +52,7 @@ void __init prom_init(void)
        /*init the uart base address */
        prom_init_uart_base();
        register_smp_ops(&loongson3_smp_ops);
+        board_nmi_handler_setup = mips_nmi_setup;
 }
 void __init prom_free_prom_memory(void)
diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/loongson-3/irq.c
index 548f759454dc..7202e52cd046 100644
--- a/arch/mips/loongson64/loongson-3/irq.c
+++ b/arch/mips/loongson64/loongson-3/irq.c
@@ -9,18 +9,69 @@
 #include "smp.h"
+extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
+unsigned int irq_cpu[16] = {[0 ... 15] = -1};
 unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
+unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
+int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
+                          bool force)
+{
+        unsigned int cpu;
+        struct cpumask new_affinity;
+        /* I/O devices are connected on package-0 */
+        cpumask_copy(&new_affinity, affinity);
+        for_each_cpu(cpu, affinity)
+                if (cpu_data[cpu].package > 0)
+                        cpumask_clear_cpu(cpu, &new_affinity);
+        if (cpumask_empty(&new_affinity))
+                return -EINVAL;
+        cpumask_copy(d->common->affinity, &new_affinity);
+        return IRQ_SET_MASK_OK_NOCOPY;
+}
 static void ht_irqdispatch(void)
 {
        unsigned int i, irq;
+        struct irq_data *irqd;
+        struct cpumask affinity;
        irq = LOONGSON_HT1_INT_VECTOR(0);
        LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
        for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
-                if (irq & (0x1 << ht_irq[i]))
+                if (!(irq & (0x1 << ht_irq[i])))
+                        continue;
+                /* handled by local core */
+                if (local_irq & (0x1 << ht_irq[i])) {
                        do_IRQ(ht_irq[i]);
+                        continue;
+                }
+                irqd = irq_get_irq_data(ht_irq[i]);
+                cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
+                if (cpumask_empty(&affinity)) {
+                        do_IRQ(ht_irq[i]);
+                        continue;
+                }
+                irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
+                if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
+                        irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
+                if (irq_cpu[ht_irq[i]] == 0) {
+                        do_IRQ(ht_irq[i]);
+                        continue;
+                }
+                /* balanced by other cores */
+                loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
        }
 }
@@ -120,11 +171,16 @@ void irq_router_init(void)
 void __init mach_init_irq(void)
 {
+        struct irq_chip *chip;
        clear_c0_status(ST0_IM | ST0_BEV);
        irq_router_init();
        mips_cpu_irq_init();
        init_i8259_irqs();
+        chip = irq_get_chip(I8259A_IRQ_BASE);
+        chip->irq_set_affinity = plat_set_irq_affinity;
        irq_set_chip_and_handler(LOONGSON_UART_IRQ,
                        &loongson_irq_chip, handle_level_irq);
diff --git a/arch/mips/loongson64/loongson-3/smp.c b/arch/mips/loongson64/loongson-3/smp.c
index 64659fc73940..b7a355c3c408 100644
--- a/arch/mips/loongson64/loongson-3/smp.c
+++ b/arch/mips/loongson64/loongson-3/smp.c
@@ -254,13 +254,21 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
                loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(i)]);
 }
+#define IPI_IRQ_OFFSET 6
+void loongson3_send_irq_by_ipi(int cpu, int irqs)
+{
+        loongson3_ipi_write32(irqs << IPI_IRQ_OFFSET, ipi_set0_regs[cpu_logical_map(cpu)]);
+}
 void loongson3_ipi_interrupt(struct pt_regs *regs)
 {
        int i, cpu = smp_processor_id();
-        unsigned int action, c0count;
+        unsigned int action, c0count, irqs;
        /* Load the ipi register to figure out what we're supposed to do */
        action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]);
+        irqs = action >> IPI_IRQ_OFFSET;
        /* Clear the ipi register to clear the interrupt */
        loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu_logical_map(cpu)]);
@@ -282,6 +290,14 @@ void loongson3_ipi_interrupt(struct pt_regs *regs)
                        core0_c0count[i] = c0count;
                __wbflush(); /* Let others see the result ASAP */
        }
+        if (irqs) {
+                int irq;
+                while ((irq = ffs(irqs))) {
+                        do_IRQ(irq-1);
+                        irqs &= ~(1<<(irq-1));
+                }
+        }
 }
 #define MAX_LOOPS 800
@@ -503,7 +519,7 @@ static void loongson3a_r1_play_dead(int *state_addr)
                : "a1");
 }
-static void loongson3a_r2_play_dead(int *state_addr)
+static void loongson3a_r2r3_play_dead(int *state_addr)
 {
        register int val;
        register long cpuid, core, node, count;
@@ -664,8 +680,9 @@ void play_dead(void)
                        (void *)CKSEG1ADDR((unsigned long)loongson3a_r1_play_dead);
                break;
        case PRID_REV_LOONGSON3A_R2:
+        case PRID_REV_LOONGSON3A_R3:
                play_dead_at_ckseg1 =
-                        (void *)CKSEG1ADDR((unsigned long)loongson3a_r2_play_dead);
+                        (void *)CKSEG1ADDR((unsigned long)loongson3a_r2r3_play_dead);
                break;
        case PRID_REV_LOONGSON3B_R1:
        case PRID_REV_LOONGSON3B_R2:
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index f12fde10c8ad..f08a7b4facb9 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1142,7 +1142,7 @@ emul:
                case mfhc_op:
                        if (!cpu_has_mips_r2_r6)
-                                goto sigill;
+                                return SIGILL;
                        /* copregister rd -> gpr[rt] */
                        if (MIPSInst_RT(ir) != 0) {
@@ -1153,7 +1153,7 @@ emul:
                case mthc_op:
                        if (!cpu_has_mips_r2_r6)
-                                goto sigill;
+                                return SIGILL;
                        /* copregister rd <- gpr[rt] */
                        SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
@@ -1376,7 +1376,6 @@ branch_common:
                                xcp->regs[MIPSInst_RS(ir)];
                break;
        default:
-sigill:
                return SIGILL;
        }
@@ -2524,6 +2523,35 @@ dcopuop:
        return 0;
 }
+/*
+ * Emulate FPU instructions.
+ *
+ * If we use FPU hardware, then we have been typically called to handle
+ * an unimplemented operation, such as where an operand is a NaN or
+ * denormalized.  In that case exit the emulation loop after a single
+ * iteration so as to let hardware execute any subsequent instructions.
+ *
+ * If we have no FPU hardware or it has been disabled, then continue
+ * emulating floating-point instructions until one of these conditions
+ * has occurred:
+ *
+ * - a non-FPU instruction has been encountered,
+ *
+ * - an attempt to emulate has ended with a signal,
+ *
+ * - the ISA mode has been switched.
+ *
+ * We need to terminate the emulation loop if we got switched to the
+ * MIPS16 mode, whether supported or not, so that we do not attempt
+ * to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
+ * Similarly if we got switched to the microMIPS mode and only the
+ * regular MIPS mode is supported, so that we do not attempt to emulate
+ * a microMIPS instruction as a regular MIPS FPU instruction.  Or if
+ * we got switched to the regular MIPS mode and only the microMIPS mode
+ * is supported, so that we do not attempt to emulate a regular MIPS
+ * instruction that should cause an Address Error exception instead.
+ * For simplicity we always terminate upon an ISA mode switch.
+ */
 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
        int has_fpu, void *__user *fault_addr)
 {
@@ -2609,6 +2637,15 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                        break;
                if (sig)
                        break;
+                /*
+                 * We have to check for the ISA bit explicitly here,
+                 * because `get_isa16_mode' may return 0 if support
+                 * for code compression has been globally disabled,
+                 * or otherwise we may produce the wrong signal or
+                 * even proceed successfully where we must not.
+                 */
+                if ((xcp->cp0_epc ^ prevepc) & 0x1)
+                        break;
                cond_resched();
        } while (xcp->cp0_epc > prevepc);
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 3fe99cb271a9..81d6a15c93d0 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1453,6 +1453,7 @@ static void probe_pcache(void)
        case CPU_20KC:
        case CPU_25KF:
        case CPU_I6400:
+        case CPU_I6500:
        case CPU_SB1:
        case CPU_SB1A:
        case CPU_XLR:
@@ -1512,6 +1513,7 @@ static void probe_pcache(void)
        case CPU_ALCHEMY:
        case CPU_I6400:
+        case CPU_I6500:
                c->icache.flags |= MIPS_CACHE_IC_F_DC;
                break;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index ed1c5297547a..5aadc69c8ce3 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -153,8 +153,7 @@ static int scratchpad_offset(int i)
 */
 static int m4kc_tlbp_war(void)
 {
-        return (current_cpu_data.processor_id & 0xffff00) ==
+        return current_cpu_type() == CPU_4KC;
-               (PRID_COMP_MIPS | PRID_IMP_4KC);
 }
 /* Handle labels (which must be positive integers). */
@@ -2015,6 +2014,26 @@ static void build_r3000_tlb_modify_handler(void)
 }
 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
+static bool cpu_has_tlbex_tlbp_race(void)
+{
+        /*
+         * When a Hardware Table Walker is running it can replace TLB entries
+         * at any time, leading to a race between it & the CPU.
+         */
+        if (cpu_has_htw)
+                return true;
+        /*
+         * If the CPU shares FTLB RAM with its siblings then our entry may be
+         * replaced at any time by a sibling performing a write to the FTLB.
+         */
+        if (cpu_has_shared_ftlb_ram)
+                return true;
+        /* In all other cases there ought to be no race condition to handle */
+        return false;
+}
 /*
 * R4000 style TLB load/store/modify handlers.
 */
@@ -2051,7 +2070,7 @@ build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
        iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
        if (!m4kc_tlbp_war()) {
                build_tlb_probe_entry(p);
-                if (cpu_has_htw) {
+                if (cpu_has_tlbex_tlbp_race()) {
                        /* race condition happens, leaving */
                        uasm_i_ehb(p);
                        uasm_i_mfc0(p, wr.r3, C0_INDEX);
@@ -2125,6 +2144,14 @@ static void build_r4000_tlb_load_handler(void)
                }
                uasm_i_nop(&p);
+                /*
+                 * Warn if something may race with us & replace the TLB entry
+                 * before we read it here. Everything with such races should
+                 * also have dedicated RiXi exception handlers, so this
+                 * shouldn't be hit.
+                 */
+                WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
                uasm_i_tlbr(&p);
                switch (current_cpu_type()) {
@@ -2192,6 +2219,14 @@ static void build_r4000_tlb_load_handler(void)
                }
                uasm_i_nop(&p);
+                /*
+                 * Warn if something may race with us & replace the TLB entry
+                 * before we read it here. Everything with such races should
+                 * also have dedicated RiXi exception handlers, so this
+                 * shouldn't be hit.
+                 */
+                WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
                uasm_i_tlbr(&p);
                switch (current_cpu_type()) {
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c
index 277cf52d80e1..c28ff53c8da0 100644
--- a/arch/mips/mm/uasm-micromips.c
+++ b/arch/mips/mm/uasm-micromips.c
@@ -40,93 +40,92 @@
 #include "uasm.c"
-static struct insn insn_table_MM[] = {
+static const struct insn const insn_table_MM[insn_invalid] = {
-        { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD },
+        [insn_addu]     = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
-        { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
+        [insn_addiu]    = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
-        { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD },
+        [insn_and]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
-        { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
+        [insn_andi]     = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
-        { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        [insn_beq]      = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
-        { insn_beql, 0, 0 },
+        [insn_beql]     = {0, 0},
-        { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM },
+        [insn_bgez]     = {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM},
-        { insn_bgezl, 0, 0 },
+        [insn_bgezl]    = {0, 0},
-        { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM },
+        [insn_bltz]     = {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM},
-        { insn_bltzl, 0, 0 },
+        [insn_bltzl]    = {0, 0},
-        { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM },
+        [insn_bne]      = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
-        { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
+        [insn_cache]    = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
-        { insn_cfc1, M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS },
+        [insn_cfc1]     = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},
-        { insn_cfcmsa, M(mm_pool32s_op, 0, msa_cfc_op, 0, 0, mm_32s_elm_op), RD | RE },
+        [insn_cfcmsa]   = {M(mm_pool32s_op, 0, msa_cfc_op, 0, 0, mm_32s_elm_op), RD | RE},
-        { insn_ctc1, M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS },
+        [insn_ctc1]     = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS},
-        { insn_ctcmsa, M(mm_pool32s_op, 0, msa_ctc_op, 0, 0, mm_32s_elm_op), RD | RE },
+        [insn_ctcmsa]   = {M(mm_pool32s_op, 0, msa_ctc_op, 0, 0, mm_32s_elm_op), RD | RE},
-        { insn_daddu, 0, 0 },
+        [insn_daddu]    = {0, 0},
-        { insn_daddiu, 0, 0 },
+        [insn_daddiu]   = {0, 0},
-        { insn_di, M(mm_pool32a_op, 0, 0, 0, mm_di_op, mm_pool32axf_op), RS },
+        [insn_di]       = {M(mm_pool32a_op, 0, 0, 0, mm_di_op, mm_pool32axf_op), RS},
-        { insn_divu, M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS },
+        [insn_divu]     = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS},
-        { insn_dmfc0, 0, 0 },
+        [insn_dmfc0]    = {0, 0},
-        { insn_dmtc0, 0, 0 },
+        [insn_dmtc0]    = {0, 0},
-        { insn_dsll, 0, 0 },
+        [insn_dsll]     = {0, 0},
-        { insn_dsll32, 0, 0 },
+        [insn_dsll32]   = {0, 0},
-        { insn_dsra, 0, 0 },
+        [insn_dsra]     = {0, 0},
-        { insn_dsrl, 0, 0 },
+        [insn_dsrl]     = {0, 0},
-        { insn_dsrl32, 0, 0 },
+        [insn_dsrl32]   = {0, 0},
-        { insn_drotr, 0, 0 },
+        [insn_drotr]    = {0, 0},
-        { insn_drotr32, 0, 0 },
+        [insn_drotr32]  = {0, 0},
-        { insn_dsubu, 0, 0 },
+        [insn_dsubu]    = {0, 0},
-        { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 },
+        [insn_eret]     = {M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0},
-        { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE },
+        [insn_ins]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE},
-        { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE },
+        [insn_ext]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE},
-        { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM },
+        [insn_j]        = {M(mm_j32_op, 0, 0, 0, 0, 0), JIMM},
-        { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM },
+        [insn_jal]      = {M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM},
-        { insn_jalr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS },
+        [insn_jalr]     = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS},
-        { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS },
+        [insn_jr]       = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS},
-        { insn_lb, M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
+        [insn_lb]       = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
-        { insn_ld, 0, 0 },
+        [insn_ld]       = {0, 0},
-        { insn_lh, M(mm_lh32_op, 0, 0, 0, 0, 0), RS | RS | SIMM },
+        [insn_lh]       = {M(mm_lh32_op, 0, 0, 0, 0, 0), RS | RS | SIMM},
-        { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM },
+        [insn_ll]       = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM},
-        { insn_lld, 0, 0 },
+        [insn_lld]      = {0, 0},
-        { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM },
+        [insn_lui]      = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM},
-        { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
+        [insn_lw]       = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
-        { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },
+        [insn_mfc0]     = {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD},
-        { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS },
+        [insn_mfhi]     = {M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS},
-        { insn_mflo, M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS },
+        [insn_mflo]     = {M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS},
-        { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },
+        [insn_mtc0]     = {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD},
-        { insn_mthi, M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS },
+        [insn_mthi]     = {M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS},
-        { insn_mtlo, M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS },
+        [insn_mtlo]     = {M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS},
-        { insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD },
+        [insn_mul]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD},
-        { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },
+        [insn_or]       = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD},
-        { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
+        [insn_ori]      = {M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
-        { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM },
+        [insn_pref]     = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM},
-        { insn_rfe, 0, 0 },
+        [insn_rfe]      = {0, 0},
-        { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM },
+        [insn_sc]       = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM},
-        { insn_scd, 0, 0 },
+        [insn_scd]      = {0, 0},
-        { insn_sd, 0, 0 },
+        [insn_sd]       = {0, 0},
-        { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },
+        [insn_sll]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD},
-        { insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD },
+        [insn_sllv]     = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD},
-        { insn_slt, M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD },
+        [insn_slt]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD},
-        { insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
+        [insn_sltiu]    = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
-        { insn_sltu, M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD },
+        [insn_sltu]     = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},
-        { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },
+        [insn_sra]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},
-        { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD },
+        [insn_srl]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},
-        { insn_srlv, M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD },
+        [insn_srlv]     = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD},
-        { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD },
+        [insn_rotr]     = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},
-        { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD },
+        [insn_subu]     = {M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD},
-        { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
+        [insn_sw]       = {M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
-        { insn_sync, M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS },
+        [insn_sync]     = {M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS},
-        { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 },
+        [insn_tlbp]     = {M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0},
-        { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 },
+        [insn_tlbr]     = {M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0},
-        { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 },
+        [insn_tlbwi]    = {M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0},
-        { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 },
+        [insn_tlbwr]    = {M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0},
-        { insn_wait, M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM },
+        [insn_wait]     = {M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM},
-        { insn_wsbh, M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS },
+        [insn_wsbh]     = {M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS},
-        { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD },
+        [insn_xor]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD},
-        { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
+        [insn_xori]     = {M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
-        { insn_dins, 0, 0 },
+        [insn_dins]     = {0, 0},
-        { insn_dinsm, 0, 0 },
+        [insn_dinsm]    = {0, 0},
-        { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
+        [insn_syscall]  = {M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
-        { insn_bbit0, 0, 0 },
+        [insn_bbit0]    = {0, 0},
-        { insn_bbit1, 0, 0 },
+        [insn_bbit1]    = {0, 0},
-        { insn_lwx, 0, 0 },
+        [insn_lwx]      = {0, 0},
-        { insn_ldx, 0, 0 },
+        [insn_ldx]      = {0, 0},
-        { insn_invalid, 0, 0 }
 };
 #undef M
@@ -156,20 +155,17 @@ static inline u32 build_jimm(u32 arg)
 */
 static void build_insn(u32 **buf, enum opcode opc, ...)
 {
-        struct insn *ip = NULL;
+        const struct insn *ip;
-        unsigned int i;
        va_list ap;
        u32 op;
-        for (i = 0; insn_table_MM[i].opcode != insn_invalid; i++)
+        if (opc < 0 || opc >= insn_invalid ||
-                if (insn_table_MM[i].opcode == opc) {
+            (opc == insn_daddiu && r4k_daddiu_bug()) ||
-                        ip = &insn_table_MM[i];
+            (insn_table_MM[opc].match == 0 && insn_table_MM[opc].fields == 0))
-                        break;
-                }
-        if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
                panic("Unsupported Micro-assembler instruction %d", opc);
+        ip = &insn_table_MM[opc];
        op = ip->match;
        va_start(ap, opc);
        if (ip->fields & RS) {
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index 2277499fe6ae..3f74f6c1f065 100644
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -48,126 +48,145 @@
 #include "uasm.c"
-static struct insn insn_table[] = {
+static const struct insn const insn_table[insn_invalid] = {
-        { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+        [insn_addiu]    = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
-        { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
+        [insn_addu]     = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
-        { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
+        [insn_and]      = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
-        { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
+        [insn_andi]     = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
-        { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        [insn_bbit0]    = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
-        { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        [insn_bbit1]    = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
-        { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        [insn_beq]      = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
-        { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        [insn_beql]     = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
-        { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
+        [insn_bgez]     = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM},
-        { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
+        [insn_bgezl]    = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM},
-        { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
+        [insn_bgtz]     = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM},
-        { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
+        [insn_blez]     = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM},
-        { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        [insn_bltz]     = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM},
+        [insn_bltzl]    = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM},
+        [insn_bne]      = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
+        [insn_break]    = {M(spec_op, 0, 0, 0, 0, break_op), SCIMM},
 #ifndef CONFIG_CPU_MIPSR6
-        { insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_cache]    = {M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
 #else
-        { insn_cache,  M6(spec3_op, 0, 0, 0, cache6_op),  RS | RT | SIMM9 },
+        [insn_cache]    = {M6(spec3_op, 0, 0, 0, cache6_op),  RS | RT | SIMM9},
 #endif
-        { insn_cfc1, M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD },
+        [insn_cfc1]     = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD},
-        { insn_cfcmsa, M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE },
+        [insn_cfcmsa]   = {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE},
-        { insn_ctc1, M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD },
+        [insn_ctc1]     = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD},
-        { insn_ctcmsa, M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE },
+        [insn_ctcmsa]   = {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE},
-        { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+        [insn_daddiu]   = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
-        { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
+        [insn_daddu]    = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
-        { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
+        [insn_ddivu]    = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},
-        { insn_di, M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT },
+        [insn_di]       = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT},
-        { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
+        [insn_dins]     = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
-        { insn_divu, M(spec_op, 0, 0, 0, 0, divu_op), RS | RT },
+        [insn_dinsm]    = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
-        { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
+        [insn_dinsu]    = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
-        { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
+        [insn_divu]     = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},
-        { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
+        [insn_dmfc0]    = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
-        { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
+        [insn_dmtc0]    = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
-        { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
+        [insn_dmultu]   = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
-        { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
+        [insn_drotr]    = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
-        { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
+        [insn_drotr32]  = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
-        { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
+        [insn_dsbh]     = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD},
-        { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
+        [insn_dshd]     = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD},
-        { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
+        [insn_dsll]     = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE},
-        { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
+        [insn_dsll32]   = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE},
-        { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
+        [insn_dsllv]    = {M(spec_op, 0, 0, 0, 0, dsllv_op),  RS | RT | RD},
-        { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
+        [insn_dsra]     = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE},
-        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
+        [insn_dsra32]   = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE},
-        { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
+        [insn_dsrav]    = {M(spec_op, 0, 0, 0, 0, dsrav_op),  RS | RT | RD},
-        { insn_jalr,  M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD },
+        [insn_dsrl]     = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE},
-        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
+        [insn_dsrl32]   = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE},
+        [insn_dsrlv]    = {M(spec_op, 0, 0, 0, 0, dsrlv_op),  RS | RT | RD},
+        [insn_dsubu]    = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD},
+        [insn_eret]     = {M(cop0_op, cop_op, 0, 0, 0, eret_op),  0},
+        [insn_ext]      = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE},
+        [insn_ins]      = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE},
+        [insn_j]        = {M(j_op, 0, 0, 0, 0, 0),  JIMM},
+        [insn_jal]      = {M(jal_op, 0, 0, 0, 0, 0),    JIMM},
+        [insn_jalr]     = {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD},
 #ifndef CONFIG_CPU_MIPSR6
-        { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
+        [insn_jr]       = {M(spec_op, 0, 0, 0, 0, jr_op),  RS},
 #else
-        { insn_jr,  M(spec_op, 0, 0, 0, 0, jalr_op),  RS },
+        [insn_jr]       = {M(spec_op, 0, 0, 0, 0, jalr_op),  RS},
 #endif
-        { insn_lb, M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+        [insn_lb]       = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
-        { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_lbu]      = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
-        { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
+        [insn_ld]       = {M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
-        { insn_lh,  M(lh_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_lddir]    = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD},
-        { insn_lhu,  M(lhu_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_ldpte]    = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD},
+        [insn_ldx]      = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD},
+        [insn_lh]       = {M(lh_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
+        [insn_lhu]      = {M(lhu_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
 #ifndef CONFIG_CPU_MIPSR6
-        { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_ll]       = {M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
-        { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_lld]      = {M(lld_op, 0, 0, 0, 0, 0),    RS | RT | SIMM},
 #else
-        { insn_lld,  M6(spec3_op, 0, 0, 0, lld6_op),  RS | RT | SIMM9 },
+        [insn_ll]       = {M6(spec3_op, 0, 0, 0, ll6_op),  RS | RT | SIMM9},
-        { insn_ll,  M6(spec3_op, 0, 0, 0, ll6_op),  RS | RT | SIMM9 },
+        [insn_lld]      = {M6(spec3_op, 0, 0, 0, lld6_op),  RS | RT | SIMM9},
 #endif
-        { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
+        [insn_lui]      = {M(lui_op, 0, 0, 0, 0, 0),    RT | SIMM},
-        { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_lw]       = {M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
-        { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
+        [insn_lwu]      = {M(lwu_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
-        { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
+        [insn_lwx]      = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD},
-        { insn_mfhc0,  M(cop0_op, mfhc0_op, 0, 0, 0, 0),  RT | RD | SET},
+        [insn_mfc0]     = {M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
-        { insn_mfhi,  M(spec_op, 0, 0, 0, 0, mfhi_op), RD },
+        [insn_mfhc0]    = {M(cop0_op, mfhc0_op, 0, 0, 0, 0),  RT | RD | SET},
-        { insn_mflo,  M(spec_op, 0, 0, 0, 0, mflo_op), RD },
+        [insn_mfhi]     = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD},
-        { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
+        [insn_mflo]     = {M(spec_op, 0, 0, 0, 0, mflo_op), RD},
-        { insn_mthc0,  M(cop0_op, mthc0_op, 0, 0, 0, 0),  RT | RD | SET},
+        [insn_movn]     = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},
-        { insn_mthi,  M(spec_op, 0, 0, 0, 0, mthi_op), RS },
+        [insn_movz]     = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},
-        { insn_mtlo,  M(spec_op, 0, 0, 0, 0, mtlo_op), RS },
+        [insn_mtc0]     = {M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
+        [insn_mthc0]    = {M(cop0_op, mthc0_op, 0, 0, 0, 0),  RT | RD | SET},
+        [insn_mthi]     = {M(spec_op, 0, 0, 0, 0, mthi_op), RS},
+        [insn_mtlo]     = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
 #ifndef CONFIG_CPU_MIPSR6
-        { insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
+        [insn_mul]      = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
 #else
-        { insn_mul, M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},
+        [insn_mul]      = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},
 #endif
-        { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
+        [insn_multu]    = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT},
-        { insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },
+        [insn_nor]      = {M(spec_op, 0, 0, 0, 0, nor_op),  RS | RT | RD},
+        [insn_or]       = {M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD},
+        [insn_ori]      = {M(ori_op, 0, 0, 0, 0, 0),    RS | RT | UIMM},
 #ifndef CONFIG_CPU_MIPSR6
-        { insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_pref]     = {M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
 #else
-        { insn_pref,  M6(spec3_op, 0, 0, 0, pref6_op),  RS | RT | SIMM9 },
+        [insn_pref]     = {M6(spec3_op, 0, 0, 0, pref6_op),  RS | RT | SIMM9},
 #endif
-        { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
+        [insn_rfe]      = {M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0},
-        { insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
+        [insn_rotr]     = {M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE},
+        [insn_sb]       = {M(sb_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
 #ifndef CONFIG_CPU_MIPSR6
-        { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_sc]       = {M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
-        { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_scd]      = {M(scd_op, 0, 0, 0, 0, 0),    RS | RT | SIMM},
 #else
-        { insn_scd,  M6(spec3_op, 0, 0, 0, scd6_op),  RS | RT | SIMM9 },
+        [insn_sc]       = {M6(spec3_op, 0, 0, 0, sc6_op),  RS | RT | SIMM9},
-        { insn_sc,  M6(spec3_op, 0, 0, 0, sc6_op),  RS | RT | SIMM9 },
+        [insn_scd]      = {M6(spec3_op, 0, 0, 0, scd6_op),  RS | RT | SIMM9},
 #endif
-        { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_sd]       = {M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
-        { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
+        [insn_sh]       = {M(sh_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
-        { insn_sllv,  M(spec_op, 0, 0, 0, 0, sllv_op),  RS | RT | RD },
+        [insn_sll]      = {M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE},
-        { insn_slt,  M(spec_op, 0, 0, 0, 0, slt_op),  RS | RT | RD },
+        [insn_sllv]     = {M(spec_op, 0, 0, 0, 0, sllv_op),  RS | RT | RD},
-        { insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+        [insn_slt]      = {M(spec_op, 0, 0, 0, 0, slt_op),  RS | RT | RD},
-        { insn_sltu, M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD },
+        [insn_slti]     = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
-        { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
+        [insn_sltiu]    = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
-        { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
+        [insn_sltu]     = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},
-        { insn_srlv,  M(spec_op, 0, 0, 0, 0, srlv_op),  RS | RT | RD },
+        [insn_sra]      = {M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE},
-        { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
+        [insn_srl]      = {M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE},
-        { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        [insn_srlv]     = {M(spec_op, 0, 0, 0, 0, srlv_op),  RS | RT | RD},
-        { insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE },
+        [insn_subu]     = {M(spec_op, 0, 0, 0, 0, subu_op),     RS | RT | RD},
-        { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
+        [insn_sw]       = {M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
-        { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
+        [insn_sync]     = {M(spec_op, 0, 0, 0, 0, sync_op), RE},
-        { insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },
+        [insn_syscall]  = {M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
-        { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
+        [insn_tlbp]     = {M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0},
-        { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
+        [insn_tlbr]     = {M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0},
-        { insn_wait, M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM },
+        [insn_tlbwi]    = {M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0},
-        { insn_wsbh, M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD },
+        [insn_tlbwr]    = {M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0},
-        { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
+        [insn_wait]     = {M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM},
-        { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
+        [insn_wsbh]     = {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD},
-        { insn_yield, M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD },
+        [insn_xor]      = {M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD},
-        { insn_ldpte, M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD },
+        [insn_xori]     = {M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM},
-        { insn_lddir, M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD },
+        [insn_yield]    = {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD},
-        { insn_invalid, 0, 0 }
 };
 #undef M
@@ -196,20 +215,17 @@ static inline u32 build_jimm(u32 arg)
 */
 static void build_insn(u32 **buf, enum opcode opc, ...)
 {
-        struct insn *ip = NULL;
+        const struct insn *ip;
-        unsigned int i;
        va_list ap;
        u32 op;
-        for (i = 0; insn_table[i].opcode != insn_invalid; i++)
+        if (opc < 0 || opc >= insn_invalid ||
-                if (insn_table[i].opcode == opc) {
+            (opc == insn_daddiu && r4k_daddiu_bug()) ||
-                        ip = &insn_table[i];
+            (insn_table[opc].match == 0 && insn_table[opc].fields == 0))
-                        break;
-                }
-        if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
                panic("Unsupported Micro-assembler instruction %d", opc);
+        ip = &insn_table[opc];
        op = ip->match;
        va_start(ap, opc);
        if (ip->fields & RS)
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 730363b59bac..57570c0649b4 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -46,26 +46,29 @@ enum fields {
 #define SIMM9_MASK      0x1ff
 enum opcode {
-        insn_invalid,
        insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
-        insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
+        insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
-        insn_bne, insn_cache, insn_cfc1, insn_cfcmsa, insn_ctc1, insn_ctcmsa,
+        insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
-        insn_daddiu, insn_daddu, insn_di, insn_dins, insn_dinsm, insn_divu,
+        insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
-        insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
+        insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, insn_dmfc0,
-        insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
+        insn_dmtc0, insn_dmultu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd,
-        insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,
+        insn_dsll, insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav,
-        insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,
+        insn_dsrl, insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext,
-        insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0,
+        insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu,
-        insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_or, insn_ori,
+        insn_ld, insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu,
-        insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll,
+        insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0,
-        insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra, insn_srl,
+        insn_mfhc0, insn_mfhi, insn_mflo, insn_movn, insn_movz, insn_mtc0,
+        insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,
+        insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,
+        insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,
+        insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl,
        insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
        insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
-        insn_xori, insn_yield, insn_lddir, insn_ldpte, insn_lhu,
+        insn_xori, insn_yield,
+        insn_invalid /* insn_invalid must be last */
 };
 struct insn {
-        enum opcode opcode;
        u32 match;
        enum fields fields;
 };
@@ -215,6 +218,13 @@ Ip_u2u1msbu3(op)					\
 }                                                       \
 UASM_EXPORT_SYMBOL(uasm_i##op);
+#define I_u2u1msb32msb3(op)                             \
+Ip_u2u1msbu3(op)                                        \
+{                                                       \
+        build_insn(buf, insn##op, b, a, c+d-33, c-32);  \
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 #define I_u2u1msbdu3(op)                                \
 Ip_u2u1msbu3(op)                                        \
 {                                                       \
@@ -265,25 +275,36 @@ I_u1u2s3(_beq)
 I_u1u2s3(_beql)
 I_u1s2(_bgez)
 I_u1s2(_bgezl)
+I_u1s2(_bgtz)
+I_u1s2(_blez)
 I_u1s2(_bltz)
 I_u1s2(_bltzl)
 I_u1u2s3(_bne)
+I_u1(_break)
 I_u2s3u1(_cache)
 I_u1u2(_cfc1)
 I_u2u1(_cfcmsa)
 I_u1u2(_ctc1)
 I_u2u1(_ctcmsa)
+I_u1u2(_ddivu)
 I_u1u2u3(_dmfc0)
 I_u1u2u3(_dmtc0)
+I_u1u2(_dmultu)
 I_u2u1s3(_daddiu)
 I_u3u1u2(_daddu)
 I_u1(_di);
 I_u1u2(_divu)
+I_u2u1(_dsbh);
+I_u2u1(_dshd);
 I_u2u1u3(_dsll)
 I_u2u1u3(_dsll32)
+I_u3u2u1(_dsllv)
 I_u2u1u3(_dsra)
+I_u2u1u3(_dsra32)
+I_u3u2u1(_dsrav)
 I_u2u1u3(_dsrl)
 I_u2u1u3(_dsrl32)
+I_u3u2u1(_dsrlv)
 I_u2u1u3(_drotr)
 I_u2u1u3(_drotr32)
 I_u3u1u2(_dsubu)
@@ -295,6 +316,7 @@ I_u1(_jal)
 I_u2u1(_jalr)
 I_u1(_jr)
 I_u2s3u1(_lb)
+I_u2s3u1(_lbu)
 I_u2s3u1(_ld)
 I_u2s3u1(_lh)
 I_u2s3u1(_lhu)
@@ -302,8 +324,11 @@ I_u2s3u1(_ll)
 I_u2s3u1(_lld)
 I_u1s2(_lui)
 I_u2s3u1(_lw)
+I_u2s3u1(_lwu)
 I_u1u2u3(_mfc0)
 I_u1u2u3(_mfhc0)
+I_u3u1u2(_movn)
+I_u3u1u2(_movz)
 I_u1(_mfhi)
 I_u1(_mflo)
 I_u1u2u3(_mtc0)
@@ -311,15 +336,20 @@ I_u1u2u3(_mthc0)
 I_u1(_mthi)
 I_u1(_mtlo)
 I_u3u1u2(_mul)
-I_u2u1u3(_ori)
+I_u1u2(_multu)
+I_u3u1u2(_nor)
 I_u3u1u2(_or)
+I_u2u1u3(_ori)
 I_0(_rfe)
+I_u2s3u1(_sb)
 I_u2s3u1(_sc)
 I_u2s3u1(_scd)
 I_u2s3u1(_sd)
+I_u2s3u1(_sh)
 I_u2u1u3(_sll)
 I_u3u2u1(_sllv)
 I_s3s1s2(_slt)
+I_u2u1s3(_slti)
 I_u2u1s3(_sltiu)
 I_u3u1u2(_sltu)
 I_u2u1u3(_sra)
@@ -340,6 +370,7 @@ I_u2u1u3(_xori)
 I_u2u1(_yield)
 I_u2u1msbu3(_dins);
 I_u2u1msb32u3(_dinsm);
+I_u2u1msb32msb3(_dinsu);
 I_u1(_syscall);
 I_u1u2s3(_bbit0);
 I_u1u2s3(_bbit1);
diff --git a/arch/mips/net/Makefile b/arch/mips/net/Makefile
index 8c2771401f54..47d678416715 100644
--- a/arch/mips/net/Makefile
+++ b/arch/mips/net/Makefile
@@ -1,3 +1,4 @@
 # MIPS networking code
-obj-$(CONFIG_BPF_JIT) += bpf_jit.o bpf_jit_asm.o
+obj-$(CONFIG_MIPS_CBPF_JIT) += bpf_jit.o bpf_jit_asm.o
+obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o
diff --git a/arch/mips/vdso/gettimeofday.c b/arch/mips/vdso/gettimeofday.c
index ce89c9e294f9..974276e828b2 100644
--- a/arch/mips/vdso/gettimeofday.c
+++ b/arch/mips/vdso/gettimeofday.c
@@ -20,6 +20,46 @@
 #include <asm/unistd.h>
 #include <asm/vdso.h>
+#ifdef CONFIG_MIPS_CLOCK_VSYSCALL
+static __always_inline long gettimeofday_fallback(struct timeval *_tv,
+                                          struct timezone *_tz)
+{
+        register struct timezone *tz asm("a1") = _tz;
+        register struct timeval *tv asm("a0") = _tv;
+        register long ret asm("v0");
+        register long nr asm("v0") = __NR_gettimeofday;
+        register long error asm("a3");
+        asm volatile(
+        "       syscall\n"
+        : "=r" (ret), "=r" (error)
+        : "r" (tv), "r" (tz), "r" (nr)
+        : "memory");
+        return error ? -ret : ret;
+}
+#endif
+static __always_inline long clock_gettime_fallback(clockid_t _clkid,
+                                           struct timespec *_ts)
+{
+        register struct timespec *ts asm("a1") = _ts;
+        register clockid_t clkid asm("a0") = _clkid;
+        register long ret asm("v0");
+        register long nr asm("v0") = __NR_clock_gettime;
+        register long error asm("a3");
+        asm volatile(
+        "       syscall\n"
+        : "=r" (ret), "=r" (error)
+        : "r" (clkid), "r" (ts), "r" (nr)
+        : "memory");
+        return error ? -ret : ret;
+}
 static __always_inline int do_realtime_coarse(struct timespec *ts,
                                              const union mips_vdso_data *data)
 {
@@ -39,8 +79,8 @@ static __always_inline int do_monotonic_coarse(struct timespec *ts,
                                               const union mips_vdso_data *data)
 {
        u32 start_seq;
-        u32 to_mono_sec;
+        u64 to_mono_sec;
-        u32 to_mono_nsec;
+        u64 to_mono_nsec;
        do {
                start_seq = vdso_data_read_begin(data);
@@ -148,8 +188,8 @@ static __always_inline int do_monotonic(struct timespec *ts,
 {
        u32 start_seq;
        u64 ns;
-        u32 to_mono_sec;
+        u64 to_mono_sec;
-        u32 to_mono_nsec;
+        u64 to_mono_nsec;
        do {
                start_seq = vdso_data_read_begin(data);
@@ -187,7 +227,7 @@ int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
        ret = do_realtime(&ts, data);
        if (ret)
-                return ret;
+                return gettimeofday_fallback(tv, tz);
        if (tv) {
                tv->tv_sec = ts.tv_sec;
@@ -202,12 +242,12 @@ int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
        return 0;
 }
-#endif /* CONFIG_CLKSRC_MIPS_GIC */
+#endif /* CONFIG_MIPS_CLOCK_VSYSCALL */
 int __vdso_clock_gettime(clockid_t clkid, struct timespec *ts)
 {
        const union mips_vdso_data *data = get_vdso_data();
-        int ret;
+        int ret = -1;
        switch (clkid) {
        case CLOCK_REALTIME_COARSE:
@@ -223,10 +263,11 @@ int __vdso_clock_gettime(clockid_t clkid, struct timespec *ts)
                ret = do_monotonic(ts, data);
                break;
        default:
-                ret = -ENOSYS;
                break;
        }
-        /* If we return -ENOSYS libc should fall back to a syscall. */
+        if (ret)
+                ret = clock_gettime_fallback(clkid, ts);
        return ret;
 }
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index d406b087553f..68ca2d9fcd73 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -221,6 +221,7 @@ config COMMON_CLK_VC5
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
+source "drivers/clk/imgtec/Kconfig"
 source "drivers/clk/keystone/Kconfig"
 source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/meson/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4f6a812342ed..cd376b3fb47a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -60,6 +60,7 @@ obj-y					+= bcm/
 obj-$(CONFIG_ARCH_BERLIN)               += berlin/
 obj-$(CONFIG_H8300)                     += h8300/
 obj-$(CONFIG_ARCH_HISI)                 += hisilicon/
+obj-y                                   += imgtec/
 obj-$(CONFIG_ARCH_MXC)                  += imx/
 obj-$(CONFIG_MACH_INGENIC)              += ingenic/
 obj-$(CONFIG_ARCH_KEYSTONE)             += keystone/
diff --git a/drivers/clk/imgtec/Kconfig b/drivers/clk/imgtec/Kconfig
new file mode 100644
index 000000000000..f6dcb748e9c4
--- /dev/null
+++ b/drivers/clk/imgtec/Kconfig
@@ -0,0 +1,9 @@
+config COMMON_CLK_BOSTON
+        bool "Clock driver for MIPS Boston boards"
+        depends on MIPS || COMPILE_TEST
+        select MFD_SYSCON
+        ---help---
+          Enable this to support the system & CPU clocks on the MIPS Boston
+          development board from Imagination Technologies. These are simple
+          fixed rate clocks whose rate is determined by reading a platform
+          provided register.
diff --git a/drivers/clk/imgtec/Makefile b/drivers/clk/imgtec/Makefile
new file mode 100644
index 000000000000..ac779b8c22f2
--- /dev/null
+++ b/drivers/clk/imgtec/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_CLK_BOSTON)         += clk-boston.o
diff --git a/drivers/clk/imgtec/clk-boston.c b/drivers/clk/imgtec/clk-boston.c
new file mode 100644
index 000000000000..f18f10351785
--- /dev/null
+++ b/drivers/clk/imgtec/clk-boston.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016-2017 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#define pr_fmt(fmt) "clk-boston: " fmt
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/clock/boston-clock.h>
+#define BOSTON_PLAT_MMCMDIV             0x30
+# define BOSTON_PLAT_MMCMDIV_CLK0DIV    (0xff << 0)
+# define BOSTON_PLAT_MMCMDIV_INPUT      (0xff << 8)
+# define BOSTON_PLAT_MMCMDIV_MUL        (0xff << 16)
+# define BOSTON_PLAT_MMCMDIV_CLK1DIV    (0xff << 24)
+#define BOSTON_CLK_COUNT 3
+static u32 ext_field(u32 val, u32 mask)
+{
+        return (val & mask) >> (ffs(mask) - 1);
+}
+static void __init clk_boston_setup(struct device_node *np)
+{
+        unsigned long in_freq, cpu_freq, sys_freq;
+        uint mmcmdiv, mul, cpu_div, sys_div;
+        struct clk_hw_onecell_data *onecell;
+        struct regmap *regmap;
+        struct clk_hw *hw;
+        int err;
+        regmap = syscon_node_to_regmap(np->parent);
+        if (IS_ERR(regmap)) {
+                pr_err("failed to find regmap\n");
+                return;
+        }
+        err = regmap_read(regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv);
+        if (err) {
+                pr_err("failed to read mmcm_div register: %d\n", err);
+                return;
+        }
+        in_freq = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT) * 1000000;
+        mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL);
+        sys_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV);
+        sys_freq = mult_frac(in_freq, mul, sys_div);
+        cpu_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV);
+        cpu_freq = mult_frac(in_freq, mul, cpu_div);
+        onecell = kzalloc(sizeof(*onecell) +
+                          (BOSTON_CLK_COUNT * sizeof(struct clk_hw *)),
+                          GFP_KERNEL);
+        if (!onecell)
+                return;
+        onecell->num = BOSTON_CLK_COUNT;
+        hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq);
+        if (IS_ERR(hw)) {
+                pr_err("failed to register input clock: %ld\n", PTR_ERR(hw));
+                return;
+        }
+        onecell->hws[BOSTON_CLK_INPUT] = hw;
+        hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq);
+        if (IS_ERR(hw)) {
+                pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw));
+                return;
+        }
+        onecell->hws[BOSTON_CLK_SYS] = hw;
+        hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq);
+        if (IS_ERR(hw)) {
+                pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw));
+                return;
+        }
+        onecell->hws[BOSTON_CLK_CPU] = hw;
+        err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, onecell);
+        if (err)
+                pr_err("failed to add DT provider: %d\n", err);
+}
+/*
+ * Use CLK_OF_DECLARE so that this driver is probed early enough to provide the
+ * CPU frequency for use with the GIC or cop0 counters/timers.
+ */
+CLK_OF_DECLARE(clk_boston, "img,boston-clock", clk_boston_setup);
diff --git a/drivers/platform/mips/cpu_hwmon.c b/drivers/platform/mips/cpu_hwmon.c
index 4300a558d0f3..322de58eebaf 100644
--- a/drivers/platform/mips/cpu_hwmon.c
+++ b/drivers/platform/mips/cpu_hwmon.c
@@ -17,17 +17,27 @@
 */
 int loongson3_cpu_temp(int cpu)
 {
-        u32 reg;
+        u32 reg, prid_rev;
        reg = LOONGSON_CHIPTEMP(cpu);
-        if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1)
+        prid_rev = read_c0_prid() & PRID_REV_MASK;
+        switch (prid_rev) {
+        case PRID_REV_LOONGSON3A_R1:
                reg = (reg >> 8) & 0xff;
-        else
+                break;
+        case PRID_REV_LOONGSON3A_R2:
+        case PRID_REV_LOONGSON3B_R1:
+        case PRID_REV_LOONGSON3B_R2:
                reg = ((reg >> 8) & 0xff) - 100;
+                break;
+        case PRID_REV_LOONGSON3A_R3:
+                reg = (reg & 0xffff)*731/0x4000 - 273;
+                break;
+        }
        return (int)reg * 1000;
 }
+static int nr_packages;
 static struct device *cpu_hwmon_dev;
 static ssize_t get_hwmon_name(struct device *dev,
@@ -51,88 +61,74 @@ static ssize_t get_hwmon_name(struct device *dev,
        return sprintf(buf, "cpu-hwmon\n");
 }
-static ssize_t get_cpu0_temp(struct device *dev,
+static ssize_t get_cpu_temp(struct device *dev,
-                        struct device_attribute *attr, char *buf);
-static ssize_t get_cpu1_temp(struct device *dev,
                        struct device_attribute *attr, char *buf);
-static ssize_t cpu0_temp_label(struct device *dev,
+static ssize_t cpu_temp_label(struct device *dev,
                        struct device_attribute *attr, char *buf);
-static ssize_t cpu1_temp_label(struct device *dev,
-                        struct device_attribute *attr, char *buf);
-static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu0_temp, NULL, 1);
-static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu0_temp_label, NULL, 1);
-static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu1_temp, NULL, 2);
-static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu1_temp_label, NULL, 2);
-static const struct attribute *hwmon_cputemp1[] = {
+static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1);
-        &sensor_dev_attr_temp1_input.dev_attr.attr,
+static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1);
-        &sensor_dev_attr_temp1_label.dev_attr.attr,
+static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2);
-        NULL
+static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2);
-};
+static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3);
+static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3);
-static const struct attribute *hwmon_cputemp2[] = {
+static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4);
-        &sensor_dev_attr_temp2_input.dev_attr.attr,
+static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4);
-        &sensor_dev_attr_temp2_label.dev_attr.attr,
-        NULL
+static const struct attribute *hwmon_cputemp[4][3] = {
+        {
+                &sensor_dev_attr_temp1_input.dev_attr.attr,
+                &sensor_dev_attr_temp1_label.dev_attr.attr,
+                NULL
+        },
+        {
+                &sensor_dev_attr_temp2_input.dev_attr.attr,
+                &sensor_dev_attr_temp2_label.dev_attr.attr,
+                NULL
+        },
+        {
+                &sensor_dev_attr_temp3_input.dev_attr.attr,
+                &sensor_dev_attr_temp3_label.dev_attr.attr,
+                NULL
+        },
+        {
+                &sensor_dev_attr_temp4_input.dev_attr.attr,
+                &sensor_dev_attr_temp4_label.dev_attr.attr,
+                NULL
+        }
 };
-static ssize_t cpu0_temp_label(struct device *dev,
+static ssize_t cpu_temp_label(struct device *dev,
-                        struct device_attribute *attr, char *buf)
-{
-        return sprintf(buf, "CPU 0 Temperature\n");
-}
-static ssize_t cpu1_temp_label(struct device *dev,
                        struct device_attribute *attr, char *buf)
 {
-        return sprintf(buf, "CPU 1 Temperature\n");
+        int id = (to_sensor_dev_attr(attr))->index - 1;
+        return sprintf(buf, "CPU %d Temperature\n", id);
 }
-static ssize_t get_cpu0_temp(struct device *dev,
+static ssize_t get_cpu_temp(struct device *dev,
                        struct device_attribute *attr, char *buf)
 {
-        int value = loongson3_cpu_temp(0);
+        int id = (to_sensor_dev_attr(attr))->index - 1;
-        return sprintf(buf, "%d\n", value);
+        int value = loongson3_cpu_temp(id);
-}
-static ssize_t get_cpu1_temp(struct device *dev,
-                        struct device_attribute *attr, char *buf)
-{
-        int value = loongson3_cpu_temp(1);
        return sprintf(buf, "%d\n", value);
 }
 static int create_sysfs_cputemp_files(struct kobject *kobj)
 {
-        int ret;
+        int i, ret = 0;
-        ret = sysfs_create_files(kobj, hwmon_cputemp1);
-        if (ret)
-                goto sysfs_create_temp1_fail;
-        if (loongson_sysconf.nr_cpus <= loongson_sysconf.cores_per_package)
-                return 0;
-        ret = sysfs_create_files(kobj, hwmon_cputemp2);
+        for (i=0; i<nr_packages; i++)
-        if (ret)
+                ret = sysfs_create_files(kobj, hwmon_cputemp[i]);
-                goto sysfs_create_temp2_fail;
-        return 0;
+        return ret;
-sysfs_create_temp2_fail:
-        sysfs_remove_files(kobj, hwmon_cputemp1);
-sysfs_create_temp1_fail:
-        return -1;
 }
 static void remove_sysfs_cputemp_files(struct kobject *kobj)
 {
-        sysfs_remove_files(&cpu_hwmon_dev->kobj, hwmon_cputemp1);
+        int i;
-        if (loongson_sysconf.nr_cpus > loongson_sysconf.cores_per_package)
+        for (i=0; i<nr_packages; i++)
-                sysfs_remove_files(&cpu_hwmon_dev->kobj, hwmon_cputemp2);
+                sysfs_remove_files(kobj, hwmon_cputemp[i]);
 }
 #define CPU_THERMAL_THRESHOLD 90000
@@ -140,8 +136,15 @@ static struct delayed_work thermal_work;
 static void do_thermal_timer(struct work_struct *work)
 {
-        int value = loongson3_cpu_temp(0);
+        int i, value, temp_max = 0;
-        if (value <= CPU_THERMAL_THRESHOLD)
+        for (i=0; i<nr_packages; i++) {
+                value = loongson3_cpu_temp(i);
+                if (value > temp_max)
+                        temp_max = value;
+        }
+        if (temp_max <= CPU_THERMAL_THRESHOLD)
                schedule_delayed_work(&thermal_work, msecs_to_jiffies(5000));
        else
                orderly_poweroff(true);
@@ -160,6 +163,9 @@ static int __init loongson_hwmon_init(void)
                goto fail_hwmon_device_register;
        }
+        nr_packages = loongson_sysconf.nr_cpus /
+                loongson_sysconf.cores_per_package;
        ret = sysfs_create_group(&cpu_hwmon_dev->kobj,
                                &cpu_hwmon_attribute_group);
        if (ret) {
diff --git a/include/dt-bindings/clock/boston-clock.h b/include/dt-bindings/clock/boston-clock.h
new file mode 100644
index 000000000000..a6f009821137
--- /dev/null
+++ b/include/dt-bindings/clock/boston-clock.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+#define BOSTON_CLK_INPUT 0
+#define BOSTON_CLK_SYS 1
+#define BOSTON_CLK_CPU 2
+#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */
author	Linus Torvalds <torvalds@linux-foundation.org>	2017-07-15 13:59:54 -0400
committer	Linus Torvalds <torvalds@linux-foundation.org>	2017-07-15 13:59:54 -0400
commit	568d135d337d3114688fef9fdbce7fb6dbbd04c7 (patch)
tree	b9355b94182a51eec5cfc69dd335e39a2e97ac7d
parent	4ecd4ff55ac5c7fe9e232f34a41c4d54f2d825c1 (diff)
parent	d40e0d4fb5613099a58c95a9403f51b03e40e861 (diff)