Merge branch 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

Misc radeon and amdgpu fixes:
- SMU firmware loading fix for Stoney
- DP audio fixes for DCE4.1
- Don't expose fbdev device if no connectors
- fix page table LRU list update handling

* 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux:
  drm/amdgpu: only move pt bos in LRU list on success
  drm/radeon: fix DP audio support for APU with DCE4.1 display engine
  drm/radeon: Add a common function for DFS handling
  drm/radeon: cleaned up VCO output settings for DP audio
  drm/amd/powerplay: Update SMU firmware loading for Stoney
  drm/amdgpu: don't init fbdev if we don't have any connectors
  drm/radeon: only init fbdev if we have connectors
  drm/radeon: Ensure radeon bo is unreserved in radeon_gem_va_ioctl
  drm/amdgpu: fix next_rptr handling for debugfs
  drm/radeon: properly byte swap vce firmware setup
  drm/amdgpu: add a message to indicate when powerplay is enabled (v2)
  drm/amdgpu: fix amdgpu_bo_pin_restricted VRAM placing v2
  drm/amd/amdgpu: Improve amdgpu_dpm* macros to avoid unexpected result (v2)
  drm/amdgpu: Allow the driver to load if amdgpu.powerplay=1 on asics without powerplay support
  drm/amdgpu: Use drm_calloc_large for VM page_tables array
  drm/amdgpu: Add some tweaks to gfx 8 soft reset
  drm/amdgpu: fix tonga smu resume

21 files changed, 192 insertions, 101 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 313b0cc8d676..82edf95b7740 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2278,60 +2278,60 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
 
 #define amdgpu_dpm_get_temperature(adev) \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
-              (adev)->pm.funcs->get_temperature((adev))
+              (adev)->pm.funcs->get_temperature((adev)))
 
 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
-              (adev)->pm.funcs->set_fan_control_mode((adev), (m))
+              (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
 
 #define amdgpu_dpm_get_fan_control_mode(adev) \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
-              (adev)->pm.funcs->get_fan_control_mode((adev))
+              (adev)->pm.funcs->get_fan_control_mode((adev)))
 
 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
-              (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
+              (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
 
 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
-              (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
+              (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
 
 #define amdgpu_dpm_get_sclk(adev, l) \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
-                (adev)->pm.funcs->get_sclk((adev), (l))
+                (adev)->pm.funcs->get_sclk((adev), (l)))
 
 #define amdgpu_dpm_get_mclk(adev, l)  \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
-              (adev)->pm.funcs->get_mclk((adev), (l))
+              (adev)->pm.funcs->get_mclk((adev), (l)))
 
 
 #define amdgpu_dpm_force_performance_level(adev, l) \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
-              (adev)->pm.funcs->force_performance_level((adev), (l))
+              (adev)->pm.funcs->force_performance_level((adev), (l)))
 
 #define amdgpu_dpm_powergate_uvd(adev, g) \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
-              (adev)->pm.funcs->powergate_uvd((adev), (g))
+              (adev)->pm.funcs->powergate_uvd((adev), (g)))
 
 #define amdgpu_dpm_powergate_vce(adev, g) \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
-              (adev)->pm.funcs->powergate_vce((adev), (g))
+              (adev)->pm.funcs->powergate_vce((adev), (g)))
 
 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
-        (adev)->pp_enabled ?                                            \
+        ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
-              (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
+              (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
 
 #define amdgpu_dpm_get_current_power_state(adev) \
         (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 6f89f8e034d0..b882e8175615 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -478,9 +478,9 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo
         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
         unsigned i;
 
-        amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
-
         if (!error) {
+                amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
+
                 /* Sort the buffer list from the smallest to largest buffer,
                  * which affects the order of buffers in the LRU list.
                  * This assures that the smallest buffers are added first
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index cfb6caad2a73..919146780a15 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -333,6 +333,10 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev)
         if (!adev->mode_info.mode_config_initialized)
                 return 0;
 
+        /* don't init fbdev if there are no connectors */
+        if (list_empty(&adev->ddev->mode_config.connector_list))
+                return 0;
+
         /* select 8 bpp console on low vram cards */
         if (adev->mc.real_vram_size <= (32*1024*1024))
                 bpp_sel = 8;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index c3ce103b6a33..a2a16acee34d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -399,7 +399,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
                 }
                 if (fpfn > bo->placements[i].fpfn)
                         bo->placements[i].fpfn = fpfn;
-                if (lpfn && lpfn < bo->placements[i].lpfn)
+                if (!bo->placements[i].lpfn ||
+                    (lpfn && lpfn < bo->placements[i].lpfn))
                         bo->placements[i].lpfn = lpfn;
                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 5ee9a0690278..b9d0d55f6b47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -99,13 +99,24 @@ static int amdgpu_pp_early_init(void *handle)
 
 #ifdef CONFIG_DRM_AMD_POWERPLAY
         switch (adev->asic_type) {
-                case CHIP_TONGA:
-                case CHIP_FIJI:
-                        adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
-                        break;
-                default:
-                        adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
-                        break;
+        case CHIP_TONGA:
+        case CHIP_FIJI:
+                adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
+                break;
+        case CHIP_CARRIZO:
+        case CHIP_STONEY:
+                adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
+                break;
+        /* These chips don't have powerplay implemenations */
+        case CHIP_BONAIRE:
+        case CHIP_HAWAII:
+        case CHIP_KABINI:
+        case CHIP_MULLINS:
+        case CHIP_KAVERI:
+        case CHIP_TOPAZ:
+        default:
+                adev->pp_enabled = false;
+                break;
         }
 #else
         adev->pp_enabled = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 78e9b0f14661..d1f234dd2126 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -487,7 +487,7 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
         seq_printf(m, "rptr: 0x%08x [%5d]\n",
                    rptr, rptr);
 
-        rptr_next = ~0;
+        rptr_next = le32_to_cpu(*ring->next_rptr_cpu_addr);
 
         seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
                    ring->wptr, ring->wptr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index aefc668e6b5d..9599f7559b3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1282,7 +1282,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 {
         const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
                 AMDGPU_VM_PTE_COUNT * 8);
-        unsigned pd_size, pd_entries, pts_size;
+        unsigned pd_size, pd_entries;
         int i, r;
 
         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
@@ -1300,8 +1300,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
         pd_entries = amdgpu_vm_num_pdes(adev);
 
         /* allocate page table array */
-        pts_size = pd_entries * sizeof(struct amdgpu_vm_pt);
-        vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
+        vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt));
         if (vm->page_tables == NULL) {
                 DRM_ERROR("Cannot allocate memory for page table array\n");
                 return -ENOMEM;
@@ -1361,7 +1360,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 
         for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
                 amdgpu_bo_unref(&vm->page_tables[i].entry.robj);
-        kfree(vm->page_tables);
+        drm_free_large(vm->page_tables);
 
         amdgpu_bo_unref(&vm->page_directory);
         fence_put(vm->page_directory_fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 13235d84e5a6..95c0cdfbd1b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4186,7 +4186,18 @@ static int gfx_v8_0_soft_reset(void *handle)
                 gfx_v8_0_cp_gfx_enable(adev, false);
 
                 /* Disable MEC parsing/prefetching */
-                /* XXX todo */
+                gfx_v8_0_cp_compute_enable(adev, false);
+
+                if (grbm_soft_reset || srbm_soft_reset) {
+                        tmp = RREG32(mmGMCON_DEBUG);
+                        tmp = REG_SET_FIELD(tmp,
+                                            GMCON_DEBUG, GFX_STALL, 1);
+                        tmp = REG_SET_FIELD(tmp,
+                                            GMCON_DEBUG, GFX_CLEAR, 1);
+                        WREG32(mmGMCON_DEBUG, tmp);
+
+                        udelay(50);
+                }
 
                 if (grbm_soft_reset) {
                         tmp = RREG32(mmGRBM_SOFT_RESET);
@@ -4215,6 +4226,16 @@ static int gfx_v8_0_soft_reset(void *handle)
                         WREG32(mmSRBM_SOFT_RESET, tmp);
                         tmp = RREG32(mmSRBM_SOFT_RESET);
                 }
+
+                if (grbm_soft_reset || srbm_soft_reset) {
+                        tmp = RREG32(mmGMCON_DEBUG);
+                        tmp = REG_SET_FIELD(tmp,
+                                            GMCON_DEBUG, GFX_STALL, 0);
+                        tmp = REG_SET_FIELD(tmp,
+                                            GMCON_DEBUG, GFX_CLEAR, 0);
+                        WREG32(mmGMCON_DEBUG, tmp);
+                }
+
                 /* Wait a little for things to settle down */
                 udelay(50);
                 gfx_v8_0_print_status((void *)adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
index f4a1346525fe..0497784b3652 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
@@ -122,25 +122,12 @@ static int tonga_dpm_hw_fini(void *handle)
 
 static int tonga_dpm_suspend(void *handle)
 {
-        return 0;
+        return tonga_dpm_hw_fini(handle);
 }
 
 static int tonga_dpm_resume(void *handle)
 {
-        int ret;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        mutex_lock(&adev->pm.mutex);
-
-        ret = tonga_smu_start(adev);
-        if (ret) {
-                DRM_ERROR("SMU start failed\n");
-                goto fail;
-        }
-
-fail:
-        mutex_unlock(&adev->pm.mutex);
-        return ret;
+        return tonga_dpm_hw_init(handle);
 }
 
 static int tonga_dpm_set_clockgating_state(void *handle,
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 8f5d5edcf193..aa67244a77ae 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -64,6 +64,11 @@ static int pp_sw_init(void *handle)
         if (ret == 0)
                 ret = hwmgr->hwmgr_func->backend_init(hwmgr);
 
+        if (ret)
+                printk("amdgpu: powerplay initialization failed\n");
+        else
+                printk("amdgpu: powerplay initialized\n");
+
         return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 873a8d264d5c..ec222c665602 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -272,6 +272,9 @@ static int cz_start_smu(struct pp_smumgr *smumgr)
                                 UCODE_ID_CP_MEC_JT1_MASK |
                                 UCODE_ID_CP_MEC_JT2_MASK;
 
+        if (smumgr->chip_id == CHIP_STONEY)
+                fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
+
         cz_request_smu_load_fw(smumgr);
         cz_check_fw_load_finish(smumgr, fw_to_check);
 
@@ -282,7 +285,7 @@ static int cz_start_smu(struct pp_smumgr *smumgr)
         return ret;
 }
 
-static uint8_t cz_translate_firmware_enum_to_arg(
+static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
                         enum cz_scratch_entry firmware_enum)
 {
         uint8_t ret = 0;
@@ -292,7 +295,10 @@ static uint8_t cz_translate_firmware_enum_to_arg(
                 ret = UCODE_ID_SDMA0;
                 break;
         case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
-                ret = UCODE_ID_SDMA1;
+                if (smumgr->chip_id == CHIP_STONEY)
+                        ret = UCODE_ID_SDMA0;
+                else
+                        ret = UCODE_ID_SDMA1;
                 break;
         case CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE:
                 ret = UCODE_ID_CP_CE;
@@ -307,7 +313,10 @@ static uint8_t cz_translate_firmware_enum_to_arg(
                 ret = UCODE_ID_CP_MEC_JT1;
                 break;
         case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
-                ret = UCODE_ID_CP_MEC_JT2;
+                if (smumgr->chip_id == CHIP_STONEY)
+                        ret = UCODE_ID_CP_MEC_JT1;
+                else
+                        ret = UCODE_ID_CP_MEC_JT2;
                 break;
         case CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG:
                 ret = UCODE_ID_GMCON_RENG;
@@ -396,7 +405,7 @@ static int cz_smu_populate_single_scratch_task(
         struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
 
         task->type = type;
-        task->arg = cz_translate_firmware_enum_to_arg(fw_enum);
+        task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum);
         task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
 
         for (i = 0; i < cz_smu->scratch_buffer_length; i++)
@@ -433,7 +442,7 @@ static int cz_smu_populate_single_ucode_load_task(
         struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
 
         task->type = TASK_TYPE_UCODE_LOAD;
-        task->arg = cz_translate_firmware_enum_to_arg(fw_enum);
+        task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum);
         task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
 
         for (i = 0; i < cz_smu->driver_buffer_length; i++)
@@ -509,8 +518,14 @@ static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_smumgr *smumgr)
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
         cz_smu_populate_single_ucode_load_task(smumgr,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
-        cz_smu_populate_single_ucode_load_task(smumgr,
+
+        if (smumgr->chip_id == CHIP_STONEY)
+                cz_smu_populate_single_ucode_load_task(smumgr,
+                                CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
+        else
+                cz_smu_populate_single_ucode_load_task(smumgr,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
+
         cz_smu_populate_single_ucode_load_task(smumgr,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
 
@@ -551,7 +566,11 @@ static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr)
 
         cz_smu_populate_single_ucode_load_task(smumgr,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
-        cz_smu_populate_single_ucode_load_task(smumgr,
+        if (smumgr->chip_id == CHIP_STONEY)
+                cz_smu_populate_single_ucode_load_task(smumgr,
+                                CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
+        else
+                cz_smu_populate_single_ucode_load_task(smumgr,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
         cz_smu_populate_single_ucode_load_task(smumgr,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
@@ -561,7 +580,11 @@ static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr)
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
         cz_smu_populate_single_ucode_load_task(smumgr,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
-        cz_smu_populate_single_ucode_load_task(smumgr,
+        if (smumgr->chip_id == CHIP_STONEY)
+                cz_smu_populate_single_ucode_load_task(smumgr,
+                                CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
+        else
+                cz_smu_populate_single_ucode_load_task(smumgr,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
         cz_smu_populate_single_ucode_load_task(smumgr,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
@@ -618,7 +641,7 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
 
         for (i = 0; i < sizeof(firmware_list)/sizeof(*firmware_list); i++) {
 
-                firmware_type = cz_translate_firmware_enum_to_arg(
+                firmware_type = cz_translate_firmware_enum_to_arg(smumgr,
                                         firmware_list[i]);
 
                 ucode_id = cz_convert_fw_type_to_cgs(firmware_type);
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
index 6bfc46369db1..367a916f364e 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -304,18 +304,10 @@ void dce6_dp_audio_set_dto(struct radeon_device *rdev,
                 unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &
                         DENTIST_DPREFCLK_WDIVIDER_MASK) >>
                         DENTIST_DPREFCLK_WDIVIDER_SHIFT;
-
-                if (div < 128 && div >= 96)
-                        div -= 64;
-                else if (div >= 64)
-                        div = div / 2 - 16;
-                else if (div >= 8)
-                        div /= 4;
-                else
-                        div = 0;
+                div = radeon_audio_decode_dfs_div(div);
 
                 if (div)
-                        clock = rdev->clock.gpupll_outputfreq * 10 / div;
+                        clock = clock * 100 / div;
 
                 WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
                 WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 9953356fe263..3cf04a2f44bb 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -289,6 +289,16 @@ void dce4_dp_audio_set_dto(struct radeon_device *rdev,
          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
          */
+        if (ASIC_IS_DCE41(rdev)) {
+                unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) &
+                        DENTIST_DPREFCLK_WDIVIDER_MASK) >>
+                        DENTIST_DPREFCLK_WDIVIDER_SHIFT;
+                div = radeon_audio_decode_dfs_div(div);
+
+                if (div)
+                        clock = 100 * clock / div;
+        }
+
         WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
         WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
 }
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 4aa5f755572b..13b6029d65cc 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -511,6 +511,11 @@
 #define DCCG_AUDIO_DTO1_CNTL              0x05cc
 #       define DCCG_AUDIO_DTO1_USE_512FBR_DTO (1 << 3)
 
+#define DCE41_DENTIST_DISPCLK_CNTL                      0x049c
+#       define DENTIST_DPREFCLK_WDIVIDER(x)             (((x) & 0x7f) << 24)
+#       define DENTIST_DPREFCLK_WDIVIDER_MASK           (0x7f << 24)
+#       define DENTIST_DPREFCLK_WDIVIDER_SHIFT          24
+
 /* DCE 4.0 AFMT */
 #define HDMI_CONTROL                         0x7030
 #       define HDMI_KEEPOUT_MODE             (1 << 0)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5ae6db98aa4d..78a51b3eda10 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -268,7 +268,7 @@ struct radeon_clock {
         uint32_t current_dispclk;
         uint32_t dp_extclk;
         uint32_t max_pixel_clock;
-        uint32_t gpupll_outputfreq;
+        uint32_t vco_freq;
 };
 
 /*
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 08fc1b5effa8..de9a2ffcf5f7 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1106,6 +1106,31 @@ union firmware_info {
         ATOM_FIRMWARE_INFO_V2_2 info_22;
 };
 
+union igp_info {
+        struct _ATOM_INTEGRATED_SYSTEM_INFO info;
+        struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
+        struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
+        struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
+        struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
+};
+
+static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
+{
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
+        union igp_info *igp_info;
+        u8 frev, crev;
+        u16 data_offset;
+
+        if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                        &frev, &crev, &data_offset)) {
+                igp_info = (union igp_info *)(mode_info->atom_context->bios +
+                        data_offset);
+                rdev->clock.vco_freq =
+                        le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
+        }
+}
+
 bool radeon_atom_get_clock_info(struct drm_device *dev)
 {
         struct radeon_device *rdev = dev->dev_private;
@@ -1257,12 +1282,18 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
                 rdev->mode_info.firmware_flags =
                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
 
-                if (ASIC_IS_DCE8(rdev)) {
-                        rdev->clock.gpupll_outputfreq =
+                if (ASIC_IS_DCE8(rdev))
+                        rdev->clock.vco_freq =
                                 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
-                        if (rdev->clock.gpupll_outputfreq == 0)
-                                rdev->clock.gpupll_outputfreq = 360000; /* 3.6 GHz */
-                }
+                else if (ASIC_IS_DCE5(rdev))
+                        rdev->clock.vco_freq = rdev->clock.current_dispclk;
+                else if (ASIC_IS_DCE41(rdev))
+                        radeon_atombios_get_dentist_vco_freq(rdev);
+                else
+                        rdev->clock.vco_freq = rdev->clock.current_dispclk;
+
+                if (rdev->clock.vco_freq == 0)
+                        rdev->clock.vco_freq = 360000;  /* 3.6 GHz */
 
                 return true;
         }
@@ -1270,14 +1301,6 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
         return false;
 }
 
-union igp_info {
-        struct _ATOM_INTEGRATED_SYSTEM_INFO info;
-        struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
-        struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
-        struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
-        struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
-};
-
 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
 {
         struct radeon_mode_info *mode_info = &rdev->mode_info;
diff --git a/drivers/gpu/drm/radeon/radeon_audio.c b/drivers/gpu/drm/radeon/radeon_audio.c
index 2c02e99b5f95..b214663b370d 100644
--- a/drivers/gpu/drm/radeon/radeon_audio.c
+++ b/drivers/gpu/drm/radeon/radeon_audio.c
@@ -739,9 +739,6 @@ static void radeon_audio_dp_mode_set(struct drm_encoder *encoder,
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
-        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
-        struct radeon_connector_atom_dig *dig_connector =
-                radeon_connector->con_priv;
 
         if (!dig || !dig->afmt)
                 return;
@@ -753,10 +750,7 @@ static void radeon_audio_dp_mode_set(struct drm_encoder *encoder,
                 radeon_audio_write_speaker_allocation(encoder);
                 radeon_audio_write_sad_regs(encoder);
                 radeon_audio_write_latency_fields(encoder, mode);
-                if (rdev->clock.dp_extclk || ASIC_IS_DCE5(rdev))
-                        radeon_audio_set_dto(encoder, rdev->clock.default_dispclk * 10);
-                else
-                        radeon_audio_set_dto(encoder, dig_connector->dp_clock);
+                radeon_audio_set_dto(encoder, rdev->clock.vco_freq * 10);
                 radeon_audio_set_audio_packet(encoder);
                 radeon_audio_select_pin(encoder);
 
@@ -781,3 +775,15 @@ void radeon_audio_dpms(struct drm_encoder *encoder, int mode)
         if (radeon_encoder->audio && radeon_encoder->audio->dpms)
                 radeon_encoder->audio->dpms(encoder, mode == DRM_MODE_DPMS_ON);
 }
+
+unsigned int radeon_audio_decode_dfs_div(unsigned int div)
+{
+        if (div >= 8 && div < 64)
+                return (div - 8) * 25 + 200;
+        else if (div >= 64 && div < 96)
+                return (div - 64) * 50 + 1600;
+        else if (div >= 96 && div < 128)
+                return (div - 96) * 100 + 3200;
+        else
+                return 0;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_audio.h b/drivers/gpu/drm/radeon/radeon_audio.h
index 059cc3012062..5c70cceaa4a6 100644
--- a/drivers/gpu/drm/radeon/radeon_audio.h
+++ b/drivers/gpu/drm/radeon/radeon_audio.h
@@ -79,5 +79,6 @@ void radeon_audio_fini(struct radeon_device *rdev);
 void radeon_audio_mode_set(struct drm_encoder *encoder,
         struct drm_display_mode *mode);
 void radeon_audio_dpms(struct drm_encoder *encoder, int mode);
+unsigned int radeon_audio_decode_dfs_div(unsigned int div);
 
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index b3bb92368ae0..298ea1c453c3 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1670,8 +1670,10 @@ int radeon_modeset_init(struct radeon_device *rdev)
         /* setup afmt */
         radeon_afmt_init(rdev);
 
-        radeon_fbdev_init(rdev);
-        drm_kms_helper_poll_init(rdev->ddev);
+        if (!list_empty(&rdev->ddev->mode_config.connector_list)) {
+                radeon_fbdev_init(rdev);
+                drm_kms_helper_poll_init(rdev->ddev);
+        }
 
         /* do pm late init */
         ret = radeon_pm_late_init(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 3dcc5733ff69..e26c963f2e93 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -663,6 +663,7 @@ int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
         bo_va = radeon_vm_bo_find(&fpriv->vm, rbo);
         if (!bo_va) {
                 args->operation = RADEON_VA_RESULT_ERROR;
+                radeon_bo_unreserve(rbo);
                 drm_gem_object_unreference_unlocked(gobj);
                 return -ENOENT;
         }
diff --git a/drivers/gpu/drm/radeon/vce_v1_0.c b/drivers/gpu/drm/radeon/vce_v1_0.c
index 07a0d378e122..a01efe39a820 100644
--- a/drivers/gpu/drm/radeon/vce_v1_0.c
+++ b/drivers/gpu/drm/radeon/vce_v1_0.c
@@ -178,12 +178,12 @@ int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data)
                 return -EINVAL;
         }
 
-        for (i = 0; i < sign->num; ++i) {
-                if (sign->val[i].chip_id == chip_id)
+        for (i = 0; i < le32_to_cpu(sign->num); ++i) {
+                if (le32_to_cpu(sign->val[i].chip_id) == chip_id)
                         break;
         }
 
-        if (i == sign->num)
+        if (i == le32_to_cpu(sign->num))
                 return -EINVAL;
 
         data += (256 - 64) / 4;
@@ -191,18 +191,18 @@ int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data)
         data[1] = sign->val[i].nonce[1];
         data[2] = sign->val[i].nonce[2];
         data[3] = sign->val[i].nonce[3];
-        data[4] = sign->len + 64;
+        data[4] = cpu_to_le32(le32_to_cpu(sign->len) + 64);
 
         memset(&data[5], 0, 44);
         memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign));
 
-        data += data[4] / 4;
+        data += le32_to_cpu(data[4]) / 4;
         data[0] = sign->val[i].sigval[0];
         data[1] = sign->val[i].sigval[1];
         data[2] = sign->val[i].sigval[2];
         data[3] = sign->val[i].sigval[3];
 
-        rdev->vce.keyselect = sign->val[i].keyselect;
+        rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect);
 
         return 0;
 }