aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAlexey Brodkin <abrodkin@synopsys.com>2014-01-27 08:51:34 -0500
committerVineet Gupta <vgupta@synopsys.com>2015-06-19 08:39:30 -0400
commit556cc1c5f528dcc87733920de17d61b6ebe8999d (patch)
tree934095ed4cb8f9454bd271cbadffa98c994dc9a2
parent4db27dca607aed14a852b21db02ddb530551c5eb (diff)
ARC: [axs101] Add support for AXS101 SDP (software development platform)
The AXS10x platforms consist of a mainboard with peripherals, on which several daughter cards can be placed. The daughter cards typically contain a CPU and memory. Signed-off-by: Mischa Jonker <mjonker@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arc/axs101.txt7
-rw-r--r--MAINTAINERS7
-rw-r--r--arch/arc/Kconfig1
-rw-r--r--arch/arc/Makefile1
-rw-r--r--arch/arc/boot/dts/axc001.dtsi79
-rw-r--r--arch/arc/boot/dts/axs101.dts21
-rw-r--r--arch/arc/boot/dts/axs10x_mb.dtsi223
-rw-r--r--arch/arc/configs/axs101_defconfig111
-rw-r--r--arch/arc/plat-axs10x/Kconfig35
-rw-r--r--arch/arc/plat-axs10x/Makefile9
-rw-r--r--arch/arc/plat-axs10x/axs10x.c298
11 files changed, 792 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arc/axs101.txt b/Documentation/devicetree/bindings/arc/axs101.txt
new file mode 100644
index 000000000000..568aa5f74de2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arc/axs101.txt
@@ -0,0 +1,7 @@
1Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
2---------------------------------------------------------------------------
3
4SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon
5
6Required root node properties:
7 - compatible = "snps,axs101";
diff --git a/MAINTAINERS b/MAINTAINERS
index f8e0afb708b4..3a9afc9ec050 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9579,6 +9579,13 @@ F: arch/arc/
9579F: Documentation/devicetree/bindings/arc/ 9579F: Documentation/devicetree/bindings/arc/
9580F: drivers/tty/serial/arc_uart.c 9580F: drivers/tty/serial/arc_uart.c
9581 9581
9582SYNOPSYS ARC SDP platform support
9583M: Alexey Brodkin <abrodkin@synopsys.com>
9584S: Supported
9585F: arch/arc/plat-axs10x
9586F: arch/arc/boot/dts/ax*
9587F: Documentation/devicetree/bindings/arc/axs10*
9588
9582SYSV FILESYSTEM 9589SYSV FILESYSTEM
9583M: Christoph Hellwig <hch@infradead.org> 9590M: Christoph Hellwig <hch@infradead.org>
9584S: Maintained 9591S: Maintained
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index b52f7eba6765..1eeefd9763d1 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -83,6 +83,7 @@ menu "ARC Platform/SoC/Board"
83 83
84source "arch/arc/plat-sim/Kconfig" 84source "arch/arc/plat-sim/Kconfig"
85source "arch/arc/plat-tb10x/Kconfig" 85source "arch/arc/plat-tb10x/Kconfig"
86source "arch/arc/plat-axs10x/Kconfig"
86#New platform adds here 87#New platform adds here
87 88
88endmenu 89endmenu
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 435b693637f6..86c71b2089d2 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -83,6 +83,7 @@ core-y += arch/arc/boot/dts/
83 83
84core-$(CONFIG_ARC_PLAT_SIM) += arch/arc/plat-sim/ 84core-$(CONFIG_ARC_PLAT_SIM) += arch/arc/plat-sim/
85core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/ 85core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/
86core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/
86 87
87drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/ 88drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/
88 89
diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi
new file mode 100644
index 000000000000..6990ca45fc7b
--- /dev/null
+++ b/arch/arc/boot/dts/axc001.dtsi
@@ -0,0 +1,79 @@
1/*
2 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device tree for AXC001 770D/EM6/AS221 CPU card
11 * Note that this file only supports the 770D CPU
12 */
13
14/ {
15 compatible = "snps,arc";
16 clock-frequency = <750000000>; /* 750 MHZ */
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpu_card {
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x00000000 0xf0000000 0x10000000>;
26
27 cpu_intc: arc700-intc@cpu {
28 compatible = "snps,arc700-intc";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 };
32
33 /*
34 * this GPIO block ORs all interrupts on CPU card (creg,..)
35 * to uplink only 1 IRQ to ARC core intc
36 */
37 dw-apb-gpio@0x2000 {
38 compatible = "snps,dw-apb-gpio";
39 reg = < 0x2000 0x80 >;
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ictl_intc: gpio-controller@0 {
44 compatible = "snps,dw-apb-gpio-port";
45 gpio-controller;
46 #gpio-cells = <2>;
47 snps,nr-gpios = <30>;
48 reg = <0>;
49 interrupt-controller;
50 #interrupt-cells = <2>;
51 interrupt-parent = <&cpu_intc>;
52 interrupts = <15>;
53 };
54 };
55
56 debug_uart: dw-apb-uart@0x5000 {
57 compatible = "snps,dw-apb-uart";
58 reg = <0x5000 0x100>;
59 clock-frequency = <33333000>;
60 interrupt-parent = <&ictl_intc>;
61 interrupts = <19 4>;
62 baud = <115200>;
63 reg-shift = <2>;
64 reg-io-width = <4>;
65 };
66
67 arcpmu0: pmu {
68 compatible = "snps,arc700-pct";
69 };
70 };
71
72 memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges = <0x00000000 0x80000000 0x40000000>;
76 device_type = "memory";
77 reg = <0x00000000 0x20000000>; /* 512MiB */
78 };
79};
diff --git a/arch/arc/boot/dts/axs101.dts b/arch/arc/boot/dts/axs101.dts
new file mode 100644
index 000000000000..6c3391da0e3b
--- /dev/null
+++ b/arch/arc/boot/dts/axs101.dts
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * ARC AXS101 S/W development platform
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10/dts-v1/;
11
12/include/ "axc001.dtsi"
13/include/ "axs10x_mb.dtsi"
14
15/ {
16 compatible = "snps,axs101";
17
18 chosen {
19 bootargs = "console=tty0 console=ttyS3,115200n8 consoleblank=0";
20 };
21};
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
new file mode 100644
index 000000000000..255c7121ea80
--- /dev/null
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -0,0 +1,223 @@
1/*
2 * Support for peripherals on the AXS10x mainboard
3 *
4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/ {
12 axs10x_mb {
13 compatible = "simple-bus";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges = <0x00000000 0xe0000000 0x10000000>;
17 interrupt-parent = <&mb_intc>;
18
19 clocks {
20 i2cclk: i2cclk {
21 compatible = "fixed-clock";
22 clock-frequency = <50000000>;
23 #clock-cells = <0>;
24 };
25
26 apbclk: apbclk {
27 compatible = "fixed-clock";
28 clock-frequency = <50000000>;
29 #clock-cells = <0>;
30 };
31
32 mmcclk: mmcclk {
33 compatible = "fixed-clock";
34 clock-frequency = <50000000>;
35 #clock-cells = <0>;
36 };
37 };
38
39 /*
40 * This INTC is actually connected to DW APB GPIO
41 * which acts as a wire between MB INTC and CPU INTC.
42 * GPIO INTC is configured in platform init code
43 * and here we mimic direct connection from MB INTC to
44 * CPU INTC, thus we set "interrupts = <7>" instead of
45 * "interrupts = <12>"
46 */
47 mb_intc: dw-apb-ictl@0x12000 {
48 #interrupt-cells = <1>;
49 compatible = "snps,dw-apb-ictl";
50 reg = < 0x12000 0x200 >;
51 interrupt-controller;
52 interrupt-parent = <&cpu_intc>;
53 interrupts = < 7 >;
54 };
55
56 ethernet@0x18000 {
57 #interrupt-cells = <1>;
58 compatible = "snps,dwmac";
59 reg = < 0x18000 0x2000 >;
60 interrupts = < 4 >;
61 interrupt-names = "macirq";
62 phy-mode = "rgmii";
63 snps,pbl = < 32 >;
64 clocks = <&apbclk>;
65 clock-names = "stmmaceth";
66 };
67
68 ehci@0x40000 {
69 compatible = "generic-ehci";
70 reg = < 0x40000 0x100 >;
71 interrupts = < 8 >;
72 };
73
74 ohci@0x60000 {
75 compatible = "generic-ohci";
76 reg = < 0x60000 0x100 >;
77 interrupts = < 8 >;
78 };
79
80 mmc@0x15000 {
81 compatible = "snps,dw-mshc";
82 reg = < 0x15000 0x400 >;
83 num-slots = < 1 >;
84 fifo-depth = < 16 >;
85 card-detect-delay = < 200 >;
86 clocks = <&apbclk>, <&mmcclk>;
87 clock-names = "biu", "ciu";
88 interrupts = < 7 >;
89 bus-width = < 4 >;
90 };
91
92 uart@0x20000 {
93 compatible = "snps,dw-apb-uart";
94 reg = <0x20000 0x100>;
95 clock-frequency = <33333333>;
96 interrupts = <17>;
97 baud = <115200>;
98 reg-shift = <2>;
99 reg-io-width = <4>;
100 };
101
102 uart@0x21000 {
103 compatible = "snps,dw-apb-uart";
104 reg = <0x21000 0x100>;
105 clock-frequency = <33333333>;
106 interrupts = <18>;
107 baud = <115200>;
108 reg-shift = <2>;
109 reg-io-width = <4>;
110 };
111
112 /* UART muxed with USB data port (ttyS3) */
113 uart@0x22000 {
114 compatible = "snps,dw-apb-uart";
115 reg = <0x22000 0x100>;
116 clock-frequency = <33333333>;
117 interrupts = <19>;
118 baud = <115200>;
119 reg-shift = <2>;
120 reg-io-width = <4>;
121 };
122
123 i2c@0x1d000 {
124 compatible = "snps,designware-i2c";
125 reg = <0x1d000 0x100>;
126 clock-frequency = <400000>;
127 clocks = <&i2cclk>;
128 interrupts = <14>;
129 };
130
131 i2c@0x1e000 {
132 compatible = "snps,designware-i2c";
133 reg = <0x1e000 0x100>;
134 clock-frequency = <400000>;
135 clocks = <&i2cclk>;
136 interrupts = <15>;
137 };
138
139 i2c@0x1f000 {
140 compatible = "snps,designware-i2c";
141 #address-cells = <1>;
142 #size-cells = <0>;
143 reg = <0x1f000 0x100>;
144 clock-frequency = <400000>;
145 clocks = <&i2cclk>;
146 interrupts = <16>;
147
148 eeprom@0x54{
149 compatible = "24c01";
150 reg = <0x54>;
151 pagesize = <0x8>;
152 };
153
154 eeprom@0x57{
155 compatible = "24c04";
156 reg = <0x57>;
157 pagesize = <0x8>;
158 };
159 };
160
161 gpio0:gpio@13000 {
162 compatible = "snps,dw-apb-gpio";
163 reg = <0x13000 0x1000>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166
167 gpio0_banka: gpio-controller@0 {
168 compatible = "snps,dw-apb-gpio-port";
169 gpio-controller;
170 #gpio-cells = <2>;
171 snps,nr-gpios = <32>;
172 reg = <0>;
173 };
174
175 gpio0_bankb: gpio-controller@1 {
176 compatible = "snps,dw-apb-gpio-port";
177 gpio-controller;
178 #gpio-cells = <2>;
179 snps,nr-gpios = <8>;
180 reg = <1>;
181 };
182
183 gpio0_bankc: gpio-controller@2 {
184 compatible = "snps,dw-apb-gpio-port";
185 gpio-controller;
186 #gpio-cells = <2>;
187 snps,nr-gpios = <8>;
188 reg = <2>;
189 };
190 };
191
192 gpio1:gpio@14000 {
193 compatible = "snps,dw-apb-gpio";
194 reg = <0x14000 0x1000>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197
198 gpio1_banka: gpio-controller@0 {
199 compatible = "snps,dw-apb-gpio-port";
200 gpio-controller;
201 #gpio-cells = <2>;
202 snps,nr-gpios = <30>;
203 reg = <0>;
204 };
205
206 gpio1_bankb: gpio-controller@1 {
207 compatible = "snps,dw-apb-gpio-port";
208 gpio-controller;
209 #gpio-cells = <2>;
210 snps,nr-gpios = <10>;
211 reg = <1>;
212 };
213
214 gpio1_bankc: gpio-controller@2 {
215 compatible = "snps,dw-apb-gpio-port";
216 gpio-controller;
217 #gpio-cells = <2>;
218 snps,nr-gpios = <8>;
219 reg = <2>;
220 };
221 };
222 };
223};
diff --git a/arch/arc/configs/axs101_defconfig b/arch/arc/configs/axs101_defconfig
new file mode 100644
index 000000000000..562dac6a7f78
--- /dev/null
+++ b/arch/arc/configs/axs101_defconfig
@@ -0,0 +1,111 @@
1CONFIG_CROSS_COMPILE="arc-linux-uclibc-"
2CONFIG_DEFAULT_HOSTNAME="ARCLinux"
3# CONFIG_SWAP is not set
4CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y
6# CONFIG_CROSS_MEMORY_ATTACH is not set
7CONFIG_NO_HZ_IDLE=y
8CONFIG_HIGH_RES_TIMERS=y
9CONFIG_IKCONFIG=y
10CONFIG_IKCONFIG_PROC=y
11CONFIG_NAMESPACES=y
12# CONFIG_UTS_NS is not set
13# CONFIG_PID_NS is not set
14CONFIG_BLK_DEV_INITRD=y
15CONFIG_INITRAMFS_SOURCE="../arc_initramfs/"
16CONFIG_EMBEDDED=y
17CONFIG_PERF_EVENTS=y
18# CONFIG_VM_EVENT_COUNTERS is not set
19# CONFIG_SLUB_DEBUG is not set
20# CONFIG_COMPAT_BRK is not set
21CONFIG_MODULES=y
22CONFIG_PARTITION_ADVANCED=y
23CONFIG_ARC_PLAT_AXS10X=y
24CONFIG_AXS101=y
25CONFIG_ARC_CACHE_LINE_SHIFT=5
26CONFIG_ARC_BUILTIN_DTB_NAME="axs101"
27CONFIG_PREEMPT=y
28# CONFIG_COMPACTION is not set
29CONFIG_NET=y
30CONFIG_PACKET=y
31CONFIG_UNIX=y
32CONFIG_NET_KEY=y
33CONFIG_INET=y
34CONFIG_IP_PNP=y
35CONFIG_IP_PNP_DHCP=y
36CONFIG_IP_PNP_BOOTP=y
37CONFIG_IP_PNP_RARP=y
38# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_IPV6 is not set
42# CONFIG_STANDALONE is not set
43# CONFIG_PREVENT_FIRMWARE_BUILD is not set
44# CONFIG_FIRMWARE_IN_KERNEL is not set
45CONFIG_SCSI=y
46CONFIG_BLK_DEV_SD=y
47CONFIG_NETDEVICES=y
48# CONFIG_NET_VENDOR_ARC is not set
49# CONFIG_NET_VENDOR_BROADCOM is not set
50# CONFIG_NET_VENDOR_INTEL is not set
51# CONFIG_NET_VENDOR_MARVELL is not set
52# CONFIG_NET_VENDOR_MICREL is not set
53# CONFIG_NET_VENDOR_NATSEMI is not set
54# CONFIG_NET_VENDOR_SEEQ is not set
55CONFIG_STMMAC_ETH=y
56# CONFIG_NET_VENDOR_VIA is not set
57# CONFIG_NET_VENDOR_WIZNET is not set
58CONFIG_NATIONAL_PHY=y
59# CONFIG_USB_NET_DRIVERS is not set
60CONFIG_INPUT_EVDEV=y
61CONFIG_MOUSE_PS2_TOUCHKIT=y
62CONFIG_MOUSE_SERIAL=y
63CONFIG_MOUSE_SYNAPTICS_USB=y
64# CONFIG_LEGACY_PTYS is not set
65# CONFIG_DEVKMEM is not set
66CONFIG_SERIAL_8250=y
67CONFIG_SERIAL_8250_CONSOLE=y
68CONFIG_SERIAL_8250_DW=y
69CONFIG_SERIAL_OF_PLATFORM=y
70# CONFIG_HW_RANDOM is not set
71CONFIG_I2C=y
72CONFIG_I2C_CHARDEV=y
73CONFIG_I2C_DESIGNWARE_PLATFORM=y
74# CONFIG_HWMON is not set
75CONFIG_FB=y
76# CONFIG_VGA_CONSOLE is not set
77CONFIG_FRAMEBUFFER_CONSOLE=y
78CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
79CONFIG_LOGO=y
80# CONFIG_LOGO_LINUX_MONO is not set
81# CONFIG_LOGO_LINUX_VGA16 is not set
82# CONFIG_LOGO_LINUX_CLUT224 is not set
83CONFIG_USB_EHCI_HCD=y
84CONFIG_USB_EHCI_HCD_PLATFORM=y
85CONFIG_USB_OHCI_HCD=y
86CONFIG_USB_OHCI_HCD_PLATFORM=y
87CONFIG_USB_STORAGE=y
88CONFIG_MMC=y
89CONFIG_MMC_SDHCI=y
90CONFIG_MMC_SDHCI_PLTFM=y
91CONFIG_MMC_DW=y
92CONFIG_MMC_DW_IDMAC=y
93# CONFIG_IOMMU_SUPPORT is not set
94CONFIG_EXT3_FS=y
95CONFIG_EXT4_FS=y
96CONFIG_MSDOS_FS=y
97CONFIG_VFAT_FS=y
98CONFIG_NTFS_FS=y
99CONFIG_TMPFS=y
100CONFIG_JFFS2_FS=y
101CONFIG_NFS_FS=y
102CONFIG_NLS_CODEPAGE_437=y
103CONFIG_NLS_ISO8859_1=y
104# CONFIG_ENABLE_WARN_DEPRECATED is not set
105# CONFIG_ENABLE_MUST_CHECK is not set
106CONFIG_STRIP_ASM_SYMS=y
107CONFIG_LOCKUP_DETECTOR=y
108CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
109# CONFIG_SCHED_DEBUG is not set
110# CONFIG_DEBUG_PREEMPT is not set
111# CONFIG_FTRACE is not set
diff --git a/arch/arc/plat-axs10x/Kconfig b/arch/arc/plat-axs10x/Kconfig
new file mode 100644
index 000000000000..45641ca8aba8
--- /dev/null
+++ b/arch/arc/plat-axs10x/Kconfig
@@ -0,0 +1,35 @@
1#
2# Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License version 2 as
6# published by the Free Software Foundation.
7#
8
9config ARC_PLAT_AXS10X
10 bool "Synopsys ARC AXS10x Software Development Platforms"
11 select DW_APB_ICTL
12 select GPIO_DWAPB
13 select OF_GPIO
14 select GENERIC_IRQ_CHIP
15 select ARCH_REQUIRE_GPIOLIB
16 help
17 Support for the ARC AXS10x Software Development Platforms.
18
19 The AXS10x Platforms consist of a mainboard with peripherals,
20 on which several daughter cards can be placed. The daughter cards
21 typically contain a CPU and memory.
22
23if ARC_PLAT_AXS10X
24
25config AXS101
26 bool "AXS101 with AXC001 CPU Card (ARC 770D/EM6/AS221)"
27 help
28 This adds support for the 770D/EM6/AS221 CPU Card. Only the ARC
29 770D is supported in Linux.
30
31 The AXS101 Platform consists of an AXS10x mainboard with
32 this daughtercard. Please use the axs101.dts device tree
33 with this configuration.
34
35endif
diff --git a/arch/arc/plat-axs10x/Makefile b/arch/arc/plat-axs10x/Makefile
new file mode 100644
index 000000000000..d4748f27f86e
--- /dev/null
+++ b/arch/arc/plat-axs10x/Makefile
@@ -0,0 +1,9 @@
1#
2# Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License version 2 as
6# published by the Free Software Foundation.
7#
8
9obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x.o
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
new file mode 100644
index 000000000000..2e7686d1382f
--- /dev/null
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -0,0 +1,298 @@
1/*
2 * AXS101 Software Development Platform
3 *
4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/of_platform.h>
18#include <asm/mach_desc.h>
19#include <asm/io.h>
20
21#define AXS_MB_CGU 0xE0010000
22#define AXS_MB_CREG 0xE0011000
23
24#define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214)
25#define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220)
26#define CREG_MB_VER (AXS_MB_CREG + 0x230)
27#define CREG_MB_CONFIG (AXS_MB_CREG + 0x234)
28
29#define AXC001_CREG 0xF0001000
30#define AXC001_GPIO_INTC 0xF0003000
31
32#define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20)
33#define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60)
34#define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34)
35#define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74)
36
37#define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
38#define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120)
39
40static void enable_gpio_intc_wire(void)
41{
42 /*
43 * Peripherals on CPU Card and Mother Board are wired to cpu intc via
44 * intermediate DW APB GPIO blocks (mainly for debouncing)
45 *
46 * ---------------------
47 * | snps,arc700-intc |
48 * ---------------------
49 * | #7 | #15
50 * ------------------- -------------------
51 * | snps,dw-apb-gpio | | snps,dw-apb-gpio |
52 * ------------------- -------------------
53 * | |
54 * | [ Debug UART on cpu card ]
55 * |
56 * ------------------------
57 * | snps,dw-apb-intc (MB)|
58 * ------------------------
59 * | | | |
60 * [eth] [uart] [... other perip on Main Board]
61 *
62 * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
63 * with stacked INTCs. In particular problem happens if its master INTC
64 * not yet instantiated. See discussion here -
65 * https://lkml.org/lkml/2015/3/4/755
66 *
67 * So setup the first gpio block as a passive pass thru and hide it from
68 * DT hardware topology - connect MB intc directly to cpu intc
69 * The GPIO "wire" needs to be init nevertheless (here)
70 *
71 * One side adv is that peripheral interrupt handling avoids one nested
72 * intc ISR hop
73 */
74#define GPIO_INTEN (AXC001_GPIO_INTC + 0x30)
75#define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34)
76#define GPIO_INTTYPE_LEVEL (AXC001_GPIO_INTC + 0x38)
77#define GPIO_INT_POLARITY (AXC001_GPIO_INTC + 0x3c)
78#define MB_TO_GPIO_IRQ 12
79
80 iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
81 iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
82 iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
83 iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
84}
85
86static void axs10x_print_board_ver(unsigned int creg, const char *str)
87{
88 union ver {
89 struct {
90#ifdef CONFIG_CPU_BIG_ENDIAN
91 unsigned int pad:11, y:12, m:4, d:5;
92#else
93 unsigned int d:5, m:4, y:12, pad:11;
94#endif
95 };
96 unsigned int val;
97 } board;
98
99 board.val = ioread32((void __iomem *)creg);
100 pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
101 board.y);
102}
103
104static void axs10x_early_init(void)
105{
106 int mb_rev;
107 char mb[32];
108
109 /* Determine motherboard version */
110 if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
111 mb_rev = 3; /* HT-3 (rev3.0) */
112 else
113 mb_rev = 2; /* HT-2 (rev2.0) */
114
115 enable_gpio_intc_wire();
116
117 scnprintf(mb, 32, "MainBoard v%d", mb_rev);
118 axs10x_print_board_ver(CREG_MB_VER, mb);
119}
120
121/*
122 * Set up System Memory Map for ARC cpu / peripherals controllers
123 *
124 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
125 * of which maps to a corresponding 256MB aperture in Target slave memory map.
126 *
127 * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
128 * (0x0000_0000) of DDR Port 0 (slave #1)
129 *
130 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
131 * which has master/slaves on both ends.
132 * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
133 * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
134 * MB AXI Tunnel Master, which also has a mem map setup
135 *
136 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
137 * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
138 */
139struct aperture {
140 unsigned int slave_sel:4, slave_off:4, pad:24;
141};
142
143/* CPU Card target slaves */
144#define AXC001_SLV_NONE 0
145#define AXC001_SLV_DDR_PORT0 1
146#define AXC001_SLV_SRAM 2
147#define AXC001_SLV_AXI_TUNNEL 3
148#define AXC001_SLV_AXI2APB 6
149#define AXC001_SLV_DDR_PORT1 7
150
151/* MB AXI Target slaves */
152#define AXS_MB_SLV_NONE 0
153#define AXS_MB_SLV_AXI_TUNNEL_CPU 1
154#define AXS_MB_SLV_AXI_TUNNEL_HAPS 2
155#define AXS_MB_SLV_SRAM 3
156#define AXS_MB_SLV_CONTROL 4
157
158/* MB AXI masters */
159#define AXS_MB_MST_TUNNEL_CPU 0
160#define AXS_MB_MST_USB_OHCI 10
161
162/*
163 * memmap for ARC core on CPU Card
164 */
165static const struct aperture axc001_memmap[16] = {
166 {AXC001_SLV_AXI_TUNNEL, 0x0},
167 {AXC001_SLV_AXI_TUNNEL, 0x1},
168 {AXC001_SLV_SRAM, 0x0}, /* 0x2000_0000: Local SRAM */
169 {AXC001_SLV_NONE, 0x0},
170 {AXC001_SLV_NONE, 0x0},
171 {AXC001_SLV_NONE, 0x0},
172 {AXC001_SLV_NONE, 0x0},
173 {AXC001_SLV_NONE, 0x0},
174 {AXC001_SLV_DDR_PORT0, 0x0}, /* 0x8000_0000: DDR 0..256M */
175 {AXC001_SLV_DDR_PORT0, 0x1}, /* 0x9000_0000: DDR 256..512M */
176 {AXC001_SLV_DDR_PORT1, 0x0},
177 {AXC001_SLV_DDR_PORT1, 0x1},
178 {AXC001_SLV_NONE, 0x0},
179 {AXC001_SLV_AXI_TUNNEL, 0xD},
180 {AXC001_SLV_AXI_TUNNEL, 0xE}, /* MB: CREG, CGU... */
181 {AXC001_SLV_AXI2APB, 0x0}, /* CPU Card local CREG, CGU... */
182};
183
184/*
185 * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
186 * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
187 */
188static const struct aperture axc001_axi_tunnel_memmap[16] = {
189 {AXC001_SLV_AXI_TUNNEL, 0x0},
190 {AXC001_SLV_AXI_TUNNEL, 0x1},
191 {AXC001_SLV_SRAM, 0x0},
192 {AXC001_SLV_NONE, 0x0},
193 {AXC001_SLV_NONE, 0x0},
194 {AXC001_SLV_NONE, 0x0},
195 {AXC001_SLV_NONE, 0x0},
196 {AXC001_SLV_NONE, 0x0},
197 {AXC001_SLV_DDR_PORT0, 0x0},
198 {AXC001_SLV_DDR_PORT0, 0x1},
199 {AXC001_SLV_DDR_PORT1, 0x0},
200 {AXC001_SLV_DDR_PORT1, 0x1},
201 {AXC001_SLV_NONE, 0x0},
202 {AXC001_SLV_AXI_TUNNEL, 0xD},
203 {AXC001_SLV_AXI_TUNNEL, 0xE},
204 {AXC001_SLV_AXI2APB, 0x0},
205};
206
207/*
208 * memmap for MB AXI Masters
209 * Same mem map for all perip controllers as well as MB AXI Tunnel Master
210 */
211static const struct aperture axs_mb_memmap[16] = {
212 {AXS_MB_SLV_SRAM, 0x0},
213 {AXS_MB_SLV_SRAM, 0x0},
214 {AXS_MB_SLV_NONE, 0x0},
215 {AXS_MB_SLV_NONE, 0x0},
216 {AXS_MB_SLV_NONE, 0x0},
217 {AXS_MB_SLV_NONE, 0x0},
218 {AXS_MB_SLV_NONE, 0x0},
219 {AXS_MB_SLV_NONE, 0x0},
220 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x8}, /* DDR on CPU Card */
221 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x9}, /* DDR on CPU Card */
222 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xA},
223 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xB},
224 {AXS_MB_SLV_NONE, 0x0},
225 {AXS_MB_SLV_AXI_TUNNEL_HAPS, 0xD},
226 {AXS_MB_SLV_CONTROL, 0x0}, /* MB Local CREG, CGU... */
227 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xF},
228};
229
230static noinline void
231axs101_set_memmap(void __iomem *base, const struct aperture map[16])
232{
233 unsigned int slave_select, slave_offset;
234 int i;
235
236 slave_select = slave_offset = 0;
237 for (i = 0; i < 8; i++) {
238 slave_select |= map[i].slave_sel << (i << 2);
239 slave_offset |= map[i].slave_off << (i << 2);
240 }
241
242 iowrite32(slave_select, base + 0x0); /* SLV0 */
243 iowrite32(slave_offset, base + 0x8); /* OFFSET0 */
244
245 slave_select = slave_offset = 0;
246 for (i = 0; i < 8; i++) {
247 slave_select |= map[i+8].slave_sel << (i << 2);
248 slave_offset |= map[i+8].slave_off << (i << 2);
249 }
250
251 iowrite32(slave_select, base + 0x4); /* SLV1 */
252 iowrite32(slave_offset, base + 0xC); /* OFFSET1 */
253}
254
255static void axs101_early_init(void)
256{
257 int i;
258
259 /* ARC 770D memory view */
260 axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
261 iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);
262
263 /* AXI tunnel memory map (incoming traffic from MB into CPU Card */
264 axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
265 axc001_axi_tunnel_memmap);
266 iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);
267
268 /* MB peripherals memory map */
269 for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
270 axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
271 axs_mb_memmap);
272
273 iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */
274
275 /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
276 iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
277
278 /* Set up the MB interrupt system: mux interrupts to GPIO7) */
279 iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
280
281 /* reset ethernet and ULPI interfaces */
282 iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);
283
284 /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
285 iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);
286
287 axs10x_early_init();
288}
289
290static const char *axs101_compat[] __initconst = {
291 "snps,axs101",
292 NULL,
293};
294
295MACHINE_START(AXS101, "axs101")
296 .dt_compat = axs101_compat,
297 .init_early = axs101_early_init,
298MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-28 13:41:11 -0400