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authorSrinath Mannam <srinath.mannam@broadcom.com>2017-06-02 02:34:35 -0400
committerFlorian Fainelli <f.fainelli@gmail.com>2017-06-05 22:07:19 -0400
commit552df26309f3aa5b9ead23c13abc2a3b2dc23eaf (patch)
treedd37b8552ac3154949671a2da10711a2c8dfa135
parent0dc454ee8915387ac4210bb771d4eafc1f82be3b (diff)
arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC
The Stingray SoC has two instances of SDHCI controller and one instance of iProc PWM. Let's enable above mentioned devices in Stingray DT. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-rw-r--r--arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi39
-rw-r--r--arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi28
2 files changed, 67 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
index ff59a26be192..5dca7d10253b 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
@@ -43,6 +43,28 @@
43 serial2 = &uart2; 43 serial2 = &uart2;
44 serial3 = &uart3; 44 serial3 = &uart3;
45 }; 45 };
46
47 sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl {
48 compatible = "regulator-gpio";
49 regulator-name = "sdio0_vddo_ctrl_reg";
50 regulator-type = "voltage";
51 regulator-min-microvolt = <1800000>;
52 regulator-max-microvolt = <3300000>;
53 gpios = <&pca9505 18 0>;
54 states = <3300000 0x0
55 1800000 0x1>;
56 };
57
58 sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl {
59 compatible = "regulator-gpio";
60 regulator-name = "sdio1_vddo_ctrl_reg";
61 regulator-type = "voltage";
62 regulator-min-microvolt = <1800000>;
63 regulator-max-microvolt = <3300000>;
64 gpios = <&pca9505 19 0>;
65 states = <3300000 0x0
66 1800000 0x1>;
67 };
46}; 68};
47 69
48&memory { /* Default DRAM banks */ 70&memory { /* Default DRAM banks */
@@ -54,6 +76,10 @@
54 status = "okay"; 76 status = "okay";
55}; 77};
56 78
79&pwm {
80 status = "okay";
81};
82
57&i2c0 { 83&i2c0 {
58 status = "okay"; 84 status = "okay";
59 85
@@ -90,3 +116,16 @@
90 #size-cells = <1>; 116 #size-cells = <1>;
91 }; 117 };
92}; 118};
119
120&sdio0 {
121 vqmmc-supply = <&sdio0_vddo_ctrl_reg>;
122 non-removable;
123 full-pwr-cycle;
124 status = "okay";
125};
126
127&sdio1 {
128 vqmmc-supply = <&sdio1_vddo_ctrl_reg>;
129 full-pwr-cycle;
130 status = "okay";
131};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 88a617690ed1..49933cf16c92 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -269,6 +269,14 @@
269 269
270 #include "stingray-pinctrl.dtsi" 270 #include "stingray-pinctrl.dtsi"
271 271
272 pwm: pwm@00010000 {
273 compatible = "brcm,iproc-pwm";
274 reg = <0x00010000 0x1000>;
275 clocks = <&crmu_ref25m>;
276 #pwm-cells = <3>;
277 status = "disabled";
278 };
279
272 i2c0: i2c@000b0000 { 280 i2c0: i2c@000b0000 {
273 compatible = "brcm,iproc-i2c"; 281 compatible = "brcm,iproc-i2c";
274 reg = <0x000b0000 0x100>; 282 reg = <0x000b0000 0x100>;
@@ -428,5 +436,25 @@
428 brcm,nand-has-wp; 436 brcm,nand-has-wp;
429 status = "disabled"; 437 status = "disabled";
430 }; 438 };
439
440 sdio0: sdhci@003f1000 {
441 compatible = "brcm,sdhci-iproc";
442 reg = <0x003f1000 0x100>;
443 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
444 bus-width = <8>;
445 clocks = <&sdio0_clk>;
446 iommus = <&smmu 0x6002 0x0000>;
447 status = "disabled";
448 };
449
450 sdio1: sdhci@003f2000 {
451 compatible = "brcm,sdhci-iproc";
452 reg = <0x003f2000 0x100>;
453 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
454 bus-width = <8>;
455 clocks = <&sdio1_clk>;
456 iommus = <&smmu 0x6003 0x0000>;
457 status = "disabled";
458 };
431 }; 459 };
432}; 460};