Merge tag 'pci-v4.19-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fixes from Bjorn Helgaas:

 - Add Tyrel Datwyler as maintainer for PPC64 RPA hotplug (Tyrel
   Datwyler)

 - Add Gustavo Pimentel as DesignWare PCI maintainer (Joao Pinto)

 - Fix a Switchtec Spectre v1 vulnerability (Gustavo A. R. Silva)

 - Revert an unnecessary Intel 300 ACS quirk (Mika Westerberg)

 - Fix pciehp hot-add/powerfault detection that left indicators in wrong
   state (Keith Busch)

 - Fix pci_reset_bus() logic error (Dennis Dalessandro)

 - Revert IB/hfi1 PCI reset change that caused a deadlock (Dennis
   Dalessandro)

 - Allow enabling PASID on Root Complex Integrated Endpoints (Felix
   Kuehling)

* tag 'pci-v4.19-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: Fix enabling of PASID on RC integrated endpoints
  IB/hfi1,PCI: Allow bus reset while probing
  PCI: Fix faulty logic in pci_reset_bus()
  PCI: pciehp: Fix hot-add vs powerfault detection order
  switchtec: Fix Spectre v1 vulnerability
  Revert "PCI: Add ACS quirk for Intel 300 series"
  MAINTAINERS: Add Gustavo Pimentel as DesignWare PCI maintainer
  MAINTAINERS: Add entries for PPC64 RPA PCI hotplug drivers

8 files changed, 41 insertions, 25 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index d870cb57c887..4130acc2e152 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7016,6 +7016,20 @@ F:	drivers/crypto/vmx/aes*
 F:      drivers/crypto/vmx/ghash*
 F:      drivers/crypto/vmx/ppc-xlate.pl
 
+IBM Power PCI Hotplug Driver for RPA-compliant PPC64 platform
+M:      Tyrel Datwyler <tyreld@linux.vnet.ibm.com>
+L:      linux-pci@vger.kernel.org
+L:      linuxppc-dev@lists.ozlabs.org
+S:      Supported
+F:      drivers/pci/hotplug/rpaphp*
+
+IBM Power IO DLPAR Driver for RPA-compliant PPC64 platform
+M:      Tyrel Datwyler <tyreld@linux.vnet.ibm.com>
+L:      linux-pci@vger.kernel.org
+L:      linuxppc-dev@lists.ozlabs.org
+S:      Supported
+F:      drivers/pci/hotplug/rpadlpar*
+
 IBM ServeRAID RAID DRIVER
 S:      Orphan
 F:      drivers/scsi/ips.*
@@ -11154,7 +11168,7 @@ F:	drivers/pci/controller/dwc/pci-exynos.c
 
 PCI DRIVER FOR SYNOPSYS DESIGNWARE
 M:      Jingoo Han <jingoohan1@gmail.com>
-M:      Joao Pinto <Joao.Pinto@synopsys.com>
+M:      Gustavo Pimentel <gustavo.pimentel@synopsys.com>
 L:      linux-pci@vger.kernel.org
 S:      Maintained
 F:      Documentation/devicetree/bindings/pci/designware-pcie.txt
diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c
index eec83757d55f..6c967dde58e7 100644
--- a/drivers/infiniband/hw/hfi1/pcie.c
+++ b/drivers/infiniband/hw/hfi1/pcie.c
@@ -893,14 +893,11 @@ static int trigger_sbr(struct hfi1_devdata *dd)
                 }
 
         /*
-         * A secondary bus reset (SBR) issues a hot reset to our device.
-         * The following routine does a 1s wait after the reset is dropped
-         * per PCI Trhfa (recovery time).  PCIe 3.0 section 6.6.1 -
-         * Conventional Reset, paragraph 3, line 35 also says that a 1s
-         * delay after a reset is required.  Per spec requirements,
-         * the link is either working or not after that point.
+         * This is an end around to do an SBR during probe time. A new API needs
+         * to be implemented to have cleaner interface but this fixes the
+         * current brokenness
          */
-        return pci_reset_bus(dev);
+        return pci_bridge_secondary_bus_reset(dev->bus->self);
 }
 
 /*
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 7136e3430925..a938abdb41ce 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -496,7 +496,7 @@ int pciehp_power_on_slot(struct slot *slot)
         u16 slot_status;
         int retval;
 
-        /* Clear sticky power-fault bit from previous power failures */
+        /* Clear power-fault bit from previous power failures */
         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
         if (slot_status & PCI_EXP_SLTSTA_PFD)
                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
@@ -646,6 +646,14 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id)
                 pciehp_handle_button_press(slot);
         }
 
+        /* Check Power Fault Detected */
+        if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
+                ctrl->power_fault_detected = 1;
+                ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
+                pciehp_set_attention_status(slot, 1);
+                pciehp_green_led_off(slot);
+        }
+
         /*
          * Disable requests have higher priority than Presence Detect Changed
          * or Data Link Layer State Changed events.
@@ -657,14 +665,6 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id)
                 pciehp_handle_presence_or_link_change(slot, events);
         up_read(&ctrl->reset_lock);
 
-        /* Check Power Fault Detected */
-        if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
-                ctrl->power_fault_detected = 1;
-                ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
-                pciehp_set_attention_status(slot, 1);
-                pciehp_green_led_off(slot);
-        }
-
         pci_config_pm_runtime_put(pdev);
         wake_up(&ctrl->requester);
         return IRQ_HANDLED;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 29ff9619b5fa..1835f3a7aa8d 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4547,6 +4547,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
 
         return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
 }
+EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
 
 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
 {
@@ -5200,7 +5201,7 @@ static int __pci_reset_bus(struct pci_bus *bus)
  */
 int pci_reset_bus(struct pci_dev *pdev)
 {
-        return pci_probe_reset_slot(pdev->slot) ?
+        return (!pci_probe_reset_slot(pdev->slot)) ?
             __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
 }
 EXPORT_SYMBOL_GPL(pci_reset_bus);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ec784009a36b..201f9e5ff55c 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2074,6 +2074,7 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
 {
 #ifdef CONFIG_PCI_PASID
         struct pci_dev *bridge;
+        int pcie_type;
         u32 cap;
 
         if (!pci_is_pcie(dev))
@@ -2083,7 +2084,9 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
         if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
                 return;
 
-        if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+        pcie_type = pci_pcie_type(dev);
+        if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
+            pcie_type == PCI_EXP_TYPE_RC_END)
                 dev->eetlp_prefix_path = 1;
         else {
                 bridge = pci_upstream_bridge(dev);
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ef7143a274e0..6bc27b7fd452 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4355,11 +4355,6 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
  *
  * 0x9d10-0x9d1b PCI Express Root port #{1-12}
  *
- * The 300 series chipset suffers from the same bug so include those root
- * ports here as well.
- *
- * 0xa32c-0xa343 PCI Express Root port #{0-24}
- *
  * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
  * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
  * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
@@ -4377,7 +4372,6 @@ static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
         case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
         case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
         case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
-        case 0xa32c ... 0xa343:                         /* 300 series */
                 return true;
         }
 
diff --git a/drivers/pci/switch/switchtec.c b/drivers/pci/switch/switchtec.c
index 9940cc70f38b..54a8b30dda38 100644
--- a/drivers/pci/switch/switchtec.c
+++ b/drivers/pci/switch/switchtec.c
@@ -14,6 +14,8 @@
 #include <linux/poll.h>
 #include <linux/wait.h>
 
+#include <linux/nospec.h>
+
 MODULE_DESCRIPTION("Microsemi Switchtec(tm) PCIe Management Driver");
 MODULE_VERSION("0.1");
 MODULE_LICENSE("GPL");
@@ -909,6 +911,8 @@ static int ioctl_port_to_pff(struct switchtec_dev *stdev,
         default:
                 if (p.port > ARRAY_SIZE(pcfg->dsp_pff_inst_id))
                         return -EINVAL;
+                p.port = array_index_nospec(p.port,
+                                        ARRAY_SIZE(pcfg->dsp_pff_inst_id) + 1);
                 p.pff = ioread32(&pcfg->dsp_pff_inst_id[p.port - 1]);
                 break;
         }
diff --git a/include/linux/pci.h b/include/linux/pci.h
index e72ca8dd6241..6925828f9f25 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1235,6 +1235,9 @@ void pci_bus_remove_resources(struct pci_bus *bus);
 int devm_request_pci_bus_resources(struct device *dev,
                                    struct list_head *resources);
 
+/* Temporary until new and working PCI SBR API in place */
+int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
+
 #define pci_bus_for_each_resource(bus, res, i)                          \
         for (i = 0;                                                     \
             (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \