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authorLinus Torvalds <torvalds@linux-foundation.org>2019-03-20 14:01:52 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2019-03-20 14:01:52 -0400
commit54c490164523de90c42b1d89e7de3befe3284d1b (patch)
tree6c10c57195dd11665f75080054669032985dc492
parentbabf09c3837f3cf4b58225225609445419c338e6 (diff)
parent9a18b5a412baf23137c8fddb4ea7f0c14087f31c (diff)
Merge tag 'arc-5.1-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta: - unaligned access support for HS cores - Removed extra memory barrier around spinlock code - HSDK platform updates: enable dmac, reset - some more boot logging updates - misc minor fixes * tag 'arc-5.1-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: arch: arc: Kconfig: pedantic formatting ARCv2: spinlock: remove the extra smp_mb before lock, after unlock ARC: unaligned: relax the check for gcc supporting -mno-unaligned-access ARC: boot log: cut down on verbosity ARCv2: boot log: refurbish HS core/release identification arc: hsdk_defconfig: Enable CONFIG_BLK_DEV_RAM ARC: u-boot args: check that magic number is correct ARC: perf: bpok condition only exists for ARCompact ARCv2: Add explcit unaligned access support (and ability to disable too) ARCv2: lib: introduce memcpy optimized for unaligned access ARC: [plat-hsdk]: Enable AXI DW DMAC support ARC: [plat-hsdk]: Add reset controller handle to manage USB reset ARC: DTB: [scripted] fix node name and address spelling
Diffstat
-rw-r--r--arch/arc/Kconfig21
-rw-r--r--arch/arc/Makefile6
-rw-r--r--arch/arc/boot/dts/abilis_tb100.dtsi58
-rw-r--r--arch/arc/boot/dts/abilis_tb100_dvk.dts14
-rw-r--r--arch/arc/boot/dts/abilis_tb101.dtsi58
-rw-r--r--arch/arc/boot/dts/abilis_tb101_dvk.dts14
-rw-r--r--arch/arc/boot/dts/abilis_tb10x.dtsi60
-rw-r--r--arch/arc/boot/dts/axc001.dtsi6
-rw-r--r--arch/arc/boot/dts/axc003.dtsi16
-rw-r--r--arch/arc/boot/dts/axc003_idu.dtsi16
-rw-r--r--arch/arc/boot/dts/axs10x_mb.dtsi22
-rw-r--r--arch/arc/boot/dts/hsdk.dts33
-rw-r--r--arch/arc/boot/dts/vdk_axc003.dtsi4
-rw-r--r--arch/arc/boot/dts/vdk_axc003_idu.dtsi4
-rw-r--r--arch/arc/boot/dts/vdk_axs10x_mb.dtsi18
-rw-r--r--arch/arc/configs/hsdk_defconfig1
-rw-r--r--arch/arc/include/asm/arcregs.h12
-rw-r--r--arch/arc/include/asm/irqflags-arcv2.h8
-rw-r--r--arch/arc/include/asm/perf_event.h2
-rw-r--r--arch/arc/include/asm/spinlock.h49
-rw-r--r--arch/arc/kernel/head.S6
-rw-r--r--arch/arc/kernel/intc-arcv2.c2
-rw-r--r--arch/arc/kernel/setup.c211
-rw-r--r--arch/arc/kernel/troubleshoot.c5
-rw-r--r--arch/arc/lib/Makefile8
-rw-r--r--arch/arc/lib/memcpy-archs-unaligned.S47
-rw-r--r--arch/arc/plat-eznps/Kconfig12
27 files changed, 399 insertions, 314 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index df55672c59e6..c781e45d1d99 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -144,11 +144,11 @@ config ARC_CPU_770
144 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 144 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
145 This core has a bunch of cool new features: 145 This core has a bunch of cool new features:
146 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 146 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
147 Shared Address Spaces (for sharing TLB entries in MMU) 147 Shared Address Spaces (for sharing TLB entries in MMU)
148 -Caches: New Prog Model, Region Flush 148 -Caches: New Prog Model, Region Flush
149 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 149 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
150 150
151endif #ISA_ARCOMPACT 151endif #ISA_ARCOMPACT
152 152
153config ARC_CPU_HS 153config ARC_CPU_HS
154 bool "ARC-HS" 154 bool "ARC-HS"
@@ -198,7 +198,7 @@ config ARC_SMP_HALT_ON_RESET
198 at designated entry point. For other case, all jump to common 198 at designated entry point. For other case, all jump to common
199 entry point and spin wait for Master's signal. 199 entry point and spin wait for Master's signal.
200 200
201endif #SMP 201endif #SMP
202 202
203config ARC_MCIP 203config ARC_MCIP
204 bool "ARConnect Multicore IP (MCIP) Support " 204 bool "ARConnect Multicore IP (MCIP) Support "
@@ -249,7 +249,7 @@ config ARC_CACHE_VIPT_ALIASING
249 bool "Support VIPT Aliasing D$" 249 bool "Support VIPT Aliasing D$"
250 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 250 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
251 251
252endif #ARC_CACHE 252endif #ARC_CACHE
253 253
254config ARC_HAS_ICCM 254config ARC_HAS_ICCM
255 bool "Use ICCM" 255 bool "Use ICCM"
@@ -370,7 +370,7 @@ config ARC_FPU_SAVE_RESTORE
370 based on actual usage of FPU by a task. Thus our implemn does 370 based on actual usage of FPU by a task. Thus our implemn does
371 this for all tasks in system. 371 this for all tasks in system.
372 372
373endif #ISA_ARCOMPACT 373endif #ISA_ARCOMPACT
374 374
375config ARC_CANT_LLSC 375config ARC_CANT_LLSC
376 def_bool n 376 def_bool n
@@ -386,6 +386,15 @@ config ARC_HAS_SWAPE
386 386
387if ISA_ARCV2 387if ISA_ARCV2
388 388
389config ARC_USE_UNALIGNED_MEM_ACCESS
390 bool "Enable unaligned access in HW"
391 default y
392 select HAVE_EFFICIENT_UNALIGNED_ACCESS
393 help
394 The ARC HS architecture supports unaligned memory access
395 which is disabled by default. Enable unaligned access in
396 hardware and use software to use it
397
389config ARC_HAS_LL64 398config ARC_HAS_LL64
390 bool "Insn: 64bit LDD/STD" 399 bool "Insn: 64bit LDD/STD"
391 help 400 help
@@ -414,7 +423,7 @@ config ARC_IRQ_NO_AUTOSAVE
414 This is programmable and can be optionally disabled in which case 423 This is programmable and can be optionally disabled in which case
415 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 424 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
416 425
417endif # ISA_ARCV2 426endif # ISA_ARCV2
418 427
419endmenu # "ARC CPU Configuration" 428endmenu # "ARC CPU Configuration"
420 429
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index df00578c279d..e2b991f75bc5 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -28,6 +28,12 @@ cflags-$(CONFIG_ARC_HAS_SWAPE) += -mswape
28 28
29ifdef CONFIG_ISA_ARCV2 29ifdef CONFIG_ISA_ARCV2
30 30
31ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
32cflags-y += -munaligned-access
33else
34cflags-y += -mno-unaligned-access
35endif
36
31ifndef CONFIG_ARC_HAS_LL64 37ifndef CONFIG_ARC_HAS_LL64
32cflags-y += -mno-ll64 38cflags-y += -mno-ll64
33endif 39endif
diff --git a/arch/arc/boot/dts/abilis_tb100.dtsi b/arch/arc/boot/dts/abilis_tb100.dtsi
index 02410b211433..c0bcd97522bb 100644
--- a/arch/arc/boot/dts/abilis_tb100.dtsi
+++ b/arch/arc/boot/dts/abilis_tb100.dtsi
@@ -38,7 +38,7 @@
38 clock-div = <6>; 38 clock-div = <6>;
39 }; 39 };
40 40
41 iomux: iomux@FF10601c { 41 iomux: iomux@ff10601c {
42 /* Port 1 */ 42 /* Port 1 */
43 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */ 43 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
44 abilis,function = "mis0"; 44 abilis,function = "mis0";
@@ -162,182 +162,182 @@
162 }; 162 };
163 }; 163 };
164 164
165 gpioa: gpio@FF140000 { 165 gpioa: gpio@ff140000 {
166 compatible = "abilis,tb10x-gpio"; 166 compatible = "abilis,tb10x-gpio";
167 interrupt-controller; 167 interrupt-controller;
168 #interrupt-cells = <1>; 168 #interrupt-cells = <1>;
169 interrupt-parent = <&tb10x_ictl>; 169 interrupt-parent = <&tb10x_ictl>;
170 interrupts = <27 2>; 170 interrupts = <27 2>;
171 reg = <0xFF140000 0x1000>; 171 reg = <0xff140000 0x1000>;
172 gpio-controller; 172 gpio-controller;
173 #gpio-cells = <2>; 173 #gpio-cells = <2>;
174 abilis,ngpio = <3>; 174 abilis,ngpio = <3>;
175 gpio-ranges = <&iomux 0 0 0>; 175 gpio-ranges = <&iomux 0 0 0>;
176 gpio-ranges-group-names = "gpioa"; 176 gpio-ranges-group-names = "gpioa";
177 }; 177 };
178 gpiob: gpio@FF141000 { 178 gpiob: gpio@ff141000 {
179 compatible = "abilis,tb10x-gpio"; 179 compatible = "abilis,tb10x-gpio";
180 interrupt-controller; 180 interrupt-controller;
181 #interrupt-cells = <1>; 181 #interrupt-cells = <1>;
182 interrupt-parent = <&tb10x_ictl>; 182 interrupt-parent = <&tb10x_ictl>;
183 interrupts = <27 2>; 183 interrupts = <27 2>;
184 reg = <0xFF141000 0x1000>; 184 reg = <0xff141000 0x1000>;
185 gpio-controller; 185 gpio-controller;
186 #gpio-cells = <2>; 186 #gpio-cells = <2>;
187 abilis,ngpio = <2>; 187 abilis,ngpio = <2>;
188 gpio-ranges = <&iomux 0 0 0>; 188 gpio-ranges = <&iomux 0 0 0>;
189 gpio-ranges-group-names = "gpiob"; 189 gpio-ranges-group-names = "gpiob";
190 }; 190 };
191 gpioc: gpio@FF142000 { 191 gpioc: gpio@ff142000 {
192 compatible = "abilis,tb10x-gpio"; 192 compatible = "abilis,tb10x-gpio";
193 interrupt-controller; 193 interrupt-controller;
194 #interrupt-cells = <1>; 194 #interrupt-cells = <1>;
195 interrupt-parent = <&tb10x_ictl>; 195 interrupt-parent = <&tb10x_ictl>;
196 interrupts = <27 2>; 196 interrupts = <27 2>;
197 reg = <0xFF142000 0x1000>; 197 reg = <0xff142000 0x1000>;
198 gpio-controller; 198 gpio-controller;
199 #gpio-cells = <2>; 199 #gpio-cells = <2>;
200 abilis,ngpio = <3>; 200 abilis,ngpio = <3>;
201 gpio-ranges = <&iomux 0 0 0>; 201 gpio-ranges = <&iomux 0 0 0>;
202 gpio-ranges-group-names = "gpioc"; 202 gpio-ranges-group-names = "gpioc";
203 }; 203 };
204 gpiod: gpio@FF143000 { 204 gpiod: gpio@ff143000 {
205 compatible = "abilis,tb10x-gpio"; 205 compatible = "abilis,tb10x-gpio";
206 interrupt-controller; 206 interrupt-controller;
207 #interrupt-cells = <1>; 207 #interrupt-cells = <1>;
208 interrupt-parent = <&tb10x_ictl>; 208 interrupt-parent = <&tb10x_ictl>;
209 interrupts = <27 2>; 209 interrupts = <27 2>;
210 reg = <0xFF143000 0x1000>; 210 reg = <0xff143000 0x1000>;
211 gpio-controller; 211 gpio-controller;
212 #gpio-cells = <2>; 212 #gpio-cells = <2>;
213 abilis,ngpio = <2>; 213 abilis,ngpio = <2>;
214 gpio-ranges = <&iomux 0 0 0>; 214 gpio-ranges = <&iomux 0 0 0>;
215 gpio-ranges-group-names = "gpiod"; 215 gpio-ranges-group-names = "gpiod";
216 }; 216 };
217 gpioe: gpio@FF144000 { 217 gpioe: gpio@ff144000 {
218 compatible = "abilis,tb10x-gpio"; 218 compatible = "abilis,tb10x-gpio";
219 interrupt-controller; 219 interrupt-controller;
220 #interrupt-cells = <1>; 220 #interrupt-cells = <1>;
221 interrupt-parent = <&tb10x_ictl>; 221 interrupt-parent = <&tb10x_ictl>;
222 interrupts = <27 2>; 222 interrupts = <27 2>;
223 reg = <0xFF144000 0x1000>; 223 reg = <0xff144000 0x1000>;
224 gpio-controller; 224 gpio-controller;
225 #gpio-cells = <2>; 225 #gpio-cells = <2>;
226 abilis,ngpio = <3>; 226 abilis,ngpio = <3>;
227 gpio-ranges = <&iomux 0 0 0>; 227 gpio-ranges = <&iomux 0 0 0>;
228 gpio-ranges-group-names = "gpioe"; 228 gpio-ranges-group-names = "gpioe";
229 }; 229 };
230 gpiof: gpio@FF145000 { 230 gpiof: gpio@ff145000 {
231 compatible = "abilis,tb10x-gpio"; 231 compatible = "abilis,tb10x-gpio";
232 interrupt-controller; 232 interrupt-controller;
233 #interrupt-cells = <1>; 233 #interrupt-cells = <1>;
234 interrupt-parent = <&tb10x_ictl>; 234 interrupt-parent = <&tb10x_ictl>;
235 interrupts = <27 2>; 235 interrupts = <27 2>;
236 reg = <0xFF145000 0x1000>; 236 reg = <0xff145000 0x1000>;
237 gpio-controller; 237 gpio-controller;
238 #gpio-cells = <2>; 238 #gpio-cells = <2>;
239 abilis,ngpio = <2>; 239 abilis,ngpio = <2>;
240 gpio-ranges = <&iomux 0 0 0>; 240 gpio-ranges = <&iomux 0 0 0>;
241 gpio-ranges-group-names = "gpiof"; 241 gpio-ranges-group-names = "gpiof";
242 }; 242 };
243 gpiog: gpio@FF146000 { 243 gpiog: gpio@ff146000 {
244 compatible = "abilis,tb10x-gpio"; 244 compatible = "abilis,tb10x-gpio";
245 interrupt-controller; 245 interrupt-controller;
246 #interrupt-cells = <1>; 246 #interrupt-cells = <1>;
247 interrupt-parent = <&tb10x_ictl>; 247 interrupt-parent = <&tb10x_ictl>;
248 interrupts = <27 2>; 248 interrupts = <27 2>;
249 reg = <0xFF146000 0x1000>; 249 reg = <0xff146000 0x1000>;
250 gpio-controller; 250 gpio-controller;
251 #gpio-cells = <2>; 251 #gpio-cells = <2>;
252 abilis,ngpio = <3>; 252 abilis,ngpio = <3>;
253 gpio-ranges = <&iomux 0 0 0>; 253 gpio-ranges = <&iomux 0 0 0>;
254 gpio-ranges-group-names = "gpiog"; 254 gpio-ranges-group-names = "gpiog";
255 }; 255 };
256 gpioh: gpio@FF147000 { 256 gpioh: gpio@ff147000 {
257 compatible = "abilis,tb10x-gpio"; 257 compatible = "abilis,tb10x-gpio";
258 interrupt-controller; 258 interrupt-controller;
259 #interrupt-cells = <1>; 259 #interrupt-cells = <1>;
260 interrupt-parent = <&tb10x_ictl>; 260 interrupt-parent = <&tb10x_ictl>;
261 interrupts = <27 2>; 261 interrupts = <27 2>;
262 reg = <0xFF147000 0x1000>; 262 reg = <0xff147000 0x1000>;
263 gpio-controller; 263 gpio-controller;
264 #gpio-cells = <2>; 264 #gpio-cells = <2>;
265 abilis,ngpio = <2>; 265 abilis,ngpio = <2>;
266 gpio-ranges = <&iomux 0 0 0>; 266 gpio-ranges = <&iomux 0 0 0>;
267 gpio-ranges-group-names = "gpioh"; 267 gpio-ranges-group-names = "gpioh";
268 }; 268 };
269 gpioi: gpio@FF148000 { 269 gpioi: gpio@ff148000 {
270 compatible = "abilis,tb10x-gpio"; 270 compatible = "abilis,tb10x-gpio";
271 interrupt-controller; 271 interrupt-controller;
272 #interrupt-cells = <1>; 272 #interrupt-cells = <1>;
273 interrupt-parent = <&tb10x_ictl>; 273 interrupt-parent = <&tb10x_ictl>;
274 interrupts = <27 2>; 274 interrupts = <27 2>;
275 reg = <0xFF148000 0x1000>; 275 reg = <0xff148000 0x1000>;
276 gpio-controller; 276 gpio-controller;
277 #gpio-cells = <2>; 277 #gpio-cells = <2>;
278 abilis,ngpio = <12>; 278 abilis,ngpio = <12>;
279 gpio-ranges = <&iomux 0 0 0>; 279 gpio-ranges = <&iomux 0 0 0>;
280 gpio-ranges-group-names = "gpioi"; 280 gpio-ranges-group-names = "gpioi";
281 }; 281 };
282 gpioj: gpio@FF149000 { 282 gpioj: gpio@ff149000 {
283 compatible = "abilis,tb10x-gpio"; 283 compatible = "abilis,tb10x-gpio";
284 interrupt-controller; 284 interrupt-controller;
285 #interrupt-cells = <1>; 285 #interrupt-cells = <1>;
286 interrupt-parent = <&tb10x_ictl>; 286 interrupt-parent = <&tb10x_ictl>;
287 interrupts = <27 2>; 287 interrupts = <27 2>;
288 reg = <0xFF149000 0x1000>; 288 reg = <0xff149000 0x1000>;
289 gpio-controller; 289 gpio-controller;
290 #gpio-cells = <2>; 290 #gpio-cells = <2>;
291 abilis,ngpio = <32>; 291 abilis,ngpio = <32>;
292 gpio-ranges = <&iomux 0 0 0>; 292 gpio-ranges = <&iomux 0 0 0>;
293 gpio-ranges-group-names = "gpioj"; 293 gpio-ranges-group-names = "gpioj";
294 }; 294 };
295 gpiok: gpio@FF14a000 { 295 gpiok: gpio@ff14a000 {
296 compatible = "abilis,tb10x-gpio"; 296 compatible = "abilis,tb10x-gpio";
297 interrupt-controller; 297 interrupt-controller;
298 #interrupt-cells = <1>; 298 #interrupt-cells = <1>;
299 interrupt-parent = <&tb10x_ictl>; 299 interrupt-parent = <&tb10x_ictl>;
300 interrupts = <27 2>; 300 interrupts = <27 2>;
301 reg = <0xFF14A000 0x1000>; 301 reg = <0xff14a000 0x1000>;
302 gpio-controller; 302 gpio-controller;
303 #gpio-cells = <2>; 303 #gpio-cells = <2>;
304 abilis,ngpio = <22>; 304 abilis,ngpio = <22>;
305 gpio-ranges = <&iomux 0 0 0>; 305 gpio-ranges = <&iomux 0 0 0>;
306 gpio-ranges-group-names = "gpiok"; 306 gpio-ranges-group-names = "gpiok";
307 }; 307 };
308 gpiol: gpio@FF14b000 { 308 gpiol: gpio@ff14b000 {
309 compatible = "abilis,tb10x-gpio"; 309 compatible = "abilis,tb10x-gpio";
310 interrupt-controller; 310 interrupt-controller;
311 #interrupt-cells = <1>; 311 #interrupt-cells = <1>;
312 interrupt-parent = <&tb10x_ictl>; 312 interrupt-parent = <&tb10x_ictl>;
313 interrupts = <27 2>; 313 interrupts = <27 2>;
314 reg = <0xFF14B000 0x1000>; 314 reg = <0xff14b000 0x1000>;
315 gpio-controller; 315 gpio-controller;
316 #gpio-cells = <2>; 316 #gpio-cells = <2>;
317 abilis,ngpio = <4>; 317 abilis,ngpio = <4>;
318 gpio-ranges = <&iomux 0 0 0>; 318 gpio-ranges = <&iomux 0 0 0>;
319 gpio-ranges-group-names = "gpiol"; 319 gpio-ranges-group-names = "gpiol";
320 }; 320 };
321 gpiom: gpio@FF14c000 { 321 gpiom: gpio@ff14c000 {
322 compatible = "abilis,tb10x-gpio"; 322 compatible = "abilis,tb10x-gpio";
323 interrupt-controller; 323 interrupt-controller;
324 #interrupt-cells = <1>; 324 #interrupt-cells = <1>;
325 interrupt-parent = <&tb10x_ictl>; 325 interrupt-parent = <&tb10x_ictl>;
326 interrupts = <27 2>; 326 interrupts = <27 2>;
327 reg = <0xFF14C000 0x1000>; 327 reg = <0xff14c000 0x1000>;
328 gpio-controller; 328 gpio-controller;
329 #gpio-cells = <2>; 329 #gpio-cells = <2>;
330 abilis,ngpio = <4>; 330 abilis,ngpio = <4>;
331 gpio-ranges = <&iomux 0 0 0>; 331 gpio-ranges = <&iomux 0 0 0>;
332 gpio-ranges-group-names = "gpiom"; 332 gpio-ranges-group-names = "gpiom";
333 }; 333 };
334 gpion: gpio@FF14d000 { 334 gpion: gpio@ff14d000 {
335 compatible = "abilis,tb10x-gpio"; 335 compatible = "abilis,tb10x-gpio";
336 interrupt-controller; 336 interrupt-controller;
337 #interrupt-cells = <1>; 337 #interrupt-cells = <1>;
338 interrupt-parent = <&tb10x_ictl>; 338 interrupt-parent = <&tb10x_ictl>;
339 interrupts = <27 2>; 339 interrupts = <27 2>;
340 reg = <0xFF14D000 0x1000>; 340 reg = <0xff14d000 0x1000>;
341 gpio-controller; 341 gpio-controller;
342 #gpio-cells = <2>; 342 #gpio-cells = <2>;
343 abilis,ngpio = <5>; 343 abilis,ngpio = <5>;
diff --git a/arch/arc/boot/dts/abilis_tb100_dvk.dts b/arch/arc/boot/dts/abilis_tb100_dvk.dts
index 3acf04db8030..c968e677db46 100644
--- a/arch/arc/boot/dts/abilis_tb100_dvk.dts
+++ b/arch/arc/boot/dts/abilis_tb100_dvk.dts
@@ -37,27 +37,27 @@
37 }; 37 };
38 38
39 soc100 { 39 soc100 {
40 uart@FF100000 { 40 uart@ff100000 {
41 pinctrl-names = "default"; 41 pinctrl-names = "default";
42 pinctrl-0 = <&pctl_uart0>; 42 pinctrl-0 = <&pctl_uart0>;
43 }; 43 };
44 ethernet@FE100000 { 44 ethernet@fe100000 {
45 phy-mode = "rgmii"; 45 phy-mode = "rgmii";
46 }; 46 };
47 47
48 i2c0: i2c@FF120000 { 48 i2c0: i2c@ff120000 {
49 i2c-sda-hold-time-ns = <432>; 49 i2c-sda-hold-time-ns = <432>;
50 }; 50 };
51 i2c1: i2c@FF121000 { 51 i2c1: i2c@ff121000 {
52 i2c-sda-hold-time-ns = <432>; 52 i2c-sda-hold-time-ns = <432>;
53 }; 53 };
54 i2c2: i2c@FF122000 { 54 i2c2: i2c@ff122000 {
55 i2c-sda-hold-time-ns = <432>; 55 i2c-sda-hold-time-ns = <432>;
56 }; 56 };
57 i2c3: i2c@FF123000 { 57 i2c3: i2c@ff123000 {
58 i2c-sda-hold-time-ns = <432>; 58 i2c-sda-hold-time-ns = <432>;
59 }; 59 };
60 i2c4: i2c@FF124000 { 60 i2c4: i2c@ff124000 {
61 i2c-sda-hold-time-ns = <432>; 61 i2c-sda-hold-time-ns = <432>;
62 }; 62 };
63 63
diff --git a/arch/arc/boot/dts/abilis_tb101.dtsi b/arch/arc/boot/dts/abilis_tb101.dtsi
index f9e7686044eb..6a1615f58f05 100644
--- a/arch/arc/boot/dts/abilis_tb101.dtsi
+++ b/arch/arc/boot/dts/abilis_tb101.dtsi
@@ -38,7 +38,7 @@
38 clock-div = <6>; 38 clock-div = <6>;
39 }; 39 };
40 40
41 iomux: iomux@FF10601c { 41 iomux: iomux@ff10601c {
42 /* Port 1 */ 42 /* Port 1 */
43 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */ 43 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
44 abilis,function = "mis0"; 44 abilis,function = "mis0";
@@ -171,182 +171,182 @@
171 }; 171 };
172 }; 172 };
173 173
174 gpioa: gpio@FF140000 { 174 gpioa: gpio@ff140000 {
175 compatible = "abilis,tb10x-gpio"; 175 compatible = "abilis,tb10x-gpio";
176 interrupt-controller; 176 interrupt-controller;
177 #interrupt-cells = <1>; 177 #interrupt-cells = <1>;
178 interrupt-parent = <&tb10x_ictl>; 178 interrupt-parent = <&tb10x_ictl>;
179 interrupts = <27 2>; 179 interrupts = <27 2>;
180 reg = <0xFF140000 0x1000>; 180 reg = <0xff140000 0x1000>;
181 gpio-controller; 181 gpio-controller;
182 #gpio-cells = <2>; 182 #gpio-cells = <2>;
183 abilis,ngpio = <3>; 183 abilis,ngpio = <3>;
184 gpio-ranges = <&iomux 0 0 0>; 184 gpio-ranges = <&iomux 0 0 0>;
185 gpio-ranges-group-names = "gpioa"; 185 gpio-ranges-group-names = "gpioa";
186 }; 186 };
187 gpiob: gpio@FF141000 { 187 gpiob: gpio@ff141000 {
188 compatible = "abilis,tb10x-gpio"; 188 compatible = "abilis,tb10x-gpio";
189 interrupt-controller; 189 interrupt-controller;
190 #interrupt-cells = <1>; 190 #interrupt-cells = <1>;
191 interrupt-parent = <&tb10x_ictl>; 191 interrupt-parent = <&tb10x_ictl>;
192 interrupts = <27 2>; 192 interrupts = <27 2>;
193 reg = <0xFF141000 0x1000>; 193 reg = <0xff141000 0x1000>;
194 gpio-controller; 194 gpio-controller;
195 #gpio-cells = <2>; 195 #gpio-cells = <2>;
196 abilis,ngpio = <2>; 196 abilis,ngpio = <2>;
197 gpio-ranges = <&iomux 0 0 0>; 197 gpio-ranges = <&iomux 0 0 0>;
198 gpio-ranges-group-names = "gpiob"; 198 gpio-ranges-group-names = "gpiob";
199 }; 199 };
200 gpioc: gpio@FF142000 { 200 gpioc: gpio@ff142000 {
201 compatible = "abilis,tb10x-gpio"; 201 compatible = "abilis,tb10x-gpio";
202 interrupt-controller; 202 interrupt-controller;
203 #interrupt-cells = <1>; 203 #interrupt-cells = <1>;
204 interrupt-parent = <&tb10x_ictl>; 204 interrupt-parent = <&tb10x_ictl>;
205 interrupts = <27 2>; 205 interrupts = <27 2>;
206 reg = <0xFF142000 0x1000>; 206 reg = <0xff142000 0x1000>;
207 gpio-controller; 207 gpio-controller;
208 #gpio-cells = <2>; 208 #gpio-cells = <2>;
209 abilis,ngpio = <3>; 209 abilis,ngpio = <3>;
210 gpio-ranges = <&iomux 0 0 0>; 210 gpio-ranges = <&iomux 0 0 0>;
211 gpio-ranges-group-names = "gpioc"; 211 gpio-ranges-group-names = "gpioc";
212 }; 212 };
213 gpiod: gpio@FF143000 { 213 gpiod: gpio@ff143000 {
214 compatible = "abilis,tb10x-gpio"; 214 compatible = "abilis,tb10x-gpio";
215 interrupt-controller; 215 interrupt-controller;
216 #interrupt-cells = <1>; 216 #interrupt-cells = <1>;
217 interrupt-parent = <&tb10x_ictl>; 217 interrupt-parent = <&tb10x_ictl>;
218 interrupts = <27 2>; 218 interrupts = <27 2>;
219 reg = <0xFF143000 0x1000>; 219 reg = <0xff143000 0x1000>;
220 gpio-controller; 220 gpio-controller;
221 #gpio-cells = <2>; 221 #gpio-cells = <2>;
222 abilis,ngpio = <2>; 222 abilis,ngpio = <2>;
223 gpio-ranges = <&iomux 0 0 0>; 223 gpio-ranges = <&iomux 0 0 0>;
224 gpio-ranges-group-names = "gpiod"; 224 gpio-ranges-group-names = "gpiod";
225 }; 225 };
226 gpioe: gpio@FF144000 { 226 gpioe: gpio@ff144000 {
227 compatible = "abilis,tb10x-gpio"; 227 compatible = "abilis,tb10x-gpio";
228 interrupt-controller; 228 interrupt-controller;
229 #interrupt-cells = <1>; 229 #interrupt-cells = <1>;
230 interrupt-parent = <&tb10x_ictl>; 230 interrupt-parent = <&tb10x_ictl>;
231 interrupts = <27 2>; 231 interrupts = <27 2>;
232 reg = <0xFF144000 0x1000>; 232 reg = <0xff144000 0x1000>;
233 gpio-controller; 233 gpio-controller;
234 #gpio-cells = <2>; 234 #gpio-cells = <2>;
235 abilis,ngpio = <3>; 235 abilis,ngpio = <3>;
236 gpio-ranges = <&iomux 0 0 0>; 236 gpio-ranges = <&iomux 0 0 0>;
237 gpio-ranges-group-names = "gpioe"; 237 gpio-ranges-group-names = "gpioe";
238 }; 238 };
239 gpiof: gpio@FF145000 { 239 gpiof: gpio@ff145000 {
240 compatible = "abilis,tb10x-gpio"; 240 compatible = "abilis,tb10x-gpio";
241 interrupt-controller; 241 interrupt-controller;
242 #interrupt-cells = <1>; 242 #interrupt-cells = <1>;
243 interrupt-parent = <&tb10x_ictl>; 243 interrupt-parent = <&tb10x_ictl>;
244 interrupts = <27 2>; 244 interrupts = <27 2>;
245 reg = <0xFF145000 0x1000>; 245 reg = <0xff145000 0x1000>;
246 gpio-controller; 246 gpio-controller;
247 #gpio-cells = <2>; 247 #gpio-cells = <2>;
248 abilis,ngpio = <2>; 248 abilis,ngpio = <2>;
249 gpio-ranges = <&iomux 0 0 0>; 249 gpio-ranges = <&iomux 0 0 0>;
250 gpio-ranges-group-names = "gpiof"; 250 gpio-ranges-group-names = "gpiof";
251 }; 251 };
252 gpiog: gpio@FF146000 { 252 gpiog: gpio@ff146000 {
253 compatible = "abilis,tb10x-gpio"; 253 compatible = "abilis,tb10x-gpio";
254 interrupt-controller; 254 interrupt-controller;
255 #interrupt-cells = <1>; 255 #interrupt-cells = <1>;
256 interrupt-parent = <&tb10x_ictl>; 256 interrupt-parent = <&tb10x_ictl>;
257 interrupts = <27 2>; 257 interrupts = <27 2>;
258 reg = <0xFF146000 0x1000>; 258 reg = <0xff146000 0x1000>;
259 gpio-controller; 259 gpio-controller;
260 #gpio-cells = <2>; 260 #gpio-cells = <2>;
261 abilis,ngpio = <3>; 261 abilis,ngpio = <3>;
262 gpio-ranges = <&iomux 0 0 0>; 262 gpio-ranges = <&iomux 0 0 0>;
263 gpio-ranges-group-names = "gpiog"; 263 gpio-ranges-group-names = "gpiog";
264 }; 264 };
265 gpioh: gpio@FF147000 { 265 gpioh: gpio@ff147000 {
266 compatible = "abilis,tb10x-gpio"; 266 compatible = "abilis,tb10x-gpio";
267 interrupt-controller; 267 interrupt-controller;
268 #interrupt-cells = <1>; 268 #interrupt-cells = <1>;
269 interrupt-parent = <&tb10x_ictl>; 269 interrupt-parent = <&tb10x_ictl>;
270 interrupts = <27 2>; 270 interrupts = <27 2>;
271 reg = <0xFF147000 0x1000>; 271 reg = <0xff147000 0x1000>;
272 gpio-controller; 272 gpio-controller;
273 #gpio-cells = <2>; 273 #gpio-cells = <2>;
274 abilis,ngpio = <2>; 274 abilis,ngpio = <2>;
275 gpio-ranges = <&iomux 0 0 0>; 275 gpio-ranges = <&iomux 0 0 0>;
276 gpio-ranges-group-names = "gpioh"; 276 gpio-ranges-group-names = "gpioh";
277 }; 277 };
278 gpioi: gpio@FF148000 { 278 gpioi: gpio@ff148000 {
279 compatible = "abilis,tb10x-gpio"; 279 compatible = "abilis,tb10x-gpio";
280 interrupt-controller; 280 interrupt-controller;
281 #interrupt-cells = <1>; 281 #interrupt-cells = <1>;
282 interrupt-parent = <&tb10x_ictl>; 282 interrupt-parent = <&tb10x_ictl>;
283 interrupts = <27 2>; 283 interrupts = <27 2>;
284 reg = <0xFF148000 0x1000>; 284 reg = <0xff148000 0x1000>;
285 gpio-controller; 285 gpio-controller;
286 #gpio-cells = <2>; 286 #gpio-cells = <2>;
287 abilis,ngpio = <12>; 287 abilis,ngpio = <12>;
288 gpio-ranges = <&iomux 0 0 0>; 288 gpio-ranges = <&iomux 0 0 0>;
289 gpio-ranges-group-names = "gpioi"; 289 gpio-ranges-group-names = "gpioi";
290 }; 290 };
291 gpioj: gpio@FF149000 { 291 gpioj: gpio@ff149000 {
292 compatible = "abilis,tb10x-gpio"; 292 compatible = "abilis,tb10x-gpio";
293 interrupt-controller; 293 interrupt-controller;
294 #interrupt-cells = <1>; 294 #interrupt-cells = <1>;
295 interrupt-parent = <&tb10x_ictl>; 295 interrupt-parent = <&tb10x_ictl>;
296 interrupts = <27 2>; 296 interrupts = <27 2>;
297 reg = <0xFF149000 0x1000>; 297 reg = <0xff149000 0x1000>;
298 gpio-controller; 298 gpio-controller;
299 #gpio-cells = <2>; 299 #gpio-cells = <2>;
300 abilis,ngpio = <32>; 300 abilis,ngpio = <32>;
301 gpio-ranges = <&iomux 0 0 0>; 301 gpio-ranges = <&iomux 0 0 0>;
302 gpio-ranges-group-names = "gpioj"; 302 gpio-ranges-group-names = "gpioj";
303 }; 303 };
304 gpiok: gpio@FF14a000 { 304 gpiok: gpio@ff14a000 {
305 compatible = "abilis,tb10x-gpio"; 305 compatible = "abilis,tb10x-gpio";
306 interrupt-controller; 306 interrupt-controller;
307 #interrupt-cells = <1>; 307 #interrupt-cells = <1>;
308 interrupt-parent = <&tb10x_ictl>; 308 interrupt-parent = <&tb10x_ictl>;
309 interrupts = <27 2>; 309 interrupts = <27 2>;
310 reg = <0xFF14A000 0x1000>; 310 reg = <0xff14a000 0x1000>;
311 gpio-controller; 311 gpio-controller;
312 #gpio-cells = <2>; 312 #gpio-cells = <2>;
313 abilis,ngpio = <22>; 313 abilis,ngpio = <22>;
314 gpio-ranges = <&iomux 0 0 0>; 314 gpio-ranges = <&iomux 0 0 0>;
315 gpio-ranges-group-names = "gpiok"; 315 gpio-ranges-group-names = "gpiok";
316 }; 316 };
317 gpiol: gpio@FF14b000 { 317 gpiol: gpio@ff14b000 {
318 compatible = "abilis,tb10x-gpio"; 318 compatible = "abilis,tb10x-gpio";
319 interrupt-controller; 319 interrupt-controller;
320 #interrupt-cells = <1>; 320 #interrupt-cells = <1>;
321 interrupt-parent = <&tb10x_ictl>; 321 interrupt-parent = <&tb10x_ictl>;
322 interrupts = <27 2>; 322 interrupts = <27 2>;
323 reg = <0xFF14B000 0x1000>; 323 reg = <0xff14b000 0x1000>;
324 gpio-controller; 324 gpio-controller;
325 #gpio-cells = <2>; 325 #gpio-cells = <2>;
326 abilis,ngpio = <4>; 326 abilis,ngpio = <4>;
327 gpio-ranges = <&iomux 0 0 0>; 327 gpio-ranges = <&iomux 0 0 0>;
328 gpio-ranges-group-names = "gpiol"; 328 gpio-ranges-group-names = "gpiol";
329 }; 329 };
330 gpiom: gpio@FF14c000 { 330 gpiom: gpio@ff14c000 {
331 compatible = "abilis,tb10x-gpio"; 331 compatible = "abilis,tb10x-gpio";
332 interrupt-controller; 332 interrupt-controller;
333 #interrupt-cells = <1>; 333 #interrupt-cells = <1>;
334 interrupt-parent = <&tb10x_ictl>; 334 interrupt-parent = <&tb10x_ictl>;
335 interrupts = <27 2>; 335 interrupts = <27 2>;
336 reg = <0xFF14C000 0x1000>; 336 reg = <0xff14c000 0x1000>;
337 gpio-controller; 337 gpio-controller;
338 #gpio-cells = <2>; 338 #gpio-cells = <2>;
339 abilis,ngpio = <4>; 339 abilis,ngpio = <4>;
340 gpio-ranges = <&iomux 0 0 0>; 340 gpio-ranges = <&iomux 0 0 0>;
341 gpio-ranges-group-names = "gpiom"; 341 gpio-ranges-group-names = "gpiom";
342 }; 342 };
343 gpion: gpio@FF14d000 { 343 gpion: gpio@ff14d000 {
344 compatible = "abilis,tb10x-gpio"; 344 compatible = "abilis,tb10x-gpio";
345 interrupt-controller; 345 interrupt-controller;
346 #interrupt-cells = <1>; 346 #interrupt-cells = <1>;
347 interrupt-parent = <&tb10x_ictl>; 347 interrupt-parent = <&tb10x_ictl>;
348 interrupts = <27 2>; 348 interrupts = <27 2>;
349 reg = <0xFF14D000 0x1000>; 349 reg = <0xff14d000 0x1000>;
350 gpio-controller; 350 gpio-controller;
351 #gpio-cells = <2>; 351 #gpio-cells = <2>;
352 abilis,ngpio = <5>; 352 abilis,ngpio = <5>;
diff --git a/arch/arc/boot/dts/abilis_tb101_dvk.dts b/arch/arc/boot/dts/abilis_tb101_dvk.dts
index 37d88c5dd181..05143ce9c120 100644
--- a/arch/arc/boot/dts/abilis_tb101_dvk.dts
+++ b/arch/arc/boot/dts/abilis_tb101_dvk.dts
@@ -37,27 +37,27 @@
37 }; 37 };
38 38
39 soc100 { 39 soc100 {
40 uart@FF100000 { 40 uart@ff100000 {
41 pinctrl-names = "default"; 41 pinctrl-names = "default";
42 pinctrl-0 = <&pctl_uart0>; 42 pinctrl-0 = <&pctl_uart0>;
43 }; 43 };
44 ethernet@FE100000 { 44 ethernet@fe100000 {
45 phy-mode = "rgmii"; 45 phy-mode = "rgmii";
46 }; 46 };
47 47
48 i2c0: i2c@FF120000 { 48 i2c0: i2c@ff120000 {
49 i2c-sda-hold-time-ns = <432>; 49 i2c-sda-hold-time-ns = <432>;
50 }; 50 };
51 i2c1: i2c@FF121000 { 51 i2c1: i2c@ff121000 {
52 i2c-sda-hold-time-ns = <432>; 52 i2c-sda-hold-time-ns = <432>;
53 }; 53 };
54 i2c2: i2c@FF122000 { 54 i2c2: i2c@ff122000 {
55 i2c-sda-hold-time-ns = <432>; 55 i2c-sda-hold-time-ns = <432>;
56 }; 56 };
57 i2c3: i2c@FF123000 { 57 i2c3: i2c@ff123000 {
58 i2c-sda-hold-time-ns = <432>; 58 i2c-sda-hold-time-ns = <432>;
59 }; 59 };
60 i2c4: i2c@FF124000 { 60 i2c4: i2c@ff124000 {
61 i2c-sda-hold-time-ns = <432>; 61 i2c-sda-hold-time-ns = <432>;
62 }; 62 };
63 63
diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi
index 3121536b25a3..2fbf1bdfe6de 100644
--- a/arch/arc/boot/dts/abilis_tb10x.dtsi
+++ b/arch/arc/boot/dts/abilis_tb10x.dtsi
@@ -54,7 +54,7 @@
54 #size-cells = <1>; 54 #size-cells = <1>;
55 device_type = "soc"; 55 device_type = "soc";
56 ranges = <0xfe000000 0xfe000000 0x02000000 56 ranges = <0xfe000000 0xfe000000 0x02000000
57 0x000F0000 0x000F0000 0x00010000>; 57 0x000f0000 0x000f0000 0x00010000>;
58 compatible = "abilis,tb10x", "simple-bus"; 58 compatible = "abilis,tb10x", "simple-bus";
59 59
60 pll0: oscillator { 60 pll0: oscillator {
@@ -75,10 +75,10 @@
75 clock-output-names = "ahb_clk"; 75 clock-output-names = "ahb_clk";
76 }; 76 };
77 77
78 iomux: iomux@FF10601c { 78 iomux: iomux@ff10601c {
79 compatible = "abilis,tb10x-iomux"; 79 compatible = "abilis,tb10x-iomux";
80 #gpio-range-cells = <3>; 80 #gpio-range-cells = <3>;
81 reg = <0xFF10601c 0x4>; 81 reg = <0xff10601c 0x4>;
82 }; 82 };
83 83
84 intc: interrupt-controller { 84 intc: interrupt-controller {
@@ -88,7 +88,7 @@
88 }; 88 };
89 tb10x_ictl: pic@fe002000 { 89 tb10x_ictl: pic@fe002000 {
90 compatible = "abilis,tb10x-ictl"; 90 compatible = "abilis,tb10x-ictl";
91 reg = <0xFE002000 0x20>; 91 reg = <0xfe002000 0x20>;
92 interrupt-controller; 92 interrupt-controller;
93 #interrupt-cells = <2>; 93 #interrupt-cells = <2>;
94 interrupt-parent = <&intc>; 94 interrupt-parent = <&intc>;
@@ -96,27 +96,27 @@
96 20 21 22 23 24 25 26 27 28 29 30 31>; 96 20 21 22 23 24 25 26 27 28 29 30 31>;
97 }; 97 };
98 98
99 uart@FF100000 { 99 uart@ff100000 {
100 compatible = "snps,dw-apb-uart"; 100 compatible = "snps,dw-apb-uart";
101 reg = <0xFF100000 0x100>; 101 reg = <0xff100000 0x100>;
102 clock-frequency = <166666666>; 102 clock-frequency = <166666666>;
103 interrupts = <25 8>; 103 interrupts = <25 8>;
104 reg-shift = <2>; 104 reg-shift = <2>;
105 reg-io-width = <4>; 105 reg-io-width = <4>;
106 interrupt-parent = <&tb10x_ictl>; 106 interrupt-parent = <&tb10x_ictl>;
107 }; 107 };
108 ethernet@FE100000 { 108 ethernet@fe100000 {
109 compatible = "snps,dwmac-3.70a","snps,dwmac"; 109 compatible = "snps,dwmac-3.70a","snps,dwmac";
110 reg = <0xFE100000 0x1058>; 110 reg = <0xfe100000 0x1058>;
111 interrupt-parent = <&tb10x_ictl>; 111 interrupt-parent = <&tb10x_ictl>;
112 interrupts = <6 8>; 112 interrupts = <6 8>;
113 interrupt-names = "macirq"; 113 interrupt-names = "macirq";
114 clocks = <&ahb_clk>; 114 clocks = <&ahb_clk>;
115 clock-names = "stmmaceth"; 115 clock-names = "stmmaceth";
116 }; 116 };
117 dma@FE000000 { 117 dma@fe000000 {
118 compatible = "snps,dma-spear1340"; 118 compatible = "snps,dma-spear1340";
119 reg = <0xFE000000 0x400>; 119 reg = <0xfe000000 0x400>;
120 interrupt-parent = <&tb10x_ictl>; 120 interrupt-parent = <&tb10x_ictl>;
121 interrupts = <14 8>; 121 interrupts = <14 8>;
122 dma-channels = <6>; 122 dma-channels = <6>;
@@ -132,70 +132,70 @@
132 multi-block = <1 1 1 1 1 1>; 132 multi-block = <1 1 1 1 1 1>;
133 }; 133 };
134 134
135 i2c0: i2c@FF120000 { 135 i2c0: i2c@ff120000 {
136 #address-cells = <1>; 136 #address-cells = <1>;
137 #size-cells = <0>; 137 #size-cells = <0>;
138 compatible = "snps,designware-i2c"; 138 compatible = "snps,designware-i2c";
139 reg = <0xFF120000 0x1000>; 139 reg = <0xff120000 0x1000>;
140 interrupt-parent = <&tb10x_ictl>; 140 interrupt-parent = <&tb10x_ictl>;
141 interrupts = <12 8>; 141 interrupts = <12 8>;
142 clocks = <&ahb_clk>; 142 clocks = <&ahb_clk>;
143 }; 143 };
144 i2c1: i2c@FF121000 { 144 i2c1: i2c@ff121000 {
145 #address-cells = <1>; 145 #address-cells = <1>;
146 #size-cells = <0>; 146 #size-cells = <0>;
147 compatible = "snps,designware-i2c"; 147 compatible = "snps,designware-i2c";
148 reg = <0xFF121000 0x1000>; 148 reg = <0xff121000 0x1000>;
149 interrupt-parent = <&tb10x_ictl>; 149 interrupt-parent = <&tb10x_ictl>;
150 interrupts = <12 8>; 150 interrupts = <12 8>;
151 clocks = <&ahb_clk>; 151 clocks = <&ahb_clk>;
152 }; 152 };
153 i2c2: i2c@FF122000 { 153 i2c2: i2c@ff122000 {
154 #address-cells = <1>; 154 #address-cells = <1>;
155 #size-cells = <0>; 155 #size-cells = <0>;
156 compatible = "snps,designware-i2c"; 156 compatible = "snps,designware-i2c";
157 reg = <0xFF122000 0x1000>; 157 reg = <0xff122000 0x1000>;
158 interrupt-parent = <&tb10x_ictl>; 158 interrupt-parent = <&tb10x_ictl>;
159 interrupts = <12 8>; 159 interrupts = <12 8>;
160 clocks = <&ahb_clk>; 160 clocks = <&ahb_clk>;
161 }; 161 };
162 i2c3: i2c@FF123000 { 162 i2c3: i2c@ff123000 {
163 #address-cells = <1>; 163 #address-cells = <1>;
164 #size-cells = <0>; 164 #size-cells = <0>;
165 compatible = "snps,designware-i2c"; 165 compatible = "snps,designware-i2c";
166 reg = <0xFF123000 0x1000>; 166 reg = <0xff123000 0x1000>;
167 interrupt-parent = <&tb10x_ictl>; 167 interrupt-parent = <&tb10x_ictl>;
168 interrupts = <12 8>; 168 interrupts = <12 8>;
169 clocks = <&ahb_clk>; 169 clocks = <&ahb_clk>;
170 }; 170 };
171 i2c4: i2c@FF124000 { 171 i2c4: i2c@ff124000 {
172 #address-cells = <1>; 172 #address-cells = <1>;
173 #size-cells = <0>; 173 #size-cells = <0>;
174 compatible = "snps,designware-i2c"; 174 compatible = "snps,designware-i2c";
175 reg = <0xFF124000 0x1000>; 175 reg = <0xff124000 0x1000>;
176 interrupt-parent = <&tb10x_ictl>; 176 interrupt-parent = <&tb10x_ictl>;
177 interrupts = <12 8>; 177 interrupts = <12 8>;
178 clocks = <&ahb_clk>; 178 clocks = <&ahb_clk>;
179 }; 179 };
180 180
181 spi0: spi@0xFE010000 { 181 spi0: spi@fe010000 {
182 #address-cells = <1>; 182 #address-cells = <1>;
183 #size-cells = <0>; 183 #size-cells = <0>;
184 cell-index = <0>; 184 cell-index = <0>;
185 compatible = "abilis,tb100-spi"; 185 compatible = "abilis,tb100-spi";
186 num-cs = <1>; 186 num-cs = <1>;
187 reg = <0xFE010000 0x20>; 187 reg = <0xfe010000 0x20>;
188 interrupt-parent = <&tb10x_ictl>; 188 interrupt-parent = <&tb10x_ictl>;
189 interrupts = <26 8>; 189 interrupts = <26 8>;
190 clocks = <&ahb_clk>; 190 clocks = <&ahb_clk>;
191 }; 191 };
192 spi1: spi@0xFE011000 { 192 spi1: spi@fe011000 {
193 #address-cells = <1>; 193 #address-cells = <1>;
194 #size-cells = <0>; 194 #size-cells = <0>;
195 cell-index = <1>; 195 cell-index = <1>;
196 compatible = "abilis,tb100-spi"; 196 compatible = "abilis,tb100-spi";
197 num-cs = <2>; 197 num-cs = <2>;
198 reg = <0xFE011000 0x20>; 198 reg = <0xfe011000 0x20>;
199 interrupt-parent = <&tb10x_ictl>; 199 interrupt-parent = <&tb10x_ictl>;
200 interrupts = <10 8>; 200 interrupts = <10 8>;
201 clocks = <&ahb_clk>; 201 clocks = <&ahb_clk>;
@@ -226,23 +226,23 @@
226 interrupts = <20 2>, <19 2>; 226 interrupts = <20 2>, <19 2>;
227 interrupt-names = "cmd_irq", "event_irq"; 227 interrupt-names = "cmd_irq", "event_irq";
228 }; 228 };
229 tb10x_mdsc0: tb10x-mdscr@FF300000 { 229 tb10x_mdsc0: tb10x-mdscr@ff300000 {
230 compatible = "abilis,tb100-mdscr"; 230 compatible = "abilis,tb100-mdscr";
231 reg = <0xFF300000 0x7000>; 231 reg = <0xff300000 0x7000>;
232 tb100-mdscr-manage-tsin; 232 tb100-mdscr-manage-tsin;
233 }; 233 };
234 tb10x_mscr0: tb10x-mdscr@FF307000 { 234 tb10x_mscr0: tb10x-mdscr@ff307000 {
235 compatible = "abilis,tb100-mdscr"; 235 compatible = "abilis,tb100-mdscr";
236 reg = <0xFF307000 0x7000>; 236 reg = <0xff307000 0x7000>;
237 }; 237 };
238 tb10x_scr0: tb10x-mdscr@ff30e000 { 238 tb10x_scr0: tb10x-mdscr@ff30e000 {
239 compatible = "abilis,tb100-mdscr"; 239 compatible = "abilis,tb100-mdscr";
240 reg = <0xFF30e000 0x4000>; 240 reg = <0xff30e000 0x4000>;
241 tb100-mdscr-manage-tsin; 241 tb100-mdscr-manage-tsin;
242 }; 242 };
243 tb10x_scr1: tb10x-mdscr@ff312000 { 243 tb10x_scr1: tb10x-mdscr@ff312000 {
244 compatible = "abilis,tb100-mdscr"; 244 compatible = "abilis,tb100-mdscr";
245 reg = <0xFF312000 0x4000>; 245 reg = <0xff312000 0x4000>;
246 tb100-mdscr-manage-tsin; 246 tb100-mdscr-manage-tsin;
247 }; 247 };
248 tb10x_wfb: tb10x-wfb@ff319000 { 248 tb10x_wfb: tb10x-wfb@ff319000 {
diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi
index fdc266504ada..37be3bf03ad6 100644
--- a/arch/arc/boot/dts/axc001.dtsi
+++ b/arch/arc/boot/dts/axc001.dtsi
@@ -41,7 +41,7 @@
41 * this GPIO block ORs all interrupts on CPU card (creg,..) 41 * this GPIO block ORs all interrupts on CPU card (creg,..)
42 * to uplink only 1 IRQ to ARC core intc 42 * to uplink only 1 IRQ to ARC core intc
43 */ 43 */
44 dw-apb-gpio@0x2000 { 44 dw-apb-gpio@2000 {
45 compatible = "snps,dw-apb-gpio"; 45 compatible = "snps,dw-apb-gpio";
46 reg = < 0x2000 0x80 >; 46 reg = < 0x2000 0x80 >;
47 #address-cells = <1>; 47 #address-cells = <1>;
@@ -60,7 +60,7 @@
60 }; 60 };
61 }; 61 };
62 62
63 debug_uart: dw-apb-uart@0x5000 { 63 debug_uart: dw-apb-uart@5000 {
64 compatible = "snps,dw-apb-uart"; 64 compatible = "snps,dw-apb-uart";
65 reg = <0x5000 0x100>; 65 reg = <0x5000 0x100>;
66 clock-frequency = <33333000>; 66 clock-frequency = <33333000>;
@@ -88,7 +88,7 @@
88 * avoid duplicating the MB dtsi file given that IRQ from 88 * avoid duplicating the MB dtsi file given that IRQ from
89 * this intc to cpu intc are different for axs101 and axs103 89 * this intc to cpu intc are different for axs101 and axs103
90 */ 90 */
91 mb_intc: dw-apb-ictl@0xe0012000 { 91 mb_intc: dw-apb-ictl@e0012000 {
92 #interrupt-cells = <1>; 92 #interrupt-cells = <1>;
93 compatible = "snps,dw-apb-ictl"; 93 compatible = "snps,dw-apb-ictl";
94 reg = < 0x0 0xe0012000 0x0 0x200 >; 94 reg = < 0x0 0xe0012000 0x0 0x200 >;
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index d75d65ddf8e3..effa37536d7a 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -55,7 +55,7 @@
55 * this GPIO block ORs all interrupts on CPU card (creg,..) 55 * this GPIO block ORs all interrupts on CPU card (creg,..)
56 * to uplink only 1 IRQ to ARC core intc 56 * to uplink only 1 IRQ to ARC core intc
57 */ 57 */
58 dw-apb-gpio@0x2000 { 58 dw-apb-gpio@2000 {
59 compatible = "snps,dw-apb-gpio"; 59 compatible = "snps,dw-apb-gpio";
60 reg = < 0x2000 0x80 >; 60 reg = < 0x2000 0x80 >;
61 #address-cells = <1>; 61 #address-cells = <1>;
@@ -74,7 +74,7 @@
74 }; 74 };
75 }; 75 };
76 76
77 debug_uart: dw-apb-uart@0x5000 { 77 debug_uart: dw-apb-uart@5000 {
78 compatible = "snps,dw-apb-uart"; 78 compatible = "snps,dw-apb-uart";
79 reg = <0x5000 0x100>; 79 reg = <0x5000 0x100>;
80 clock-frequency = <33333000>; 80 clock-frequency = <33333000>;
@@ -102,19 +102,19 @@
102 * external DMA buffer located outside of IOC aperture. 102 * external DMA buffer located outside of IOC aperture.
103 */ 103 */
104 axs10x_mb { 104 axs10x_mb {
105 ethernet@0x18000 { 105 ethernet@18000 {
106 dma-coherent; 106 dma-coherent;
107 }; 107 };
108 108
109 ehci@0x40000 { 109 ehci@40000 {
110 dma-coherent; 110 dma-coherent;
111 }; 111 };
112 112
113 ohci@0x60000 { 113 ohci@60000 {
114 dma-coherent; 114 dma-coherent;
115 }; 115 };
116 116
117 mmc@0x15000 { 117 mmc@15000 {
118 dma-coherent; 118 dma-coherent;
119 }; 119 };
120 }; 120 };
@@ -132,7 +132,7 @@
132 * avoid duplicating the MB dtsi file given that IRQ from 132 * avoid duplicating the MB dtsi file given that IRQ from
133 * this intc to cpu intc are different for axs101 and axs103 133 * this intc to cpu intc are different for axs101 and axs103
134 */ 134 */
135 mb_intc: dw-apb-ictl@0xe0012000 { 135 mb_intc: dw-apb-ictl@e0012000 {
136 #interrupt-cells = <1>; 136 #interrupt-cells = <1>;
137 compatible = "snps,dw-apb-ictl"; 137 compatible = "snps,dw-apb-ictl";
138 reg = < 0x0 0xe0012000 0x0 0x200 >; 138 reg = < 0x0 0xe0012000 0x0 0x200 >;
@@ -153,7 +153,7 @@
153 #size-cells = <2>; 153 #size-cells = <2>;
154 ranges; 154 ranges;
155 /* 155 /*
156 * Move frame buffer out of IOC aperture (0x8z-0xAz). 156 * Move frame buffer out of IOC aperture (0x8z-0xaz).
157 */ 157 */
158 frame_buffer: frame_buffer@be000000 { 158 frame_buffer: frame_buffer@be000000 {
159 compatible = "shared-dma-pool"; 159 compatible = "shared-dma-pool";
diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
index a05bb737ea63..e401e59f6180 100644
--- a/arch/arc/boot/dts/axc003_idu.dtsi
+++ b/arch/arc/boot/dts/axc003_idu.dtsi
@@ -62,7 +62,7 @@
62 * this GPIO block ORs all interrupts on CPU card (creg,..) 62 * this GPIO block ORs all interrupts on CPU card (creg,..)
63 * to uplink only 1 IRQ to ARC core intc 63 * to uplink only 1 IRQ to ARC core intc
64 */ 64 */
65 dw-apb-gpio@0x2000 { 65 dw-apb-gpio@2000 {
66 compatible = "snps,dw-apb-gpio"; 66 compatible = "snps,dw-apb-gpio";
67 reg = < 0x2000 0x80 >; 67 reg = < 0x2000 0x80 >;
68 #address-cells = <1>; 68 #address-cells = <1>;
@@ -81,7 +81,7 @@
81 }; 81 };
82 }; 82 };
83 83
84 debug_uart: dw-apb-uart@0x5000 { 84 debug_uart: dw-apb-uart@5000 {
85 compatible = "snps,dw-apb-uart"; 85 compatible = "snps,dw-apb-uart";
86 reg = <0x5000 0x100>; 86 reg = <0x5000 0x100>;
87 clock-frequency = <33333000>; 87 clock-frequency = <33333000>;
@@ -109,19 +109,19 @@
109 * external DMA buffer located outside of IOC aperture. 109 * external DMA buffer located outside of IOC aperture.
110 */ 110 */
111 axs10x_mb { 111 axs10x_mb {
112 ethernet@0x18000 { 112 ethernet@18000 {
113 dma-coherent; 113 dma-coherent;
114 }; 114 };
115 115
116 ehci@0x40000 { 116 ehci@40000 {
117 dma-coherent; 117 dma-coherent;
118 }; 118 };
119 119
120 ohci@0x60000 { 120 ohci@60000 {
121 dma-coherent; 121 dma-coherent;
122 }; 122 };
123 123
124 mmc@0x15000 { 124 mmc@15000 {
125 dma-coherent; 125 dma-coherent;
126 }; 126 };
127 }; 127 };
@@ -138,7 +138,7 @@
138 * avoid duplicating the MB dtsi file given that IRQ from 138 * avoid duplicating the MB dtsi file given that IRQ from
139 * this intc to cpu intc are different for axs101 and axs103 139 * this intc to cpu intc are different for axs101 and axs103
140 */ 140 */
141 mb_intc: dw-apb-ictl@0xe0012000 { 141 mb_intc: dw-apb-ictl@e0012000 {
142 #interrupt-cells = <1>; 142 #interrupt-cells = <1>;
143 compatible = "snps,dw-apb-ictl"; 143 compatible = "snps,dw-apb-ictl";
144 reg = < 0x0 0xe0012000 0x0 0x200 >; 144 reg = < 0x0 0xe0012000 0x0 0x200 >;
@@ -159,7 +159,7 @@
159 #size-cells = <2>; 159 #size-cells = <2>;
160 ranges; 160 ranges;
161 /* 161 /*
162 * Move frame buffer out of IOC aperture (0x8z-0xAz). 162 * Move frame buffer out of IOC aperture (0x8z-0xaz).
163 */ 163 */
164 frame_buffer: frame_buffer@be000000 { 164 frame_buffer: frame_buffer@be000000 {
165 compatible = "shared-dma-pool"; 165 compatible = "shared-dma-pool";
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 37bafd44e36d..4ead6dc9af2f 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -72,7 +72,7 @@
72 }; 72 };
73 }; 73 };
74 74
75 gmac: ethernet@0x18000 { 75 gmac: ethernet@18000 {
76 #interrupt-cells = <1>; 76 #interrupt-cells = <1>;
77 compatible = "snps,dwmac"; 77 compatible = "snps,dwmac";
78 reg = < 0x18000 0x2000 >; 78 reg = < 0x18000 0x2000 >;
@@ -88,13 +88,13 @@
88 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 88 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
89 }; 89 };
90 90
91 ehci@0x40000 { 91 ehci@40000 {
92 compatible = "generic-ehci"; 92 compatible = "generic-ehci";
93 reg = < 0x40000 0x100 >; 93 reg = < 0x40000 0x100 >;
94 interrupts = < 8 >; 94 interrupts = < 8 >;
95 }; 95 };
96 96
97 ohci@0x60000 { 97 ohci@60000 {
98 compatible = "generic-ohci"; 98 compatible = "generic-ohci";
99 reg = < 0x60000 0x100 >; 99 reg = < 0x60000 0x100 >;
100 interrupts = < 8 >; 100 interrupts = < 8 >;
@@ -118,7 +118,7 @@
118 * dw_mci_pltfm_prepare_command() is used in generic platform 118 * dw_mci_pltfm_prepare_command() is used in generic platform
119 * code. 119 * code.
120 */ 120 */
121 mmc@0x15000 { 121 mmc@15000 {
122 compatible = "altr,socfpga-dw-mshc"; 122 compatible = "altr,socfpga-dw-mshc";
123 reg = < 0x15000 0x400 >; 123 reg = < 0x15000 0x400 >;
124 fifo-depth = < 16 >; 124 fifo-depth = < 16 >;
@@ -129,7 +129,7 @@
129 bus-width = < 4 >; 129 bus-width = < 4 >;
130 }; 130 };
131 131
132 uart@0x20000 { 132 uart@20000 {
133 compatible = "snps,dw-apb-uart"; 133 compatible = "snps,dw-apb-uart";
134 reg = <0x20000 0x100>; 134 reg = <0x20000 0x100>;
135 clock-frequency = <33333333>; 135 clock-frequency = <33333333>;
@@ -139,7 +139,7 @@
139 reg-io-width = <4>; 139 reg-io-width = <4>;
140 }; 140 };
141 141
142 uart@0x21000 { 142 uart@21000 {
143 compatible = "snps,dw-apb-uart"; 143 compatible = "snps,dw-apb-uart";
144 reg = <0x21000 0x100>; 144 reg = <0x21000 0x100>;
145 clock-frequency = <33333333>; 145 clock-frequency = <33333333>;
@@ -150,7 +150,7 @@
150 }; 150 };
151 151
152 /* UART muxed with USB data port (ttyS3) */ 152 /* UART muxed with USB data port (ttyS3) */
153 uart@0x22000 { 153 uart@22000 {
154 compatible = "snps,dw-apb-uart"; 154 compatible = "snps,dw-apb-uart";
155 reg = <0x22000 0x100>; 155 reg = <0x22000 0x100>;
156 clock-frequency = <33333333>; 156 clock-frequency = <33333333>;
@@ -160,7 +160,7 @@
160 reg-io-width = <4>; 160 reg-io-width = <4>;
161 }; 161 };
162 162
163 i2c@0x1d000 { 163 i2c@1d000 {
164 compatible = "snps,designware-i2c"; 164 compatible = "snps,designware-i2c";
165 reg = <0x1d000 0x100>; 165 reg = <0x1d000 0x100>;
166 clock-frequency = <400000>; 166 clock-frequency = <400000>;
@@ -177,7 +177,7 @@
177 #sound-dai-cells = <0>; 177 #sound-dai-cells = <0>;
178 }; 178 };
179 179
180 i2c@0x1f000 { 180 i2c@1f000 {
181 compatible = "snps,designware-i2c"; 181 compatible = "snps,designware-i2c";
182 #address-cells = <1>; 182 #address-cells = <1>;
183 #size-cells = <0>; 183 #size-cells = <0>;
@@ -218,13 +218,13 @@
218 }; 218 };
219 }; 219 };
220 220
221 eeprom@0x54{ 221 eeprom@54{
222 compatible = "atmel,24c01"; 222 compatible = "atmel,24c01";
223 reg = <0x54>; 223 reg = <0x54>;
224 pagesize = <0x8>; 224 pagesize = <0x8>;
225 }; 225 };
226 226
227 eeprom@0x57{ 227 eeprom@57{
228 compatible = "atmel,24c04"; 228 compatible = "atmel,24c04";
229 reg = <0x57>; 229 reg = <0x57>;
230 pagesize = <0x8>; 230 pagesize = <0x8>;
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
index 43f17b51ee89..69bc1c9e8e50 100644
--- a/arch/arc/boot/dts/hsdk.dts
+++ b/arch/arc/boot/dts/hsdk.dts
@@ -110,12 +110,12 @@
110 cgu_rst: reset-controller@8a0 { 110 cgu_rst: reset-controller@8a0 {
111 compatible = "snps,hsdk-reset"; 111 compatible = "snps,hsdk-reset";
112 #reset-cells = <1>; 112 #reset-cells = <1>;
113 reg = <0x8A0 0x4>, <0xFF0 0x4>; 113 reg = <0x8a0 0x4>, <0xff0 0x4>;
114 }; 114 };
115 115
116 core_clk: core-clk@0 { 116 core_clk: core-clk@0 {
117 compatible = "snps,hsdk-core-pll-clock"; 117 compatible = "snps,hsdk-core-pll-clock";
118 reg = <0x00 0x10>, <0x14B8 0x4>; 118 reg = <0x00 0x10>, <0x14b8 0x4>;
119 #clock-cells = <0>; 119 #clock-cells = <0>;
120 clocks = <&input_clk>; 120 clocks = <&input_clk>;
121 121
@@ -167,6 +167,18 @@
167 #clock-cells = <0>; 167 #clock-cells = <0>;
168 }; 168 };
169 169
170 dmac_core_clk: dmac-core-clk {
171 compatible = "fixed-clock";
172 clock-frequency = <400000000>;
173 #clock-cells = <0>;
174 };
175
176 dmac_cfg_clk: dmac-gpu-cfg-clk {
177 compatible = "fixed-clock";
178 clock-frequency = <200000000>;
179 #clock-cells = <0>;
180 };
181
170 gmac: ethernet@8000 { 182 gmac: ethernet@8000 {
171 #interrupt-cells = <1>; 183 #interrupt-cells = <1>;
172 compatible = "snps,dwmac"; 184 compatible = "snps,dwmac";
@@ -200,6 +212,7 @@
200 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 212 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
201 reg = <0x60000 0x100>; 213 reg = <0x60000 0x100>;
202 interrupts = <15>; 214 interrupts = <15>;
215 resets = <&cgu_rst HSDK_USB_RESET>;
203 dma-coherent; 216 dma-coherent;
204 }; 217 };
205 218
@@ -207,6 +220,7 @@
207 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 220 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
208 reg = <0x40000 0x100>; 221 reg = <0x40000 0x100>;
209 interrupts = <15>; 222 interrupts = <15>;
223 resets = <&cgu_rst HSDK_USB_RESET>;
210 dma-coherent; 224 dma-coherent;
211 }; 225 };
212 226
@@ -237,6 +251,21 @@
237 reg = <0>; 251 reg = <0>;
238 }; 252 };
239 }; 253 };
254
255 dmac: dmac@80000 {
256 compatible = "snps,axi-dma-1.01a";
257 reg = <0x80000 0x400>;
258 interrupts = <27>;
259 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
260 clock-names = "core-clk", "cfgr-clk";
261
262 dma-channels = <4>;
263 snps,dma-masters = <2>;
264 snps,data-width = <3>;
265 snps,block-size = <4096 4096 4096 4096>;
266 snps,priority = <0 1 2 3>;
267 snps,axi-max-burst-len = <16>;
268 };
240 }; 269 };
241 270
242 memory@80000000 { 271 memory@80000000 {
diff --git a/arch/arc/boot/dts/vdk_axc003.dtsi b/arch/arc/boot/dts/vdk_axc003.dtsi
index 0fd6ba985b16..84e8766c8ca2 100644
--- a/arch/arc/boot/dts/vdk_axc003.dtsi
+++ b/arch/arc/boot/dts/vdk_axc003.dtsi
@@ -36,7 +36,7 @@
36 #interrupt-cells = <1>; 36 #interrupt-cells = <1>;
37 }; 37 };
38 38
39 debug_uart: dw-apb-uart@0x5000 { 39 debug_uart: dw-apb-uart@5000 {
40 compatible = "snps,dw-apb-uart"; 40 compatible = "snps,dw-apb-uart";
41 reg = <0x5000 0x100>; 41 reg = <0x5000 0x100>;
42 clock-frequency = <2403200>; 42 clock-frequency = <2403200>;
@@ -49,7 +49,7 @@
49 49
50 }; 50 };
51 51
52 mb_intc: dw-apb-ictl@0xe0012000 { 52 mb_intc: dw-apb-ictl@e0012000 {
53 #interrupt-cells = <1>; 53 #interrupt-cells = <1>;
54 compatible = "snps,dw-apb-ictl"; 54 compatible = "snps,dw-apb-ictl";
55 reg = < 0xe0012000 0x200 >; 55 reg = < 0xe0012000 0x200 >;
diff --git a/arch/arc/boot/dts/vdk_axc003_idu.dtsi b/arch/arc/boot/dts/vdk_axc003_idu.dtsi
index 28956f9a9f3d..eb7e705e8a27 100644
--- a/arch/arc/boot/dts/vdk_axc003_idu.dtsi
+++ b/arch/arc/boot/dts/vdk_axc003_idu.dtsi
@@ -44,7 +44,7 @@
44 #interrupt-cells = <1>; 44 #interrupt-cells = <1>;
45 }; 45 };
46 46
47 debug_uart: dw-apb-uart@0x5000 { 47 debug_uart: dw-apb-uart@5000 {
48 compatible = "snps,dw-apb-uart"; 48 compatible = "snps,dw-apb-uart";
49 reg = <0x5000 0x100>; 49 reg = <0x5000 0x100>;
50 clock-frequency = <2403200>; 50 clock-frequency = <2403200>;
@@ -57,7 +57,7 @@
57 57
58 }; 58 };
59 59
60 mb_intc: dw-apb-ictl@0xe0012000 { 60 mb_intc: dw-apb-ictl@e0012000 {
61 #interrupt-cells = <1>; 61 #interrupt-cells = <1>;
62 compatible = "snps,dw-apb-ictl"; 62 compatible = "snps,dw-apb-ictl";
63 reg = < 0xe0012000 0x200 >; 63 reg = < 0xe0012000 0x200 >;
diff --git a/arch/arc/boot/dts/vdk_axs10x_mb.dtsi b/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
index 48bb4b4cd234..925d5cc95dbb 100644
--- a/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
@@ -36,7 +36,7 @@
36 }; 36 };
37 }; 37 };
38 38
39 ethernet@0x18000 { 39 ethernet@18000 {
40 #interrupt-cells = <1>; 40 #interrupt-cells = <1>;
41 compatible = "snps,dwmac"; 41 compatible = "snps,dwmac";
42 reg = < 0x18000 0x2000 >; 42 reg = < 0x18000 0x2000 >;
@@ -49,13 +49,13 @@
49 clock-names = "stmmaceth"; 49 clock-names = "stmmaceth";
50 }; 50 };
51 51
52 ehci@0x40000 { 52 ehci@40000 {
53 compatible = "generic-ehci"; 53 compatible = "generic-ehci";
54 reg = < 0x40000 0x100 >; 54 reg = < 0x40000 0x100 >;
55 interrupts = < 8 >; 55 interrupts = < 8 >;
56 }; 56 };
57 57
58 uart@0x20000 { 58 uart@20000 {
59 compatible = "snps,dw-apb-uart"; 59 compatible = "snps,dw-apb-uart";
60 reg = <0x20000 0x100>; 60 reg = <0x20000 0x100>;
61 clock-frequency = <2403200>; 61 clock-frequency = <2403200>;
@@ -65,7 +65,7 @@
65 reg-io-width = <4>; 65 reg-io-width = <4>;
66 }; 66 };
67 67
68 uart@0x21000 { 68 uart@21000 {
69 compatible = "snps,dw-apb-uart"; 69 compatible = "snps,dw-apb-uart";
70 reg = <0x21000 0x100>; 70 reg = <0x21000 0x100>;
71 clock-frequency = <2403200>; 71 clock-frequency = <2403200>;
@@ -75,7 +75,7 @@
75 reg-io-width = <4>; 75 reg-io-width = <4>;
76 }; 76 };
77 77
78 uart@0x22000 { 78 uart@22000 {
79 compatible = "snps,dw-apb-uart"; 79 compatible = "snps,dw-apb-uart";
80 reg = <0x22000 0x100>; 80 reg = <0x22000 0x100>;
81 clock-frequency = <2403200>; 81 clock-frequency = <2403200>;
@@ -101,7 +101,7 @@
101 interrupt-names = "arc_ps2_irq"; 101 interrupt-names = "arc_ps2_irq";
102 }; 102 };
103 103
104 mmc@0x15000 { 104 mmc@15000 {
105 compatible = "snps,dw-mshc"; 105 compatible = "snps,dw-mshc";
106 reg = <0x15000 0x400>; 106 reg = <0x15000 0x400>;
107 fifo-depth = <1024>; 107 fifo-depth = <1024>;
@@ -117,11 +117,11 @@
117 * Embedded Vision subsystem UIO mappings; only relevant for EV VDK 117 * Embedded Vision subsystem UIO mappings; only relevant for EV VDK
118 * 118 *
119 * This node is intentionally put outside of MB above becase 119 * This node is intentionally put outside of MB above becase
120 * it maps areas outside of MB's 0xEz-0xFz. 120 * it maps areas outside of MB's 0xez-0xfz.
121 */ 121 */
122 uio_ev: uio@0xD0000000 { 122 uio_ev: uio@d0000000 {
123 compatible = "generic-uio"; 123 compatible = "generic-uio";
124 reg = <0xD0000000 0x2000 0xD1000000 0x2000 0x90000000 0x10000000 0xC0000000 0x10000000>; 124 reg = <0xd0000000 0x2000 0xd1000000 0x2000 0x90000000 0x10000000 0xc0000000 0x10000000>;
125 reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem"; 125 reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
126 interrupt-parent = <&mb_intc>; 126 interrupt-parent = <&mb_intc>;
127 interrupts = <23>; 127 interrupts = <23>;
diff --git a/arch/arc/configs/hsdk_defconfig b/arch/arc/configs/hsdk_defconfig
index 6fd3d29546af..0e5fd29ed238 100644
--- a/arch/arc/configs/hsdk_defconfig
+++ b/arch/arc/configs/hsdk_defconfig
@@ -8,6 +8,7 @@ CONFIG_NAMESPACES=y
8# CONFIG_UTS_NS is not set 8# CONFIG_UTS_NS is not set
9# CONFIG_PID_NS is not set 9# CONFIG_PID_NS is not set
10CONFIG_BLK_DEV_INITRD=y 10CONFIG_BLK_DEV_INITRD=y
11CONFIG_BLK_DEV_RAM=y
11CONFIG_EMBEDDED=y 12CONFIG_EMBEDDED=y
12CONFIG_PERF_EVENTS=y 13CONFIG_PERF_EVENTS=y
13# CONFIG_VM_EVENT_COUNTERS is not set 14# CONFIG_VM_EVENT_COUNTERS is not set
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index a27eafdc8260..a7d4be87b2f0 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -82,6 +82,7 @@
82#define ECR_V_DTLB_MISS 0x05 82#define ECR_V_DTLB_MISS 0x05
83#define ECR_V_PROTV 0x06 83#define ECR_V_PROTV 0x06
84#define ECR_V_TRAP 0x09 84#define ECR_V_TRAP 0x09
85#define ECR_V_MISALIGN 0x0d
85#endif 86#endif
86 87
87/* DTLB Miss and Protection Violation Cause Codes */ 88/* DTLB Miss and Protection Violation Cause Codes */
@@ -167,14 +168,6 @@ struct bcr_mpy {
167#endif 168#endif
168}; 169};
169 170
170struct bcr_extn_xymem {
171#ifdef CONFIG_CPU_BIG_ENDIAN
172 unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
173#else
174 unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
175#endif
176};
177
178struct bcr_iccm_arcompact { 171struct bcr_iccm_arcompact {
179#ifdef CONFIG_CPU_BIG_ENDIAN 172#ifdef CONFIG_CPU_BIG_ENDIAN
180 unsigned int base:16, pad:5, sz:3, ver:8; 173 unsigned int base:16, pad:5, sz:3, ver:8;
@@ -312,7 +305,7 @@ struct cpuinfo_arc {
312 struct cpuinfo_arc_bpu bpu; 305 struct cpuinfo_arc_bpu bpu;
313 struct bcr_identity core; 306 struct bcr_identity core;
314 struct bcr_isa_arcv2 isa; 307 struct bcr_isa_arcv2 isa;
315 const char *details, *name; 308 const char *release, *name;
316 unsigned int vec_base; 309 unsigned int vec_base;
317 struct cpuinfo_arc_ccm iccm, dccm; 310 struct cpuinfo_arc_ccm iccm, dccm;
318 struct { 311 struct {
@@ -322,7 +315,6 @@ struct cpuinfo_arc {
322 timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4; 315 timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
323 } extn; 316 } extn;
324 struct bcr_mpy extn_mpy; 317 struct bcr_mpy extn_mpy;
325 struct bcr_extn_xymem extn_xymem;
326}; 318};
327 319
328extern struct cpuinfo_arc cpuinfo_arc700[]; 320extern struct cpuinfo_arc cpuinfo_arc700[];
diff --git a/arch/arc/include/asm/irqflags-arcv2.h b/arch/arc/include/asm/irqflags-arcv2.h
index 8a4f77ea3238..e66d0339e1d8 100644
--- a/arch/arc/include/asm/irqflags-arcv2.h
+++ b/arch/arc/include/asm/irqflags-arcv2.h
@@ -44,7 +44,13 @@
44#define ARCV2_IRQ_DEF_PRIO 1 44#define ARCV2_IRQ_DEF_PRIO 1
45 45
46/* seed value for status register */ 46/* seed value for status register */
47#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \ 47#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
48#define __AD_ENB STATUS_AD_MASK
49#else
50#define __AD_ENB 0
51#endif
52
53#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | __AD_ENB | \
48 (ARCV2_IRQ_DEF_PRIO << 1)) 54 (ARCV2_IRQ_DEF_PRIO << 1))
49 55
50#ifndef __ASSEMBLY__ 56#ifndef __ASSEMBLY__
diff --git a/arch/arc/include/asm/perf_event.h b/arch/arc/include/asm/perf_event.h
index 6958545390f0..9cd7ee4fad39 100644
--- a/arch/arc/include/asm/perf_event.h
+++ b/arch/arc/include/asm/perf_event.h
@@ -105,10 +105,10 @@ static const char * const arc_pmu_ev_hw_map[] = {
105 [PERF_COUNT_HW_INSTRUCTIONS] = "iall", 105 [PERF_COUNT_HW_INSTRUCTIONS] = "iall",
106 /* All jump instructions that are taken */ 106 /* All jump instructions that are taken */
107 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak", 107 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak",
108 [PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */
109#ifdef CONFIG_ISA_ARCV2 108#ifdef CONFIG_ISA_ARCV2
110 [PERF_COUNT_HW_BRANCH_MISSES] = "bpmp", 109 [PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",
111#else 110#else
111 [PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */
112 [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */ 112 [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
113#endif 113#endif
114 [PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */ 114 [PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */
diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
index 2ba04a7db621..daa914da7968 100644
--- a/arch/arc/include/asm/spinlock.h
+++ b/arch/arc/include/asm/spinlock.h
@@ -21,8 +21,6 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
21{ 21{
22 unsigned int val; 22 unsigned int val;
23 23
24 smp_mb();
25
26 __asm__ __volatile__( 24 __asm__ __volatile__(
27 "1: llock %[val], [%[slock]] \n" 25 "1: llock %[val], [%[slock]] \n"
28 " breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */ 26 " breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */
@@ -34,6 +32,14 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
34 [LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__) 32 [LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
35 : "memory", "cc"); 33 : "memory", "cc");
36 34
35 /*
36 * ACQUIRE barrier to ensure load/store after taking the lock
37 * don't "bleed-up" out of the critical section (leak-in is allowed)
38 * http://www.spinics.net/lists/kernel/msg2010409.html
39 *
40 * ARCv2 only has load-load, store-store and all-all barrier
41 * thus need the full all-all barrier
42 */
37 smp_mb(); 43 smp_mb();
38} 44}
39 45
@@ -42,8 +48,6 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
42{ 48{
43 unsigned int val, got_it = 0; 49 unsigned int val, got_it = 0;
44 50
45 smp_mb();
46
47 __asm__ __volatile__( 51 __asm__ __volatile__(
48 "1: llock %[val], [%[slock]] \n" 52 "1: llock %[val], [%[slock]] \n"
49 " breq %[val], %[LOCKED], 4f \n" /* already LOCKED, just bail */ 53 " breq %[val], %[LOCKED], 4f \n" /* already LOCKED, just bail */
@@ -67,9 +71,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
67{ 71{
68 smp_mb(); 72 smp_mb();
69 73
70 lock->slock = __ARCH_SPIN_LOCK_UNLOCKED__; 74 WRITE_ONCE(lock->slock, __ARCH_SPIN_LOCK_UNLOCKED__);
71
72 smp_mb();
73} 75}
74 76
75/* 77/*
@@ -81,8 +83,6 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
81{ 83{
82 unsigned int val; 84 unsigned int val;
83 85
84 smp_mb();
85
86 /* 86 /*
87 * zero means writer holds the lock exclusively, deny Reader. 87 * zero means writer holds the lock exclusively, deny Reader.
88 * Otherwise grant lock to first/subseq reader 88 * Otherwise grant lock to first/subseq reader
@@ -113,8 +113,6 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
113{ 113{
114 unsigned int val, got_it = 0; 114 unsigned int val, got_it = 0;
115 115
116 smp_mb();
117
118 __asm__ __volatile__( 116 __asm__ __volatile__(
119 "1: llock %[val], [%[rwlock]] \n" 117 "1: llock %[val], [%[rwlock]] \n"
120 " brls %[val], %[WR_LOCKED], 4f\n" /* <= 0: already write locked, bail */ 118 " brls %[val], %[WR_LOCKED], 4f\n" /* <= 0: already write locked, bail */
@@ -140,8 +138,6 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
140{ 138{
141 unsigned int val; 139 unsigned int val;
142 140
143 smp_mb();
144
145 /* 141 /*
146 * If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__), 142 * If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
147 * deny writer. Otherwise if unlocked grant to writer 143 * deny writer. Otherwise if unlocked grant to writer
@@ -175,8 +171,6 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
175{ 171{
176 unsigned int val, got_it = 0; 172 unsigned int val, got_it = 0;
177 173
178 smp_mb();
179
180 __asm__ __volatile__( 174 __asm__ __volatile__(
181 "1: llock %[val], [%[rwlock]] \n" 175 "1: llock %[val], [%[rwlock]] \n"
182 " brne %[val], %[UNLOCKED], 4f \n" /* !UNLOCKED, bail */ 176 " brne %[val], %[UNLOCKED], 4f \n" /* !UNLOCKED, bail */
@@ -217,17 +211,13 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
217 : [val] "=&r" (val) 211 : [val] "=&r" (val)
218 : [rwlock] "r" (&(rw->counter)) 212 : [rwlock] "r" (&(rw->counter))
219 : "memory", "cc"); 213 : "memory", "cc");
220
221 smp_mb();
222} 214}
223 215
224static inline void arch_write_unlock(arch_rwlock_t *rw) 216static inline void arch_write_unlock(arch_rwlock_t *rw)
225{ 217{
226 smp_mb(); 218 smp_mb();
227 219
228 rw->counter = __ARCH_RW_LOCK_UNLOCKED__; 220 WRITE_ONCE(rw->counter, __ARCH_RW_LOCK_UNLOCKED__);
229
230 smp_mb();
231} 221}
232 222
233#else /* !CONFIG_ARC_HAS_LLSC */ 223#else /* !CONFIG_ARC_HAS_LLSC */
@@ -237,10 +227,9 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
237 unsigned int val = __ARCH_SPIN_LOCK_LOCKED__; 227 unsigned int val = __ARCH_SPIN_LOCK_LOCKED__;
238 228
239 /* 229 /*
240 * This smp_mb() is technically superfluous, we only need the one 230 * Per lkmm, smp_mb() is only required after _lock (and before_unlock)
241 * after the lock for providing the ACQUIRE semantics. 231 * for ACQ and REL semantics respectively. However EX based spinlocks
242 * However doing the "right" thing was regressing hackbench 232 * need the extra smp_mb to workaround a hardware quirk.
243 * so keeping this, pending further investigation
244 */ 233 */
245 smp_mb(); 234 smp_mb();
246 235
@@ -257,14 +246,6 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
257#endif 246#endif
258 : "memory"); 247 : "memory");
259 248
260 /*
261 * ACQUIRE barrier to ensure load/store after taking the lock
262 * don't "bleed-up" out of the critical section (leak-in is allowed)
263 * http://www.spinics.net/lists/kernel/msg2010409.html
264 *
265 * ARCv2 only has load-load, store-store and all-all barrier
266 * thus need the full all-all barrier
267 */
268 smp_mb(); 249 smp_mb();
269} 250}
270 251
@@ -309,8 +290,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
309 : "memory"); 290 : "memory");
310 291
311 /* 292 /*
312 * superfluous, but keeping for now - see pairing version in 293 * see pairing version/comment in arch_spin_lock above
313 * arch_spin_lock above
314 */ 294 */
315 smp_mb(); 295 smp_mb();
316} 296}
@@ -344,7 +324,6 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
344 arch_spin_unlock(&(rw->lock_mutex)); 324 arch_spin_unlock(&(rw->lock_mutex));
345 local_irq_restore(flags); 325 local_irq_restore(flags);
346 326
347 smp_mb();
348 return ret; 327 return ret;
349} 328}
350 329
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 30e090625916..8f6e0447dd17 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -54,7 +54,12 @@
54 ; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access 54 ; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access
55 ; by default 55 ; by default
56 lr r5, [status32] 56 lr r5, [status32]
57#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
57 bset r5, r5, STATUS_AD_BIT 58 bset r5, r5, STATUS_AD_BIT
59#else
60 ; Although disabled at reset, bootloader might have enabled it
61 bclr r5, r5, STATUS_AD_BIT
62#endif
58 kflag r5 63 kflag r5
59#endif 64#endif
60.endm 65.endm
@@ -106,6 +111,7 @@ ENTRY(stext)
106 ; r2 = pointer to uboot provided cmdline or external DTB in mem 111 ; r2 = pointer to uboot provided cmdline or external DTB in mem
107 ; These are handled later in handle_uboot_args() 112 ; These are handled later in handle_uboot_args()
108 st r0, [@uboot_tag] 113 st r0, [@uboot_tag]
114 st r1, [@uboot_magic]
109 st r2, [@uboot_arg] 115 st r2, [@uboot_arg]
110 116
111 ; setup "current" tsk and optionally cache it in dedicated r25 117 ; setup "current" tsk and optionally cache it in dedicated r25
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index cf18b3e5a934..c0d0124de089 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -95,7 +95,7 @@ void arc_init_IRQ(void)
95 95
96 /* setup status32, don't enable intr yet as kernel doesn't want */ 96 /* setup status32, don't enable intr yet as kernel doesn't want */
97 tmp = read_aux_reg(ARC_REG_STATUS32); 97 tmp = read_aux_reg(ARC_REG_STATUS32);
98 tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1); 98 tmp |= ARCV2_IRQ_DEF_PRIO << 1;
99 tmp &= ~STATUS_IE_MASK; 99 tmp &= ~STATUS_IE_MASK;
100 asm volatile("kflag %0 \n"::"r"(tmp)); 100 asm volatile("kflag %0 \n"::"r"(tmp));
101} 101}
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 7b2340996cf8..a9c88b7e9182 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -36,6 +36,7 @@ unsigned int intr_to_DE_cnt;
36 36
37/* Part of U-boot ABI: see head.S */ 37/* Part of U-boot ABI: see head.S */
38int __initdata uboot_tag; 38int __initdata uboot_tag;
39int __initdata uboot_magic;
39char __initdata *uboot_arg; 40char __initdata *uboot_arg;
40 41
41const struct machine_desc *machine_desc; 42const struct machine_desc *machine_desc;
@@ -44,29 +45,24 @@ struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
44 45
45struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; 46struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
46 47
47static const struct id_to_str arc_cpu_rel[] = { 48static const struct id_to_str arc_legacy_rel[] = {
49 /* ID.ARCVER, Release */
48#ifdef CONFIG_ISA_ARCOMPACT 50#ifdef CONFIG_ISA_ARCOMPACT
49 { 0x34, "R4.10"}, 51 { 0x34, "R4.10"},
50 { 0x35, "R4.11"}, 52 { 0x35, "R4.11"},
51#else 53#else
52 { 0x51, "R2.0" }, 54 { 0x51, "R2.0" },
53 { 0x52, "R2.1" }, 55 { 0x52, "R2.1" },
54 { 0x53, "R3.0" }, 56 { 0x53, "R3.0" },
55 { 0x54, "R3.10a" },
56#endif 57#endif
57 { 0x00, NULL } 58 { 0x00, NULL }
58}; 59};
59 60
60static const struct id_to_str arc_cpu_nm[] = { 61static const struct id_to_str arc_cpu_rel[] = {
61#ifdef CONFIG_ISA_ARCOMPACT 62 /* UARCH.MAJOR, Release */
62 { 0x20, "ARC 600" }, 63 { 0, "R3.10a"},
63 { 0x30, "ARC 770" }, /* 750 identified seperately */ 64 { 1, "R3.50a"},
64#else 65 { 0xFF, NULL }
65 { 0x40, "ARC EM" },
66 { 0x50, "ARC HS38" },
67 { 0x54, "ARC HS48" },
68#endif
69 { 0x00, "Unknown" }
70}; 66};
71 67
72static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) 68static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
@@ -116,31 +112,72 @@ static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
116 } 112 }
117} 113}
118 114
115static void decode_arc_core(struct cpuinfo_arc *cpu)
116{
117 struct bcr_uarch_build_arcv2 uarch;
118 const struct id_to_str *tbl;
119
120 /*
121 * Up until (including) the first core4 release (0x54) things were
122 * simple: AUX IDENTITY.ARCVER was sufficient to identify arc family
123 * and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue)
124 */
125
126 if (cpu->core.family < 0x54) { /* includes arc700 */
127
128 for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
129 if (cpu->core.family == tbl->id) {
130 cpu->release = tbl->str;
131 break;
132 }
133 }
134
135 if (is_isa_arcompact())
136 cpu->name = "ARC700";
137 else if (tbl->str)
138 cpu->name = "HS38";
139 else
140 cpu->name = cpu->release = "Unknown";
141
142 return;
143 }
144
145 /*
146 * However the subsequent HS release (same 0x54) allow HS38 or HS48
147 * configurations and encode this info in a different BCR.
148 * The BCR was introduced in 0x54 so can't be read unconditionally.
149 */
150
151 READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
152
153 if (uarch.prod == 4) {
154 cpu->name = "HS48";
155 cpu->extn.dual = 1;
156
157 } else {
158 cpu->name = "HS38";
159 }
160
161 for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) {
162 if (uarch.maj == tbl->id) {
163 cpu->release = tbl->str;
164 break;
165 }
166 }
167}
168
119static void read_arc_build_cfg_regs(void) 169static void read_arc_build_cfg_regs(void)
120{ 170{
121 struct bcr_timer timer; 171 struct bcr_timer timer;
122 struct bcr_generic bcr; 172 struct bcr_generic bcr;
123 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 173 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
124 const struct id_to_str *tbl;
125 struct bcr_isa_arcv2 isa; 174 struct bcr_isa_arcv2 isa;
126 struct bcr_actionpoint ap; 175 struct bcr_actionpoint ap;
127 176
128 FIX_PTR(cpu); 177 FIX_PTR(cpu);
129 178
130 READ_BCR(AUX_IDENTITY, cpu->core); 179 READ_BCR(AUX_IDENTITY, cpu->core);
131 180 decode_arc_core(cpu);
132 for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
133 if (cpu->core.family == tbl->id) {
134 cpu->details = tbl->str;
135 break;
136 }
137 }
138
139 for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
140 if ((cpu->core.family & 0xF4) == tbl->id)
141 break;
142 }
143 cpu->name = tbl->str;
144 181
145 READ_BCR(ARC_REG_TIMERS_BCR, timer); 182 READ_BCR(ARC_REG_TIMERS_BCR, timer);
146 cpu->extn.timer0 = timer.t0; 183 cpu->extn.timer0 = timer.t0;
@@ -151,16 +188,6 @@ static void read_arc_build_cfg_regs(void)
151 188
152 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); 189 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
153 190
154 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */
155 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */
156 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */
157 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
158 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
159 cpu->extn.swape = (cpu->core.family >= 0x34) ? 1 :
160 IS_ENABLED(CONFIG_ARC_HAS_SWAPE);
161
162 READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
163
164 /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ 191 /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
165 read_decode_ccm_bcr(cpu); 192 read_decode_ccm_bcr(cpu);
166 193
@@ -198,30 +225,12 @@ static void read_arc_build_cfg_regs(void)
198 cpu->bpu.num_pred = 2048 << bpu.pte; 225 cpu->bpu.num_pred = 2048 << bpu.pte;
199 cpu->bpu.ret_stk = 4 << bpu.rse; 226 cpu->bpu.ret_stk = 4 << bpu.rse;
200 227
201 if (cpu->core.family >= 0x54) { 228 /* if dual issue hardware, is it enabled ? */
202 229 if (cpu->extn.dual) {
203 struct bcr_uarch_build_arcv2 uarch; 230 unsigned int exec_ctrl;
204
205 /*
206 * The first 0x54 core (uarch maj:min 0:1 or 0:2) was
207 * dual issue only (HS4x). But next uarch rev (1:0)
208 * allows it be configured for single issue (HS3x)
209 * Ensure we fiddle with dual issue only on HS4x
210 */
211 READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
212
213 if (uarch.prod == 4) {
214 unsigned int exec_ctrl;
215
216 /* dual issue hardware always present */
217 cpu->extn.dual = 1;
218
219 READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
220 231
221 /* dual issue hardware enabled ? */ 232 READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
222 cpu->extn.dual_enb = !(exec_ctrl & 1); 233 cpu->extn.dual_enb = !(exec_ctrl & 1);
223
224 }
225 } 234 }
226 } 235 }
227 236
@@ -263,7 +272,8 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
263{ 272{
264 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 273 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
265 struct bcr_identity *core = &cpu->core; 274 struct bcr_identity *core = &cpu->core;
266 int i, n = 0, ua = 0; 275 char mpy_opt[16];
276 int n = 0;
267 277
268 FIX_PTR(cpu); 278 FIX_PTR(cpu);
269 279
@@ -272,7 +282,7 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
272 core->family, core->cpu_id, core->chip_id); 282 core->family, core->cpu_id, core->chip_id);
273 283
274 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n", 284 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
275 cpu_id, cpu->name, cpu->details, 285 cpu_id, cpu->name, cpu->release,
276 is_isa_arcompact() ? "ARCompact" : "ARCv2", 286 is_isa_arcompact() ? "ARCompact" : "ARCv2",
277 IS_AVAIL1(cpu->isa.be, "[Big-Endian]"), 287 IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
278 IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue ")); 288 IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));
@@ -283,61 +293,50 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
283 IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), 293 IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
284 IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT)); 294 IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT));
285 295
286#ifdef __ARC_UNALIGNED__
287 ua = 1;
288#endif
289 n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s%s",
290 IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
291 IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
292 IS_AVAIL1(cpu->isa.unalign, "unalign "), IS_USED_RUN(ua));
293
294 if (i)
295 n += scnprintf(buf + n, len - n, "\n\t\t: ");
296
297 if (cpu->extn_mpy.ver) { 296 if (cpu->extn_mpy.ver) {
298 if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */ 297 if (is_isa_arcompact()) {
299 n += scnprintf(buf + n, len - n, "mpy "); 298 scnprintf(mpy_opt, 16, "mpy");
300 } else { 299 } else {
300
301 int opt = 2; /* stock MPY/MPYH */ 301 int opt = 2; /* stock MPY/MPYH */
302 302
303 if (cpu->extn_mpy.dsp) /* OPT 7-9 */ 303 if (cpu->extn_mpy.dsp) /* OPT 7-9 */
304 opt = cpu->extn_mpy.dsp + 6; 304 opt = cpu->extn_mpy.dsp + 6;
305 305
306 n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt); 306 scnprintf(mpy_opt, 16, "mpy[opt %d] ", opt);
307 } 307 }
308 } 308 }
309 309
310 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", 310 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
311 IS_AVAIL1(cpu->isa.div_rem, "div_rem "), 311 IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
312 IS_AVAIL1(cpu->extn.norm, "norm "), 312 IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
313 IS_AVAIL1(cpu->extn.barrel, "barrel-shift "), 313 IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS),
314 IS_AVAIL1(cpu->extn.swap, "swap "), 314 IS_AVAIL1(cpu->extn_mpy.ver, mpy_opt),
315 IS_AVAIL1(cpu->extn.minmax, "minmax "), 315 IS_AVAIL1(cpu->isa.div_rem, "div_rem "));
316 IS_AVAIL1(cpu->extn.crc, "crc "), 316
317 IS_AVAIL2(cpu->extn.swape, "swape", CONFIG_ARC_HAS_SWAPE)); 317 if (cpu->bpu.ver) {
318
319 if (cpu->bpu.ver)
320 n += scnprintf(buf + n, len - n, 318 n += scnprintf(buf + n, len - n,
321 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d", 319 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d",
322 IS_AVAIL1(cpu->bpu.full, "full"), 320 IS_AVAIL1(cpu->bpu.full, "full"),
323 IS_AVAIL1(!cpu->bpu.full, "partial"), 321 IS_AVAIL1(!cpu->bpu.full, "partial"),
324 cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk); 322 cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk);
325 323
326 if (is_isa_arcv2()) { 324 if (is_isa_arcv2()) {
327 struct bcr_lpb lpb; 325 struct bcr_lpb lpb;
328 326
329 READ_BCR(ARC_REG_LPB_BUILD, lpb); 327 READ_BCR(ARC_REG_LPB_BUILD, lpb);
330 if (lpb.ver) { 328 if (lpb.ver) {
331 unsigned int ctl; 329 unsigned int ctl;
332 ctl = read_aux_reg(ARC_REG_LPB_CTRL); 330 ctl = read_aux_reg(ARC_REG_LPB_CTRL);
333 331
334 n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s", 332 n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
335 lpb.entries, 333 lpb.entries,
336 IS_DISABLED_RUN(!ctl)); 334 IS_DISABLED_RUN(!ctl));
335 }
337 } 336 }
337 n += scnprintf(buf + n, len - n, "\n");
338 } 338 }
339 339
340 n += scnprintf(buf + n, len - n, "\n");
341 return buf; 340 return buf;
342} 341}
343 342
@@ -390,11 +389,6 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
390 } 389 }
391 } 390 }
392 391
393 n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n",
394 EF_ARC_OSABI_CURRENT >> 8,
395 EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ?
396 "no-legacy-syscalls" : "64-bit data any register aligned");
397
398 return buf; 392 return buf;
399} 393}
400 394
@@ -497,6 +491,8 @@ static inline bool uboot_arg_invalid(unsigned long addr)
497#define UBOOT_TAG_NONE 0 491#define UBOOT_TAG_NONE 0
498#define UBOOT_TAG_CMDLINE 1 492#define UBOOT_TAG_CMDLINE 1
499#define UBOOT_TAG_DTB 2 493#define UBOOT_TAG_DTB 2
494/* We always pass 0 as magic from U-boot */
495#define UBOOT_MAGIC_VALUE 0
500 496
501void __init handle_uboot_args(void) 497void __init handle_uboot_args(void)
502{ 498{
@@ -511,6 +507,11 @@ void __init handle_uboot_args(void)
511 goto ignore_uboot_args; 507 goto ignore_uboot_args;
512 } 508 }
513 509
510 if (uboot_magic != UBOOT_MAGIC_VALUE) {
511 pr_warn(IGNORE_ARGS "non zero uboot magic\n");
512 goto ignore_uboot_args;
513 }
514
514 if (uboot_tag != UBOOT_TAG_NONE && 515 if (uboot_tag != UBOOT_TAG_NONE &&
515 uboot_arg_invalid((unsigned long)uboot_arg)) { 516 uboot_arg_invalid((unsigned long)uboot_arg)) {
516 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg); 517 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg);
diff --git a/arch/arc/kernel/troubleshoot.c b/arch/arc/kernel/troubleshoot.c
index 215f515442e0..b0aa8c028331 100644
--- a/arch/arc/kernel/troubleshoot.c
+++ b/arch/arc/kernel/troubleshoot.c
@@ -145,7 +145,8 @@ static void show_ecr_verbose(struct pt_regs *regs)
145 } else if (vec == ECR_V_PROTV) { 145 } else if (vec == ECR_V_PROTV) {
146 if (cause_code == ECR_C_PROTV_INST_FETCH) 146 if (cause_code == ECR_C_PROTV_INST_FETCH)
147 pr_cont("Execute from Non-exec Page\n"); 147 pr_cont("Execute from Non-exec Page\n");
148 else if (cause_code == ECR_C_PROTV_MISALIG_DATA) 148 else if (cause_code == ECR_C_PROTV_MISALIG_DATA &&
149 IS_ENABLED(CONFIG_ISA_ARCOMPACT))
149 pr_cont("Misaligned r/w from 0x%08lx\n", address); 150 pr_cont("Misaligned r/w from 0x%08lx\n", address);
150 else 151 else
151 pr_cont("%s access not allowed on page\n", 152 pr_cont("%s access not allowed on page\n",
@@ -161,6 +162,8 @@ static void show_ecr_verbose(struct pt_regs *regs)
161 pr_cont("Bus Error from Data Mem\n"); 162 pr_cont("Bus Error from Data Mem\n");
162 else 163 else
163 pr_cont("Bus Error, check PRM\n"); 164 pr_cont("Bus Error, check PRM\n");
165 } else if (vec == ECR_V_MISALIGN) {
166 pr_cont("Misaligned r/w from 0x%08lx\n", address);
164#endif 167#endif
165 } else if (vec == ECR_V_TRAP) { 168 } else if (vec == ECR_V_TRAP) {
166 if (regs->ecr_param == 5) 169 if (regs->ecr_param == 5)
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
index b1656d156097..f7537b466b23 100644
--- a/arch/arc/lib/Makefile
+++ b/arch/arc/lib/Makefile
@@ -8,4 +8,10 @@
8lib-y := strchr-700.o strcpy-700.o strlen.o memcmp.o 8lib-y := strchr-700.o strcpy-700.o strlen.o memcmp.o
9 9
10lib-$(CONFIG_ISA_ARCOMPACT) += memcpy-700.o memset.o strcmp.o 10lib-$(CONFIG_ISA_ARCOMPACT) += memcpy-700.o memset.o strcmp.o
11lib-$(CONFIG_ISA_ARCV2) += memcpy-archs.o memset-archs.o strcmp-archs.o 11lib-$(CONFIG_ISA_ARCV2) += memset-archs.o strcmp-archs.o
12
13ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
14lib-$(CONFIG_ISA_ARCV2) +=memcpy-archs-unaligned.o
15else
16lib-$(CONFIG_ISA_ARCV2) +=memcpy-archs.o
17endif
diff --git a/arch/arc/lib/memcpy-archs-unaligned.S b/arch/arc/lib/memcpy-archs-unaligned.S
new file mode 100644
index 000000000000..28993a73fdde
--- /dev/null
+++ b/arch/arc/lib/memcpy-archs-unaligned.S
@@ -0,0 +1,47 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * ARCv2 memcpy implementation optimized for unaligned memory access using.
4 *
5 * Copyright (C) 2019 Synopsys
6 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
7 */
8
9#include <linux/linkage.h>
10
11#ifdef CONFIG_ARC_HAS_LL64
12# define LOADX(DST,RX) ldd.ab DST, [RX, 8]
13# define STOREX(SRC,RX) std.ab SRC, [RX, 8]
14# define ZOLSHFT 5
15# define ZOLAND 0x1F
16#else
17# define LOADX(DST,RX) ld.ab DST, [RX, 4]
18# define STOREX(SRC,RX) st.ab SRC, [RX, 4]
19# define ZOLSHFT 4
20# define ZOLAND 0xF
21#endif
22
23ENTRY_CFI(memcpy)
24 mov r3, r0 ; don;t clobber ret val
25
26 lsr.f lp_count, r2, ZOLSHFT
27 lpnz @.Lcopy32_64bytes
28 ;; LOOP START
29 LOADX (r6, r1)
30 LOADX (r8, r1)
31 LOADX (r10, r1)
32 LOADX (r4, r1)
33 STOREX (r6, r3)
34 STOREX (r8, r3)
35 STOREX (r10, r3)
36 STOREX (r4, r3)
37.Lcopy32_64bytes:
38
39 and.f lp_count, r2, ZOLAND ;Last remaining 31 bytes
40 lpnz @.Lcopyremainingbytes
41 ;; LOOP START
42 ldb.ab r5, [r1, 1]
43 stb.ab r5, [r3, 1]
44.Lcopyremainingbytes:
45
46 j [blink]
47END_CFI(memcpy)
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 8eff057efcae..2eaecfb063a7 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -26,8 +26,8 @@ config EZNPS_MTM_EXT
26 help 26 help
27 Here we add new hierarchy for CPUs topology. 27 Here we add new hierarchy for CPUs topology.
28 We got: 28 We got:
29 Core 29 Core
30 Thread 30 Thread
31 At the new thread level each CPU represent one HW thread. 31 At the new thread level each CPU represent one HW thread.
32 At highest hierarchy each core contain 16 threads, 32 At highest hierarchy each core contain 16 threads,
33 any of them seem like CPU from Linux point of view. 33 any of them seem like CPU from Linux point of view.
@@ -35,10 +35,10 @@ config EZNPS_MTM_EXT
35 core and HW scheduler round robin between them. 35 core and HW scheduler round robin between them.
36 36
37config EZNPS_MEM_ERROR_ALIGN 37config EZNPS_MEM_ERROR_ALIGN
38 bool "ARC-EZchip Memory error as an exception" 38 bool "ARC-EZchip Memory error as an exception"
39 depends on EZNPS_MTM_EXT 39 depends on EZNPS_MTM_EXT
40 default n 40 default n
41 help 41 help
42 On the real chip of the NPS, user memory errors are handled 42 On the real chip of the NPS, user memory errors are handled
43 as a machine check exception, which is fatal, whereas on 43 as a machine check exception, which is fatal, whereas on
44 simulator platform for NPS, is handled as a Level 2 interrupt 44 simulator platform for NPS, is handled as a Level 2 interrupt
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 08:53:14 -0400