Merge tag 'for-v3.13/cm-scm-cleanup-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.13/cm-scm-cleanup

Move some of the OMAP2+ CM and System Control Module direct
register accesses into CM- and System Control
Module-specific "drivers" underneath arch/arm/mach-omap2/.  This
is a prerequisite for moving this code out of arch/arm/mach-omap2/ into
drivers/.

Basic test logs are available here:

http://www.pwsan.com/omap/testlogs/cm_scm_cleanup_a_v3.13/20131019101809/

14 files changed, 177 insertions, 98 deletions

diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 25b1feed480d..c78e893eba7d 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -52,7 +52,7 @@ static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
 
         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 
-        r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        r = omap2xxx_cm_get_pll_status();
 
         return ((r & apll_mask) == apll_mask) ? true : false;
 }
@@ -126,7 +126,7 @@ u32 omap2xxx_get_apll_clkin(void)
 {
         u32 aplls, srate = 0;
 
-        aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+        aplls = omap2xxx_cm_get_pll_config();
         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index d8620105c42a..3ff32543493c 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -60,8 +60,7 @@ unsigned long omap2xxx_clk_get_core_rate(void)
 
         core_clk = omap2_get_dpll_rate(dpll_core_ck);
 
-        v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        v &= OMAP24XX_CORE_CLK_SRC_MASK;
+        v = omap2xxx_cm_get_core_clk_src();
 
         if (v == CORE_CLK_SRC_32K)
                 core_clk = 32768;
@@ -79,8 +78,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
 {
         u32 high, low, core_clk_src;
 
-        core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+        core_clk_src = omap2xxx_cm_get_core_clk_src();
 
         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
                 high = curr_prcm_set->dpll_speed * 2;
@@ -120,8 +118,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
         const struct dpll_data *dd;
 
         cur_rate = omap2xxx_clk_get_core_rate();
-        mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
+        mult = omap2xxx_cm_get_core_clk_src();
 
         if ((rate == (cur_rate / 2)) && (mult == 2)) {
                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
@@ -145,7 +142,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
                                            dd->div1_mask);
                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-                tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+                tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config();
                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
                 if (rate > low) {
                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index ae2b35e76dc8..b935ed2922d8 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -98,7 +98,7 @@ long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
 int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
                             unsigned long parent_rate)
 {
-        u32 cur_rate, done_rate, bypass = 0, tmp;
+        u32 cur_rate, done_rate, bypass = 0;
         const struct prcm_config *prcm;
         unsigned long found_speed = 0;
         unsigned long flags;
@@ -141,23 +141,11 @@ int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
                 else
                         done_rate = CORE_CLK_SRC_DPLL;
 
-                /* MPU divider */
-                omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
-
-                /* dsp + iva1 div(2420), iva2.1(2430) */
-                omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
-                                 OMAP24XX_DSP_MOD, CM_CLKSEL);
-
-                omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
-
-                /* Major subsystem dividers */
-                tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
-                omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
-                                 CM_CLKSEL1);
-
-                if (cpu_is_omap2430())
-                        omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
-                                         OMAP2430_MDM_MOD, CM_CLKSEL);
+                omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu,
+                                             prcm->cm_clksel_dsp,
+                                             prcm->cm_clksel_gfx,
+                                             prcm->cm_clksel1_core,
+                                             prcm->cm_clksel_mdm);
 
                 /* x2 to enter omap2xxx_sdrc_init_params() */
                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca96c840..c7c5d31e9082 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -543,6 +543,44 @@ int omap2_clk_disable_autoidle_all(void)
 }
 
 /**
+ * omap2_clk_deny_idle - disable autoidle on an OMAP clock
+ * @clk: struct clk * to disable autoidle for
+ *
+ * Disable autoidle on an OMAP clock.
+ */
+int omap2_clk_deny_idle(struct clk *clk)
+{
+        struct clk_hw_omap *c;
+
+        if (__clk_get_flags(clk) & CLK_IS_BASIC)
+                return -EINVAL;
+
+        c = to_clk_hw_omap(__clk_get_hw(clk));
+        if (c->ops && c->ops->deny_idle)
+                c->ops->deny_idle(c);
+        return 0;
+}
+
+/**
+ * omap2_clk_allow_idle - enable autoidle on an OMAP clock
+ * @clk: struct clk * to enable autoidle for
+ *
+ * Enable autoidle on an OMAP clock.
+ */
+int omap2_clk_allow_idle(struct clk *clk)
+{
+        struct clk_hw_omap *c;
+
+        if (__clk_get_flags(clk) & CLK_IS_BASIC)
+                return -EINVAL;
+
+        c = to_clk_hw_omap(__clk_get_hw(clk));
+        if (c->ops && c->ops->allow_idle)
+                c->ops->allow_idle(c);
+        return 0;
+}
+
+/**
  * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
  * @clk_names: ptr to an array of strings of clock names to enable
  * @num_clocks: number of clock names in @clk_names
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd292f9..82916cc82c92 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -411,6 +411,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap2_clk_enable_autoidle_all(void);
 int omap2_clk_disable_autoidle_all(void);
+int omap2_clk_allow_idle(struct clk *clk);
+int omap2_clk_deny_idle(struct clk *clk);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 6774a53a3874..ce25abbcffae 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -327,6 +327,73 @@ struct clkdm_ops omap2_clkdm_operations = {
         .clkdm_clk_disable      = omap2xxx_clkdm_clk_disable,
 };
 
+int omap2xxx_cm_fclks_active(void)
+{
+        u32 f1, f2;
+
+        f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+
+        return (f1 | f2) ? 1 : 0;
+}
+
+int omap2xxx_cm_mpu_retention_allowed(void)
+{
+        u32 l;
+
+        /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
+        l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
+                 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
+                 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
+                return 0;
+        /* Check for UART3. */
+        l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+        if (l & OMAP24XX_EN_UART3_MASK)
+                return 0;
+
+        return 1;
+}
+
+u32 omap2xxx_cm_get_core_clk_src(void)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        v &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        return v;
+}
+
+u32 omap2xxx_cm_get_core_pll_config(void)
+{
+        return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+}
+
+u32 omap2xxx_cm_get_pll_config(void)
+{
+        return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+}
+
+u32 omap2xxx_cm_get_pll_status(void)
+{
+        return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+}
+
+void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
+{
+        u32 tmp;
+
+        omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
+        omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
+        omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
+        tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
+                OMAP24XX_CLKSEL_DSS2_MASK;
+        omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
+        if (cpu_is_omap2430())
+                omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
+}
+
 /*
  *
  */
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 4cbb39b051d2..891d81c3c8f4 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -62,6 +62,14 @@ extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
                                          u8 idlest_shift);
 extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
                                         s16 *prcm_inst, u8 *idlest_reg_id);
+extern int omap2xxx_cm_fclks_active(void);
+extern int omap2xxx_cm_mpu_retention_allowed(void);
+extern u32 omap2xxx_cm_get_core_clk_src(void);
+extern u32 omap2xxx_cm_get_core_pll_config(void);
+extern u32 omap2xxx_cm_get_pll_config(void);
+extern u32 omap2xxx_cm_get_pll_status(void);
+extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
+                                         u32 mdm);
 
 extern int __init omap2xxx_cm_init(void);
 
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 9061c307d915..f6f028867bfe 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -636,6 +636,28 @@ void omap3_cm_restore_context(void)
                                OMAP3_CM_CLKOUT_CTRL_OFFSET);
 }
 
+void omap3_cm_save_scratchpad_contents(u32 *ptr)
+{
+        *ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
+        *ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
+        *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+
+        /*
+         * As per erratum i671, ROM code does not respect the PER DPLL
+         * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
+         * Then,  in anycase, clear these bits to avoid extra latencies.
+         */
+        *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
+                ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
+        *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
+        *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
+        *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
+        *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
+        *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
+        *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
+        *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
+}
+
 /*
  *
  */
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index e8e146f4a43f..8224c91b4d7a 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -83,6 +83,7 @@ extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
 
 extern void omap3_cm_save_context(void);
 extern void omap3_cm_restore_context(void);
+extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
 
 extern int __init omap3xxx_cm_init(void);
 
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 31e0dfe4a4ea..44bb4d544dcf 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -46,17 +46,7 @@ struct omap3_scratchpad {
 struct omap3_scratchpad_prcm_block {
         u32 prm_clksrc_ctrl;
         u32 prm_clksel;
-        u32 cm_clksel_core;
-        u32 cm_clksel_wkup;
-        u32 cm_clken_pll;
-        u32 cm_autoidle_pll;
-        u32 cm_clksel1_pll;
-        u32 cm_clksel2_pll;
-        u32 cm_clksel3_pll;
-        u32 cm_clken_pll_mpu;
-        u32 cm_autoidle_pll_mpu;
-        u32 cm_clksel1_pll_mpu;
-        u32 cm_clksel2_pll_mpu;
+        u32 cm_contents[11];
         u32 prcm_block_size;
 };
 
@@ -347,34 +337,9 @@ void omap3_save_scratchpad_contents(void)
         prcm_block_contents.prm_clksel =
                 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
                                        OMAP3_PRM_CLKSEL_OFFSET);
-        prcm_block_contents.cm_clksel_core =
-                        omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
-        prcm_block_contents.cm_clksel_wkup =
-                        omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
-        prcm_block_contents.cm_clken_pll =
-                        omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-        /*
-         * As per erratum i671, ROM code does not respect the PER DPLL
-         * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
-         * Then,  in anycase, clear these bits to avoid extra latencies.
-         */
-        prcm_block_contents.cm_autoidle_pll =
-                        omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
-                        ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
-        prcm_block_contents.cm_clksel1_pll =
-                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
-        prcm_block_contents.cm_clksel2_pll =
-                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
-        prcm_block_contents.cm_clksel3_pll =
-                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
-        prcm_block_contents.cm_clken_pll_mpu =
-                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
-        prcm_block_contents.cm_autoidle_pll_mpu =
-                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
-        prcm_block_contents.cm_clksel1_pll_mpu =
-                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
-        prcm_block_contents.cm_clksel2_pll_mpu =
-                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
+
+        omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
+
         prcm_block_contents.prcm_block_size = 0x0;
 
         /* Populate the SDRC block contents */
@@ -604,4 +569,15 @@ int omap3_ctrl_save_padconf(void)
         return 0;
 }
 
+/**
+ * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
+ *
+ * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
+ * force disable IVA2 so that it does not prevent any low-power states.
+ */
+void omap3_ctrl_set_iva_bootmode_idle(void)
+{
+        omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
+                         OMAP343X_CONTROL_IVA2_BOOTMOD);
+}
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index f7d7c2ef1b40..da054801b114 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -427,6 +427,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
 extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
+extern void omap3_ctrl_set_iva_bootmode_idle(void);
 extern void omap2_set_globals_control(void __iomem *ctrl,
                                       void __iomem *ctrl_pad);
 #else
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 5d8768075dd9..b4ac3af1160c 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -25,6 +25,7 @@
 
 #include "soc.h"
 #include "omap_device.h"
+#include "clock.h"
 
 /*
  * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
@@ -33,22 +34,18 @@
 #include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
 
+static struct clk *mcbsp_iclks[5];
+
 static int omap3_enable_st_clock(unsigned int id, bool enable)
 {
-        unsigned int w;
-
         /*
          * Sidetone uses McBSP ICLK - which must not idle when sidetones
          * are enabled or sidetones start sounding ugly.
          */
-        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
         if (enable)
-                w &= ~(1 << (id - 2));
+                return omap2_clk_deny_idle(mcbsp_iclks[id]);
         else
-                w |= 1 << (id - 2);
-        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
-
-        return 0;
+                return omap2_clk_allow_idle(mcbsp_iclks[id]);
 }
 
 static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
@@ -58,6 +55,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
         struct omap_hwmod *oh_device[2];
         struct omap_mcbsp_platform_data *pdata = NULL;
         struct platform_device *pdev;
+        char clk_name[11];
 
         sscanf(oh->name, "mcbsp%d", &id);
 
@@ -99,6 +97,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                 oh_device[1] = omap_hwmod_lookup((
                 (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
                 pdata->enable_st_clock = omap3_enable_st_clock;
+                sprintf(clk_name, "mcbsp%d_ick", id);
+                mcbsp_iclks[id] = clk_get(NULL, clk_name);
                 count++;
         }
         pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index ce956b0a7ba4..8c0759496c8d 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -62,16 +62,6 @@ static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
 
 static struct clk *osc_ck, *emul_ck;
 
-static int omap2_fclks_active(void)
-{
-        u32 f1, f2;
-
-        f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-        f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-
-        return (f1 | f2) ? 1 : 0;
-}
-
 static int omap2_enter_full_retention(void)
 {
         u32 l;
@@ -142,17 +132,7 @@ static int sti_console_enabled;
 
 static int omap2_allow_mpu_retention(void)
 {
-        u32 l;
-
-        /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
-        l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-        if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
-                 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
-                 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
-                return 0;
-        /* Check for UART3. */
-        l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-        if (l & OMAP24XX_EN_UART3_MASK)
+        if (!omap2xxx_cm_mpu_retention_allowed())
                 return 0;
         if (sti_console_enabled)
                 return 0;
@@ -188,7 +168,7 @@ static void omap2_enter_mpu_retention(void)
 
 static int omap2_can_sleep(void)
 {
-        if (omap2_fclks_active())
+        if (omap2xxx_cm_fclks_active())
                 return 0;
         if (__clk_is_enabled(osc_ck))
                 return 0;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 5a2d8034c8de..93b80e5da8d4 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -430,8 +430,7 @@ static void __init omap3_iva_idle(void)
                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* Set IVA2 boot mode to 'idle' */
-        omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
-                         OMAP343X_CONTROL_IVA2_BOOTMOD);
+        omap3_ctrl_set_iva_bootmode_idle();
 
         /* Un-reset IVA2 */
         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);