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authorChris Wilson <chris@chris-wilson.co.uk>2016-11-07 06:01:28 -0500
committerJani Nikula <jani.nikula@intel.com>2016-11-07 12:02:35 -0500
commit54905ab5fe7aa453610e31cec640e528aaedb2e2 (patch)
tree3a91f27b980fd21a34d75ce6495d4b1b54eb265a
parentc4b8c570447a7bc171829532269878345b3ea9d0 (diff)
drm/i915: Limit Valleyview and earlier to only using mappable scanout
Valleyview appears to be limited to only scanning out from the first 512MiB of the Global GTT. Lets presume that this behaviour was inherited from the display block copied from g4x (not Ironlake) and all earlier generations are similarly affected, though testing suggests different symptoms. For simplicity, impose that these platforms must scanout from the mappable region. (For extra simplicity, use HAS_GMCH_DISPLAY even though this catches Cherryview which does not appear to be limited to the low aperture for its scanout.) v2: Use HAS_GMCH_DISPLAY() to more clearly convey my intent about limiting this workaround to the old style of display engine. v3: Update changelog to reflect testing by Ville Syrjälä v4: Include the changes to the comments as well Reported-by: Luis Botello <luis.botello.ortega@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98036 Fixes: 2efb813d5388 ("drm/i915: Fallback to using unmappable memory for scanout") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Akash Goel <akash.goel@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.9-rc1+ Link: http://patchwork.freedesktop.org/patch/msgid/20161107110128.28762-1-chris@chris-wilson.co.uk Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (cherry picked from commit 767a222e47cc13239d38018887f911fec06169ea) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c18
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 44b3f01faed3..91ab7e9d6d2e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3543,8 +3543,22 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3543 if (view->type == I915_GGTT_VIEW_NORMAL) 3543 if (view->type == I915_GGTT_VIEW_NORMAL)
3544 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, 3544 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3545 PIN_MAPPABLE | PIN_NONBLOCK); 3545 PIN_MAPPABLE | PIN_NONBLOCK);
3546 if (IS_ERR(vma)) 3546 if (IS_ERR(vma)) {
3547 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, 0); 3547 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3548 unsigned int flags;
3549
3550 /* Valleyview is definitely limited to scanning out the first
3551 * 512MiB. Lets presume this behaviour was inherited from the
3552 * g4x display engine and that all earlier gen are similarly
3553 * limited. Testing suggests that it is a little more
3554 * complicated than this. For example, Cherryview appears quite
3555 * happy to scanout from anywhere within its global aperture.
3556 */
3557 flags = 0;
3558 if (HAS_GMCH_DISPLAY(i915))
3559 flags = PIN_MAPPABLE;
3560 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3561 }
3548 if (IS_ERR(vma)) 3562 if (IS_ERR(vma))
3549 goto err_unpin_display; 3563 goto err_unpin_display;
3550 3564