arm64: dts: uniphier: Add USB2 PHY nodes

Add nodes of USB2 physical layer for UniPhier SoC. This supports LD11.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

1 files changed, 27 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index f72f2a317725..31ba52b14e99 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -454,6 +454,8 @@
                                  <&mio_clk 12>;
                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
                                  <&mio_rst 12>;
+                        phy-names = "usb";
+                        phys = <&usb_phy0>;
                         has-transaction-translator;
                 };
 
@@ -468,6 +470,8 @@
                                  <&mio_clk 13>;
                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
                                  <&mio_rst 13>;
+                        phy-names = "usb";
+                        phys = <&usb_phy1>;
                         has-transaction-translator;
                 };
 
@@ -482,6 +486,8 @@
                                  <&mio_clk 14>;
                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
                                  <&mio_rst 14>;
+                        phy-names = "usb";
+                        phys = <&usb_phy2>;
                         has-transaction-translator;
                 };
 
@@ -510,6 +516,27 @@
                         pinctrl: pinctrl {
                                 compatible = "socionext,uniphier-ld11-pinctrl";
                         };
+
+                        usb-phy {
+                                compatible = "socionext,uniphier-ld11-usb2-phy";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                usb_phy0: phy@0 {
+                                        reg = <0>;
+                                        #phy-cells = <0>;
+                                };
+
+                                usb_phy1: phy@1 {
+                                        reg = <1>;
+                                        #phy-cells = <0>;
+                                };
+
+                                usb_phy2: phy@2 {
+                                        reg = <2>;
+                                        #phy-cells = <0>;
+                                };
+                        };
                 };
 
                 soc-glue@5f900000 {