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authorLeo Liu <leo.liu@amd.com>2019-07-18 11:38:46 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-18 15:18:07 -0400
commit53ef3969ddb88a2ee0b69d37f60bd2b1f02f23c9 (patch)
tree6c15d99ea0fbeeaf25fe4495c659ace76885f5f8
parentb64d98656f0284cb88fa203541d4d0404b0e6c1a (diff)
drm/amdgpu: use VCN firmware offset for cache window
Since we are using the signed FW now, and also using PSP firmware loading, but it's still potential to break driver when loading FW directly instead of PSP, so we should add offset. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 31539e6a16b4..a022e47f2a1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -379,11 +379,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
379 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 379 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
380 upper_32_bits(adev->vcn.inst->gpu_addr)); 380 upper_32_bits(adev->vcn.inst->gpu_addr));
381 offset = size; 381 offset = size;
382 /* No signed header for now from firmware
383 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 382 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
384 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 383 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
385 */
386 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
387 } 384 }
388 385
389 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 386 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);