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authorBen Skeggs <bskeggs@redhat.com>2015-08-20 00:54:21 -0400
committerBen Skeggs <bskeggs@redhat.com>2015-08-27 22:40:45 -0400
commit53e60da43aee440d3f75000cdd269bd1324a8ad4 (patch)
treedebcc53c945ff6ffa4ca3f886a86387e7bfeec0c
parent437b2296ced574eada632b11346e22f6b0103e17 (diff)
drm/nouveau/falcon: convert to new-style nvkm_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h5
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h43
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h9
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h7
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h10
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c109
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c43
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c216
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c40
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c21
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c9
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c28
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/falcon.c114
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c32
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c52
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c49
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c53
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c43
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h11
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c31
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c50
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c49
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c43
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h9
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild3
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c31
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c51
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c49
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c53
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c43
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c43
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h11
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c43
36 files changed, 640 insertions, 771 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
index 43c18abd4034..d0ce89b5be3a 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
@@ -4,9 +4,8 @@
4 4
5void gt215_ce_intr(struct nvkm_falcon *, struct nvkm_fifo_chan *); 5void gt215_ce_intr(struct nvkm_falcon *, struct nvkm_fifo_chan *);
6 6
7extern struct nvkm_oclass gt215_ce_oclass; 7int gt215_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
8extern struct nvkm_oclass gf100_ce0_oclass; 8int gf100_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
9extern struct nvkm_oclass gf100_ce1_oclass;
10extern struct nvkm_oclass gk104_ce0_oclass; 9extern struct nvkm_oclass gk104_ce0_oclass;
11extern struct nvkm_oclass gk104_ce1_oclass; 10extern struct nvkm_oclass gk104_ce1_oclass;
12extern struct nvkm_oclass gk104_ce2_oclass; 11extern struct nvkm_oclass gk104_ce2_oclass;
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
index cd113fcbfccb..81c0bc66a9f8 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
@@ -4,13 +4,9 @@
4#include <core/engine.h> 4#include <core/engine.h>
5struct nvkm_fifo_chan; 5struct nvkm_fifo_chan;
6 6
7struct nvkm_falcon_data {
8 bool external;
9};
10
11struct nvkm_falcon { 7struct nvkm_falcon {
12 struct nvkm_engine engine;
13 const struct nvkm_falcon_func *func; 8 const struct nvkm_falcon_func *func;
9 struct nvkm_engine engine;
14 10
15 u32 addr; 11 u32 addr;
16 u8 version; 12 u8 version;
@@ -32,32 +28,21 @@ struct nvkm_falcon {
32 } data; 28 } data;
33}; 29};
34 30
31int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
32 int index, bool enable, u32 addr, struct nvkm_engine **);
33
35struct nvkm_falcon_func { 34struct nvkm_falcon_func {
35 struct {
36 u32 *data;
37 u32 size;
38 } code;
39 struct {
40 u32 *data;
41 u32 size;
42 } data;
43 u32 pmc_enable;
44 void (*init)(struct nvkm_falcon *);
36 void (*intr)(struct nvkm_falcon *, struct nvkm_fifo_chan *); 45 void (*intr)(struct nvkm_falcon *, struct nvkm_fifo_chan *);
37 struct nvkm_sclass sclass[]; 46 struct nvkm_sclass sclass[];
38}; 47};
39
40#define nv_falcon(priv) ((struct nvkm_falcon *)priv)
41
42#define nvkm_falcon_create(a,p,e,c,b,d,i,f,r) \
43 nvkm_falcon_create_((a), (p), (e), (c), (b), (d), (i), (f), \
44 sizeof(**r),(void **)r)
45#define nvkm_falcon_destroy(p) \
46 nvkm_engine_destroy(&(p)->engine)
47#define nvkm_falcon_init(p) ({ \
48 struct nvkm_falcon *_falcon = (p); \
49 _nvkm_falcon_init(nv_object(_falcon)); \
50})
51#define nvkm_falcon_fini(p,s) ({ \
52 struct nvkm_falcon *_falcon = (p); \
53 _nvkm_falcon_fini(nv_object(_falcon), (s)); \
54})
55
56int nvkm_falcon_create_(const struct nvkm_falcon_func *,
57 struct nvkm_object *, struct nvkm_object *,
58 struct nvkm_oclass *, u32, bool, const char *,
59 const char *, int, void **);
60#define _nvkm_falcon_dtor _nvkm_engine_dtor
61int _nvkm_falcon_init(struct nvkm_object *);
62int _nvkm_falcon_fini(struct nvkm_object *, bool);
63#endif 48#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
index 54b7672eed9c..08516ca82e04 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
@@ -1,7 +1,8 @@
1#ifndef __NVKM_MSPDEC_H__ 1#ifndef __NVKM_MSPDEC_H__
2#define __NVKM_MSPDEC_H__ 2#define __NVKM_MSPDEC_H__
3#include <core/engine.h> 3#include <engine/falcon.h>
4extern struct nvkm_oclass g98_mspdec_oclass; 4int g98_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
5extern struct nvkm_oclass gf100_mspdec_oclass; 5int gt215_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
6extern struct nvkm_oclass gk104_mspdec_oclass; 6int gf100_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
7int gk104_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
7#endif 8#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
index c6c69d0a8d01..85fd306021ac 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
@@ -1,6 +1,7 @@
1#ifndef __NVKM_MSPPP_H__ 1#ifndef __NVKM_MSPPP_H__
2#define __NVKM_MSPPP_H__ 2#define __NVKM_MSPPP_H__
3#include <core/engine.h> 3#include <engine/falcon.h>
4extern struct nvkm_oclass g98_msppp_oclass; 4int g98_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);
5extern struct nvkm_oclass gf100_msppp_oclass; 5int gt215_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);
6int gf100_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);
6#endif 7#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
index 1f193b7bd6c5..99757ed96f76 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
@@ -1,7 +1,9 @@
1#ifndef __NVKM_MSVLD_H__ 1#ifndef __NVKM_MSVLD_H__
2#define __NVKM_MSVLD_H__ 2#define __NVKM_MSVLD_H__
3#include <core/engine.h> 3#include <engine/falcon.h>
4extern struct nvkm_oclass g98_msvld_oclass; 4int g98_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
5extern struct nvkm_oclass gf100_msvld_oclass; 5int gt215_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
6extern struct nvkm_oclass gk104_msvld_oclass; 6int mcp89_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
7int gf100_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
8int gk104_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
7#endif 9#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
index 44590a2a479d..7317ef4c0207 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
@@ -1,5 +1,5 @@
1#ifndef __NVKM_SEC_H__ 1#ifndef __NVKM_SEC_H__
2#define __NVKM_SEC_H__ 2#define __NVKM_SEC_H__
3#include <core/engine.h> 3#include <engine/falcon.h>
4extern struct nvkm_oclass g98_sec_oclass; 4int g98_sec_new(struct nvkm_device *, int, struct nvkm_engine **);
5#endif 5#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
index 3abab3992e7c..e45c6d703c00 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
@@ -22,30 +22,26 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include <engine/ce.h> 24#include <engine/ce.h>
25#include <engine/falcon.h>
26#include "fuc/gf100.fuc3.h" 25#include "fuc/gf100.fuc3.h"
27 26
28#include <nvif/class.h> 27#include <nvif/class.h>
29 28
30static int 29static void
31gf100_ce_init(struct nvkm_object *object) 30gf100_ce_init(struct nvkm_falcon *ce)
32{ 31{
33 struct nvkm_falcon *ce = (void *)object;
34 struct nvkm_device *device = ce->engine.subdev.device; 32 struct nvkm_device *device = ce->engine.subdev.device;
35 const int idx = nv_engidx(&ce->engine) - NVDEV_ENGINE_CE0; 33 const int index = ce->engine.subdev.index - NVDEV_ENGINE_CE0;
36 u32 base = idx * 0x1000; 34 nvkm_wr32(device, ce->addr + 0x084, index);
37 int ret;
38
39 ret = nvkm_falcon_init(ce);
40 if (ret)
41 return ret;
42
43 nvkm_wr32(device, 0x104084 + base, idx);
44 return 0;
45} 35}
46 36
47static const struct nvkm_falcon_func 37static const struct nvkm_falcon_func
48gf100_ce0_func = { 38gf100_ce0 = {
39 .code.data = gf100_ce_code,
40 .code.size = sizeof(gf100_ce_code),
41 .data.data = gf100_ce_data,
42 .data.size = sizeof(gf100_ce_data),
43 .pmc_enable = 0x00000040,
44 .init = gf100_ce_init,
49 .intr = gt215_ce_intr, 45 .intr = gt215_ce_intr,
50 .sclass = { 46 .sclass = {
51 { -1, -1, FERMI_DMA }, 47 { -1, -1, FERMI_DMA },
@@ -53,30 +49,14 @@ gf100_ce0_func = {
53 } 49 }
54}; 50};
55 51
56static int
57gf100_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
58 struct nvkm_oclass *oclass, void *data, u32 size,
59 struct nvkm_object **pobject)
60{
61 struct nvkm_falcon *ce;
62 int ret;
63
64 ret = nvkm_falcon_create(&gf100_ce0_func, parent, engine, oclass,
65 0x104000, true, "PCE0", "ce0", &ce);
66 *pobject = nv_object(ce);
67 if (ret)
68 return ret;
69
70 nv_subdev(ce)->unit = 0x00000040;
71 nv_falcon(ce)->code.data = gf100_ce_code;
72 nv_falcon(ce)->code.size = sizeof(gf100_ce_code);
73 nv_falcon(ce)->data.data = gf100_ce_data;
74 nv_falcon(ce)->data.size = sizeof(gf100_ce_data);
75 return 0;
76}
77
78static const struct nvkm_falcon_func 52static const struct nvkm_falcon_func
79gf100_ce1_func = { 53gf100_ce1 = {
54 .code.data = gf100_ce_code,
55 .code.size = sizeof(gf100_ce_code),
56 .data.data = gf100_ce_data,
57 .data.size = sizeof(gf100_ce_data),
58 .pmc_enable = 0x00000080,
59 .init = gf100_ce_init,
80 .intr = gt215_ce_intr, 60 .intr = gt215_ce_intr,
81 .sclass = { 61 .sclass = {
82 { -1, -1, FERMI_DECOMPRESS }, 62 { -1, -1, FERMI_DECOMPRESS },
@@ -84,46 +64,17 @@ gf100_ce1_func = {
84 } 64 }
85}; 65};
86 66
87static int 67int
88gf100_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 68gf100_ce_new(struct nvkm_device *device, int index,
89 struct nvkm_oclass *oclass, void *data, u32 size, 69 struct nvkm_engine **pengine)
90 struct nvkm_object **pobject)
91{ 70{
92 struct nvkm_falcon *ce; 71 if (index == NVDEV_ENGINE_CE0) {
93 int ret; 72 return nvkm_falcon_new_(&gf100_ce0, device, index, true,
94 73 0x104000, pengine);
95 ret = nvkm_falcon_create(&gf100_ce1_func, parent, engine, oclass, 74 } else
96 0x105000, true, "PCE1", "ce1", &ce); 75 if (index == NVDEV_ENGINE_CE1) {
97 *pobject = nv_object(ce); 76 return nvkm_falcon_new_(&gf100_ce1, device, index, true,
98 if (ret) 77 0x105000, pengine);
99 return ret; 78 }
100 79 return -ENODEV;
101 nv_subdev(ce)->unit = 0x00000080;
102 nv_falcon(ce)->code.data = gf100_ce_code;
103 nv_falcon(ce)->code.size = sizeof(gf100_ce_code);
104 nv_falcon(ce)->data.data = gf100_ce_data;
105 nv_falcon(ce)->data.size = sizeof(gf100_ce_data);
106 return 0;
107} 80}
108
109struct nvkm_oclass
110gf100_ce0_oclass = {
111 .handle = NV_ENGINE(CE0, 0xc0),
112 .ofuncs = &(struct nvkm_ofuncs) {
113 .ctor = gf100_ce0_ctor,
114 .dtor = _nvkm_falcon_dtor,
115 .init = gf100_ce_init,
116 .fini = _nvkm_falcon_fini,
117 },
118};
119
120struct nvkm_oclass
121gf100_ce1_oclass = {
122 .handle = NV_ENGINE(CE1, 0xc0),
123 .ofuncs = &(struct nvkm_ofuncs) {
124 .ctor = gf100_ce1_ctor,
125 .dtor = _nvkm_falcon_dtor,
126 .init = gf100_ce_init,
127 .fini = _nvkm_falcon_fini,
128 },
129};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
index 35e4d578b153..f8223d696598 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
@@ -61,7 +61,12 @@ gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan)
61} 61}
62 62
63static const struct nvkm_falcon_func 63static const struct nvkm_falcon_func
64gt215_ce_func = { 64gt215_ce = {
65 .code.data = gt215_ce_code,
66 .code.size = sizeof(gt215_ce_code),
67 .data.data = gt215_ce_data,
68 .data.size = sizeof(gt215_ce_data),
69 .pmc_enable = 0x00802000,
65 .intr = gt215_ce_intr, 70 .intr = gt215_ce_intr,
66 .sclass = { 71 .sclass = {
67 { -1, -1, GT212_DMA }, 72 { -1, -1, GT212_DMA },
@@ -69,36 +74,10 @@ gt215_ce_func = {
69 } 74 }
70}; 75};
71 76
72static int 77int
73gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 78gt215_ce_new(struct nvkm_device *device, int index,
74 struct nvkm_oclass *oclass, void *data, u32 size, 79 struct nvkm_engine **pengine)
75 struct nvkm_object **pobject)
76{ 80{
77 bool enable = (nv_device(parent)->chipset != 0xaf); 81 return nvkm_falcon_new_(&gt215_ce, device, index,
78 struct nvkm_falcon *ce; 82 (device->chipset != 0xaf), 0x104000, pengine);
79 int ret;
80
81 ret = nvkm_falcon_create(&gt215_ce_func, parent, engine, oclass,
82 0x104000, enable, "PCE0", "ce0", &ce);
83 *pobject = nv_object(ce);
84 if (ret)
85 return ret;
86
87 nv_subdev(ce)->unit = 0x00802000;
88 nv_falcon(ce)->code.data = gt215_ce_code;
89 nv_falcon(ce)->code.size = sizeof(gt215_ce_code);
90 nv_falcon(ce)->data.data = gt215_ce_data;
91 nv_falcon(ce)->data.size = sizeof(gt215_ce_data);
92 return 0;
93} 83}
94
95struct nvkm_oclass
96gt215_ce_oclass = {
97 .handle = NV_ENGINE(CE0, 0xa3),
98 .ofuncs = &(struct nvkm_ofuncs) {
99 .ctor = gt215_ce_ctor,
100 .dtor = _nvkm_falcon_dtor,
101 .init = _nvkm_falcon_init,
102 .fini = _nvkm_falcon_fini,
103 },
104};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 7f858efb2c44..0556316e27c8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -1056,10 +1056,10 @@ nv98_chipset = {
1056// .fifo = g84_fifo_new, 1056// .fifo = g84_fifo_new,
1057// .sw = nv50_sw_new, 1057// .sw = nv50_sw_new,
1058// .gr = nv50_gr_new, 1058// .gr = nv50_gr_new,
1059// .mspdec = g98_mspdec_new, 1059 .mspdec = g98_mspdec_new,
1060// .sec = g98_sec_new, 1060 .sec = g98_sec_new,
1061// .msvld = g98_msvld_new, 1061 .msvld = g98_msvld_new,
1062// .msppp = g98_msppp_new, 1062 .msppp = g98_msppp_new,
1063// .disp = g94_disp_new, 1063// .disp = g94_disp_new,
1064// .pm = g84_pm_new, 1064// .pm = g84_pm_new,
1065}; 1065};
@@ -1115,15 +1115,15 @@ nva3_chipset = {
1115 .therm = gt215_therm_new, 1115 .therm = gt215_therm_new,
1116 .timer = nv41_timer_new, 1116 .timer = nv41_timer_new,
1117 .volt = nv40_volt_new, 1117 .volt = nv40_volt_new,
1118// .ce[0] = gt215_ce_new, 1118 .ce[0] = gt215_ce_new,
1119// .disp = gt215_disp_new, 1119// .disp = gt215_disp_new,
1120// .dma = nv50_dma_new, 1120// .dma = nv50_dma_new,
1121// .fifo = g84_fifo_new, 1121// .fifo = g84_fifo_new,
1122// .gr = nv50_gr_new, 1122// .gr = nv50_gr_new,
1123// .mpeg = g84_mpeg_new, 1123// .mpeg = g84_mpeg_new,
1124// .mspdec = g98_mspdec_new, 1124 .mspdec = gt215_mspdec_new,
1125// .msppp = g98_msppp_new, 1125 .msppp = gt215_msppp_new,
1126// .msvld = g98_msvld_new, 1126 .msvld = gt215_msvld_new,
1127// .pm = gt215_pm_new, 1127// .pm = gt215_pm_new,
1128// .sw = nv50_sw_new, 1128// .sw = nv50_sw_new,
1129}; 1129};
@@ -1148,14 +1148,14 @@ nva5_chipset = {
1148 .therm = gt215_therm_new, 1148 .therm = gt215_therm_new,
1149 .timer = nv41_timer_new, 1149 .timer = nv41_timer_new,
1150 .volt = nv40_volt_new, 1150 .volt = nv40_volt_new,
1151// .ce[0] = gt215_ce_new, 1151 .ce[0] = gt215_ce_new,
1152// .disp = gt215_disp_new, 1152// .disp = gt215_disp_new,
1153// .dma = nv50_dma_new, 1153// .dma = nv50_dma_new,
1154// .fifo = g84_fifo_new, 1154// .fifo = g84_fifo_new,
1155// .gr = nv50_gr_new, 1155// .gr = nv50_gr_new,
1156// .mspdec = g98_mspdec_new, 1156 .mspdec = gt215_mspdec_new,
1157// .msppp = g98_msppp_new, 1157 .msppp = gt215_msppp_new,
1158// .msvld = g98_msvld_new, 1158 .msvld = gt215_msvld_new,
1159// .pm = gt215_pm_new, 1159// .pm = gt215_pm_new,
1160// .sw = nv50_sw_new, 1160// .sw = nv50_sw_new,
1161}; 1161};
@@ -1180,14 +1180,14 @@ nva8_chipset = {
1180 .therm = gt215_therm_new, 1180 .therm = gt215_therm_new,
1181 .timer = nv41_timer_new, 1181 .timer = nv41_timer_new,
1182 .volt = nv40_volt_new, 1182 .volt = nv40_volt_new,
1183// .ce[0] = gt215_ce_new, 1183 .ce[0] = gt215_ce_new,
1184// .disp = gt215_disp_new, 1184// .disp = gt215_disp_new,
1185// .dma = nv50_dma_new, 1185// .dma = nv50_dma_new,
1186// .fifo = g84_fifo_new, 1186// .fifo = g84_fifo_new,
1187// .gr = nv50_gr_new, 1187// .gr = nv50_gr_new,
1188// .mspdec = g98_mspdec_new, 1188 .mspdec = gt215_mspdec_new,
1189// .msppp = g98_msppp_new, 1189 .msppp = gt215_msppp_new,
1190// .msvld = g98_msvld_new, 1190 .msvld = gt215_msvld_new,
1191// .pm = gt215_pm_new, 1191// .pm = gt215_pm_new,
1192// .sw = nv50_sw_new, 1192// .sw = nv50_sw_new,
1193}; 1193};
@@ -1215,11 +1215,11 @@ nvaa_chipset = {
1215// .dma = nv50_dma_new, 1215// .dma = nv50_dma_new,
1216// .fifo = g84_fifo_new, 1216// .fifo = g84_fifo_new,
1217// .gr = nv50_gr_new, 1217// .gr = nv50_gr_new,
1218// .mspdec = g98_mspdec_new, 1218 .mspdec = g98_mspdec_new,
1219// .msppp = g98_msppp_new, 1219 .msppp = g98_msppp_new,
1220// .msvld = g98_msvld_new, 1220 .msvld = g98_msvld_new,
1221// .pm = g84_pm_new, 1221// .pm = g84_pm_new,
1222// .sec = g98_sec_new, 1222 .sec = g98_sec_new,
1223// .sw = nv50_sw_new, 1223// .sw = nv50_sw_new,
1224}; 1224};
1225 1225
@@ -1246,11 +1246,11 @@ nvac_chipset = {
1246// .dma = nv50_dma_new, 1246// .dma = nv50_dma_new,
1247// .fifo = g84_fifo_new, 1247// .fifo = g84_fifo_new,
1248// .gr = nv50_gr_new, 1248// .gr = nv50_gr_new,
1249// .mspdec = g98_mspdec_new, 1249 .mspdec = g98_mspdec_new,
1250// .msppp = g98_msppp_new, 1250 .msppp = g98_msppp_new,
1251// .msvld = g98_msvld_new, 1251 .msvld = g98_msvld_new,
1252// .pm = g84_pm_new, 1252// .pm = g84_pm_new,
1253// .sec = g98_sec_new, 1253 .sec = g98_sec_new,
1254// .sw = nv50_sw_new, 1254// .sw = nv50_sw_new,
1255}; 1255};
1256 1256
@@ -1274,14 +1274,14 @@ nvaf_chipset = {
1274 .therm = gt215_therm_new, 1274 .therm = gt215_therm_new,
1275 .timer = nv41_timer_new, 1275 .timer = nv41_timer_new,
1276 .volt = nv40_volt_new, 1276 .volt = nv40_volt_new,
1277// .ce[0] = gt215_ce_new, 1277 .ce[0] = gt215_ce_new,
1278// .disp = gt215_disp_new, 1278// .disp = gt215_disp_new,
1279// .dma = nv50_dma_new, 1279// .dma = nv50_dma_new,
1280// .fifo = g84_fifo_new, 1280// .fifo = g84_fifo_new,
1281// .gr = nv50_gr_new, 1281// .gr = nv50_gr_new,
1282// .mspdec = g98_mspdec_new, 1282 .mspdec = gt215_mspdec_new,
1283// .msppp = g98_msppp_new, 1283 .msppp = gt215_msppp_new,
1284// .msvld = g98_msvld_new, 1284 .msvld = mcp89_msvld_new,
1285// .pm = gt215_pm_new, 1285// .pm = gt215_pm_new,
1286// .sw = nv50_sw_new, 1286// .sw = nv50_sw_new,
1287}; 1287};
@@ -1308,15 +1308,15 @@ nvc0_chipset = {
1308 .therm = gt215_therm_new, 1308 .therm = gt215_therm_new,
1309 .timer = nv41_timer_new, 1309 .timer = nv41_timer_new,
1310 .volt = nv40_volt_new, 1310 .volt = nv40_volt_new,
1311// .ce[0] = gf100_ce0_new, 1311 .ce[0] = gf100_ce_new,
1312// .ce[1] = gf100_ce1_new, 1312 .ce[1] = gf100_ce_new,
1313// .disp = gt215_disp_new, 1313// .disp = gt215_disp_new,
1314// .dma = gf100_dma_new, 1314// .dma = gf100_dma_new,
1315// .fifo = gf100_fifo_new, 1315// .fifo = gf100_fifo_new,
1316// .gr = gf100_gr_new, 1316// .gr = gf100_gr_new,
1317// .mspdec = gf100_mspdec_new, 1317 .mspdec = gf100_mspdec_new,
1318// .msppp = gf100_msppp_new, 1318 .msppp = gf100_msppp_new,
1319// .msvld = gf100_msvld_new, 1319 .msvld = gf100_msvld_new,
1320// .pm = gf100_pm_new, 1320// .pm = gf100_pm_new,
1321// .sw = gf100_sw_new, 1321// .sw = gf100_sw_new,
1322}; 1322};
@@ -1343,14 +1343,14 @@ nvc1_chipset = {
1343 .therm = gt215_therm_new, 1343 .therm = gt215_therm_new,
1344 .timer = nv41_timer_new, 1344 .timer = nv41_timer_new,
1345 .volt = nv40_volt_new, 1345 .volt = nv40_volt_new,
1346// .ce[0] = gf100_ce0_new, 1346 .ce[0] = gf100_ce_new,
1347// .disp = gt215_disp_new, 1347// .disp = gt215_disp_new,
1348// .dma = gf100_dma_new, 1348// .dma = gf100_dma_new,
1349// .fifo = gf100_fifo_new, 1349// .fifo = gf100_fifo_new,
1350// .gr = gf108_gr_new, 1350// .gr = gf108_gr_new,
1351// .mspdec = gf100_mspdec_new, 1351 .mspdec = gf100_mspdec_new,
1352// .msppp = gf100_msppp_new, 1352 .msppp = gf100_msppp_new,
1353// .msvld = gf100_msvld_new, 1353 .msvld = gf100_msvld_new,
1354// .pm = gf108_pm_new, 1354// .pm = gf108_pm_new,
1355// .sw = gf100_sw_new, 1355// .sw = gf100_sw_new,
1356}; 1356};
@@ -1377,14 +1377,14 @@ nvc3_chipset = {
1377 .therm = gt215_therm_new, 1377 .therm = gt215_therm_new,
1378 .timer = nv41_timer_new, 1378 .timer = nv41_timer_new,
1379 .volt = nv40_volt_new, 1379 .volt = nv40_volt_new,
1380// .ce[0] = gf100_ce0_new, 1380 .ce[0] = gf100_ce_new,
1381// .disp = gt215_disp_new, 1381// .disp = gt215_disp_new,
1382// .dma = gf100_dma_new, 1382// .dma = gf100_dma_new,
1383// .fifo = gf100_fifo_new, 1383// .fifo = gf100_fifo_new,
1384// .gr = gf104_gr_new, 1384// .gr = gf104_gr_new,
1385// .mspdec = gf100_mspdec_new, 1385 .mspdec = gf100_mspdec_new,
1386// .msppp = gf100_msppp_new, 1386 .msppp = gf100_msppp_new,
1387// .msvld = gf100_msvld_new, 1387 .msvld = gf100_msvld_new,
1388// .pm = gf100_pm_new, 1388// .pm = gf100_pm_new,
1389// .sw = gf100_sw_new, 1389// .sw = gf100_sw_new,
1390}; 1390};
@@ -1411,15 +1411,15 @@ nvc4_chipset = {
1411 .therm = gt215_therm_new, 1411 .therm = gt215_therm_new,
1412 .timer = nv41_timer_new, 1412 .timer = nv41_timer_new,
1413 .volt = nv40_volt_new, 1413 .volt = nv40_volt_new,
1414// .ce[0] = gf100_ce0_new, 1414 .ce[0] = gf100_ce_new,
1415// .ce[1] = gf100_ce1_new, 1415 .ce[1] = gf100_ce_new,
1416// .disp = gt215_disp_new, 1416// .disp = gt215_disp_new,
1417// .dma = gf100_dma_new, 1417// .dma = gf100_dma_new,
1418// .fifo = gf100_fifo_new, 1418// .fifo = gf100_fifo_new,
1419// .gr = gf104_gr_new, 1419// .gr = gf104_gr_new,
1420// .mspdec = gf100_mspdec_new, 1420 .mspdec = gf100_mspdec_new,
1421// .msppp = gf100_msppp_new, 1421 .msppp = gf100_msppp_new,
1422// .msvld = gf100_msvld_new, 1422 .msvld = gf100_msvld_new,
1423// .pm = gf100_pm_new, 1423// .pm = gf100_pm_new,
1424// .sw = gf100_sw_new, 1424// .sw = gf100_sw_new,
1425}; 1425};
@@ -1446,15 +1446,15 @@ nvc8_chipset = {
1446 .therm = gt215_therm_new, 1446 .therm = gt215_therm_new,
1447 .timer = nv41_timer_new, 1447 .timer = nv41_timer_new,
1448 .volt = nv40_volt_new, 1448 .volt = nv40_volt_new,
1449// .ce[0] = gf100_ce0_new, 1449 .ce[0] = gf100_ce_new,
1450// .ce[1] = gf100_ce1_new, 1450 .ce[1] = gf100_ce_new,
1451// .disp = gt215_disp_new, 1451// .disp = gt215_disp_new,
1452// .dma = gf100_dma_new, 1452// .dma = gf100_dma_new,
1453// .fifo = gf100_fifo_new, 1453// .fifo = gf100_fifo_new,
1454// .gr = gf110_gr_new, 1454// .gr = gf110_gr_new,
1455// .mspdec = gf100_mspdec_new, 1455 .mspdec = gf100_mspdec_new,
1456// .msppp = gf100_msppp_new, 1456 .msppp = gf100_msppp_new,
1457// .msvld = gf100_msvld_new, 1457 .msvld = gf100_msvld_new,
1458// .pm = gf100_pm_new, 1458// .pm = gf100_pm_new,
1459// .sw = gf100_sw_new, 1459// .sw = gf100_sw_new,
1460}; 1460};
@@ -1481,15 +1481,15 @@ nvce_chipset = {
1481 .therm = gt215_therm_new, 1481 .therm = gt215_therm_new,
1482 .timer = nv41_timer_new, 1482 .timer = nv41_timer_new,
1483 .volt = nv40_volt_new, 1483 .volt = nv40_volt_new,
1484// .ce[0] = gf100_ce0_new, 1484 .ce[0] = gf100_ce_new,
1485// .ce[1] = gf100_ce1_new, 1485 .ce[1] = gf100_ce_new,
1486// .disp = gt215_disp_new, 1486// .disp = gt215_disp_new,
1487// .dma = gf100_dma_new, 1487// .dma = gf100_dma_new,
1488// .fifo = gf100_fifo_new, 1488// .fifo = gf100_fifo_new,
1489// .gr = gf104_gr_new, 1489// .gr = gf104_gr_new,
1490// .mspdec = gf100_mspdec_new, 1490 .mspdec = gf100_mspdec_new,
1491// .msppp = gf100_msppp_new, 1491 .msppp = gf100_msppp_new,
1492// .msvld = gf100_msvld_new, 1492 .msvld = gf100_msvld_new,
1493// .pm = gf100_pm_new, 1493// .pm = gf100_pm_new,
1494// .sw = gf100_sw_new, 1494// .sw = gf100_sw_new,
1495}; 1495};
@@ -1516,14 +1516,14 @@ nvcf_chipset = {
1516 .therm = gt215_therm_new, 1516 .therm = gt215_therm_new,
1517 .timer = nv41_timer_new, 1517 .timer = nv41_timer_new,
1518 .volt = nv40_volt_new, 1518 .volt = nv40_volt_new,
1519// .ce[0] = gf100_ce0_new, 1519 .ce[0] = gf100_ce_new,
1520// .disp = gt215_disp_new, 1520// .disp = gt215_disp_new,
1521// .dma = gf100_dma_new, 1521// .dma = gf100_dma_new,
1522// .fifo = gf100_fifo_new, 1522// .fifo = gf100_fifo_new,
1523// .gr = gf104_gr_new, 1523// .gr = gf104_gr_new,
1524// .mspdec = gf100_mspdec_new, 1524 .mspdec = gf100_mspdec_new,
1525// .msppp = gf100_msppp_new, 1525 .msppp = gf100_msppp_new,
1526// .msvld = gf100_msvld_new, 1526 .msvld = gf100_msvld_new,
1527// .pm = gf100_pm_new, 1527// .pm = gf100_pm_new,
1528// .sw = gf100_sw_new, 1528// .sw = gf100_sw_new,
1529}; 1529};
@@ -1548,14 +1548,14 @@ nvd7_chipset = {
1548 .mxm = nv50_mxm_new, 1548 .mxm = nv50_mxm_new,
1549 .therm = gf119_therm_new, 1549 .therm = gf119_therm_new,
1550 .timer = nv41_timer_new, 1550 .timer = nv41_timer_new,
1551// .ce[0] = gf100_ce0_new, 1551 .ce[0] = gf100_ce_new,
1552// .disp = gf119_disp_new, 1552// .disp = gf119_disp_new,
1553// .dma = gf119_dma_new, 1553// .dma = gf119_dma_new,
1554// .fifo = gf100_fifo_new, 1554// .fifo = gf100_fifo_new,
1555// .gr = gf117_gr_new, 1555// .gr = gf117_gr_new,
1556// .mspdec = gf100_mspdec_new, 1556 .mspdec = gf100_mspdec_new,
1557// .msppp = gf100_msppp_new, 1557 .msppp = gf100_msppp_new,
1558// .msvld = gf100_msvld_new, 1558 .msvld = gf100_msvld_new,
1559// .pm = gf117_pm_new, 1559// .pm = gf117_pm_new,
1560// .sw = gf100_sw_new, 1560// .sw = gf100_sw_new,
1561}; 1561};
@@ -1582,14 +1582,14 @@ nvd9_chipset = {
1582 .therm = gf119_therm_new, 1582 .therm = gf119_therm_new,
1583 .timer = nv41_timer_new, 1583 .timer = nv41_timer_new,
1584 .volt = nv40_volt_new, 1584 .volt = nv40_volt_new,
1585// .ce[0] = gf100_ce0_new, 1585 .ce[0] = gf100_ce_new,
1586// .disp = gf119_disp_new, 1586// .disp = gf119_disp_new,
1587// .dma = gf119_dma_new, 1587// .dma = gf119_dma_new,
1588// .fifo = gf100_fifo_new, 1588// .fifo = gf100_fifo_new,
1589// .gr = gf119_gr_new, 1589// .gr = gf119_gr_new,
1590// .mspdec = gf100_mspdec_new, 1590 .mspdec = gf100_mspdec_new,
1591// .msppp = gf100_msppp_new, 1591 .msppp = gf100_msppp_new,
1592// .msvld = gf100_msvld_new, 1592 .msvld = gf100_msvld_new,
1593// .pm = gf117_pm_new, 1593// .pm = gf117_pm_new,
1594// .sw = gf100_sw_new, 1594// .sw = gf100_sw_new,
1595}; 1595};
@@ -1616,16 +1616,16 @@ nve4_chipset = {
1616 .therm = gf119_therm_new, 1616 .therm = gf119_therm_new,
1617 .timer = nv41_timer_new, 1617 .timer = nv41_timer_new,
1618 .volt = nv40_volt_new, 1618 .volt = nv40_volt_new,
1619// .ce[0] = gk104_ce0_new, 1619// .ce[0] = gk104_ce_new,
1620// .ce[1] = gk104_ce1_new, 1620// .ce[1] = gk104_ce_new,
1621// .ce[2] = gk104_ce2_new, 1621// .ce[2] = gk104_ce2_new,
1622// .disp = gk104_disp_new, 1622// .disp = gk104_disp_new,
1623// .dma = gf119_dma_new, 1623// .dma = gf119_dma_new,
1624// .fifo = gk104_fifo_new, 1624// .fifo = gk104_fifo_new,
1625// .gr = gk104_gr_new, 1625// .gr = gk104_gr_new,
1626// .mspdec = gk104_mspdec_new, 1626 .mspdec = gk104_mspdec_new,
1627// .msppp = gf100_msppp_new, 1627 .msppp = gf100_msppp_new,
1628// .msvld = gk104_msvld_new, 1628 .msvld = gk104_msvld_new,
1629// .pm = gk104_pm_new, 1629// .pm = gk104_pm_new,
1630// .sw = gf100_sw_new, 1630// .sw = gf100_sw_new,
1631}; 1631};
@@ -1652,16 +1652,16 @@ nve6_chipset = {
1652 .therm = gf119_therm_new, 1652 .therm = gf119_therm_new,
1653 .timer = nv41_timer_new, 1653 .timer = nv41_timer_new,
1654 .volt = nv40_volt_new, 1654 .volt = nv40_volt_new,
1655// .ce[0] = gk104_ce0_new, 1655// .ce[0] = gk104_ce_new,
1656// .ce[1] = gk104_ce1_new, 1656// .ce[1] = gk104_ce_new,
1657// .ce[2] = gk104_ce2_new, 1657// .ce[2] = gk104_ce2_new,
1658// .disp = gk104_disp_new, 1658// .disp = gk104_disp_new,
1659// .dma = gf119_dma_new, 1659// .dma = gf119_dma_new,
1660// .fifo = gk104_fifo_new, 1660// .fifo = gk104_fifo_new,
1661// .gr = gk104_gr_new, 1661// .gr = gk104_gr_new,
1662// .mspdec = gk104_mspdec_new, 1662 .mspdec = gk104_mspdec_new,
1663// .msppp = gf100_msppp_new, 1663 .msppp = gf100_msppp_new,
1664// .msvld = gk104_msvld_new, 1664 .msvld = gk104_msvld_new,
1665// .pm = gk104_pm_new, 1665// .pm = gk104_pm_new,
1666// .sw = gf100_sw_new, 1666// .sw = gf100_sw_new,
1667}; 1667};
@@ -1688,16 +1688,16 @@ nve7_chipset = {
1688 .therm = gf119_therm_new, 1688 .therm = gf119_therm_new,
1689 .timer = nv41_timer_new, 1689 .timer = nv41_timer_new,
1690 .volt = nv40_volt_new, 1690 .volt = nv40_volt_new,
1691// .ce[0] = gk104_ce0_new, 1691// .ce[0] = gk104_ce_new,
1692// .ce[1] = gk104_ce1_new, 1692// .ce[1] = gk104_ce_new,
1693// .ce[2] = gk104_ce2_new, 1693// .ce[2] = gk104_ce2_new,
1694// .disp = gk104_disp_new, 1694// .disp = gk104_disp_new,
1695// .dma = gf119_dma_new, 1695// .dma = gf119_dma_new,
1696// .fifo = gk104_fifo_new, 1696// .fifo = gk104_fifo_new,
1697// .gr = gk104_gr_new, 1697// .gr = gk104_gr_new,
1698// .mspdec = gk104_mspdec_new, 1698 .mspdec = gk104_mspdec_new,
1699// .msppp = gf100_msppp_new, 1699 .msppp = gf100_msppp_new,
1700// .msvld = gk104_msvld_new, 1700 .msvld = gk104_msvld_new,
1701// .pm = gk104_pm_new, 1701// .pm = gk104_pm_new,
1702// .sw = gf100_sw_new, 1702// .sw = gf100_sw_new,
1703}; 1703};
@@ -1748,16 +1748,16 @@ nvf0_chipset = {
1748 .therm = gf119_therm_new, 1748 .therm = gf119_therm_new,
1749 .timer = nv41_timer_new, 1749 .timer = nv41_timer_new,
1750 .volt = nv40_volt_new, 1750 .volt = nv40_volt_new,
1751// .ce[0] = gk104_ce0_new, 1751// .ce[0] = gk104_ce_new,
1752// .ce[1] = gk104_ce1_new, 1752// .ce[1] = gk104_ce_new,
1753// .ce[2] = gk104_ce2_new, 1753// .ce[2] = gk104_ce2_new,
1754// .disp = gk110_disp_new, 1754// .disp = gk110_disp_new,
1755// .dma = gf119_dma_new, 1755// .dma = gf119_dma_new,
1756// .fifo = gk104_fifo_new, 1756// .fifo = gk104_fifo_new,
1757// .gr = gk110_gr_new, 1757// .gr = gk110_gr_new,
1758// .mspdec = gk104_mspdec_new, 1758 .mspdec = gk104_mspdec_new,
1759// .msppp = gf100_msppp_new, 1759 .msppp = gf100_msppp_new,
1760// .msvld = gk104_msvld_new, 1760 .msvld = gk104_msvld_new,
1761// .pm = gk110_pm_new, 1761// .pm = gk110_pm_new,
1762// .sw = gf100_sw_new, 1762// .sw = gf100_sw_new,
1763}; 1763};
@@ -1784,16 +1784,16 @@ nvf1_chipset = {
1784 .therm = gf119_therm_new, 1784 .therm = gf119_therm_new,
1785 .timer = nv41_timer_new, 1785 .timer = nv41_timer_new,
1786 .volt = nv40_volt_new, 1786 .volt = nv40_volt_new,
1787// .ce[0] = gk104_ce0_new, 1787// .ce[0] = gk104_ce_new,
1788// .ce[1] = gk104_ce1_new, 1788// .ce[1] = gk104_ce_new,
1789// .ce[2] = gk104_ce2_new, 1789// .ce[2] = gk104_ce2_new,
1790// .disp = gk110_disp_new, 1790// .disp = gk110_disp_new,
1791// .dma = gf119_dma_new, 1791// .dma = gf119_dma_new,
1792// .fifo = gk104_fifo_new, 1792// .fifo = gk104_fifo_new,
1793// .gr = gk110b_gr_new, 1793// .gr = gk110b_gr_new,
1794// .mspdec = gk104_mspdec_new, 1794 .mspdec = gk104_mspdec_new,
1795// .msppp = gf100_msppp_new, 1795 .msppp = gf100_msppp_new,
1796// .msvld = gk104_msvld_new, 1796 .msvld = gk104_msvld_new,
1797// .pm = gk110_pm_new, 1797// .pm = gk110_pm_new,
1798// .sw = gf100_sw_new, 1798// .sw = gf100_sw_new,
1799}; 1799};
@@ -1820,16 +1820,16 @@ nv106_chipset = {
1820 .therm = gf119_therm_new, 1820 .therm = gf119_therm_new,
1821 .timer = nv41_timer_new, 1821 .timer = nv41_timer_new,
1822 .volt = nv40_volt_new, 1822 .volt = nv40_volt_new,
1823// .ce[0] = gk104_ce0_new, 1823// .ce[0] = gk104_ce_new,
1824// .ce[1] = gk104_ce1_new, 1824// .ce[1] = gk104_ce_new,
1825// .ce[2] = gk104_ce2_new, 1825// .ce[2] = gk104_ce2_new,
1826// .disp = gk110_disp_new, 1826// .disp = gk110_disp_new,
1827// .dma = gf119_dma_new, 1827// .dma = gf119_dma_new,
1828// .fifo = gk208_fifo_new, 1828// .fifo = gk208_fifo_new,
1829// .gr = gk208_gr_new, 1829// .gr = gk208_gr_new,
1830// .mspdec = gk104_mspdec_new, 1830 .mspdec = gk104_mspdec_new,
1831// .msppp = gf100_msppp_new, 1831 .msppp = gf100_msppp_new,
1832// .msvld = gk104_msvld_new, 1832 .msvld = gk104_msvld_new,
1833// .sw = gf100_sw_new, 1833// .sw = gf100_sw_new,
1834}; 1834};
1835 1835
@@ -1855,16 +1855,16 @@ nv108_chipset = {
1855 .therm = gf119_therm_new, 1855 .therm = gf119_therm_new,
1856 .timer = nv41_timer_new, 1856 .timer = nv41_timer_new,
1857 .volt = nv40_volt_new, 1857 .volt = nv40_volt_new,
1858// .ce[0] = gk104_ce0_new, 1858// .ce[0] = gk104_ce_new,
1859// .ce[1] = gk104_ce1_new, 1859// .ce[1] = gk104_ce_new,
1860// .ce[2] = gk104_ce2_new, 1860// .ce[2] = gk104_ce2_new,
1861// .disp = gk110_disp_new, 1861// .disp = gk110_disp_new,
1862// .dma = gf119_dma_new, 1862// .dma = gf119_dma_new,
1863// .fifo = gk208_fifo_new, 1863// .fifo = gk208_fifo_new,
1864// .gr = gk208_gr_new, 1864// .gr = gk208_gr_new,
1865// .mspdec = gk104_mspdec_new, 1865 .mspdec = gk104_mspdec_new,
1866// .msppp = gf100_msppp_new, 1866 .msppp = gf100_msppp_new,
1867// .msvld = gk104_msvld_new, 1867 .msvld = gk104_msvld_new,
1868// .sw = gf100_sw_new, 1868// .sw = gf100_sw_new,
1869}; 1869};
1870 1870
@@ -1889,7 +1889,7 @@ nv117_chipset = {
1889 .pmu = gm107_pmu_new, 1889 .pmu = gm107_pmu_new,
1890 .therm = gm107_therm_new, 1890 .therm = gm107_therm_new,
1891 .timer = gk20a_timer_new, 1891 .timer = gk20a_timer_new,
1892// .ce[0] = gk104_ce0_new, 1892// .ce[0] = gk104_ce_new,
1893// .ce[2] = gk104_ce2_new, 1893// .ce[2] = gk104_ce2_new,
1894// .disp = gm107_disp_new, 1894// .disp = gm107_disp_new,
1895// .dma = gf119_dma_new, 1895// .dma = gf119_dma_new,
@@ -1917,8 +1917,8 @@ nv124_chipset = {
1917 .mxm = nv50_mxm_new, 1917 .mxm = nv50_mxm_new,
1918 .pmu = gm107_pmu_new, 1918 .pmu = gm107_pmu_new,
1919 .timer = gk20a_timer_new, 1919 .timer = gk20a_timer_new,
1920// .ce[0] = gm204_ce0_new, 1920// .ce[0] = gm204_ce_new,
1921// .ce[1] = gm204_ce1_new, 1921// .ce[1] = gm204_ce_new,
1922// .ce[2] = gm204_ce2_new, 1922// .ce[2] = gm204_ce2_new,
1923// .disp = gm204_disp_new, 1923// .disp = gm204_disp_new,
1924// .dma = gf119_dma_new, 1924// .dma = gf119_dma_new,
@@ -1946,8 +1946,8 @@ nv126_chipset = {
1946 .mxm = nv50_mxm_new, 1946 .mxm = nv50_mxm_new,
1947 .pmu = gm107_pmu_new, 1947 .pmu = gm107_pmu_new,
1948 .timer = gk20a_timer_new, 1948 .timer = gk20a_timer_new,
1949// .ce[0] = gm204_ce0_new, 1949// .ce[0] = gm204_ce_new,
1950// .ce[1] = gm204_ce1_new, 1950// .ce[1] = gm204_ce_new,
1951// .ce[2] = gm204_ce2_new, 1951// .ce[2] = gm204_ce2_new,
1952// .disp = gm204_disp_new, 1952// .disp = gm204_disp_new,
1953// .dma = gf119_dma_new, 1953// .dma = gf119_dma_new,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
index 1f273e108618..336964a0cd92 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
@@ -32,11 +32,6 @@ gf100_identify(struct nvkm_device *device)
32 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 32 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
33 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 33 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
34 device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; 34 device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
35 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
36 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
37 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
38 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
39 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
40 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 35 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
41 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 36 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
42 break; 37 break;
@@ -45,11 +40,6 @@ gf100_identify(struct nvkm_device *device)
45 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 40 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
46 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 41 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
47 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 42 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
48 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
49 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
50 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
51 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
52 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
53 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 43 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
54 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 44 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
55 break; 45 break;
@@ -58,10 +48,6 @@ gf100_identify(struct nvkm_device *device)
58 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 48 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
59 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 49 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
60 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 50 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
61 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
62 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
63 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
64 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
65 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 51 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
66 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 52 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
67 break; 53 break;
@@ -70,11 +56,6 @@ gf100_identify(struct nvkm_device *device)
70 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 56 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
71 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 57 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
72 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 58 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
73 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
74 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
75 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
76 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
77 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
78 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 59 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
79 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 60 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
80 break; 61 break;
@@ -83,10 +64,6 @@ gf100_identify(struct nvkm_device *device)
83 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 64 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
84 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 65 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
85 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 66 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
86 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
87 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
88 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
89 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
90 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 67 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
91 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 68 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
92 break; 69 break;
@@ -95,10 +72,6 @@ gf100_identify(struct nvkm_device *device)
95 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 72 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
96 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 73 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
97 device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; 74 device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
98 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
99 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
100 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
101 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
102 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 75 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
103 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; 76 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
104 break; 77 break;
@@ -107,11 +80,6 @@ gf100_identify(struct nvkm_device *device)
107 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 80 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
108 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 81 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
109 device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; 82 device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
110 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
111 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
112 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
113 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
114 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
115 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 83 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
116 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 84 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
117 break; 85 break;
@@ -120,10 +88,6 @@ gf100_identify(struct nvkm_device *device)
120 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 88 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
121 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 89 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
122 device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; 90 device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
123 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
124 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
125 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
126 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
127 device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; 91 device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
128 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; 92 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
129 break; 93 break;
@@ -132,10 +96,6 @@ gf100_identify(struct nvkm_device *device)
132 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 96 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
133 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 97 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
134 device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; 98 device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
135 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
136 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
137 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
138 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
139 device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; 99 device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
140 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; 100 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
141 break; 101 break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
index 414ff61873b9..1162c030f4a2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
@@ -36,9 +36,6 @@ gk104_identify(struct nvkm_device *device)
36 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; 36 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
37 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; 37 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
38 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; 38 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
39 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
40 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
41 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
42 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 39 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
43 break; 40 break;
44 case 0xe7: 41 case 0xe7:
@@ -50,9 +47,6 @@ gk104_identify(struct nvkm_device *device)
50 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; 47 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
51 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; 48 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
52 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; 49 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
53 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
54 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
55 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
56 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 50 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
57 break; 51 break;
58 case 0xe6: 52 case 0xe6:
@@ -64,9 +58,6 @@ gk104_identify(struct nvkm_device *device)
64 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; 58 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
65 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; 59 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
66 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; 60 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
67 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
68 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
69 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
70 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 61 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
71 break; 62 break;
72 case 0xea: 63 case 0xea:
@@ -86,9 +77,6 @@ gk104_identify(struct nvkm_device *device)
86 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; 77 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
87 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; 78 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
88 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; 79 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
89 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
90 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
91 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
92 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; 80 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
93 break; 81 break;
94 case 0xf1: 82 case 0xf1:
@@ -100,9 +88,6 @@ gk104_identify(struct nvkm_device *device)
100 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; 88 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
101 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; 89 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
102 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; 90 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
103 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
104 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
105 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
106 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; 91 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
107 break; 92 break;
108 case 0x106: 93 case 0x106:
@@ -114,9 +99,6 @@ gk104_identify(struct nvkm_device *device)
114 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; 99 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
115 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; 100 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
116 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; 101 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
117 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
118 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
119 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
120 break; 102 break;
121 case 0x108: 103 case 0x108:
122 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 104 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
@@ -127,9 +109,6 @@ gk104_identify(struct nvkm_device *device)
127 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; 109 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
128 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; 110 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
129 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; 111 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
130 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
131 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
132 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
133 break; 112 break;
134 default: 113 default:
135 return -EINVAL; 114 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index c16d9586708b..b7b10ca427b8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -42,9 +42,6 @@ gm100_identify(struct nvkm_device *device)
42#endif 42#endif
43 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; 43 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
44#if 0 44#if 0
45 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
46 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
47 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
48#endif 45#endif
49 break; 46 break;
50 case 0x124: 47 case 0x124:
@@ -63,9 +60,6 @@ gm100_identify(struct nvkm_device *device)
63 device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; 60 device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
64 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; 61 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
65#if 0 62#if 0
66 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
67 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
68 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
69#endif 63#endif
70 break; 64 break;
71 case 0x126: 65 case 0x126:
@@ -84,9 +78,6 @@ gm100_identify(struct nvkm_device *device)
84 device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; 78 device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
85 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; 79 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
86#if 0 80#if 0
87 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
88 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
89 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
90#endif 81#endif
91 break; 82 break;
92 case 0x12b: 83 case 0x12b:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 7e2a4a93b2a7..bcbf2d8f692a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -101,10 +101,6 @@ nv50_identify(struct nvkm_device *device)
101 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 101 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
102 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 102 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
103 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 103 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
104 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
105 device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
106 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
107 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
108 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; 104 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
109 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 105 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
110 break; 106 break;
@@ -125,10 +121,6 @@ nv50_identify(struct nvkm_device *device)
125 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 121 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
126 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 122 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
127 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 123 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
128 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
129 device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
130 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
131 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
132 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; 124 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
133 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 125 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
134 break; 126 break;
@@ -137,10 +129,6 @@ nv50_identify(struct nvkm_device *device)
137 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 129 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
138 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 130 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
139 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 131 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
140 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
141 device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
142 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
143 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
144 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; 132 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
145 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 133 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
146 break; 134 break;
@@ -150,10 +138,6 @@ nv50_identify(struct nvkm_device *device)
150 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 138 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
151 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 139 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
152 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 140 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
153 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
154 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
155 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
156 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
157 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 141 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
158 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 142 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
159 break; 143 break;
@@ -162,10 +146,6 @@ nv50_identify(struct nvkm_device *device)
162 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 146 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
163 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 147 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
164 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 148 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
165 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
166 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
167 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
168 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
169 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 149 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
170 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 150 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
171 break; 151 break;
@@ -174,10 +154,6 @@ nv50_identify(struct nvkm_device *device)
174 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 154 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
175 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 155 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
176 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 156 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
177 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
178 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
179 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
180 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
181 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 157 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
182 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 158 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
183 break; 159 break;
@@ -186,10 +162,6 @@ nv50_identify(struct nvkm_device *device)
186 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 162 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
187 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 163 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
188 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 164 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
189 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
190 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
191 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
192 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
193 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; 165 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
194 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 166 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
195 break; 167 break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
index 3d3e73cfb6b0..e51372bdbf54 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
@@ -54,10 +54,11 @@ nvkm_falcon_cclass = {
54}; 54};
55 55
56static void 56static void
57nvkm_falcon_intr(struct nvkm_subdev *subdev) 57nvkm_falcon_intr(struct nvkm_engine *engine)
58{ 58{
59 struct nvkm_falcon *falcon = (void *)subdev; 59 struct nvkm_falcon *falcon = nvkm_falcon(engine);
60 struct nvkm_device *device = falcon->engine.subdev.device; 60 struct nvkm_subdev *subdev = &falcon->engine.subdev;
61 struct nvkm_device *device = subdev->device;
61 const u32 base = falcon->addr; 62 const u32 base = falcon->addr;
62 u32 dest = nvkm_rd32(device, base + 0x01c); 63 u32 dest = nvkm_rd32(device, base + 0x01c);
63 u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); 64 u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16);
@@ -89,6 +90,27 @@ nvkm_falcon_intr(struct nvkm_subdev *subdev)
89 nvkm_fifo_chan_put(device->fifo, flags, &chan); 90 nvkm_fifo_chan_put(device->fifo, flags, &chan);
90} 91}
91 92
93static int
94nvkm_falcon_fini(struct nvkm_engine *engine, bool suspend)
95{
96 struct nvkm_falcon *falcon = nvkm_falcon(engine);
97 struct nvkm_device *device = falcon->engine.subdev.device;
98 const u32 base = falcon->addr;
99
100 if (!suspend) {
101 nvkm_memory_del(&falcon->core);
102 if (falcon->external) {
103 vfree(falcon->data.data);
104 vfree(falcon->code.data);
105 falcon->code.data = NULL;
106 }
107 }
108
109 nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000);
110 nvkm_wr32(device, base + 0x014, 0xffffffff);
111 return 0;
112}
113
92static void * 114static void *
93vmemdup(const void *src, size_t len) 115vmemdup(const void *src, size_t len)
94{ 116{
@@ -99,23 +121,16 @@ vmemdup(const void *src, size_t len)
99 return p; 121 return p;
100} 122}
101 123
102int 124static int
103_nvkm_falcon_init(struct nvkm_object *object) 125nvkm_falcon_oneinit(struct nvkm_engine *engine)
104{ 126{
105 struct nvkm_falcon *falcon = (void *)object; 127 struct nvkm_falcon *falcon = nvkm_falcon(engine);
106 struct nvkm_subdev *subdev = &falcon->engine.subdev; 128 struct nvkm_subdev *subdev = &falcon->engine.subdev;
107 struct nvkm_device *device = subdev->device; 129 struct nvkm_device *device = subdev->device;
108 const struct firmware *fw;
109 char name[32] = "internal";
110 const u32 base = falcon->addr; 130 const u32 base = falcon->addr;
111 int ret, i;
112 u32 caps; 131 u32 caps;
113 132
114 /* enable engine, and determine its capabilities */ 133 /* determine falcon capabilities */
115 ret = nvkm_engine_init_old(&falcon->engine);
116 if (ret)
117 return ret;
118
119 if (device->chipset < 0xa3 || 134 if (device->chipset < 0xa3 ||
120 device->chipset == 0xaa || device->chipset == 0xac) { 135 device->chipset == 0xaa || device->chipset == 0xac) {
121 falcon->version = 0; 136 falcon->version = 0;
@@ -134,6 +149,19 @@ _nvkm_falcon_init(struct nvkm_object *object)
134 nvkm_debug(subdev, "secret level: %d\n", falcon->secret); 149 nvkm_debug(subdev, "secret level: %d\n", falcon->secret);
135 nvkm_debug(subdev, "code limit: %d\n", falcon->code.limit); 150 nvkm_debug(subdev, "code limit: %d\n", falcon->code.limit);
136 nvkm_debug(subdev, "data limit: %d\n", falcon->data.limit); 151 nvkm_debug(subdev, "data limit: %d\n", falcon->data.limit);
152 return 0;
153}
154
155static int
156nvkm_falcon_init(struct nvkm_engine *engine)
157{
158 struct nvkm_falcon *falcon = nvkm_falcon(engine);
159 struct nvkm_subdev *subdev = &falcon->engine.subdev;
160 struct nvkm_device *device = subdev->device;
161 const struct firmware *fw;
162 char name[32] = "internal";
163 const u32 base = falcon->addr;
164 int ret, i;
137 165
138 /* wait for 'uc halted' to be signalled before continuing */ 166 /* wait for 'uc halted' to be signalled before continuing */
139 if (falcon->secret && falcon->version < 4) { 167 if (falcon->secret && falcon->version < 4) {
@@ -279,56 +307,46 @@ _nvkm_falcon_init(struct nvkm_object *object)
279 nvkm_wr32(device, base + 0x104, 0x00000000); /* ENTRY */ 307 nvkm_wr32(device, base + 0x104, 0x00000000); /* ENTRY */
280 nvkm_wr32(device, base + 0x100, 0x00000002); /* TRIGGER */ 308 nvkm_wr32(device, base + 0x100, 0x00000002); /* TRIGGER */
281 nvkm_wr32(device, base + 0x048, 0x00000003); /* FIFO | CHSW */ 309 nvkm_wr32(device, base + 0x048, 0x00000003); /* FIFO | CHSW */
310
311 if (falcon->func->init)
312 falcon->func->init(falcon);
282 return 0; 313 return 0;
283} 314}
284 315
285int 316static void *
286_nvkm_falcon_fini(struct nvkm_object *object, bool suspend) 317nvkm_falcon_dtor(struct nvkm_engine *engine)
287{ 318{
288 struct nvkm_falcon *falcon = (void *)object; 319 return nvkm_falcon(engine);
289 struct nvkm_device *device = falcon->engine.subdev.device;
290 const u32 base = falcon->addr;
291
292 if (!suspend) {
293 nvkm_memory_del(&falcon->core);
294 if (falcon->external) {
295 vfree(falcon->data.data);
296 vfree(falcon->code.data);
297 falcon->code.data = NULL;
298 }
299 }
300
301 nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000);
302 nvkm_wr32(device, base + 0x014, 0xffffffff);
303
304 return nvkm_engine_fini_old(&falcon->engine, suspend);
305} 320}
306 321
307static const struct nvkm_engine_func 322static const struct nvkm_engine_func
308nvkm_falcon = { 323nvkm_falcon = {
324 .dtor = nvkm_falcon_dtor,
325 .oneinit = nvkm_falcon_oneinit,
326 .init = nvkm_falcon_init,
327 .fini = nvkm_falcon_fini,
328 .intr = nvkm_falcon_intr,
309 .fifo.sclass = nvkm_falcon_oclass_get, 329 .fifo.sclass = nvkm_falcon_oclass_get,
310 .cclass = &nvkm_falcon_cclass, 330 .cclass = &nvkm_falcon_cclass,
311}; 331};
312 332
313int 333int
314nvkm_falcon_create_(const struct nvkm_falcon_func *func, 334nvkm_falcon_new_(const struct nvkm_falcon_func *func,
315 struct nvkm_object *parent, struct nvkm_object *engine, 335 struct nvkm_device *device, int index, bool enable,
316 struct nvkm_oclass *oclass, u32 addr, bool enable, 336 u32 addr, struct nvkm_engine **pengine)
317 const char *iname, const char *fname,
318 int length, void **pobject)
319{ 337{
320 struct nvkm_falcon *falcon; 338 struct nvkm_falcon *falcon;
321 int ret;
322
323 ret = nvkm_engine_create_(parent, engine, oclass, enable, iname,
324 fname, length, pobject);
325 falcon = *pobject;
326 if (ret)
327 return ret;
328 339
329 falcon->engine.subdev.intr = nvkm_falcon_intr; 340 if (!(falcon = kzalloc(sizeof(*falcon), GFP_KERNEL)))
330 falcon->engine.func = &nvkm_falcon; 341 return -ENOMEM;
331 falcon->func = func; 342 falcon->func = func;
332 falcon->addr = addr; 343 falcon->addr = addr;
333 return 0; 344 falcon->code.data = func->code.data;
345 falcon->code.size = func->code.size;
346 falcon->data.data = func->data.data;
347 falcon->data.size = func->data.size;
348 *pengine = &falcon->engine;
349
350 return nvkm_engine_ctor(&nvkm_falcon, device, index, func->pmc_enable,
351 enable, &falcon->engine);
334} 352}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
index c59c83a67315..1a7151146e9d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
@@ -1,3 +1,5 @@
1nvkm-y += nvkm/engine/mspdec/base.o
1nvkm-y += nvkm/engine/mspdec/g98.o 2nvkm-y += nvkm/engine/mspdec/g98.o
3nvkm-y += nvkm/engine/mspdec/gt215.o
2nvkm-y += nvkm/engine/mspdec/gf100.o 4nvkm-y += nvkm/engine/mspdec/gf100.o
3nvkm-y += nvkm/engine/mspdec/gk104.o 5nvkm-y += nvkm/engine/mspdec/gk104.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c
new file mode 100644
index 000000000000..80211f76093b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2015 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24#include "priv.h"
25
26int
27nvkm_mspdec_new_(const struct nvkm_falcon_func *func,
28 struct nvkm_device *device, int index,
29 struct nvkm_engine **pengine)
30{
31 return nvkm_falcon_new_(func, device, index, true, 0x085000, pengine);
32}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c
index f14971783270..1f1a99e927b2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c
@@ -21,61 +21,31 @@
21 * 21 *
22 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin 22 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
23 */ 23 */
24#include <engine/mspdec.h> 24#include "priv.h"
25#include <engine/falcon.h>
26 25
27#include <nvif/class.h> 26#include <nvif/class.h>
28 27
29static int 28void
30g98_mspdec_init(struct nvkm_object *object) 29g98_mspdec_init(struct nvkm_falcon *mspdec)
31{ 30{
32 struct nvkm_falcon *mspdec = (void *)object;
33 struct nvkm_device *device = mspdec->engine.subdev.device; 31 struct nvkm_device *device = mspdec->engine.subdev.device;
34 int ret;
35
36 ret = nvkm_falcon_init(mspdec);
37 if (ret)
38 return ret;
39
40 nvkm_wr32(device, 0x085010, 0x0000ffd2); 32 nvkm_wr32(device, 0x085010, 0x0000ffd2);
41 nvkm_wr32(device, 0x08501c, 0x0000fff2); 33 nvkm_wr32(device, 0x08501c, 0x0000fff2);
42 return 0;
43} 34}
44 35
45static const struct nvkm_falcon_func 36static const struct nvkm_falcon_func
46g98_mspdec_func = { 37g98_mspdec = {
38 .pmc_enable = 0x01020000,
39 .init = g98_mspdec_init,
47 .sclass = { 40 .sclass = {
48 { -1, -1, G98_MSPDEC }, 41 { -1, -1, G98_MSPDEC },
49 { -1, -1, GT212_MSPDEC },
50 {} 42 {}
51 }, 43 }
52}; 44};
53 45
54static int 46int
55g98_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 47g98_mspdec_new(struct nvkm_device *device, int index,
56 struct nvkm_oclass *oclass, void *data, u32 size, 48 struct nvkm_engine **pengine)
57 struct nvkm_object **pobject)
58{ 49{
59 struct nvkm_falcon *mspdec; 50 return nvkm_mspdec_new_(&g98_mspdec, device, index, pengine);
60 int ret;
61
62 ret = nvkm_falcon_create(&g98_mspdec_func, parent, engine, oclass,
63 0x085000, true, "PMSPDEC", "mspdec", &mspdec);
64 *pobject = nv_object(mspdec);
65 if (ret)
66 return ret;
67
68 nv_subdev(mspdec)->unit = 0x01020000;
69 return 0;
70} 51}
71
72struct nvkm_oclass
73g98_mspdec_oclass = {
74 .handle = NV_ENGINE(MSPDEC, 0x98),
75 .ofuncs = &(struct nvkm_ofuncs) {
76 .ctor = g98_mspdec_ctor,
77 .dtor = _nvkm_falcon_dtor,
78 .init = g98_mspdec_init,
79 .fini = _nvkm_falcon_fini,
80 },
81};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c
index 1296f775ea31..371fd6c3c663 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c
@@ -21,60 +21,31 @@
21 * 21 *
22 * Authors: Maarten Lankhorst 22 * Authors: Maarten Lankhorst
23 */ 23 */
24#include <engine/mspdec.h> 24#include "priv.h"
25#include <engine/falcon.h>
26 25
27#include <nvif/class.h> 26#include <nvif/class.h>
28 27
29static int 28void
30gf100_mspdec_init(struct nvkm_object *object) 29gf100_mspdec_init(struct nvkm_falcon *mspdec)
31{ 30{
32 struct nvkm_falcon *mspdec = (void *)object;
33 struct nvkm_device *device = mspdec->engine.subdev.device; 31 struct nvkm_device *device = mspdec->engine.subdev.device;
34 int ret;
35
36 ret = nvkm_falcon_init(mspdec);
37 if (ret)
38 return ret;
39
40 nvkm_wr32(device, 0x085010, 0x0000fff2); 32 nvkm_wr32(device, 0x085010, 0x0000fff2);
41 nvkm_wr32(device, 0x08501c, 0x0000fff2); 33 nvkm_wr32(device, 0x08501c, 0x0000fff2);
42 return 0;
43} 34}
44 35
45static const struct nvkm_falcon_func 36static const struct nvkm_falcon_func
46gf100_mspdec_func = { 37gf100_mspdec = {
38 .pmc_enable = 0x00020000,
39 .init = gf100_mspdec_init,
47 .sclass = { 40 .sclass = {
48 { -1, -1, GF100_MSPDEC }, 41 { -1, -1, GF100_MSPDEC },
49 {} 42 {}
50 } 43 }
51}; 44};
52 45
53static int 46int
54gf100_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 47gf100_mspdec_new(struct nvkm_device *device, int index,
55 struct nvkm_oclass *oclass, void *data, u32 size, 48 struct nvkm_engine **pengine)
56 struct nvkm_object **pobject)
57{ 49{
58 struct nvkm_falcon *mspdec; 50 return nvkm_mspdec_new_(&gf100_mspdec, device, index, pengine);
59 int ret;
60
61 ret = nvkm_falcon_create(&gf100_mspdec_func, parent, engine, oclass,
62 0x085000, true, "PMSPDEC", "mspdec", &mspdec);
63 *pobject = nv_object(mspdec);
64 if (ret)
65 return ret;
66
67 nv_subdev(mspdec)->unit = 0x00020000;
68 return 0;
69} 51}
70
71struct nvkm_oclass
72gf100_mspdec_oclass = {
73 .handle = NV_ENGINE(MSPDEC, 0xc0),
74 .ofuncs = &(struct nvkm_ofuncs) {
75 .ctor = gf100_mspdec_ctor,
76 .dtor = _nvkm_falcon_dtor,
77 .init = gf100_mspdec_init,
78 .fini = _nvkm_falcon_fini,
79 },
80};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c
index 315da1695c72..de804a15bfd4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c
@@ -21,60 +21,23 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include <engine/mspdec.h> 24#include "priv.h"
25#include <engine/falcon.h>
26 25
27#include <nvif/class.h> 26#include <nvif/class.h>
28 27
29static int
30gk104_mspdec_init(struct nvkm_object *object)
31{
32 struct nvkm_falcon *mspdec = (void *)object;
33 struct nvkm_device *device = mspdec->engine.subdev.device;
34 int ret;
35
36 ret = nvkm_falcon_init(mspdec);
37 if (ret)
38 return ret;
39
40 nvkm_wr32(device, 0x085010, 0x0000fff2);
41 nvkm_wr32(device, 0x08501c, 0x0000fff2);
42 return 0;
43}
44
45static const struct nvkm_falcon_func 28static const struct nvkm_falcon_func
46gk104_mspdec_func = { 29gk104_mspdec = {
30 .pmc_enable = 0x00020000,
31 .init = gf100_mspdec_init,
47 .sclass = { 32 .sclass = {
48 { -1, -1, GK104_MSPDEC }, 33 { -1, -1, GK104_MSPDEC },
49 {} 34 {}
50 } 35 }
51}; 36};
52 37
53static int 38int
54gk104_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 39gk104_mspdec_new(struct nvkm_device *device, int index,
55 struct nvkm_oclass *oclass, void *data, u32 size, 40 struct nvkm_engine **pengine)
56 struct nvkm_object **pobject)
57{ 41{
58 struct nvkm_falcon *falcon; 42 return nvkm_mspdec_new_(&gk104_mspdec, device, index, pengine);
59 int ret;
60
61 ret = nvkm_falcon_create(&gk104_mspdec_func, parent, engine, oclass,
62 0x085000, true, "PMSPDEC", "mspdec", &falcon);
63 *pobject = nv_object(falcon);
64 if (ret)
65 return ret;
66
67 nv_subdev(falcon)->unit = 0x00020000;
68 return 0;
69} 43}
70
71struct nvkm_oclass
72gk104_mspdec_oclass = {
73 .handle = NV_ENGINE(MSPDEC, 0xe0),
74 .ofuncs = &(struct nvkm_ofuncs) {
75 .ctor = gk104_mspdec_ctor,
76 .dtor = _nvkm_falcon_dtor,
77 .init = gk104_mspdec_init,
78 .fini = _nvkm_falcon_fini,
79 },
80};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c
new file mode 100644
index 000000000000..835631713c95
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c
@@ -0,0 +1,43 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
23 */
24#include "priv.h"
25
26#include <nvif/class.h>
27
28static const struct nvkm_falcon_func
29gt215_mspdec = {
30 .pmc_enable = 0x01020000,
31 .init = g98_mspdec_init,
32 .sclass = {
33 { -1, -1, GT212_MSPDEC },
34 {}
35 }
36};
37
38int
39gt215_mspdec_new(struct nvkm_device *device, int index,
40 struct nvkm_engine **pengine)
41{
42 return nvkm_mspdec_new_(&gt215_mspdec, device, index, pengine);
43}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h
new file mode 100644
index 000000000000..d518af4bc9de
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h
@@ -0,0 +1,11 @@
1#ifndef __NVKM_MSPDEC_PRIV_H__
2#define __NVKM_MSPDEC_PRIV_H__
3#include <engine/mspdec.h>
4
5int nvkm_mspdec_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
6 int index, struct nvkm_engine **);
7
8void g98_mspdec_init(struct nvkm_falcon *);
9
10void gf100_mspdec_init(struct nvkm_falcon *);
11#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
index 4576a9eee39d..3ea7eafb408f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
@@ -1,2 +1,4 @@
1nvkm-y += nvkm/engine/msppp/base.o
1nvkm-y += nvkm/engine/msppp/g98.o 2nvkm-y += nvkm/engine/msppp/g98.o
3nvkm-y += nvkm/engine/msppp/gt215.o
2nvkm-y += nvkm/engine/msppp/gf100.o 4nvkm-y += nvkm/engine/msppp/gf100.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c
new file mode 100644
index 000000000000..bfae5e60e925
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c
@@ -0,0 +1,31 @@
1/*
2 * Copyright 2015 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24#include "priv.h"
25
26int
27nvkm_msppp_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device,
28 int index, struct nvkm_engine **pengine)
29{
30 return nvkm_falcon_new_(func, device, index, true, 0x086000, pengine);
31}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
index 314736d6aa5b..73f633ae2ee7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
@@ -21,61 +21,31 @@
21 * 21 *
22 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin 22 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
23 */ 23 */
24#include <engine/msppp.h> 24#include "priv.h"
25#include <engine/falcon.h>
26 25
27#include <nvif/class.h> 26#include <nvif/class.h>
28 27
29static int 28void
30g98_msppp_init(struct nvkm_object *object) 29g98_msppp_init(struct nvkm_falcon *msppp)
31{ 30{
32 struct nvkm_falcon *msppp = (void *)object;
33 struct nvkm_device *device = msppp->engine.subdev.device; 31 struct nvkm_device *device = msppp->engine.subdev.device;
34 int ret;
35
36 ret = nvkm_falcon_init(msppp);
37 if (ret)
38 return ret;
39
40 nvkm_wr32(device, 0x086010, 0x0000ffd2); 32 nvkm_wr32(device, 0x086010, 0x0000ffd2);
41 nvkm_wr32(device, 0x08601c, 0x0000fff2); 33 nvkm_wr32(device, 0x08601c, 0x0000fff2);
42 return 0;
43} 34}
44 35
45static const struct nvkm_falcon_func 36static const struct nvkm_falcon_func
46g98_msppp_func = { 37g98_msppp = {
38 .pmc_enable = 0x00400002,
39 .init = g98_msppp_init,
47 .sclass = { 40 .sclass = {
48 { -1, -1, G98_MSPPP }, 41 { -1, -1, G98_MSPPP },
49 { -1, -1, GT212_MSPPP },
50 {} 42 {}
51 } 43 }
52}; 44};
53 45
54static int 46int
55g98_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 47g98_msppp_new(struct nvkm_device *device, int index,
56 struct nvkm_oclass *oclass, void *data, u32 size, 48 struct nvkm_engine **pengine)
57 struct nvkm_object **pobject)
58{ 49{
59 struct nvkm_falcon *msppp; 50 return nvkm_msppp_new_(&g98_msppp, device, index, pengine);
60 int ret;
61
62 ret = nvkm_falcon_create(&g98_msppp_func, parent, engine, oclass,
63 0x086000, true, "PMSPPP", "msppp", &msppp);
64 *pobject = nv_object(msppp);
65 if (ret)
66 return ret;
67
68 nv_subdev(msppp)->unit = 0x00400002;
69 return 0;
70} 51}
71
72struct nvkm_oclass
73g98_msppp_oclass = {
74 .handle = NV_ENGINE(MSPPP, 0x98),
75 .ofuncs = &(struct nvkm_ofuncs) {
76 .ctor = g98_msppp_ctor,
77 .dtor = _nvkm_falcon_dtor,
78 .init = g98_msppp_init,
79 .fini = _nvkm_falcon_fini,
80 },
81};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
index f977c2adf9d2..c42c0c07e2db 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
@@ -21,60 +21,31 @@
21 * 21 *
22 * Authors: Maarten Lankhorst 22 * Authors: Maarten Lankhorst
23 */ 23 */
24#include <engine/msppp.h> 24#include "priv.h"
25#include <engine/falcon.h>
26 25
27#include <nvif/class.h> 26#include <nvif/class.h>
28 27
29static int 28static void
30gf100_msppp_init(struct nvkm_object *object) 29gf100_msppp_init(struct nvkm_falcon *msppp)
31{ 30{
32 struct nvkm_falcon *msppp = (void *)object;
33 struct nvkm_device *device = msppp->engine.subdev.device; 31 struct nvkm_device *device = msppp->engine.subdev.device;
34 int ret;
35
36 ret = nvkm_falcon_init(msppp);
37 if (ret)
38 return ret;
39
40 nvkm_wr32(device, 0x086010, 0x0000fff2); 32 nvkm_wr32(device, 0x086010, 0x0000fff2);
41 nvkm_wr32(device, 0x08601c, 0x0000fff2); 33 nvkm_wr32(device, 0x08601c, 0x0000fff2);
42 return 0;
43} 34}
44 35
45static const struct nvkm_falcon_func 36static const struct nvkm_falcon_func
46gf100_msppp_func = { 37gf100_msppp = {
38 .pmc_enable = 0x00000002,
39 .init = gf100_msppp_init,
47 .sclass = { 40 .sclass = {
48 { -1, -1, GF100_MSPPP }, 41 { -1, -1, GF100_MSPPP },
49 {} 42 {}
50 } 43 }
51}; 44};
52 45
53static int 46int
54gf100_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 47gf100_msppp_new(struct nvkm_device *device, int index,
55 struct nvkm_oclass *oclass, void *data, u32 size, 48 struct nvkm_engine **pengine)
56 struct nvkm_object **pobject)
57{ 49{
58 struct nvkm_falcon *msppp; 50 return nvkm_msppp_new_(&gf100_msppp, device, index, pengine);
59 int ret;
60
61 ret = nvkm_falcon_create(&gf100_msppp_func, parent, engine, oclass,
62 0x086000, true, "PMSPPP", "msppp", &msppp);
63 *pobject = nv_object(msppp);
64 if (ret)
65 return ret;
66
67 nv_subdev(msppp)->unit = 0x00000002;
68 return 0;
69} 51}
70
71struct nvkm_oclass
72gf100_msppp_oclass = {
73 .handle = NV_ENGINE(MSPPP, 0xc0),
74 .ofuncs = &(struct nvkm_ofuncs) {
75 .ctor = gf100_msppp_ctor,
76 .dtor = _nvkm_falcon_dtor,
77 .init = gf100_msppp_init,
78 .fini = _nvkm_falcon_fini,
79 },
80};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c
new file mode 100644
index 000000000000..00e7795f1d51
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c
@@ -0,0 +1,43 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
23 */
24#include "priv.h"
25
26#include <nvif/class.h>
27
28static const struct nvkm_falcon_func
29gt215_msppp = {
30 .pmc_enable = 0x00400002,
31 .init = g98_msppp_init,
32 .sclass = {
33 { -1, -1, GT212_MSPPP },
34 {}
35 }
36};
37
38int
39gt215_msppp_new(struct nvkm_device *device, int index,
40 struct nvkm_engine **pengine)
41{
42 return nvkm_msppp_new_(&gt215_msppp, device, index, pengine);
43}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h
new file mode 100644
index 000000000000..37a91f9d9181
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h
@@ -0,0 +1,9 @@
1#ifndef __NVKM_MSPPP_PRIV_H__
2#define __NVKM_MSPPP_PRIV_H__
3#include <engine/msppp.h>
4
5int nvkm_msppp_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
6 int index, struct nvkm_engine **);
7
8void g98_msppp_init(struct nvkm_falcon *);
9#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
index 0c9811009e28..28c8ecd27b6d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
@@ -1,3 +1,6 @@
1nvkm-y += nvkm/engine/msvld/base.o
1nvkm-y += nvkm/engine/msvld/g98.o 2nvkm-y += nvkm/engine/msvld/g98.o
3nvkm-y += nvkm/engine/msvld/gt215.o
4nvkm-y += nvkm/engine/msvld/mcp89.o
2nvkm-y += nvkm/engine/msvld/gf100.o 5nvkm-y += nvkm/engine/msvld/gf100.o
3nvkm-y += nvkm/engine/msvld/gk104.o 6nvkm-y += nvkm/engine/msvld/gk104.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c
new file mode 100644
index 000000000000..745bbb653dc0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c
@@ -0,0 +1,31 @@
1/*
2 * Copyright 2015 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24#include "priv.h"
25
26int
27nvkm_msvld_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device,
28 int index, struct nvkm_engine **pengine)
29{
30 return nvkm_falcon_new_(func, device, index, true, 0x084000, pengine);
31}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c
index 0ee767373f79..47e2929bfaf0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c
@@ -21,62 +21,31 @@
21 * 21 *
22 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin 22 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
23 */ 23 */
24#include <engine/msvld.h> 24#include "priv.h"
25#include <engine/falcon.h>
26 25
27#include <nvif/class.h> 26#include <nvif/class.h>
28 27
29static int 28void
30g98_msvld_init(struct nvkm_object *object) 29g98_msvld_init(struct nvkm_falcon *msvld)
31{ 30{
32 struct nvkm_falcon *msvld = (void *)object;
33 struct nvkm_device *device = msvld->engine.subdev.device; 31 struct nvkm_device *device = msvld->engine.subdev.device;
34 int ret;
35
36 ret = nvkm_falcon_init(msvld);
37 if (ret)
38 return ret;
39
40 nvkm_wr32(device, 0x084010, 0x0000ffd2); 32 nvkm_wr32(device, 0x084010, 0x0000ffd2);
41 nvkm_wr32(device, 0x08401c, 0x0000fff2); 33 nvkm_wr32(device, 0x08401c, 0x0000fff2);
42 return 0;
43} 34}
44 35
45static const struct nvkm_falcon_func 36static const struct nvkm_falcon_func
46g98_msvld_func = { 37g98_msvld = {
38 .pmc_enable = 0x04008000,
39 .init = g98_msvld_init,
47 .sclass = { 40 .sclass = {
48 { -1, -1, G98_MSVLD }, 41 { -1, -1, G98_MSVLD },
49 { -1, -1, GT212_MSVLD },
50 { -1, -1, IGT21A_MSVLD },
51 {} 42 {}
52 } 43 }
53}; 44};
54 45
55static int 46int
56g98_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 47g98_msvld_new(struct nvkm_device *device, int index,
57 struct nvkm_oclass *oclass, void *data, u32 size, 48 struct nvkm_engine **pengine)
58 struct nvkm_object **pobject)
59{ 49{
60 struct nvkm_falcon *msvld; 50 return nvkm_msvld_new_(&g98_msvld, device, index, pengine);
61 int ret;
62
63 ret = nvkm_falcon_create(&g98_msvld_func, parent, engine, oclass,
64 0x084000, true, "PMSVLD", "msvld", &msvld);
65 *pobject = nv_object(msvld);
66 if (ret)
67 return ret;
68
69 nv_subdev(msvld)->unit = 0x04008000;
70 return 0;
71} 51}
72
73struct nvkm_oclass
74g98_msvld_oclass = {
75 .handle = NV_ENGINE(MSVLD, 0x98),
76 .ofuncs = &(struct nvkm_ofuncs) {
77 .ctor = g98_msvld_ctor,
78 .dtor = _nvkm_falcon_dtor,
79 .init = g98_msvld_init,
80 .fini = _nvkm_falcon_fini,
81 },
82};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c
index 839d648dcfdf..1ac581ba9f96 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c
@@ -21,60 +21,31 @@
21 * 21 *
22 * Authors: Maarten Lankhorst 22 * Authors: Maarten Lankhorst
23 */ 23 */
24#include <engine/msvld.h> 24#include "priv.h"
25#include <engine/falcon.h>
26 25
27#include <nvif/class.h> 26#include <nvif/class.h>
28 27
29static int 28void
30gf100_msvld_init(struct nvkm_object *object) 29gf100_msvld_init(struct nvkm_falcon *msvld)
31{ 30{
32 struct nvkm_falcon *msvld = (void *)object;
33 struct nvkm_device *device = msvld->engine.subdev.device; 31 struct nvkm_device *device = msvld->engine.subdev.device;
34 int ret;
35
36 ret = nvkm_falcon_init(msvld);
37 if (ret)
38 return ret;
39
40 nvkm_wr32(device, 0x084010, 0x0000fff2); 32 nvkm_wr32(device, 0x084010, 0x0000fff2);
41 nvkm_wr32(device, 0x08401c, 0x0000fff2); 33 nvkm_wr32(device, 0x08401c, 0x0000fff2);
42 return 0;
43} 34}
44 35
45static const struct nvkm_falcon_func 36static const struct nvkm_falcon_func
46gf100_msvld_func = { 37gf100_msvld = {
38 .pmc_enable = 0x00008000,
39 .init = gf100_msvld_init,
47 .sclass = { 40 .sclass = {
48 { -1, -1, GF100_MSVLD }, 41 { -1, -1, GF100_MSVLD },
49 {} 42 {}
50 } 43 }
51}; 44};
52 45
53static int 46int
54gf100_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 47gf100_msvld_new(struct nvkm_device *device, int index,
55 struct nvkm_oclass *oclass, void *data, u32 size, 48 struct nvkm_engine **pengine)
56 struct nvkm_object **pobject)
57{ 49{
58 struct nvkm_falcon *msvld; 50 return nvkm_msvld_new_(&gf100_msvld, device, index, pengine);
59 int ret;
60
61 ret = nvkm_falcon_create(&gf100_msvld_func, parent, engine, oclass,
62 0x084000, true, "PMSVLD", "msvld", &msvld);
63 *pobject = nv_object(msvld);
64 if (ret)
65 return ret;
66
67 nv_subdev(msvld)->unit = 0x00008000;
68 return 0;
69} 51}
70
71struct nvkm_oclass
72gf100_msvld_oclass = {
73 .handle = NV_ENGINE(MSVLD, 0xc0),
74 .ofuncs = &(struct nvkm_ofuncs) {
75 .ctor = gf100_msvld_ctor,
76 .dtor = _nvkm_falcon_dtor,
77 .init = gf100_msvld_init,
78 .fini = _nvkm_falcon_fini,
79 },
80};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c
index 74bdca359d4a..4bba16e0f560 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c
@@ -21,60 +21,23 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include <engine/msvld.h> 24#include "priv.h"
25#include <engine/falcon.h>
26 25
27#include <nvif/class.h> 26#include <nvif/class.h>
28 27
29static int
30gk104_msvld_init(struct nvkm_object *object)
31{
32 struct nvkm_falcon *msvld = (void *)object;
33 struct nvkm_device *device = msvld->engine.subdev.device;
34 int ret;
35
36 ret = nvkm_falcon_init(msvld);
37 if (ret)
38 return ret;
39
40 nvkm_wr32(device, 0x084010, 0x0000fff2);
41 nvkm_wr32(device, 0x08401c, 0x0000fff2);
42 return 0;
43}
44
45static const struct nvkm_falcon_func 28static const struct nvkm_falcon_func
46gk104_msvld_func = { 29gk104_msvld = {
30 .pmc_enable = 0x00008000,
31 .init = gf100_msvld_init,
47 .sclass = { 32 .sclass = {
48 { -1, -1, GK104_MSVLD }, 33 { -1, -1, GK104_MSVLD },
49 {} 34 {}
50 } 35 }
51}; 36};
52 37
53static int 38int
54gk104_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 39gk104_msvld_new(struct nvkm_device *device, int index,
55 struct nvkm_oclass *oclass, void *data, u32 size, 40 struct nvkm_engine **pengine)
56 struct nvkm_object **pobject)
57{ 41{
58 struct nvkm_falcon *msvld; 42 return nvkm_msvld_new_(&gk104_msvld, device, index, pengine);
59 int ret;
60
61 ret = nvkm_falcon_create(&gk104_msvld_func, parent, engine, oclass,
62 0x084000, true, "PMSVLD", "msvld", &msvld);
63 *pobject = nv_object(msvld);
64 if (ret)
65 return ret;
66
67 nv_subdev(msvld)->unit = 0x00008000;
68 return 0;
69} 43}
70
71struct nvkm_oclass
72gk104_msvld_oclass = {
73 .handle = NV_ENGINE(MSVLD, 0xe0),
74 .ofuncs = &(struct nvkm_ofuncs) {
75 .ctor = gk104_msvld_ctor,
76 .dtor = _nvkm_falcon_dtor,
77 .init = gk104_msvld_init,
78 .fini = _nvkm_falcon_fini,
79 },
80};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c
new file mode 100644
index 000000000000..e17cb5605b2d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c
@@ -0,0 +1,43 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
23 */
24#include "priv.h"
25
26#include <nvif/class.h>
27
28static const struct nvkm_falcon_func
29gt215_msvld = {
30 .pmc_enable = 0x04008000,
31 .init = g98_msvld_init,
32 .sclass = {
33 { -1, -1, GT212_MSVLD },
34 {}
35 }
36};
37
38int
39gt215_msvld_new(struct nvkm_device *device, int index,
40 struct nvkm_engine **pengine)
41{
42 return nvkm_msvld_new_(&gt215_msvld, device, index, pengine);
43}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c
new file mode 100644
index 000000000000..511800f6a43b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c
@@ -0,0 +1,43 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
23 */
24#include "priv.h"
25
26#include <nvif/class.h>
27
28static const struct nvkm_falcon_func
29mcp89_msvld = {
30 .pmc_enable = 0x04008000,
31 .init = g98_msvld_init,
32 .sclass = {
33 { -1, -1, IGT21A_MSVLD },
34 {}
35 }
36};
37
38int
39mcp89_msvld_new(struct nvkm_device *device, int index,
40 struct nvkm_engine **pengine)
41{
42 return nvkm_msvld_new_(&mcp89_msvld, device, index, pengine);
43}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h
new file mode 100644
index 000000000000..9dc1da67d929
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h
@@ -0,0 +1,11 @@
1#ifndef __NVKM_MSVLD_PRIV_H__
2#define __NVKM_MSVLD_PRIV_H__
3#include <engine/msvld.h>
4
5int nvkm_msvld_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
6 int index, struct nvkm_engine **);
7
8void g98_msvld_init(struct nvkm_falcon *);
9
10void gf100_msvld_init(struct nvkm_falcon *);
11#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
index aae0e85b1075..1ec4f4fde1c2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
@@ -22,7 +22,6 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include <engine/sec.h> 24#include <engine/sec.h>
25#include <engine/falcon.h>
26#include <engine/fifo.h> 25#include <engine/fifo.h>
27#include "fuc/g98.fuc0s.h" 26#include "fuc/g98.fuc0s.h"
28 27
@@ -61,7 +60,12 @@ g98_sec_intr(struct nvkm_falcon *sec, struct nvkm_fifo_chan *chan)
61} 60}
62 61
63static const struct nvkm_falcon_func 62static const struct nvkm_falcon_func
64g98_sec_func = { 63g98_sec = {
64 .code.data = g98_sec_code,
65 .code.size = sizeof(g98_sec_code),
66 .data.data = g98_sec_data,
67 .data.size = sizeof(g98_sec_data),
68 .pmc_enable = 0x00004000,
65 .intr = g98_sec_intr, 69 .intr = g98_sec_intr,
66 .sclass = { 70 .sclass = {
67 { -1, -1, G98_SEC }, 71 { -1, -1, G98_SEC },
@@ -69,35 +73,10 @@ g98_sec_func = {
69 } 73 }
70}; 74};
71 75
72static int 76int
73g98_sec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 77g98_sec_new(struct nvkm_device *device, int index,
74 struct nvkm_oclass *oclass, void *data, u32 size, 78 struct nvkm_engine **pengine)
75 struct nvkm_object **pobject)
76{ 79{
77 struct nvkm_falcon *sec; 80 return nvkm_falcon_new_(&g98_sec, device, index,
78 int ret; 81 true, 0x087000, pengine);
79
80 ret = nvkm_falcon_create(&g98_sec_func, parent, engine, oclass,
81 0x087000, true, "PSEC", "sec", &sec);
82 *pobject = nv_object(sec);
83 if (ret)
84 return ret;
85
86 nv_subdev(sec)->unit = 0x00004000;
87 nv_falcon(sec)->code.data = g98_sec_code;
88 nv_falcon(sec)->code.size = sizeof(g98_sec_code);
89 nv_falcon(sec)->data.data = g98_sec_data;
90 nv_falcon(sec)->data.size = sizeof(g98_sec_data);
91 return 0;
92} 82}
93
94struct nvkm_oclass
95g98_sec_oclass = {
96 .handle = NV_ENGINE(SEC, 0x98),
97 .ofuncs = &(struct nvkm_ofuncs) {
98 .ctor = g98_sec_ctor,
99 .dtor = _nvkm_falcon_dtor,
100 .init = _nvkm_falcon_init,
101 .fini = _nvkm_falcon_fini,
102 },
103};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 10:59:12 -0400