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authorOlof Johansson <olof@lixom.net>2017-03-21 20:34:09 -0400
committerOlof Johansson <olof@lixom.net>2017-03-21 20:34:09 -0400
commit5344df631b9991328943cc931bc677325b09d863 (patch)
tree1d155a423f3e1eb3b8a792f01b503dd9c3565d67
parent7df6fcfb520fbc5249caa8a0676bd3a8309acbb0 (diff)
parent3cbe33367d4fd480a92fbc131a96fa925be9e95d (diff)
Merge tag 'renesas-arm64-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Renesas ARM64 Based SoC DT Updates for v4.12 Cleanup: * Drop superfluous status update for frequency override from all r8a779[56] boards * Tidyup Audio-DMAC channel for DVC for r8a7795 SoC * Remove unit-address and reg from integrated cache on r8a779[56] SoCs Enhancements: * Add all Cortex-A53 and Cortex-A57 CPU cores to r8a7796 SoC * Add Cortex-A53 CPU cores to r8a7795 SoC * Update memory node to 4 GiB map on h3ulcb board * Upgrade to PSCI v1.0 to support Suspend-to-RAM on r8a779[56] SoCs * Add SCIF1 (DEBUG1) to r8a7796/salvator-x board * Add all SCIF and HSCIF nodes with DMA enabled to r8a7796 SoC * Set drive-strength for ravb pins for r8a7795/salvator-x board * Enable gigabit ethernet on r8a779[56]/salvator-x boards * Enable I2C for DVFS device r8a779[56]/salvator-x boards * tag 'renesas-arm64-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (32 commits) arm64: dts: r8a7796: salvator-x: Drop superfluous status update for frequency override arm64: dts: m3ulcb: Drop superfluous status update for frequency override arm64: dts: r8a7795: salvator-x: Drop superfluous status updates for frequency overrides arm64: dts: h3ulcb: Drop superfluous status update for frequency override arm64: dts: r8a7796: Add Cortex-A53 PMU node arm64: dts: r8a7796: Add Cortex-A53 CPU cores arm64: dts: r8a7796: Add CA53 L2 cache-controller node arm64: dts: r8a7796: Add Cortex-A57 PMU node arm64: dts: r8a7796: Add Cortex-A57 CPU cores arm64: dts: r8a7795: Tidyup Audio-DMAC channel for DVC arm64: dts: r8a7795: salvator-x: Set drive-strength for ravb pins arm64: dts: r8a7796: Remove unit-address and reg from integrated cache arm64: dts: r8a7795: Remove unit-addresses and regs from integrated caches arm64: dts: r8a7796: Upgrade to PSCI v1.0 to support Suspend-to-RAM arm64: dts: r8a7795: Upgrade to PSCI v1.0 to support Suspend-to-RAM arm64: dts: r8a7795: Add Cortex-A53 PMU node arm64: dts: r8a7795: Add Cortex-A53 CPU cores arm64: dts: r8a7796: Enable HSCIF DMA arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1) arm64: dts: r8a7796: Enable SCIF DMA ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts29
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts37
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi86
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts1
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts32
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi265
6 files changed, 384 insertions, 66 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index c5f8f69a4f5f..ab352159de65 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -33,6 +33,21 @@
33 reg = <0x0 0x48000000 0x0 0x38000000>; 33 reg = <0x0 0x48000000 0x0 0x38000000>;
34 }; 34 };
35 35
36 memory@500000000 {
37 device_type = "memory";
38 reg = <0x5 0x00000000 0x0 0x40000000>;
39 };
40
41 memory@600000000 {
42 device_type = "memory";
43 reg = <0x6 0x00000000 0x0 0x40000000>;
44 };
45
46 memory@700000000 {
47 device_type = "memory";
48 reg = <0x7 0x00000000 0x0 0x40000000>;
49 };
50
36 leds { 51 leds {
37 compatible = "gpio-leds"; 52 compatible = "gpio-leds";
38 53
@@ -213,7 +228,6 @@
213 228
214&scif_clk { 229&scif_clk {
215 clock-frequency = <14745600>; 230 clock-frequency = <14745600>;
216 status = "okay";
217}; 231};
218 232
219&i2c2 { 233&i2c2 {
@@ -339,18 +353,7 @@
339 status = "okay"; 353 status = "okay";
340 354
341 phy0: ethernet-phy@0 { 355 phy0: ethernet-phy@0 {
342 rxc-skew-ps = <900>; 356 rxc-skew-ps = <1500>;
343 rxdv-skew-ps = <0>;
344 rxd0-skew-ps = <0>;
345 rxd1-skew-ps = <0>;
346 rxd2-skew-ps = <0>;
347 rxd3-skew-ps = <0>;
348 txc-skew-ps = <900>;
349 txen-skew-ps = <0>;
350 txd0-skew-ps = <0>;
351 txd1-skew-ps = <0>;
352 txd2-skew-ps = <0>;
353 txd3-skew-ps = <0>;
354 reg = <0>; 357 reg = <0>;
355 interrupt-parent = <&gpio2>; 358 interrupt-parent = <&gpio2>;
356 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 359 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 7a8986edcdc0..f25241921067 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -247,8 +247,22 @@
247 }; 247 };
248 248
249 avb_pins: avb { 249 avb_pins: avb {
250 groups = "avb_mdc"; 250 mux {
251 function = "avb"; 251 groups = "avb_link", "avb_phy_int", "avb_mdc",
252 "avb_mii";
253 function = "avb";
254 };
255
256 pins_mdc {
257 groups = "avb_mdc";
258 drive-strength = <24>;
259 };
260
261 pins_mii_tx {
262 pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
263 "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
264 drive-strength = <12>;
265 };
252 }; 266 };
253 267
254 du_pins: du { 268 du_pins: du {
@@ -348,7 +362,6 @@
348 362
349&scif_clk { 363&scif_clk {
350 clock-frequency = <14745600>; 364 clock-frequency = <14745600>;
351 status = "okay";
352}; 365};
353 366
354&i2c2 { 367&i2c2 {
@@ -485,6 +498,10 @@
485 clock-frequency = <22579200>; 498 clock-frequency = <22579200>;
486}; 499};
487 500
501&i2c_dvfs {
502 status = "okay";
503};
504
488&avb { 505&avb {
489 pinctrl-0 = <&avb_pins>; 506 pinctrl-0 = <&avb_pins>;
490 pinctrl-names = "default"; 507 pinctrl-names = "default";
@@ -493,18 +510,7 @@
493 status = "okay"; 510 status = "okay";
494 511
495 phy0: ethernet-phy@0 { 512 phy0: ethernet-phy@0 {
496 rxc-skew-ps = <900>; 513 rxc-skew-ps = <1500>;
497 rxdv-skew-ps = <0>;
498 rxd0-skew-ps = <0>;
499 rxd1-skew-ps = <0>;
500 rxd2-skew-ps = <0>;
501 rxd3-skew-ps = <0>;
502 txc-skew-ps = <900>;
503 txen-skew-ps = <0>;
504 txd0-skew-ps = <0>;
505 txd1-skew-ps = <0>;
506 txd2-skew-ps = <0>;
507 txd3-skew-ps = <0>;
508 reg = <0>; 514 reg = <0>;
509 interrupt-parent = <&gpio2>; 515 interrupt-parent = <&gpio2>;
510 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 516 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
@@ -567,7 +573,6 @@
567 573
568&pcie_bus_clk { 574&pcie_bus_clk {
569 clock-frequency = <100000000>; 575 clock-frequency = <100000000>;
570 status = "okay";
571}; 576};
572 577
573&pciec0 { 578&pciec0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index eac4f29aa5cd..55c09f1b89c9 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -25,10 +25,11 @@
25 i2c4 = &i2c4; 25 i2c4 = &i2c4;
26 i2c5 = &i2c5; 26 i2c5 = &i2c5;
27 i2c6 = &i2c6; 27 i2c6 = &i2c6;
28 i2c7 = &i2c_dvfs;
28 }; 29 };
29 30
30 psci { 31 psci {
31 compatible = "arm,psci-0.2"; 32 compatible = "arm,psci-1.0", "arm,psci-0.2";
32 method = "smc"; 33 method = "smc";
33 }; 34 };
34 35
@@ -72,17 +73,51 @@
72 enable-method = "psci"; 73 enable-method = "psci";
73 }; 74 };
74 75
75 L2_CA57: cache-controller@0 { 76 a53_0: cpu@100 {
77 compatible = "arm,cortex-a53", "arm,armv8";
78 reg = <0x100>;
79 device_type = "cpu";
80 power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
81 next-level-cache = <&L2_CA53>;
82 enable-method = "psci";
83 };
84
85 a53_1: cpu@101 {
86 compatible = "arm,cortex-a53","arm,armv8";
87 reg = <0x101>;
88 device_type = "cpu";
89 power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
90 next-level-cache = <&L2_CA53>;
91 enable-method = "psci";
92 };
93
94 a53_2: cpu@102 {
95 compatible = "arm,cortex-a53","arm,armv8";
96 reg = <0x102>;
97 device_type = "cpu";
98 power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
99 next-level-cache = <&L2_CA53>;
100 enable-method = "psci";
101 };
102
103 a53_3: cpu@103 {
104 compatible = "arm,cortex-a53","arm,armv8";
105 reg = <0x103>;
106 device_type = "cpu";
107 power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
108 next-level-cache = <&L2_CA53>;
109 enable-method = "psci";
110 };
111
112 L2_CA57: cache-controller-0 {
76 compatible = "cache"; 113 compatible = "cache";
77 reg = <0>;
78 power-domains = <&sysc R8A7795_PD_CA57_SCU>; 114 power-domains = <&sysc R8A7795_PD_CA57_SCU>;
79 cache-unified; 115 cache-unified;
80 cache-level = <2>; 116 cache-level = <2>;
81 }; 117 };
82 118
83 L2_CA53: cache-controller@100 { 119 L2_CA53: cache-controller-1 {
84 compatible = "cache"; 120 compatible = "cache";
85 reg = <0x100>;
86 power-domains = <&sysc R8A7795_PD_CA53_SCU>; 121 power-domains = <&sysc R8A7795_PD_CA53_SCU>;
87 cache-unified; 122 cache-unified;
88 cache-level = <2>; 123 cache-level = <2>;
@@ -165,7 +200,7 @@
165 <0x0 0xf1040000 0 0x20000>, 200 <0x0 0xf1040000 0 0x20000>,
166 <0x0 0xf1060000 0 0x20000>; 201 <0x0 0xf1060000 0 0x20000>;
167 interrupts = <GIC_PPI 9 202 interrupts = <GIC_PPI 9
168 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 203 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
169 clocks = <&cpg CPG_MOD 408>; 204 clocks = <&cpg CPG_MOD 408>;
170 clock-names = "clk"; 205 clock-names = "clk";
171 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 206 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -303,16 +338,28 @@
303 <&a57_3>; 338 <&a57_3>;
304 }; 339 };
305 340
341 pmu_a53 {
342 compatible = "arm,cortex-a53-pmu";
343 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
347 interrupt-affinity = <&a53_0>,
348 <&a53_1>,
349 <&a53_2>,
350 <&a53_3>;
351 };
352
306 timer { 353 timer {
307 compatible = "arm,armv8-timer"; 354 compatible = "arm,armv8-timer";
308 interrupts = <GIC_PPI 13 355 interrupts = <GIC_PPI 13
309 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 356 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
310 <GIC_PPI 14 357 <GIC_PPI 14
311 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 358 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
312 <GIC_PPI 11 359 <GIC_PPI 11
313 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 360 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
314 <GIC_PPI 10 361 <GIC_PPI 10
315 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 362 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
316 }; 363 };
317 364
318 cpg: clock-controller@e6150000 { 365 cpg: clock-controller@e6150000 {
@@ -563,7 +610,7 @@
563 "ch24"; 610 "ch24";
564 clocks = <&cpg CPG_MOD 812>; 611 clocks = <&cpg CPG_MOD 812>;
565 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 612 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
566 phy-mode = "rgmii-id"; 613 phy-mode = "rgmii-txid";
567 #address-cells = <1>; 614 #address-cells = <1>;
568 #size-cells = <0>; 615 #size-cells = <0>;
569 status = "disabled"; 616 status = "disabled";
@@ -793,6 +840,19 @@
793 status = "disabled"; 840 status = "disabled";
794 }; 841 };
795 842
843 i2c_dvfs: i2c@e60b0000 {
844 #address-cells = <1>;
845 #size-cells = <0>;
846 compatible = "renesas,iic-r8a7795",
847 "renesas,rcar-gen3-iic",
848 "renesas,rmobile-iic";
849 reg = <0 0xe60b0000 0 0x425>;
850 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&cpg CPG_MOD 926>;
852 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
853 status = "disabled";
854 };
855
796 i2c0: i2c@e6500000 { 856 i2c0: i2c@e6500000 {
797 #address-cells = <1>; 857 #address-cells = <1>;
798 #size-cells = <0>; 858 #size-cells = <0>;
@@ -1015,11 +1075,11 @@
1015 1075
1016 rcar_sound,dvc { 1076 rcar_sound,dvc {
1017 dvc0: dvc-0 { 1077 dvc0: dvc-0 {
1018 dmas = <&audma0 0xbc>; 1078 dmas = <&audma1 0xbc>;
1019 dma-names = "tx"; 1079 dma-names = "tx";
1020 }; 1080 };
1021 dvc1: dvc-1 { 1081 dvc1: dvc-1 {
1022 dmas = <&audma0 0xbe>; 1082 dmas = <&audma1 0xbe>;
1023 dma-names = "tx"; 1083 dma-names = "tx";
1024 }; 1084 };
1025 }; 1085 };
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index c3f064ac2cb4..372b2a944716 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -180,7 +180,6 @@
180 180
181&scif_clk { 181&scif_clk {
182 clock-frequency = <14745600>; 182 clock-frequency = <14745600>;
183 status = "okay";
184}; 183};
185 184
186&wdt0 { 185&wdt0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index c7f40f8f3169..c9f59b6ce33f 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -18,6 +18,7 @@
18 18
19 aliases { 19 aliases {
20 serial0 = &scif2; 20 serial0 = &scif2;
21 serial1 = &scif1;
21 ethernet0 = &avb; 22 ethernet0 = &avb;
22 }; 23 };
23 24
@@ -113,6 +114,11 @@
113 function = "avb"; 114 function = "avb";
114 }; 115 };
115 116
117 scif1_pins: scif1 {
118 groups = "scif1_data_a", "scif1_ctrl";
119 function = "scif1";
120 };
121
116 scif2_pins: scif2 { 122 scif2_pins: scif2 {
117 groups = "scif2_data_a"; 123 groups = "scif2_data_a";
118 function = "scif2"; 124 function = "scif2";
@@ -172,18 +178,7 @@
172 status = "okay"; 178 status = "okay";
173 179
174 phy0: ethernet-phy@0 { 180 phy0: ethernet-phy@0 {
175 rxc-skew-ps = <900>; 181 rxc-skew-ps = <1500>;
176 rxdv-skew-ps = <0>;
177 rxd0-skew-ps = <0>;
178 rxd1-skew-ps = <0>;
179 rxd2-skew-ps = <0>;
180 rxd3-skew-ps = <0>;
181 txc-skew-ps = <900>;
182 txen-skew-ps = <0>;
183 txd0-skew-ps = <0>;
184 txd1-skew-ps = <0>;
185 txd2-skew-ps = <0>;
186 txd3-skew-ps = <0>;
187 reg = <0>; 182 reg = <0>;
188 interrupt-parent = <&gpio2>; 183 interrupt-parent = <&gpio2>;
189 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 184 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
@@ -239,6 +234,14 @@
239 status = "okay"; 234 status = "okay";
240}; 235};
241 236
237&scif1 {
238 pinctrl-0 = <&scif1_pins>;
239 pinctrl-names = "default";
240
241 uart-has-rtscts;
242 status = "okay";
243};
244
242&scif2 { 245&scif2 {
243 pinctrl-0 = <&scif2_pins>; 246 pinctrl-0 = <&scif2_pins>;
244 pinctrl-names = "default"; 247 pinctrl-names = "default";
@@ -247,7 +250,6 @@
247 250
248&scif_clk { 251&scif_clk {
249 clock-frequency = <14745600>; 252 clock-frequency = <14745600>;
250 status = "okay";
251}; 253};
252 254
253&i2c2 { 255&i2c2 {
@@ -261,3 +263,7 @@
261 timeout-sec = <60>; 263 timeout-sec = <60>;
262 status = "okay"; 264 status = "okay";
263}; 265};
266
267&i2c_dvfs {
268 status = "okay";
269};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index f7120cdedd0d..a90abf14dc4e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -25,10 +25,11 @@
25 i2c4 = &i2c4; 25 i2c4 = &i2c4;
26 i2c5 = &i2c5; 26 i2c5 = &i2c5;
27 i2c6 = &i2c6; 27 i2c6 = &i2c6;
28 i2c7 = &i2c_dvfs;
28 }; 29 };
29 30
30 psci { 31 psci {
31 compatible = "arm,psci-0.2"; 32 compatible = "arm,psci-1.0", "arm,psci-0.2";
32 method = "smc"; 33 method = "smc";
33 }; 34 };
34 35
@@ -36,7 +37,6 @@
36 #address-cells = <1>; 37 #address-cells = <1>;
37 #size-cells = <0>; 38 #size-cells = <0>;
38 39
39 /* 1 core only at this point */
40 a57_0: cpu@0 { 40 a57_0: cpu@0 {
41 compatible = "arm,cortex-a57", "arm,armv8"; 41 compatible = "arm,cortex-a57", "arm,armv8";
42 reg = <0x0>; 42 reg = <0x0>;
@@ -46,13 +46,64 @@
46 enable-method = "psci"; 46 enable-method = "psci";
47 }; 47 };
48 48
49 L2_CA57: cache-controller@0 { 49 a57_1: cpu@1 {
50 compatible = "arm,cortex-a57","arm,armv8";
51 reg = <0x1>;
52 device_type = "cpu";
53 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
54 next-level-cache = <&L2_CA57>;
55 enable-method = "psci";
56 };
57
58 a53_0: cpu@100 {
59 compatible = "arm,cortex-a53", "arm,armv8";
60 reg = <0x100>;
61 device_type = "cpu";
62 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
63 next-level-cache = <&L2_CA53>;
64 enable-method = "psci";
65 };
66
67 a53_1: cpu@101 {
68 compatible = "arm,cortex-a53","arm,armv8";
69 reg = <0x101>;
70 device_type = "cpu";
71 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
72 next-level-cache = <&L2_CA53>;
73 enable-method = "psci";
74 };
75
76 a53_2: cpu@102 {
77 compatible = "arm,cortex-a53","arm,armv8";
78 reg = <0x102>;
79 device_type = "cpu";
80 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
81 next-level-cache = <&L2_CA53>;
82 enable-method = "psci";
83 };
84
85 a53_3: cpu@103 {
86 compatible = "arm,cortex-a53","arm,armv8";
87 reg = <0x103>;
88 device_type = "cpu";
89 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
90 next-level-cache = <&L2_CA53>;
91 enable-method = "psci";
92 };
93
94 L2_CA57: cache-controller-0 {
50 compatible = "cache"; 95 compatible = "cache";
51 reg = <0>;
52 power-domains = <&sysc R8A7796_PD_CA57_SCU>; 96 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
53 cache-unified; 97 cache-unified;
54 cache-level = <2>; 98 cache-level = <2>;
55 }; 99 };
100
101 L2_CA53: cache-controller-1 {
102 compatible = "cache";
103 power-domains = <&sysc R8A7796_PD_CA53_SCU>;
104 cache-unified;
105 cache-level = <2>;
106 };
56 }; 107 };
57 108
58 extal_clk: extal { 109 extal_clk: extal {
@@ -100,7 +151,7 @@
100 <0x0 0xf1040000 0 0x20000>, 151 <0x0 0xf1040000 0 0x20000>,
101 <0x0 0xf1060000 0 0x20000>; 152 <0x0 0xf1060000 0 0x20000>;
102 interrupts = <GIC_PPI 9 153 interrupts = <GIC_PPI 9
103 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 154 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
104 clocks = <&cpg CPG_MOD 408>; 155 clocks = <&cpg CPG_MOD 408>;
105 clock-names = "clk"; 156 clock-names = "clk";
106 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 157 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -109,13 +160,13 @@
109 timer { 160 timer {
110 compatible = "arm,armv8-timer"; 161 compatible = "arm,armv8-timer";
111 interrupts = <GIC_PPI 13 162 interrupts = <GIC_PPI 13
112 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 163 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 14 164 <GIC_PPI 14
114 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 165 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 11 166 <GIC_PPI 11
116 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 167 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 10 168 <GIC_PPI 10
118 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 169 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
119 }; 170 };
120 171
121 wdt0: watchdog@e6020000 { 172 wdt0: watchdog@e6020000 {
@@ -244,6 +295,26 @@
244 reg = <0 0xe6060000 0 0x50c>; 295 reg = <0 0xe6060000 0 0x50c>;
245 }; 296 };
246 297
298 pmu_a57 {
299 compatible = "arm,cortex-a57-pmu";
300 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-affinity = <&a57_0>,
303 <&a57_1>;
304 };
305
306 pmu_a53 {
307 compatible = "arm,cortex-a53-pmu";
308 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-affinity = <&a53_0>,
313 <&a53_1>,
314 <&a53_2>,
315 <&a53_3>;
316 };
317
247 cpg: clock-controller@e6150000 { 318 cpg: clock-controller@e6150000 {
248 compatible = "renesas,r8a7796-cpg-mssr"; 319 compatible = "renesas,r8a7796-cpg-mssr";
249 reg = <0 0xe6150000 0 0x1000>; 320 reg = <0 0xe6150000 0 0x1000>;
@@ -269,6 +340,19 @@
269 #power-domain-cells = <1>; 340 #power-domain-cells = <1>;
270 }; 341 };
271 342
343 i2c_dvfs: i2c@e60b0000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "renesas,iic-r8a7796",
347 "renesas,rcar-gen3-iic",
348 "renesas,rmobile-iic";
349 reg = <0 0xe60b0000 0 0x425>;
350 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&cpg CPG_MOD 926>;
352 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
353 status = "disabled";
354 };
355
272 i2c0: i2c@e6500000 { 356 i2c0: i2c@e6500000 {
273 #address-cells = <1>; 357 #address-cells = <1>;
274 #size-cells = <0>; 358 #size-cells = <0>;
@@ -469,12 +553,127 @@
469 "ch24"; 553 "ch24";
470 clocks = <&cpg CPG_MOD 812>; 554 clocks = <&cpg CPG_MOD 812>;
471 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 555 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
472 phy-mode = "rgmii-id"; 556 phy-mode = "rgmii-txid";
473 #address-cells = <1>; 557 #address-cells = <1>;
474 #size-cells = <0>; 558 #size-cells = <0>;
475 status = "disabled"; 559 status = "disabled";
476 }; 560 };
477 561
562 hscif0: serial@e6540000 {
563 compatible = "renesas,hscif-r8a7796",
564 "renesas,rcar-gen3-hscif",
565 "renesas,hscif";
566 reg = <0 0xe6540000 0 0x60>;
567 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&cpg CPG_MOD 520>,
569 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
570 <&scif_clk>;
571 clock-names = "fck", "brg_int", "scif_clk";
572 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
573 <&dmac2 0x31>, <&dmac2 0x30>;
574 dma-names = "tx", "rx", "tx", "rx";
575 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
576 status = "disabled";
577 };
578
579 hscif1: serial@e6550000 {
580 compatible = "renesas,hscif-r8a7796",
581 "renesas,rcar-gen3-hscif",
582 "renesas,hscif";
583 reg = <0 0xe6550000 0 0x60>;
584 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&cpg CPG_MOD 519>,
586 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
587 <&scif_clk>;
588 clock-names = "fck", "brg_int", "scif_clk";
589 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
590 <&dmac2 0x33>, <&dmac2 0x32>;
591 dma-names = "tx", "rx", "tx", "rx";
592 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
593 status = "disabled";
594 };
595
596 hscif2: serial@e6560000 {
597 compatible = "renesas,hscif-r8a7796",
598 "renesas,rcar-gen3-hscif",
599 "renesas,hscif";
600 reg = <0 0xe6560000 0 0x60>;
601 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&cpg CPG_MOD 518>,
603 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
604 <&scif_clk>;
605 clock-names = "fck", "brg_int", "scif_clk";
606 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
607 <&dmac2 0x35>, <&dmac2 0x34>;
608 dma-names = "tx", "rx", "tx", "rx";
609 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
610 status = "disabled";
611 };
612
613 hscif3: serial@e66a0000 {
614 compatible = "renesas,hscif-r8a7796",
615 "renesas,rcar-gen3-hscif",
616 "renesas,hscif";
617 reg = <0 0xe66a0000 0 0x60>;
618 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cpg CPG_MOD 517>,
620 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
621 <&scif_clk>;
622 clock-names = "fck", "brg_int", "scif_clk";
623 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
624 dma-names = "tx", "rx";
625 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
626 status = "disabled";
627 };
628
629 hscif4: serial@e66b0000 {
630 compatible = "renesas,hscif-r8a7796",
631 "renesas,rcar-gen3-hscif",
632 "renesas,hscif";
633 reg = <0 0xe66b0000 0 0x60>;
634 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cpg CPG_MOD 516>,
636 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
637 <&scif_clk>;
638 clock-names = "fck", "brg_int", "scif_clk";
639 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
640 dma-names = "tx", "rx";
641 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
642 status = "disabled";
643 };
644
645 scif0: serial@e6e60000 {
646 compatible = "renesas,scif-r8a7796",
647 "renesas,rcar-gen3-scif", "renesas,scif";
648 reg = <0 0xe6e60000 0 64>;
649 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&cpg CPG_MOD 207>,
651 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
652 <&scif_clk>;
653 clock-names = "fck", "brg_int", "scif_clk";
654 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
655 <&dmac2 0x51>, <&dmac2 0x50>;
656 dma-names = "tx", "rx", "tx", "rx";
657 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
658 status = "disabled";
659 };
660
661 scif1: serial@e6e68000 {
662 compatible = "renesas,scif-r8a7796",
663 "renesas,rcar-gen3-scif", "renesas,scif";
664 reg = <0 0xe6e68000 0 64>;
665 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&cpg CPG_MOD 206>,
667 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
668 <&scif_clk>;
669 clock-names = "fck", "brg_int", "scif_clk";
670 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
671 <&dmac2 0x53>, <&dmac2 0x52>;
672 dma-names = "tx", "rx", "tx", "rx";
673 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
674 status = "disabled";
675 };
676
478 scif2: serial@e6e88000 { 677 scif2: serial@e6e88000 {
479 compatible = "renesas,scif-r8a7796", 678 compatible = "renesas,scif-r8a7796",
480 "renesas,rcar-gen3-scif", "renesas,scif"; 679 "renesas,rcar-gen3-scif", "renesas,scif";
@@ -488,6 +687,52 @@
488 status = "disabled"; 687 status = "disabled";
489 }; 688 };
490 689
690 scif3: serial@e6c50000 {
691 compatible = "renesas,scif-r8a7796",
692 "renesas,rcar-gen3-scif", "renesas,scif";
693 reg = <0 0xe6c50000 0 64>;
694 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&cpg CPG_MOD 204>,
696 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
697 <&scif_clk>;
698 clock-names = "fck", "brg_int", "scif_clk";
699 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
700 dma-names = "tx", "rx";
701 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
702 status = "disabled";
703 };
704
705 scif4: serial@e6c40000 {
706 compatible = "renesas,scif-r8a7796",
707 "renesas,rcar-gen3-scif", "renesas,scif";
708 reg = <0 0xe6c40000 0 64>;
709 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&cpg CPG_MOD 203>,
711 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
712 <&scif_clk>;
713 clock-names = "fck", "brg_int", "scif_clk";
714 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
715 dma-names = "tx", "rx";
716 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
717 status = "disabled";
718 };
719
720 scif5: serial@e6f30000 {
721 compatible = "renesas,scif-r8a7796",
722 "renesas,rcar-gen3-scif", "renesas,scif";
723 reg = <0 0xe6f30000 0 64>;
724 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&cpg CPG_MOD 202>,
726 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
727 <&scif_clk>;
728 clock-names = "fck", "brg_int", "scif_clk";
729 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
730 <&dmac2 0x5b>, <&dmac2 0x5a>;
731 dma-names = "tx", "rx", "tx", "rx";
732 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
733 status = "disabled";
734 };
735
491 msiof0: spi@e6e90000 { 736 msiof0: spi@e6e90000 {
492 compatible = "renesas,msiof-r8a7796", 737 compatible = "renesas,msiof-r8a7796",
493 "renesas,rcar-gen3-msiof"; 738 "renesas,rcar-gen3-msiof";
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 01:58:35 -0400