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authorStephen Boyd <sboyd@kernel.org>2018-06-01 13:26:06 -0400
committerStephen Boyd <sboyd@kernel.org>2018-06-01 13:26:06 -0400
commit533dfd6050356b5c341ec058058c94301e837f45 (patch)
treed95a0a3079504c5ce3b1d1eb830fd0d7e5e3ae0c
parent60cc43fc888428bb2f18f08997432d426a243338 (diff)
parent1d646229f28d2c413572905f03f71af33b903cc5 (diff)
Merge tag 'v4.18-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull rockchip clk driver updates from Heiko Stuebner: Conversion to match_string helper of open-coded string comparison and removal of the initial devicetree-based gate-clocks, which were deprecated since 2014. * tag 'v4.18-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: remove deprecated gate-clk code and dt-binding clk: rockchip: use match_string() helper
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip.txt77
-rw-r--r--drivers/clk/rockchip/Makefile1
-rw-r--r--drivers/clk/rockchip/clk-rockchip.c98
-rw-r--r--drivers/clk/rockchip/clk.c16
4 files changed, 5 insertions, 187 deletions
diff --git a/Documentation/devicetree/bindings/clock/rockchip.txt b/Documentation/devicetree/bindings/clock/rockchip.txt
deleted file mode 100644
index 22f6769e5d4a..000000000000
--- a/Documentation/devicetree/bindings/clock/rockchip.txt
+++ /dev/null
@@ -1,77 +0,0 @@
1Device Tree Clock bindings for arch-rockchip
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7== Gate clocks ==
8
9These bindings are deprecated!
10Please use the soc specific CRU bindings instead.
11
12The gate registers form a continuos block which makes the dt node
13structure a matter of taste, as either all gates can be put into
14one gate clock spanning all registers or they can be divided into
15the 10 individual gates containing 16 clocks each.
16The code supports both approaches.
17
18Required properties:
19- compatible : "rockchip,rk2928-gate-clk"
20- reg : shall be the control register address(es) for the clock.
21- #clock-cells : from common clock binding; shall be set to 1
22- clock-output-names : the corresponding gate names that the clock controls
23- clocks : should contain the parent clock for each individual gate,
24 therefore the number of clocks elements should match the number of
25 clock-output-names
26
27Example using multiple gate clocks:
28
29 clk_gates0: gate-clk@200000d0 {
30 compatible = "rockchip,rk2928-gate-clk";
31 reg = <0x200000d0 0x4>;
32 clocks = <&dummy>, <&dummy>,
33 <&dummy>, <&dummy>,
34 <&dummy>, <&dummy>,
35 <&dummy>, <&dummy>,
36 <&dummy>, <&dummy>,
37 <&dummy>, <&dummy>,
38 <&dummy>, <&dummy>,
39 <&dummy>, <&dummy>;
40
41 clock-output-names =
42 "gate_core_periph", "gate_cpu_gpll",
43 "gate_ddrphy", "gate_aclk_cpu",
44 "gate_hclk_cpu", "gate_pclk_cpu",
45 "gate_atclk_cpu", "gate_i2s0",
46 "gate_i2s0_frac", "gate_i2s1",
47 "gate_i2s1_frac", "gate_i2s2",
48 "gate_i2s2_frac", "gate_spdif",
49 "gate_spdif_frac", "gate_testclk";
50
51 #clock-cells = <1>;
52 };
53
54 clk_gates1: gate-clk@200000d4 {
55 compatible = "rockchip,rk2928-gate-clk";
56 reg = <0x200000d4 0x4>;
57 clocks = <&xin24m>, <&xin24m>,
58 <&xin24m>, <&dummy>,
59 <&dummy>, <&xin24m>,
60 <&xin24m>, <&dummy>,
61 <&xin24m>, <&dummy>,
62 <&xin24m>, <&dummy>,
63 <&xin24m>, <&dummy>,
64 <&xin24m>, <&dummy>;
65
66 clock-output-names =
67 "gate_timer0", "gate_timer1",
68 "gate_timer2", "gate_jtag",
69 "gate_aclk_lcdc1_src", "gate_otgphy0",
70 "gate_otgphy1", "gate_ddr_gpll",
71 "gate_uart0", "gate_frac_uart0",
72 "gate_uart1", "gate_frac_uart1",
73 "gate_uart2", "gate_frac_uart2",
74 "gate_uart3", "gate_frac_uart3";
75
76 #clock-cells = <1>;
77 };
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 59b8d320960a..98e7b9429b83 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -3,7 +3,6 @@
3# Rockchip Clock specific Makefile 3# Rockchip Clock specific Makefile
4# 4#
5 5
6obj-y += clk-rockchip.o
7obj-y += clk.o 6obj-y += clk.o
8obj-y += clk-pll.o 7obj-y += clk-pll.o
9obj-y += clk-cpu.o 8obj-y += clk-cpu.o
diff --git a/drivers/clk/rockchip/clk-rockchip.c b/drivers/clk/rockchip/clk-rockchip.c
deleted file mode 100644
index 2c9bb81144c9..000000000000
--- a/drivers/clk/rockchip/clk-rockchip.c
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/clkdev.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20
21static DEFINE_SPINLOCK(clk_lock);
22
23/*
24 * Gate clocks
25 */
26
27static void __init rk2928_gate_clk_init(struct device_node *node)
28{
29 struct clk_onecell_data *clk_data;
30 const char *clk_parent;
31 const char *clk_name;
32 void __iomem *reg;
33 void __iomem *reg_idx;
34 int flags;
35 int qty;
36 int reg_bit;
37 int clkflags = CLK_SET_RATE_PARENT;
38 int i;
39
40 qty = of_property_count_strings(node, "clock-output-names");
41 if (qty < 0) {
42 pr_err("%s: error in clock-output-names %d\n", __func__, qty);
43 return;
44 }
45
46 if (qty == 0) {
47 pr_info("%s: nothing to do\n", __func__);
48 return;
49 }
50
51 reg = of_iomap(node, 0);
52 if (!reg)
53 return;
54
55 clk_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
56 if (!clk_data) {
57 iounmap(reg);
58 return;
59 }
60
61 clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL);
62 if (!clk_data->clks) {
63 kfree(clk_data);
64 iounmap(reg);
65 return;
66 }
67
68 flags = CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE;
69
70 for (i = 0; i < qty; i++) {
71 of_property_read_string_index(node, "clock-output-names",
72 i, &clk_name);
73
74 /* ignore empty slots */
75 if (!strcmp("reserved", clk_name))
76 continue;
77
78 clk_parent = of_clk_get_parent_name(node, i);
79
80 /* keep all gates untouched for now */
81 clkflags |= CLK_IGNORE_UNUSED;
82
83 reg_idx = reg + (4 * (i / 16));
84 reg_bit = (i % 16);
85
86 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
87 clk_parent, clkflags,
88 reg_idx, reg_bit,
89 flags,
90 &clk_lock);
91 WARN_ON(IS_ERR(clk_data->clks[i]));
92 }
93
94 clk_data->clk_num = qty;
95
96 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
97}
98CLK_OF_DECLARE(rk2928_gate, "rockchip,rk2928-gate-clk", rk2928_gate_clk_init);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 3cd8ad59e0b7..326b3fa44f5d 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -274,18 +274,10 @@ static struct clk *rockchip_clk_register_frac_branch(
274 struct clk_mux *frac_mux = &frac->mux; 274 struct clk_mux *frac_mux = &frac->mux;
275 struct clk_init_data init; 275 struct clk_init_data init;
276 struct clk *mux_clk; 276 struct clk *mux_clk;
277 int i, ret; 277 int ret;
278
279 frac->mux_frac_idx = -1;
280 for (i = 0; i < child->num_parents; i++) {
281 if (!strcmp(name, child->parent_names[i])) {
282 pr_debug("%s: found fractional parent in mux at pos %d\n",
283 __func__, i);
284 frac->mux_frac_idx = i;
285 break;
286 }
287 }
288 278
279 frac->mux_frac_idx = match_string(child->parent_names,
280 child->num_parents, name);
289 frac->mux_ops = &clk_mux_ops; 281 frac->mux_ops = &clk_mux_ops;
290 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb; 282 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
291 283
@@ -312,6 +304,8 @@ static struct clk *rockchip_clk_register_frac_branch(
312 304
313 /* notifier on the fraction divider to catch rate changes */ 305 /* notifier on the fraction divider to catch rate changes */
314 if (frac->mux_frac_idx >= 0) { 306 if (frac->mux_frac_idx >= 0) {
307 pr_debug("%s: found fractional parent in mux at pos %d\n",
308 __func__, frac->mux_frac_idx);
315 ret = clk_notifier_register(clk, &frac->clk_nb); 309 ret = clk_notifier_register(clk, &frac->clk_nb);
316 if (ret) 310 if (ret)
317 pr_err("%s: failed to register clock notifier for %s\n", 311 pr_err("%s: failed to register clock notifier for %s\n",
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 09:51:30 -0400