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authorOlof Johansson <olof@lixom.net>2018-01-05 02:17:16 -0500
committerOlof Johansson <olof@lixom.net>2018-01-05 02:17:16 -0500
commit5333aeb10132549c5893ce5822652ae2f3770d26 (patch)
treee271ce39cf56e28923c0a096f3e509901731e402
parent0e9288e003f496132cb7147ae006da69aa04d123 (diff)
parent2ce3dc66d75fc204cc42bc4ee9c6f612ef4a8949 (diff)
Merge tag 'sunxi-dt-for-4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner DT changes for 4.16 A random assortment of improvements. GPIO device nodes are added for the AXP813/AXP818 PMICs, meaning we can finally use the GPIO pins on the PMICs. The LDOs on the GPIO pins can also be properly muxed and guarded. EMAC Ethernet support is enabled for more H3 boards, and also for the A83T, following the return of the bindings in 4.15, after a last minute revert in 4.13. This will make the H3/A83T boards much more useful in headless applications. Two new boards are introduced. The Orange Pi R1 is a small board with two Ethernet interfaces (one EMAC-based and one USB-based) and a WiFi chip. This board is fully supported, with the exception of TV-out on the expansion header, which will not be enabled by default. The WiFi chip (RTL8189FTV) requires an out-of-tree driver. The Libre Computer Board ALL-H3-CC H3 version is a newcomer to the Allwinner SBC space, which was mostly represented by a bunch of fruit-Pis. It is mostly supported, with the exception of HDMI and camera sensor interface, which have not been implemented yet. Two minor patches enable the audio codec on the A13 Olinuxino, and HDMI output on the pcDuino3 Nano. * tag 'sunxi-dt-for-4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: dts: sun8i: h3: nanopi-m1-plus: fix missing ethernet 0 in aliases ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Nanopi M1 ARM: dts: sun7i: Enable HDMI on pcDuino3 Nano ARM: dts: sun8i: a83t: Add I2C device nodes and pinmux settings ARM: dts: sun8i: a83t: Add I2S controller device nodes ARM: dts: sun8i-h3: Remove allwinner,leds-active-low for non internal PHY ARM: dts: sun8i: a83t: Enable Ethernet on two boards ARM: dts: sun8i: a83t: add dwmac-sun8i device node ARM: dts: sun8i: h3: enable USB OTG for NanoPi Neo board ARM: dts: sun8i: h3: Add dts file for Libre Computer Board ALL-H3-CC H3 ver. ARM: dtsi: axp81x: set pinmux for GPIO0/1 when used as LDOs ARM: dtsi: axp81x: add GPIO DT node ARM: dts: sun8i: add support for Orange Pi R1 ARM: dts: sunxi: Add codec for A13 Olinuxino Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/axp81x.dtsi20
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts4
-rw-r--r--arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts25
-rw-r--r--arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts19
-rw-r--r--arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts17
-rw-r--r--arch/arm/boot/dts/sun8i-a83t.dtsi135
-rw-r--r--arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts73
-rw-r--r--arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts1
-rw-r--r--arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts196
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts3
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts11
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts17
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts1
14 files changed, 520 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a5d8dcc4b2b6..5da0108883ab 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -951,9 +951,11 @@ dtb-$(CONFIG_MACH_SUN8I) += \
951 sun8i-a83t-bananapi-m3.dtb \ 951 sun8i-a83t-bananapi-m3.dtb \
952 sun8i-a83t-cubietruck-plus.dtb \ 952 sun8i-a83t-cubietruck-plus.dtb \
953 sun8i-a83t-tbs-a711.dtb \ 953 sun8i-a83t-tbs-a711.dtb \
954 sun8i-h2-plus-orangepi-r1.dtb \
954 sun8i-h2-plus-orangepi-zero.dtb \ 955 sun8i-h2-plus-orangepi-zero.dtb \
955 sun8i-h3-bananapi-m2-plus.dtb \ 956 sun8i-h3-bananapi-m2-plus.dtb \
956 sun8i-h3-beelink-x2.dtb \ 957 sun8i-h3-beelink-x2.dtb \
958 sun8i-h3-libretech-all-h3-cc.dtb \
957 sun8i-h3-nanopi-m1.dtb \ 959 sun8i-h3-nanopi-m1.dtb \
958 sun8i-h3-nanopi-m1-plus.dtb \ 960 sun8i-h3-nanopi-m1-plus.dtb \
959 sun8i-h3-nanopi-neo.dtb \ 961 sun8i-h3-nanopi-neo.dtb \
diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
index 73b761f850c5..fd55b896afa1 100644
--- a/arch/arm/boot/dts/axp81x.dtsi
+++ b/arch/arm/boot/dts/axp81x.dtsi
@@ -48,6 +48,22 @@
48 interrupt-controller; 48 interrupt-controller;
49 #interrupt-cells = <1>; 49 #interrupt-cells = <1>;
50 50
51 axp_gpio: axp-gpio {
52 compatible = "x-powers,axp813-gpio";
53 gpio-controller;
54 #gpio-cells = <2>;
55
56 gpio0_ldo: gpio0-ldo {
57 pins = "GPIO0";
58 function = "ldo";
59 };
60
61 gpio1_ldo: gpio1-ldo {
62 pins = "GPIO1";
63 function = "ldo";
64 };
65 };
66
51 regulators { 67 regulators {
52 /* Default work frequency for buck regulators */ 68 /* Default work frequency for buck regulators */
53 x-powers,dcdc-freq = <3000>; 69 x-powers,dcdc-freq = <3000>;
@@ -113,11 +129,15 @@
113 }; 129 };
114 130
115 reg_ldo_io0: ldo-io0 { 131 reg_ldo_io0: ldo-io0 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&gpio0_ldo>;
116 /* Disable by default to avoid conflicts with GPIO */ 134 /* Disable by default to avoid conflicts with GPIO */
117 status = "disabled"; 135 status = "disabled";
118 }; 136 };
119 137
120 reg_ldo_io1: ldo-io1 { 138 reg_ldo_io1: ldo-io1 {
139 pinctrl-names = "default";
140 pinctrl-0 = <&gpio1_ldo>;
121 /* Disable by default to avoid conflicts with GPIO */ 141 /* Disable by default to avoid conflicts with GPIO */
122 status = "disabled"; 142 status = "disabled";
123 }; 143 };
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 38072c7e10e2..4b9af423c6d5 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -114,6 +114,10 @@
114 status = "okay"; 114 status = "okay";
115}; 115};
116 116
117&codec {
118 status = "okay";
119};
120
117&ehci0 { 121&ehci0 {
118 status = "okay"; 122 status = "okay";
119}; 123};
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index 39bc73db72e5..fb591f32252c 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -58,6 +58,17 @@
58 stdout-path = "serial0:115200n8"; 58 stdout-path = "serial0:115200n8";
59 }; 59 };
60 60
61 hdmi-connector {
62 compatible = "hdmi-connector";
63 type = "a";
64
65 port {
66 hdmi_con_in: endpoint {
67 remote-endpoint = <&hdmi_out_con>;
68 };
69 };
70 };
71
61 leds { 72 leds {
62 compatible = "gpio-leds"; 73 compatible = "gpio-leds";
63 pinctrl-names = "default"; 74 pinctrl-names = "default";
@@ -90,6 +101,10 @@
90 cpu-supply = <&reg_dcdc2>; 101 cpu-supply = <&reg_dcdc2>;
91}; 102};
92 103
104&de {
105 status = "okay";
106};
107
93&ehci0 { 108&ehci0 {
94 status = "okay"; 109 status = "okay";
95}; 110};
@@ -110,6 +125,16 @@
110 }; 125 };
111}; 126};
112 127
128&hdmi {
129 status = "okay";
130};
131
132&hdmi_out {
133 hdmi_out_con: endpoint {
134 remote-endpoint = <&hdmi_con_in>;
135 };
136};
137
113&i2c0 { 138&i2c0 {
114 pinctrl-names = "default"; 139 pinctrl-names = "default";
115 pinctrl-0 = <&i2c0_pins_a>; 140 pinctrl-0 = <&i2c0_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index c606af3dbfed..6550bf0e594b 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -52,6 +52,7 @@
52 compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t"; 52 compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
53 53
54 aliases { 54 aliases {
55 ethernet0 = &emac;
55 serial0 = &uart0; 56 serial0 = &uart0;
56 }; 57 };
57 58
@@ -88,6 +89,24 @@
88 /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */ 89 /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
89}; 90};
90 91
92&emac {
93 pinctrl-names = "default";
94 pinctrl-0 = <&emac_rgmii_pins>;
95 phy-supply = <&reg_sw>;
96 phy-handle = <&rgmii_phy>;
97 phy-mode = "rgmii";
98 allwinner,rx-delay-ps = <700>;
99 allwinner,tx-delay-ps = <700>;
100 status = "okay";
101};
102
103&mdio {
104 rgmii_phy: ethernet-phy@1 {
105 compatible = "ethernet-phy-ieee802.3-c22";
106 reg = <1>;
107 };
108};
109
91&mmc0 { 110&mmc0 {
92 pinctrl-names = "default"; 111 pinctrl-names = "default";
93 pinctrl-0 = <&mmc0_pins>; 112 pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index 7f0a3f6d0cf2..6da08cd0e107 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -52,6 +52,7 @@
52 compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t"; 52 compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
53 53
54 aliases { 54 aliases {
55 ethernet0 = &emac;
55 serial0 = &uart0; 56 serial0 = &uart0;
56 }; 57 };
57 58
@@ -154,6 +155,22 @@
154 status = "okay"; 155 status = "okay";
155}; 156};
156 157
158&emac {
159 pinctrl-names = "default";
160 pinctrl-0 = <&emac_rgmii_pins>;
161 phy-supply = <&reg_dldo4>;
162 phy-handle = <&rgmii_phy>;
163 phy-mode = "rgmii";
164 status = "okay";
165};
166
167&mdio {
168 rgmii_phy: ethernet-phy@1 {
169 compatible = "ethernet-phy-ieee802.3-c22";
170 reg = <1>;
171 };
172};
173
157&mmc0 { 174&mmc0 {
158 pinctrl-names = "default"; 175 pinctrl-names = "default";
159 pinctrl-0 = <&mmc0_pins>; 176 pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 19acae1b4089..de5119a2a91c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -336,6 +336,39 @@
336 #interrupt-cells = <3>; 336 #interrupt-cells = <3>;
337 #gpio-cells = <3>; 337 #gpio-cells = <3>;
338 338
339 emac_rgmii_pins: emac-rgmii-pins {
340 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
341 "PD11", "PD12", "PD13", "PD14", "PD18",
342 "PD19", "PD21", "PD22", "PD23";
343 function = "gmac";
344 /*
345 * data lines in RGMII mode use DDR mode
346 * and need a higher signal drive strength
347 */
348 drive-strength = <40>;
349 };
350
351 i2c0_pins: i2c0-pins {
352 pins = "PH0", "PH1";
353 function = "i2c0";
354 };
355
356 i2c1_pins: i2c1-pins {
357 pins = "PH2", "PH3";
358 function = "i2c1";
359 };
360
361 i2c2_ph_pins: i2c2-ph-pins {
362 pins = "PH4", "PH5";
363 function = "i2c2";
364 };
365
366 i2s1_pins: i2s1-pins {
367 /* I2S1 does not have external MCLK pin */
368 pins = "PG10", "PG11", "PG12", "PG13";
369 function = "i2s1";
370 };
371
339 mmc0_pins: mmc0-pins { 372 mmc0_pins: mmc0-pins {
340 pins = "PF0", "PF1", "PF2", 373 pins = "PF0", "PF1", "PF2",
341 "PF3", "PF4", "PF5"; 374 "PF3", "PF4", "PF5";
@@ -418,6 +451,47 @@
418 status = "disabled"; 451 status = "disabled";
419 }; 452 };
420 453
454 i2s0: i2s@1c22000 {
455 #sound-dai-cells = <0>;
456 compatible = "allwinner,sun8i-a83t-i2s";
457 reg = <0x01c22000 0x400>;
458 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
460 clock-names = "apb", "mod";
461 dmas = <&dma 3>, <&dma 3>;
462 resets = <&ccu RST_BUS_I2S0>;
463 dma-names = "rx", "tx";
464 status = "disabled";
465 };
466
467 i2s1: i2s@1c22400 {
468 #sound-dai-cells = <0>;
469 compatible = "allwinner,sun8i-a83t-i2s";
470 reg = <0x01c22400 0x400>;
471 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
473 clock-names = "apb", "mod";
474 dmas = <&dma 4>, <&dma 4>;
475 resets = <&ccu RST_BUS_I2S1>;
476 dma-names = "rx", "tx";
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2s1_pins>;
479 status = "disabled";
480 };
481
482 i2s2: i2s@1c22800 {
483 #sound-dai-cells = <0>;
484 compatible = "allwinner,sun8i-a83t-i2s";
485 reg = <0x01c22800 0x400>;
486 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
488 clock-names = "apb", "mod";
489 dmas = <&dma 27>;
490 resets = <&ccu RST_BUS_I2S2>;
491 dma-names = "tx";
492 status = "disabled";
493 };
494
421 uart0: serial@1c28000 { 495 uart0: serial@1c28000 {
422 compatible = "snps,dw-apb-uart"; 496 compatible = "snps,dw-apb-uart";
423 reg = <0x01c28000 0x400>; 497 reg = <0x01c28000 0x400>;
@@ -440,6 +514,67 @@
440 status = "disabled"; 514 status = "disabled";
441 }; 515 };
442 516
517 i2c0: i2c@1c2ac00 {
518 compatible = "allwinner,sun8i-a83t-i2c",
519 "allwinner,sun6i-a31-i2c";
520 reg = <0x01c2ac00 0x400>;
521 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&ccu CLK_BUS_I2C0>;
523 resets = <&ccu RST_BUS_I2C0>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&i2c0_pins>;
526 status = "disabled";
527 #address-cells = <1>;
528 #size-cells = <0>;
529 };
530
531 i2c1: i2c@1c2b000 {
532 compatible = "allwinner,sun8i-a83t-i2c",
533 "allwinner,sun6i-a31-i2c";
534 reg = <0x01c2b000 0x400>;
535 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&ccu CLK_BUS_I2C1>;
537 resets = <&ccu RST_BUS_I2C1>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c1_pins>;
540 status = "disabled";
541 #address-cells = <1>;
542 #size-cells = <0>;
543 };
544
545 i2c2: i2c@1c2b400 {
546 compatible = "allwinner,sun8i-a83t-i2c",
547 "allwinner,sun6i-a31-i2c";
548 reg = <0x01c2b400 0x400>;
549 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&ccu CLK_BUS_I2C2>;
551 resets = <&ccu RST_BUS_I2C2>;
552 status = "disabled";
553 #address-cells = <1>;
554 #size-cells = <0>;
555 };
556
557 emac: ethernet@1c30000 {
558 compatible = "allwinner,sun8i-a83t-emac";
559 syscon = <&syscon>;
560 reg = <0x01c30000 0x104>;
561 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
562 interrupt-names = "macirq";
563 resets = <&ccu 13>;
564 reset-names = "stmmaceth";
565 clocks = <&ccu 27>;
566 clock-names = "stmmaceth";
567 #address-cells = <1>;
568 #size-cells = <0>;
569 status = "disabled";
570
571 mdio: mdio {
572 compatible = "snps,dwmac-mdio";
573 #address-cells = <1>;
574 #size-cells = <0>;
575 };
576 };
577
443 gic: interrupt-controller@1c81000 { 578 gic: interrupt-controller@1c81000 {
444 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 579 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
445 reg = <0x01c81000 0x1000>, 580 reg = <0x01c81000 0x1000>,
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
new file mode 100644
index 000000000000..32a6d312422e
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
@@ -0,0 +1,73 @@
1/*
2 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/* Orange Pi R1 is based on Orange Pi Zero design */
44#include "sun8i-h2-plus-orangepi-zero.dts"
45
46/ {
47 model = "Xunlong Orange Pi R1";
48 compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus";
49
50 /delete-node/ reg_vcc_wifi;
51
52 aliases {
53 ethernet1 = &rtl8189etv;
54 };
55};
56
57&ohci1 {
58 /*
59 * RTL8152B USB-Ethernet adapter is connected to USB1,
60 * and it's a USB 2.0 device. So the OHCI1 controller
61 * can be left disabled.
62 */
63 status = "disabled";
64};
65
66&mmc1 {
67 vmmc-supply = <&reg_vcc3v3>;
68 vqmmc-supply = <&reg_vcc3v3>;
69
70 rtl8189etv: sdio_wifi@1 {
71 reg = <1>;
72 };
73};
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index f2292deaa590..f1c3f1cc4d97 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -119,7 +119,6 @@
119 phy-handle = <&ext_rgmii_phy>; 119 phy-handle = <&ext_rgmii_phy>;
120 phy-mode = "rgmii"; 120 phy-mode = "rgmii";
121 121
122 allwinner,leds-active-low;
123 status = "okay"; 122 status = "okay";
124}; 123};
125 124
diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
new file mode 100644
index 000000000000..d406571a0dd6
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
@@ -0,0 +1,196 @@
1/*
2 * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7/dts-v1/;
8#include "sun8i-h3.dtsi"
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12
13/ {
14 model = "Libre Computer Board ALL-H3-CC H3";
15 compatible = "libretech,all-h3-cc-h3", "allwinner,sun8i-h3";
16
17 aliases {
18 ethernet0 = &emac;
19 serial0 = &uart0;
20 };
21
22 chosen {
23 stdout-path = "serial0:115200n8";
24 };
25
26 leds {
27 compatible = "gpio-leds";
28
29 pwr_led {
30 label = "librecomputer:green:pwr";
31 gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
32 default-state = "on";
33 };
34
35 status_led {
36 label = "librecomputer:blue:status";
37 gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
38 };
39 };
40
41 gpio_keys {
42 compatible = "gpio-keys";
43
44 power {
45 label = "power";
46 linux,code = <KEY_POWER>;
47 gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
48 };
49 };
50
51 reg_vcc1v2: vcc1v2 {
52 compatible = "regulator-fixed";
53 regulator-name = "vcc1v2";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 regulator-always-on;
57 regulator-boot-on;
58 vin-supply = <&reg_vcc5v0>;
59 gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
60 enable-active-high;
61 };
62
63 reg_vcc3v3: vcc3v3 {
64 compatible = "regulator-fixed";
65 regulator-name = "vcc3v3";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
68 vin-supply = <&reg_vcc5v0>;
69 };
70
71 /* This represents the board's 5V input */
72 reg_vcc5v0: vcc5v0 {
73 compatible = "regulator-fixed";
74 regulator-name = "vcc5v0";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 };
78
79 reg_vcc_dram: vcc-dram {
80 compatible = "regulator-fixed";
81 regulator-name = "vcc-dram";
82 regulator-min-microvolt = <1500000>;
83 regulator-max-microvolt = <1500000>;
84 regulator-always-on;
85 regulator-boot-on;
86 vin-supply = <&reg_vcc5v0>;
87 gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
88 enable-active-high;
89 };
90
91 reg_vcc_io: vcc-io {
92 compatible = "regulator-fixed";
93 regulator-name = "vcc-io";
94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>;
96 regulator-always-on;
97 regulator-boot-on;
98 vin-supply = <&reg_vcc3v3>;
99 gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
100 };
101
102 reg_vdd_cpux: vdd-cpux {
103 compatible = "regulator-fixed";
104 regulator-name = "vdd-cpux";
105 regulator-min-microvolt = <3300000>;
106 regulator-max-microvolt = <3300000>;
107 regulator-always-on;
108 regulator-boot-on;
109 vin-supply = <&reg_vcc5v0>;
110 gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
111 enable-active-high;
112 };
113};
114
115&codec {
116 allwinner,audio-routing =
117 "Line Out", "LINEOUT",
118 "MIC1", "Mic",
119 "Mic", "MBIAS";
120 status = "okay";
121};
122
123&ehci0 {
124 status = "okay";
125};
126
127&ehci1 {
128 status = "okay";
129};
130
131&ehci2 {
132 status = "okay";
133};
134
135&ehci3 {
136 status = "okay";
137};
138
139&emac {
140 phy-handle = <&int_mii_phy>;
141 phy-mode = "mii";
142 allwinner,leds-active-low;
143 status = "okay";
144};
145
146&ir {
147 pinctrl-names = "default";
148 pinctrl-0 = <&ir_pins_a>;
149 status = "okay";
150};
151
152&mmc0 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&mmc0_pins_a>;
155 vmmc-supply = <&reg_vcc_io>;
156 bus-width = <4>;
157 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
158 cd-inverted;
159 status = "okay";
160};
161
162&ohci0 {
163 status = "okay";
164};
165
166&ohci1 {
167 status = "okay";
168};
169
170&ohci2 {
171 status = "okay";
172};
173
174&ohci3 {
175 status = "okay";
176};
177
178&uart0 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&uart0_pins_a>;
181 status = "okay";
182};
183
184&usb_otg {
185 dr_mode = "host";
186 status = "okay";
187};
188
189&usbphy {
190 /* VBUS on USB ports are always on */
191 usb0_vbus-supply = <&reg_vcc5v0>;
192 usb1_vbus-supply = <&reg_vcc5v0>;
193 usb2_vbus-supply = <&reg_vcc5v0>;
194 usb3_vbus-supply = <&reg_vcc5v0>;
195 status = "okay";
196};
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 0a8b79cf5954..a6e61915d648 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -48,6 +48,7 @@
48 48
49 aliases { 49 aliases {
50 serial1 = &uart3; 50 serial1 = &uart3;
51 ethernet0 = &emac;
51 ethernet1 = &sdio_wifi; 52 ethernet1 = &sdio_wifi;
52 }; 53 };
53 54
@@ -83,8 +84,6 @@
83 phy-handle = <&ext_rgmii_phy>; 84 phy-handle = <&ext_rgmii_phy>;
84 phy-mode = "rgmii"; 85 phy-mode = "rgmii";
85 86
86 allwinner,leds-active-low;
87
88 status = "okay"; 87 status = "okay";
89}; 88};
90 89
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
index 3a2ccdb28afd..c77fbca4f227 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
@@ -45,6 +45,10 @@
45/ { 45/ {
46 model = "FriendlyArm NanoPi M1"; 46 model = "FriendlyArm NanoPi M1";
47 compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3"; 47 compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3";
48
49 aliases {
50 ethernet0 = &emac;
51 };
48}; 52};
49 53
50&ehci1 { 54&ehci1 {
@@ -55,6 +59,13 @@
55 status = "okay"; 59 status = "okay";
56}; 60};
57 61
62&emac {
63 phy-handle = <&int_mii_phy>;
64 phy-mode = "mii";
65 allwinner,leds-active-low;
66 status = "okay";
67};
68
58&ir { 69&ir {
59 pinctrl-names = "default"; 70 pinctrl-names = "default";
60 pinctrl-0 = <&ir_pins_a>; 71 pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 78f6c24952dd..9f33f6fae595 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -47,9 +47,26 @@
47 compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; 47 compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
48}; 48};
49 49
50&ehci0 {
51 status = "okay";
52};
53
50&emac { 54&emac {
51 phy-handle = <&int_mii_phy>; 55 phy-handle = <&int_mii_phy>;
52 phy-mode = "mii"; 56 phy-mode = "mii";
53 allwinner,leds-active-low; 57 allwinner,leds-active-low;
54 status = "okay"; 58 status = "okay";
55}; 59};
60
61&ohci0 {
62 status = "okay";
63};
64
65&usb_otg {
66 status = "okay";
67 dr_mode = "peripheral";
68};
69
70&usbphy {
71 usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
72};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index cbc499b04de4..b403e5d787cb 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -85,7 +85,6 @@
85 phy-handle = <&ext_rgmii_phy>; 85 phy-handle = <&ext_rgmii_phy>;
86 phy-mode = "rgmii"; 86 phy-mode = "rgmii";
87 87
88 allwinner,leds-active-low;
89 status = "okay"; 88 status = "okay";
90}; 89};
91 90
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