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authorChris Wilson <chris@chris-wilson.co.uk>2017-10-04 08:41:52 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2017-10-04 10:05:40 -0400
commit53221e11c7a0e85004c1a28f74e4e173f098d262 (patch)
tree3891da9a6d4b94d961885d0a8063f69259b703ba
parent32ced39c1b122679f829cfdac5a679b3a5aefeaf (diff)
drm/i915: Move MMCD_MISC_CTRL from context w/a to standard
Looking at gem_workarounds shows us that MMCD_MISC_CTRL is not restored following a suspend-resume cycle. This implies that MMCD_MISC_CTRL is not stored in the context, but is an ordinary register w/a that we need to restore during init_hw. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171004124153.14142-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
-rw-r--r--drivers/gpu/drm/i915/intel_engine_cs.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a75f5e889927..8625feb0939e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -980,7 +980,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
980 GEN9_PBE_COMPRESSED_HASH_SELECTION); 980 GEN9_PBE_COMPRESSED_HASH_SELECTION);
981 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 981 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
982 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 982 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
983 WA_SET_BIT(MMCD_MISC_CTRL, MMCD_PCLA | MMCD_HOTSPOT_EN); 983
984 I915_WRITE(MMCD_MISC_CTRL,
985 I915_READ(MMCD_MISC_CTRL) |
986 MMCD_PCLA |
987 MMCD_HOTSPOT_EN);
984 } 988 }
985 989
986 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 990 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */