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authorAlex Deucher <alexander.deucher@amd.com>2016-02-05 11:11:51 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-02-08 10:37:48 -0500
commit52b52a87814b4016bb324c0d1b45eb6e6f4cea3b (patch)
tree8318cf858322586783526a51299529069ecb99cf
parente3b04bc790ecd6d08d4699bc60b4f5a76f7f7b6b (diff)
drm/amdgpu/tonga: plumb pg flags through to powerplay
Enable vce and uvd pg based on single set of pg flags. Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 69c81c14d89c..980d3bf8ea76 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -4451,6 +4451,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4451 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; 4451 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
4452 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 4452 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4453 phw_tonga_ulv_parm *ulv; 4453 phw_tonga_ulv_parm *ulv;
4454 struct cgs_system_info sys_info = {0};
4454 4455
4455 PP_ASSERT_WITH_CODE((NULL != hwmgr), 4456 PP_ASSERT_WITH_CODE((NULL != hwmgr),
4456 "Invalid Parameter!", return -1;); 4457 "Invalid Parameter!", return -1;);
@@ -4619,10 +4620,19 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4619 PHM_PlatformCaps_UVDPowerGating); 4620 PHM_PlatformCaps_UVDPowerGating);
4620 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 4621 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4621 PHM_PlatformCaps_VCEPowerGating); 4622 PHM_PlatformCaps_VCEPowerGating);
4623 sys_info.size = sizeof(struct cgs_system_info);
4624 sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
4625 result = cgs_query_system_info(hwmgr->device, &sys_info);
4626 if (!result) {
4627 if (sys_info.value & AMD_PG_SUPPORT_UVD)
4628 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4629 PHM_PlatformCaps_UVDPowerGating);
4630 if (sys_info.value & AMD_PG_SUPPORT_VCE)
4631 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4632 PHM_PlatformCaps_VCEPowerGating);
4633 }
4622 4634
4623 if (0 == result) { 4635 if (0 == result) {
4624 struct cgs_system_info sys_info = {0};
4625
4626 data->is_tlu_enabled = 0; 4636 data->is_tlu_enabled = 0;
4627 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 4637 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
4628 TONGA_MAX_HARDWARE_POWERLEVELS; 4638 TONGA_MAX_HARDWARE_POWERLEVELS;