Merge tag 'renesas-arm-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Second Round of Renesas ARM Based SoC DT Updates for v4.20

* RZ/G1M (r8a7743) based iWave G20D-Q7 board and camera daughter board
  - Move PCIe node out of common dtsi to allow reuse of the common dtsi
    on the iWave RZ/G1N board
* RZ/G1C (r8a77470) SoC: Add I2C4, SDHI2 and SMP support
* R-Car Gen1 based boards and R-Car Gen2 SoCs:
  - Enhance top-of-file comments to include SoC name
* RZ/N1D (r9a06g032) SoC:
  - Correct UART0 description and add all other UARTs

* tag 'renesas-arm-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: dts: iwg20d-q7-common: Move pciec node out of common dtsi
  ARM: dts: r8a77470: Add I2C4 support
  ARM: dts: r8a77470: Add SDHI2 support
  ARM: dts: r8a77470: Add SMP support
  ARM: dts: R-Car Gen1 board comment update
  ARM: dts: Include R-Car Gen2 product name in DTSI files
  ARM: dts: r9a06g032: Correct UART and add all other UARTs

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

12 files changed, 140 insertions, 14 deletions

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index 5cae74eb6cdd..ca9154dd8052 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -160,10 +160,6 @@
         clock-frequency = <100000000>;
 };
 
-&pciec {
-        status = "okay";
-};
-
 &pfc {
         can0_pins: can0 {
                 groups = "can0_data_d";
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
index 327545119ee3..0d006aea99da 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
@@ -14,3 +14,7 @@
         model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board";
         compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
 };
+
+&pciec {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index b683db4da8b1..498e223a5f93 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -13,3 +13,7 @@
         model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";
         compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
 };
+
+&pciec {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index c053a28cd132..9ec78d3d0ca8 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -17,6 +17,7 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
+                enable-method = "renesas,apmu";
 
                 cpu0: cpu@0 {
                         device_type = "cpu";
@@ -28,6 +29,15 @@
                         next-level-cache = <&L2_CA7>;
                 };
 
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <1>;
+                        clock-frequency = <1000000000>;
+                        clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
+                        power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
+                        next-level-cache = <&L2_CA7>;
+                };
 
                 L2_CA7: cache-controller-0 {
                         compatible = "cache";
@@ -167,6 +177,12 @@
                         #reset-cells = <1>;
                 };
 
+                apmu@e6151000 {
+                        compatible = "renesas,r8a77470-apmu", "renesas,apmu";
+                        reg = <0 0xe6151000 0 0x188>;
+                        cpus = <&cpu0 &cpu1>;
+                };
+
                 rst: reset-controller@e6160000 {
                         compatible = "renesas,r8a77470-rst";
                         reg = <0 0xe6160000 0 0x100>;
@@ -221,6 +237,20 @@
                         reg = <0 0xe6300000 0 0x20000>;
                 };
 
+                i2c4: i2c@e6520000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77470",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6520000 0 0x40>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 927>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                        resets = <&cpg 927>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
                 dmac0: dma-controller@e6700000 {
                         compatible = "renesas,dmac-r8a77470",
                                      "renesas,rcar-dmac";
@@ -396,6 +426,21 @@
                         status = "disabled";
                 };
 
+                sdhi2: sd@ee160000 {
+                        compatible = "renesas,sdhi-r8a77470",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee160000 0 0x328>;
+                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 312>;
+                        dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                               <&dmac1 0xd3>, <&dmac1 0xd4>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                        resets = <&cpg 312>;
+                        status = "disabled";
+                };
+
                 gic: interrupt-controller@f1001000 {
                         compatible = "arm,gic-400";
                         #interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index de808d2ea856..cecb22924ec4 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Reference Device Tree Source for the Bock-W board
+ * Reference Device Tree Source for the R-Car M1A (R8A77781) Bock-W board
  *
  * Copyright (C) 2013  Renesas Solutions Corp.
  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index a4d0038363f0..abc14e7a4c93 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the Marzen board
+ * Device Tree Source for the R-Car H1 (R8A77790) Marzen board
  *
  * Copyright (C) 2013 Renesas Solutions Corp.
  * Copyright (C) 2013 Simon Horman
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 52a757f47bf0..5a2747758f67 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7790 SoC
+ * Device Tree Source for the R-Car H2 (R8A77900) SoC
  *
  * Copyright (C) 2015 Renesas Electronics Corporation
  * Copyright (C) 2013-2014 Renesas Solutions Corp.
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 25b6a99dd87a..6f875502453c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7791 SoC
+ * Device Tree Source for the R-Car M2-W (R8A77910) SoC
  *
  * Copyright (C) 2013-2015 Renesas Electronics Corporation
  * Copyright (C) 2013-2014 Renesas Solutions Corp.
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 52d16a260db0..8e9eb4b704d3 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7792 SoC
+ * Device Tree Source for the R-Car V2H (R8A77920) SoC
  *
  * Copyright (C) 2016 Cogent Embedded Inc.
  */
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 620a570307ff..bf05110fac4e 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7793 SoC
+ * Device Tree Source for the R-Car M2-N (R8A77930) SoC
  *
  * Copyright (C) 2014-2015 Renesas Electronics Corporation
  */
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 886135a273cb..8d797d34816e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7794 SoC
+ * Device Tree Source for the R-Car E2 (R8A77940) SoC
  *
  * Copyright (C) 2014 Renesas Electronics Corporation
  * Copyright (C) 2014 Ulrich Hecht
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 3e45375b79aa..eaf94976ed6d 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -78,13 +78,90 @@
                 };
 
                 uart0: serial@40060000 {
-                        compatible = "snps,dw-apb-uart";
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
                         reg = <0x40060000 0x400>;
                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&sysctrl R9A06G032_CLK_UART0>;
-                        clock-names = "baudclk";
+                        clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart1: serial@40061000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
+                        reg = <0x40061000 0x400>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart2: serial@40062000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
+                        reg = <0x40062000 0x400>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart3: serial@50000000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+                        reg = <0x50000000 0x400>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart4: serial@50001000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+                        reg = <0x50001000 0x400>;
+                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart5: serial@50002000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+                        reg = <0x50002000 0x400>;
+                        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart6: serial@50003000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+                        reg = <0x50003000 0x400>;
+                        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart7: serial@50004000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+                        reg = <0x50004000 0x400>;
+                        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
+                        clock-names = "baudclk", "apb_pclk";
                         status = "disabled";
                 };