PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ

The PCIe IP block has an additional clock, "pcie_aux", that needs to
be controlled by the driver. Add code to support it.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org

1 files changed, 17 insertions, 1 deletions

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 64c74334f7d0..f5a16fd15be5 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -66,6 +66,7 @@ struct imx6_pcie {
         struct clk              *pcie_phy;
         struct clk              *pcie_inbound_axi;
         struct clk              *pcie;
+        struct clk              *pcie_aux;
         struct regmap           *iomuxc_gpr;
         u32                     controller_id;
         struct reset_control    *pciephy_reset;
@@ -459,6 +460,12 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
         case IMX7D:
                 break;
         case IMX8MQ:
+                ret = clk_prepare_enable(imx6_pcie->pcie_aux);
+                if (ret) {
+                        dev_err(dev, "unable to enable pcie_aux clock\n");
+                        break;
+                }
+
                 offset = imx6_pcie_grp_offset(imx6_pcie);
                 /*
                  * Set the over ride low and enabled
@@ -976,6 +983,9 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
                                    IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
                                    IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
                 break;
+        case IMX8MQ:
+                clk_disable_unprepare(imx6_pcie->pcie_aux);
+                break;
         default:
                 break;
         }
@@ -1121,8 +1131,14 @@ static int imx6_pcie_probe(struct platform_device *pdev)
                         return PTR_ERR(imx6_pcie->pcie_inbound_axi);
                 }
                 break;
-        case IMX7D:
         case IMX8MQ:
+                imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
+                if (IS_ERR(imx6_pcie->pcie_aux)) {
+                        dev_err(dev, "pcie_aux clock source missing or invalid\n");
+                        return PTR_ERR(imx6_pcie->pcie_aux);
+                }
+                /* fall through */
+        case IMX7D:
                 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
                         imx6_pcie->controller_id = 1;