drm/exynos/mixer: remove mixer_resources sub-structure

mixer_resources adds only unnecessary redirection, removing it makes the
code shorter and cleaner.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

1 files changed, 148 insertions, 176 deletions

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index fba120346189..c0e92021748b 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -67,19 +67,6 @@
 #define MXR_FORMAT_ARGB4444     6
 #define MXR_FORMAT_ARGB8888     7
 
-struct mixer_resources {
-        int                     irq;
-        void __iomem            *mixer_regs;
-        void __iomem            *vp_regs;
-        spinlock_t              reg_slock;
-        struct clk              *mixer;
-        struct clk              *vp;
-        struct clk              *hdmi;
-        struct clk              *sclk_mixer;
-        struct clk              *sclk_hdmi;
-        struct clk              *mout_mixer;
-};
-
 enum mixer_version_id {
         MXR_VER_0_0_0_16,
         MXR_VER_16_0_33_0,
@@ -117,7 +104,16 @@ struct mixer_context {
         struct exynos_drm_plane planes[MIXER_WIN_NR];
         unsigned long           flags;
 
-        struct mixer_resources  mixer_res;
+        int                     irq;
+        void __iomem            *mixer_regs;
+        void __iomem            *vp_regs;
+        spinlock_t              reg_slock;
+        struct clk              *mixer;
+        struct clk              *vp;
+        struct clk              *hdmi;
+        struct clk              *sclk_mixer;
+        struct clk              *sclk_hdmi;
+        struct clk              *mout_mixer;
         enum mixer_version_id   mxr_ver;
 };
 
@@ -194,44 +190,44 @@ static inline bool is_alpha_format(unsigned int pixel_format)
         }
 }
 
-static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id)
+static inline u32 vp_reg_read(struct mixer_context *ctx, u32 reg_id)
 {
-        return readl(res->vp_regs + reg_id);
+        return readl(ctx->vp_regs + reg_id);
 }
 
-static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id,
+static inline void vp_reg_write(struct mixer_context *ctx, u32 reg_id,
                                  u32 val)
 {
-        writel(val, res->vp_regs + reg_id);
+        writel(val, ctx->vp_regs + reg_id);
 }
 
-static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id,
+static inline void vp_reg_writemask(struct mixer_context *ctx, u32 reg_id,
                                  u32 val, u32 mask)
 {
-        u32 old = vp_reg_read(res, reg_id);
+        u32 old = vp_reg_read(ctx, reg_id);
 
         val = (val & mask) | (old & ~mask);
-        writel(val, res->vp_regs + reg_id);
+        writel(val, ctx->vp_regs + reg_id);
 }
 
-static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id)
+static inline u32 mixer_reg_read(struct mixer_context *ctx, u32 reg_id)
 {
-        return readl(res->mixer_regs + reg_id);
+        return readl(ctx->mixer_regs + reg_id);
 }
 
-static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id,
+static inline void mixer_reg_write(struct mixer_context *ctx, u32 reg_id,
                                  u32 val)
 {
-        writel(val, res->mixer_regs + reg_id);
+        writel(val, ctx->mixer_regs + reg_id);
 }
 
-static inline void mixer_reg_writemask(struct mixer_resources *res,
+static inline void mixer_reg_writemask(struct mixer_context *ctx,
                                  u32 reg_id, u32 val, u32 mask)
 {
-        u32 old = mixer_reg_read(res, reg_id);
+        u32 old = mixer_reg_read(ctx, reg_id);
 
         val = (val & mask) | (old & ~mask);
-        writel(val, res->mixer_regs + reg_id);
+        writel(val, ctx->mixer_regs + reg_id);
 }
 
 static void mixer_regs_dump(struct mixer_context *ctx)
@@ -239,7 +235,7 @@ static void mixer_regs_dump(struct mixer_context *ctx)
 #define DUMPREG(reg_id) \
 do { \
         DRM_DEBUG_KMS(#reg_id " = %08x\n", \
-                (u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \
+                (u32)readl(ctx->mixer_regs + reg_id)); \
 } while (0)
 
         DUMPREG(MXR_STATUS);
@@ -271,7 +267,7 @@ static void vp_regs_dump(struct mixer_context *ctx)
 #define DUMPREG(reg_id) \
 do { \
         DRM_DEBUG_KMS(#reg_id " = %08x\n", \
-                (u32) readl(ctx->mixer_res.vp_regs + reg_id)); \
+                (u32) readl(ctx->vp_regs + reg_id)); \
 } while (0)
 
         DUMPREG(VP_ENABLE);
@@ -301,7 +297,7 @@ do { \
 #undef DUMPREG
 }
 
-static inline void vp_filter_set(struct mixer_resources *res,
+static inline void vp_filter_set(struct mixer_context *ctx,
                 int reg_id, const u8 *data, unsigned int size)
 {
         /* assure 4-byte align */
@@ -309,24 +305,23 @@ static inline void vp_filter_set(struct mixer_resources *res,
         for (; size; size -= 4, reg_id += 4, data += 4) {
                 u32 val = (data[0] << 24) |  (data[1] << 16) |
                         (data[2] << 8) | data[3];
-                vp_reg_write(res, reg_id, val);
+                vp_reg_write(ctx, reg_id, val);
         }
 }
 
-static void vp_default_filter(struct mixer_resources *res)
+static void vp_default_filter(struct mixer_context *ctx)
 {
-        vp_filter_set(res, VP_POLY8_Y0_LL,
+        vp_filter_set(ctx, VP_POLY8_Y0_LL,
                 filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
-        vp_filter_set(res, VP_POLY4_Y0_LL,
+        vp_filter_set(ctx, VP_POLY4_Y0_LL,
                 filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
-        vp_filter_set(res, VP_POLY4_C0_LL,
+        vp_filter_set(ctx, VP_POLY4_C0_LL,
                 filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
 }
 
 static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
                                 bool alpha)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
         u32 val;
 
         val  = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
@@ -335,13 +330,12 @@ static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
                 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
                 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
         }
-        mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
+        mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win),
                             val, MXR_GRP_CFG_MISC_MASK);
 }
 
 static void mixer_cfg_vp_blend(struct mixer_context *ctx)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
         u32 val;
 
         /*
@@ -351,25 +345,22 @@ static void mixer_cfg_vp_blend(struct mixer_context *ctx)
          * support blending of the video layer through this.
          */
         val = 0;
-        mixer_reg_write(res, MXR_VIDEO_CFG, val);
+        mixer_reg_write(ctx, MXR_VIDEO_CFG, val);
 }
 
 static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
-
         /* block update on vsync */
-        mixer_reg_writemask(res, MXR_STATUS, enable ?
+        mixer_reg_writemask(ctx, MXR_STATUS, enable ?
                         MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
 
         if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags))
-                vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
+                vp_reg_write(ctx, VP_SHADOW_UPDATE, enable ?
                         VP_SHADOW_UPDATE_ENABLE : 0);
 }
 
 static void mixer_cfg_scan(struct mixer_context *ctx, int width, int height)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
         u32 val;
 
         /* choosing between interlace and progressive mode */
@@ -378,7 +369,7 @@ static void mixer_cfg_scan(struct mixer_context *ctx, int width, int height)
 
         /* setup display size */
         if (ctx->mxr_ver == MXR_VER_128_0_0_184) {
-                mixer_reg_write(&ctx->mixer_res, MXR_RESOLUTION,
+                mixer_reg_write(ctx, MXR_RESOLUTION,
                         MXR_MXR_RES_HEIGHT(height) | MXR_MXR_RES_WIDTH(width));
         } else {
                 /* choosing between proper HD and SD mode */
@@ -394,12 +385,11 @@ static void mixer_cfg_scan(struct mixer_context *ctx, int width, int height)
                         val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
         }
 
-        mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
+        mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_SCAN_MASK);
 }
 
 static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
         u32 val;
 
         switch (height) {
@@ -412,45 +402,44 @@ static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
         default:
                 val = MXR_CFG_RGB709_16_235;
                 /* Configure the BT.709 CSC matrix for full range RGB. */
-                mixer_reg_write(res, MXR_CM_COEFF_Y,
+                mixer_reg_write(ctx, MXR_CM_COEFF_Y,
                         MXR_CSC_CT( 0.184,  0.614,  0.063) |
                         MXR_CM_COEFF_RGB_FULL);
-                mixer_reg_write(res, MXR_CM_COEFF_CB,
+                mixer_reg_write(ctx, MXR_CM_COEFF_CB,
                         MXR_CSC_CT(-0.102, -0.338,  0.440));
-                mixer_reg_write(res, MXR_CM_COEFF_CR,
+                mixer_reg_write(ctx, MXR_CM_COEFF_CR,
                         MXR_CSC_CT( 0.440, -0.399, -0.040));
                 break;
         }
 
-        mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
+        mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
 }
 
 static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
                             unsigned int priority, bool enable)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
         u32 val = enable ? ~0 : 0;
 
         switch (win) {
         case 0:
-                mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
-                mixer_reg_writemask(res, MXR_LAYER_CFG,
+                mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
+                mixer_reg_writemask(ctx, MXR_LAYER_CFG,
                                     MXR_LAYER_CFG_GRP0_VAL(priority),
                                     MXR_LAYER_CFG_GRP0_MASK);
                 break;
         case 1:
-                mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
-                mixer_reg_writemask(res, MXR_LAYER_CFG,
+                mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
+                mixer_reg_writemask(ctx, MXR_LAYER_CFG,
                                     MXR_LAYER_CFG_GRP1_VAL(priority),
                                     MXR_LAYER_CFG_GRP1_MASK);
 
                 break;
         case VP_DEFAULT_WIN:
                 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
-                        vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
-                        mixer_reg_writemask(res, MXR_CFG, val,
+                        vp_reg_writemask(ctx, VP_ENABLE, val, VP_ENABLE_ON);
+                        mixer_reg_writemask(ctx, MXR_CFG, val,
                                 MXR_CFG_VP_ENABLE);
-                        mixer_reg_writemask(res, MXR_LAYER_CFG,
+                        mixer_reg_writemask(ctx, MXR_LAYER_CFG,
                                             MXR_LAYER_CFG_VP_VAL(priority),
                                             MXR_LAYER_CFG_VP_MASK);
                 }
@@ -460,19 +449,16 @@ static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
 
 static void mixer_run(struct mixer_context *ctx)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
-
-        mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
+        mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
 }
 
 static void mixer_stop(struct mixer_context *ctx)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
         int timeout = 20;
 
-        mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN);
+        mixer_reg_writemask(ctx, MXR_STATUS, 0, MXR_STATUS_REG_RUN);
 
-        while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
+        while (!(mixer_reg_read(ctx, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
                         --timeout)
                 usleep_range(10000, 12000);
 }
@@ -496,7 +482,6 @@ static void vp_video_buffer(struct mixer_context *ctx,
 {
         struct exynos_drm_plane_state *state =
                                 to_exynos_plane_state(plane->base.state);
-        struct mixer_resources *res = &ctx->mixer_res;
         struct drm_framebuffer *fb = state->base.fb;
         unsigned int priority = state->base.normalized_zpos + 1;
         unsigned long flags;
@@ -523,55 +508,55 @@ static void vp_video_buffer(struct mixer_context *ctx,
                 chroma_addr[1] = 0;
         }
 
-        spin_lock_irqsave(&res->reg_slock, flags);
+        spin_lock_irqsave(&ctx->reg_slock, flags);
 
         /* interlace or progressive scan mode */
         val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0);
-        vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
+        vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP);
 
         /* setup format */
         val = (is_nv21 ? VP_MODE_NV21 : VP_MODE_NV12);
         val |= (is_tiled ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
-        vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
+        vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_FMT_MASK);
 
         /* setting size of input image */
-        vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
+        vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
                 VP_IMG_VSIZE(fb->height));
         /* chroma plane for NV12/NV21 is half the height of the luma plane */
-        vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) |
+        vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) |
                 VP_IMG_VSIZE(fb->height / 2));
 
-        vp_reg_write(res, VP_SRC_WIDTH, state->src.w);
-        vp_reg_write(res, VP_SRC_HEIGHT, state->src.h);
-        vp_reg_write(res, VP_SRC_H_POSITION,
+        vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w);
+        vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
+        vp_reg_write(ctx, VP_SRC_H_POSITION,
                         VP_SRC_H_POSITION_VAL(state->src.x));
-        vp_reg_write(res, VP_SRC_V_POSITION, state->src.y);
+        vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
 
-        vp_reg_write(res, VP_DST_WIDTH, state->crtc.w);
-        vp_reg_write(res, VP_DST_H_POSITION, state->crtc.x);
+        vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w);
+        vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x);
         if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
-                vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h / 2);
-                vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y / 2);
+                vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2);
+                vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2);
         } else {
-                vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h);
-                vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y);
+                vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h);
+                vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y);
         }
 
-        vp_reg_write(res, VP_H_RATIO, state->h_ratio);
-        vp_reg_write(res, VP_V_RATIO, state->v_ratio);
+        vp_reg_write(ctx, VP_H_RATIO, state->h_ratio);
+        vp_reg_write(ctx, VP_V_RATIO, state->v_ratio);
 
-        vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
+        vp_reg_write(ctx, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
 
         /* set buffer address to vp */
-        vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]);
-        vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]);
-        vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]);
-        vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]);
+        vp_reg_write(ctx, VP_TOP_Y_PTR, luma_addr[0]);
+        vp_reg_write(ctx, VP_BOT_Y_PTR, luma_addr[1]);
+        vp_reg_write(ctx, VP_TOP_C_PTR, chroma_addr[0]);
+        vp_reg_write(ctx, VP_BOT_C_PTR, chroma_addr[1]);
 
         mixer_cfg_layer(ctx, plane->index, priority, true);
         mixer_cfg_vp_blend(ctx);
 
-        spin_unlock_irqrestore(&res->reg_slock, flags);
+        spin_unlock_irqrestore(&ctx->reg_slock, flags);
 
         mixer_regs_dump(ctx);
         vp_regs_dump(ctx);
@@ -579,9 +564,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
 
 static void mixer_layer_update(struct mixer_context *ctx)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
-
-        mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
+        mixer_reg_writemask(ctx, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
 }
 
 static void mixer_graph_buffer(struct mixer_context *ctx,
@@ -589,7 +572,6 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
 {
         struct exynos_drm_plane_state *state =
                                 to_exynos_plane_state(plane->base.state);
-        struct mixer_resources *res = &ctx->mixer_res;
         struct drm_framebuffer *fb = state->base.fb;
         unsigned int priority = state->base.normalized_zpos + 1;
         unsigned long flags;
@@ -634,29 +616,29 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
                 + (state->src.x * fb->format->cpp[0])
                 + (state->src.y * fb->pitches[0]);
 
-        spin_lock_irqsave(&res->reg_slock, flags);
+        spin_lock_irqsave(&ctx->reg_slock, flags);
 
         /* setup format */
-        mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
+        mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win),
                 MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);
 
         /* setup geometry */
-        mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
+        mixer_reg_write(ctx, MXR_GRAPHIC_SPAN(win),
                         fb->pitches[0] / fb->format->cpp[0]);
 
         val  = MXR_GRP_WH_WIDTH(state->src.w);
         val |= MXR_GRP_WH_HEIGHT(state->src.h);
         val |= MXR_GRP_WH_H_SCALE(x_ratio);
         val |= MXR_GRP_WH_V_SCALE(y_ratio);
-        mixer_reg_write(res, MXR_GRAPHIC_WH(win), val);
+        mixer_reg_write(ctx, MXR_GRAPHIC_WH(win), val);
 
         /* setup offsets in display image */
         val  = MXR_GRP_DXY_DX(dst_x_offset);
         val |= MXR_GRP_DXY_DY(dst_y_offset);
-        mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val);
+        mixer_reg_write(ctx, MXR_GRAPHIC_DXY(win), val);
 
         /* set buffer address to mixer */
-        mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr);
+        mixer_reg_write(ctx, MXR_GRAPHIC_BASE(win), dma_addr);
 
         mixer_cfg_layer(ctx, win, priority, true);
         mixer_cfg_gfx_blend(ctx, win, is_alpha_format(fb->format->format));
@@ -666,20 +648,19 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
                 ctx->mxr_ver == MXR_VER_128_0_0_184)
                 mixer_layer_update(ctx);
 
-        spin_unlock_irqrestore(&res->reg_slock, flags);
+        spin_unlock_irqrestore(&ctx->reg_slock, flags);
 
         mixer_regs_dump(ctx);
 }
 
 static void vp_win_reset(struct mixer_context *ctx)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
         unsigned int tries = 100;
 
-        vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING);
+        vp_reg_write(ctx, VP_SRESET, VP_SRESET_PROCESSING);
         while (--tries) {
                 /* waiting until VP_SRESET_PROCESSING is 0 */
-                if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)
+                if (~vp_reg_read(ctx, VP_SRESET) & VP_SRESET_PROCESSING)
                         break;
                 mdelay(10);
         }
@@ -688,57 +669,55 @@ static void vp_win_reset(struct mixer_context *ctx)
 
 static void mixer_win_reset(struct mixer_context *ctx)
 {
-        struct mixer_resources *res = &ctx->mixer_res;
         unsigned long flags;
 
-        spin_lock_irqsave(&res->reg_slock, flags);
+        spin_lock_irqsave(&ctx->reg_slock, flags);
 
-        mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
+        mixer_reg_writemask(ctx, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
 
         /* set output in RGB888 mode */
-        mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);
+        mixer_reg_writemask(ctx, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);
 
         /* 16 beat burst in DMA */
-        mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,
+        mixer_reg_writemask(ctx, MXR_STATUS, MXR_STATUS_16_BURST,
                 MXR_STATUS_BURST_MASK);
 
         /* reset default layer priority */
-        mixer_reg_write(res, MXR_LAYER_CFG, 0);
+        mixer_reg_write(ctx, MXR_LAYER_CFG, 0);
 
         /* set all background colors to RGB (0,0,0) */
-        mixer_reg_write(res, MXR_BG_COLOR0, MXR_YCBCR_VAL(0, 128, 128));
-        mixer_reg_write(res, MXR_BG_COLOR1, MXR_YCBCR_VAL(0, 128, 128));
-        mixer_reg_write(res, MXR_BG_COLOR2, MXR_YCBCR_VAL(0, 128, 128));
+        mixer_reg_write(ctx, MXR_BG_COLOR0, MXR_YCBCR_VAL(0, 128, 128));
+        mixer_reg_write(ctx, MXR_BG_COLOR1, MXR_YCBCR_VAL(0, 128, 128));
+        mixer_reg_write(ctx, MXR_BG_COLOR2, MXR_YCBCR_VAL(0, 128, 128));
 
         if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
                 /* configuration of Video Processor Registers */
                 vp_win_reset(ctx);
-                vp_default_filter(res);
+                vp_default_filter(ctx);
         }
 
         /* disable all layers */
-        mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
-        mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
+        mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
+        mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
         if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags))
-                mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
+                mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
 
         /* set all source image offsets to zero */
-        mixer_reg_write(res, MXR_GRAPHIC_SXY(0), 0);
-        mixer_reg_write(res, MXR_GRAPHIC_SXY(1), 0);
+        mixer_reg_write(ctx, MXR_GRAPHIC_SXY(0), 0);
+        mixer_reg_write(ctx, MXR_GRAPHIC_SXY(1), 0);
 
-        spin_unlock_irqrestore(&res->reg_slock, flags);
+        spin_unlock_irqrestore(&ctx->reg_slock, flags);
 }
 
 static irqreturn_t mixer_irq_handler(int irq, void *arg)
 {
         struct mixer_context *ctx = arg;
-        struct mixer_resources *res = &ctx->mixer_res;
         u32 val, base, shadow;
 
-        spin_lock(&res->reg_slock);
+        spin_lock(&ctx->reg_slock);
 
         /* read interrupt status for handling and clearing flags for VSYNC */
-        val = mixer_reg_read(res, MXR_INT_STATUS);
+        val = mixer_reg_read(ctx, MXR_INT_STATUS);
 
         /* handling VSYNC */
         if (val & MXR_INT_STATUS_VSYNC) {
@@ -748,13 +727,13 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
 
                 /* interlace scan need to check shadow register */
                 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
-                        base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
-                        shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
+                        base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0));
+                        shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0));
                         if (base != shadow)
                                 goto out;
 
-                        base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));
-                        shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
+                        base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(1));
+                        shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(1));
                         if (base != shadow)
                                 goto out;
                 }
@@ -764,9 +743,9 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
 
 out:
         /* clear interrupts */
-        mixer_reg_write(res, MXR_INT_STATUS, val);
+        mixer_reg_write(ctx, MXR_INT_STATUS, val);
 
-        spin_unlock(&res->reg_slock);
+        spin_unlock(&ctx->reg_slock);
 
         return IRQ_HANDLED;
 }
@@ -774,26 +753,25 @@ out:
 static int mixer_resources_init(struct mixer_context *mixer_ctx)
 {
         struct device *dev = &mixer_ctx->pdev->dev;
-        struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
         struct resource *res;
         int ret;
 
-        spin_lock_init(&mixer_res->reg_slock);
+        spin_lock_init(&mixer_ctx->reg_slock);
 
-        mixer_res->mixer = devm_clk_get(dev, "mixer");
-        if (IS_ERR(mixer_res->mixer)) {
+        mixer_ctx->mixer = devm_clk_get(dev, "mixer");
+        if (IS_ERR(mixer_ctx->mixer)) {
                 dev_err(dev, "failed to get clock 'mixer'\n");
                 return -ENODEV;
         }
 
-        mixer_res->hdmi = devm_clk_get(dev, "hdmi");
-        if (IS_ERR(mixer_res->hdmi)) {
+        mixer_ctx->hdmi = devm_clk_get(dev, "hdmi");
+        if (IS_ERR(mixer_ctx->hdmi)) {
                 dev_err(dev, "failed to get clock 'hdmi'\n");
-                return PTR_ERR(mixer_res->hdmi);
+                return PTR_ERR(mixer_ctx->hdmi);
         }
 
-        mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
-        if (IS_ERR(mixer_res->sclk_hdmi)) {
+        mixer_ctx->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
+        if (IS_ERR(mixer_ctx->sclk_hdmi)) {
                 dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
                 return -ENODEV;
         }
@@ -803,9 +781,9 @@ static int mixer_resources_init(struct mixer_context *mixer_ctx)
                 return -ENXIO;
         }
 
-        mixer_res->mixer_regs = devm_ioremap(dev, res->start,
+        mixer_ctx->mixer_regs = devm_ioremap(dev, res->start,
                                                         resource_size(res));
-        if (mixer_res->mixer_regs == NULL) {
+        if (mixer_ctx->mixer_regs == NULL) {
                 dev_err(dev, "register mapping failed.\n");
                 return -ENXIO;
         }
@@ -822,7 +800,7 @@ static int mixer_resources_init(struct mixer_context *mixer_ctx)
                 dev_err(dev, "request interrupt failed.\n");
                 return ret;
         }
-        mixer_res->irq = res->start;
+        mixer_ctx->irq = res->start;
 
         return 0;
 }
@@ -830,30 +808,29 @@ static int mixer_resources_init(struct mixer_context *mixer_ctx)
 static int vp_resources_init(struct mixer_context *mixer_ctx)
 {
         struct device *dev = &mixer_ctx->pdev->dev;
-        struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
         struct resource *res;
 
-        mixer_res->vp = devm_clk_get(dev, "vp");
-        if (IS_ERR(mixer_res->vp)) {
+        mixer_ctx->vp = devm_clk_get(dev, "vp");
+        if (IS_ERR(mixer_ctx->vp)) {
                 dev_err(dev, "failed to get clock 'vp'\n");
                 return -ENODEV;
         }
 
         if (test_bit(MXR_BIT_HAS_SCLK, &mixer_ctx->flags)) {
-                mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
-                if (IS_ERR(mixer_res->sclk_mixer)) {
+                mixer_ctx->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
+                if (IS_ERR(mixer_ctx->sclk_mixer)) {
                         dev_err(dev, "failed to get clock 'sclk_mixer'\n");
                         return -ENODEV;
                 }
-                mixer_res->mout_mixer = devm_clk_get(dev, "mout_mixer");
-                if (IS_ERR(mixer_res->mout_mixer)) {
+                mixer_ctx->mout_mixer = devm_clk_get(dev, "mout_mixer");
+                if (IS_ERR(mixer_ctx->mout_mixer)) {
                         dev_err(dev, "failed to get clock 'mout_mixer'\n");
                         return -ENODEV;
                 }
 
-                if (mixer_res->sclk_hdmi && mixer_res->mout_mixer)
-                        clk_set_parent(mixer_res->mout_mixer,
-                                       mixer_res->sclk_hdmi);
+                if (mixer_ctx->sclk_hdmi && mixer_ctx->mout_mixer)
+                        clk_set_parent(mixer_ctx->mout_mixer,
+                                       mixer_ctx->sclk_hdmi);
         }
 
         res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1);
@@ -862,9 +839,9 @@ static int vp_resources_init(struct mixer_context *mixer_ctx)
                 return -ENXIO;
         }
 
-        mixer_res->vp_regs = devm_ioremap(dev, res->start,
+        mixer_ctx->vp_regs = devm_ioremap(dev, res->start,
                                                         resource_size(res));
-        if (mixer_res->vp_regs == NULL) {
+        if (mixer_ctx->vp_regs == NULL) {
                 dev_err(dev, "register mapping failed.\n");
                 return -ENXIO;
         }
@@ -908,15 +885,14 @@ static void mixer_ctx_remove(struct mixer_context *mixer_ctx)
 static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
 {
         struct mixer_context *mixer_ctx = crtc->ctx;
-        struct mixer_resources *res = &mixer_ctx->mixer_res;
 
         __set_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
         if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
                 return 0;
 
         /* enable vsync interrupt */
-        mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
-        mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
+        mixer_reg_writemask(mixer_ctx, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
+        mixer_reg_writemask(mixer_ctx, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
 
         return 0;
 }
@@ -924,7 +900,6 @@ static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
 static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
 {
         struct mixer_context *mixer_ctx = crtc->ctx;
-        struct mixer_resources *res = &mixer_ctx->mixer_res;
 
         __clear_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
 
@@ -932,8 +907,8 @@ static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
                 return;
 
         /* disable vsync interrupt */
-        mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
-        mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
+        mixer_reg_writemask(mixer_ctx, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
+        mixer_reg_writemask(mixer_ctx, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
 }
 
 static void mixer_atomic_begin(struct exynos_drm_crtc *crtc)
@@ -966,7 +941,6 @@ static void mixer_disable_plane(struct exynos_drm_crtc *crtc,
                                 struct exynos_drm_plane *plane)
 {
         struct mixer_context *mixer_ctx = crtc->ctx;
-        struct mixer_resources *res = &mixer_ctx->mixer_res;
         unsigned long flags;
 
         DRM_DEBUG_KMS("win: %d\n", plane->index);
@@ -974,9 +948,9 @@ static void mixer_disable_plane(struct exynos_drm_crtc *crtc,
         if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
                 return;
 
-        spin_lock_irqsave(&res->reg_slock, flags);
+        spin_lock_irqsave(&mixer_ctx->reg_slock, flags);
         mixer_cfg_layer(mixer_ctx, plane->index, 0, false);
-        spin_unlock_irqrestore(&res->reg_slock, flags);
+        spin_unlock_irqrestore(&mixer_ctx->reg_slock, flags);
 }
 
 static void mixer_atomic_flush(struct exynos_drm_crtc *crtc)
@@ -993,7 +967,6 @@ static void mixer_atomic_flush(struct exynos_drm_crtc *crtc)
 static void mixer_enable(struct exynos_drm_crtc *crtc)
 {
         struct mixer_context *ctx = crtc->ctx;
-        struct mixer_resources *res = &ctx->mixer_res;
 
         if (test_bit(MXR_BIT_POWERED, &ctx->flags))
                 return;
@@ -1004,11 +977,12 @@ static void mixer_enable(struct exynos_drm_crtc *crtc)
 
         mixer_vsync_set_update(ctx, false);
 
-        mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
+        mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
 
         if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) {
-                mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
-                mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
+                mixer_reg_writemask(ctx, MXR_INT_STATUS, ~0,
+                                        MXR_INT_CLEAR_VSYNC);
+                mixer_reg_writemask(ctx, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
         }
         mixer_win_reset(ctx);
 
@@ -1211,14 +1185,13 @@ static int mixer_remove(struct platform_device *pdev)
 static int __maybe_unused exynos_mixer_suspend(struct device *dev)
 {
         struct mixer_context *ctx = dev_get_drvdata(dev);
-        struct mixer_resources *res = &ctx->mixer_res;
 
-        clk_disable_unprepare(res->hdmi);
-        clk_disable_unprepare(res->mixer);
+        clk_disable_unprepare(ctx->hdmi);
+        clk_disable_unprepare(ctx->mixer);
         if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
-                clk_disable_unprepare(res->vp);
+                clk_disable_unprepare(ctx->vp);
                 if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags))
-                        clk_disable_unprepare(res->sclk_mixer);
+                        clk_disable_unprepare(ctx->sclk_mixer);
         }
 
         return 0;
@@ -1227,28 +1200,27 @@ static int __maybe_unused exynos_mixer_suspend(struct device *dev)
 static int __maybe_unused exynos_mixer_resume(struct device *dev)
 {
         struct mixer_context *ctx = dev_get_drvdata(dev);
-        struct mixer_resources *res = &ctx->mixer_res;
         int ret;
 
-        ret = clk_prepare_enable(res->mixer);
+        ret = clk_prepare_enable(ctx->mixer);
         if (ret < 0) {
                 DRM_ERROR("Failed to prepare_enable the mixer clk [%d]\n", ret);
                 return ret;
         }
-        ret = clk_prepare_enable(res->hdmi);
+        ret = clk_prepare_enable(ctx->hdmi);
         if (ret < 0) {
                 DRM_ERROR("Failed to prepare_enable the hdmi clk [%d]\n", ret);
                 return ret;
         }
         if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
-                ret = clk_prepare_enable(res->vp);
+                ret = clk_prepare_enable(ctx->vp);
                 if (ret < 0) {
                         DRM_ERROR("Failed to prepare_enable the vp clk [%d]\n",
                                   ret);
                         return ret;
                 }
                 if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) {
-                        ret = clk_prepare_enable(res->sclk_mixer);
+                        ret = clk_prepare_enable(ctx->sclk_mixer);
                         if (ret < 0) {
                                 DRM_ERROR("Failed to prepare_enable the " \
                                            "sclk_mixer clk [%d]\n",