powerpc/eeh: Cache normal BARs, not windows or IOV BARs

This restricts the EEH address cache to use only the first 7 BARs. This
makes __eeh_addr_cache_insert_dev() ignore PCI bridge window and IOV BARs.
As the result of this change, eeh_addr_cache_get_dev() will return VFs from
VF's resource addresses instead of parent PFs.

This also removes PCI bridge check as we limit __eeh_addr_cache_insert_dev()
to 7 BARs and this effectively excludes PCI bridges from being cached.

Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

1 files changed, 5 insertions, 6 deletions

diff --git a/arch/powerpc/kernel/eeh_cache.c b/arch/powerpc/kernel/eeh_cache.c
index a1e86e172e3c..ddbcfab7efdf 100644
--- a/arch/powerpc/kernel/eeh_cache.c
+++ b/arch/powerpc/kernel/eeh_cache.c
@@ -195,8 +195,11 @@ static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
                 return;
         }
 
-        /* Walk resources on this device, poke them into the tree */
-        for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+        /*
+         * Walk resources on this device, poke the first 7 (6 normal BAR and 1
+         * ROM BAR) into the tree.
+         */
+        for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
                 resource_size_t start = pci_resource_start(dev,i);
                 resource_size_t end = pci_resource_end(dev,i);
                 unsigned long flags = pci_resource_flags(dev,i);
@@ -222,10 +225,6 @@ void eeh_addr_cache_insert_dev(struct pci_dev *dev)
 {
         unsigned long flags;
 
-        /* Ignore PCI bridges */
-        if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
-                return;
-
         spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
         __eeh_addr_cache_insert_dev(dev);
         spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);