diff options
author | Vineet Gupta <vgupta@synopsys.com> | 2017-01-19 20:05:00 -0500 |
---|---|---|
committer | Vineet Gupta <vgupta@synopsys.com> | 2017-01-24 14:05:59 -0500 |
commit | 517e7610d2ce04d1b8d8b6c6d1a36dcce5cac6ab (patch) | |
tree | be95871b4aa158d5bfc410a46d86594618dcb662 | |
parent | 36425cd67052e3becf325fd4d3ba5691791ef7e4 (diff) |
ARCv2: MCIP: update the BCR per current changes
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
-rw-r--r-- | arch/arc/kernel/mcip.c | 3 | ||||
-rw-r--r-- | include/soc/arc/mcip.h | 16 |
2 files changed, 9 insertions, 10 deletions
diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c index 9988b427a1e0..9f6b68fd4f3b 100644 --- a/arch/arc/kernel/mcip.c +++ b/arch/arc/kernel/mcip.c | |||
@@ -93,11 +93,10 @@ static void mcip_probe_n_setup(void) | |||
93 | READ_BCR(ARC_REG_MCIP_BCR, mp); | 93 | READ_BCR(ARC_REG_MCIP_BCR, mp); |
94 | 94 | ||
95 | sprintf(smp_cpuinfo_buf, | 95 | sprintf(smp_cpuinfo_buf, |
96 | "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n", | 96 | "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n", |
97 | mp.ver, mp.num_cores, | 97 | mp.ver, mp.num_cores, |
98 | IS_AVAIL1(mp.ipi, "IPI "), | 98 | IS_AVAIL1(mp.ipi, "IPI "), |
99 | IS_AVAIL1(mp.idu, "IDU "), | 99 | IS_AVAIL1(mp.idu, "IDU "), |
100 | IS_AVAIL1(mp.llm, "LLM "), | ||
101 | IS_AVAIL1(mp.dbg, "DEBUG "), | 100 | IS_AVAIL1(mp.dbg, "DEBUG "), |
102 | IS_AVAIL1(mp.gfrc, "GFRC")); | 101 | IS_AVAIL1(mp.gfrc, "GFRC")); |
103 | 102 | ||
diff --git a/include/soc/arc/mcip.h b/include/soc/arc/mcip.h index 6902c2a8bd23..4b6b489a8d7c 100644 --- a/include/soc/arc/mcip.h +++ b/include/soc/arc/mcip.h | |||
@@ -55,17 +55,17 @@ struct mcip_cmd { | |||
55 | 55 | ||
56 | struct mcip_bcr { | 56 | struct mcip_bcr { |
57 | #ifdef CONFIG_CPU_BIG_ENDIAN | 57 | #ifdef CONFIG_CPU_BIG_ENDIAN |
58 | unsigned int pad3:8, | 58 | unsigned int pad4:6, pw_dom:1, pad3:1, |
59 | idu:1, llm:1, num_cores:6, | 59 | idu:1, pad2:1, num_cores:6, |
60 | iocoh:1, gfrc:1, dbg:1, pad2:1, | 60 | pad:1, gfrc:1, dbg:1, pw:1, |
61 | msg:1, sem:1, ipi:1, pad:1, | 61 | msg:1, sem:1, ipi:1, slv:1, |
62 | ver:8; | 62 | ver:8; |
63 | #else | 63 | #else |
64 | unsigned int ver:8, | 64 | unsigned int ver:8, |
65 | pad:1, ipi:1, sem:1, msg:1, | 65 | slv:1, ipi:1, sem:1, msg:1, |
66 | pad2:1, dbg:1, gfrc:1, iocoh:1, | 66 | pw:1, dbg:1, gfrc:1, pad:1, |
67 | num_cores:6, llm:1, idu:1, | 67 | num_cores:6, pad2:1, idu:1, |
68 | pad3:8; | 68 | pad3:1, pw_dom:1, pad4:6; |
69 | #endif | 69 | #endif |
70 | }; | 70 | }; |
71 | 71 | ||