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authorRoger Quadros <rogerq@ti.com>2014-05-26 04:54:45 -0400
committerRoger Quadros <rogerq@ti.com>2016-04-15 04:53:46 -0400
commit51735caad3db6237fa9d31a2ce8b54cbd42ff6f0 (patch)
treeacb7a7e0d1025abbfa0ef4cfaab0b8fe784e11f6
parentc9711ec5250b22fd94e9b34c17c095e001a90e66 (diff)
mtd: nand: omap: Update DT binding documentation
Add compatible id and interrupts. The NAND interrupts are provided by the GPMC controller node. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--Documentation/devicetree/bindings/mtd/gpmc-nand.txt17
1 files changed, 13 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index fb733c4e1c11..ff3215d20343 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -13,7 +13,11 @@ Documentation/devicetree/bindings/mtd/nand.txt
13 13
14Required properties: 14Required properties:
15 15
16 - reg: The CS line the peripheral is connected to 16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
18 NAND I/O space
19 - interrupt-parent: must point to gpmc node
20 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
17 21
18Optional properties: 22Optional properties:
19 23
@@ -55,17 +59,22 @@ Example for an AM33xx board:
55 gpmc: gpmc@50000000 { 59 gpmc: gpmc@50000000 {
56 compatible = "ti,am3352-gpmc"; 60 compatible = "ti,am3352-gpmc";
57 ti,hwmods = "gpmc"; 61 ti,hwmods = "gpmc";
58 reg = <0x50000000 0x1000000>; 62 reg = <0x50000000 0x36c>;
59 interrupts = <100>; 63 interrupts = <100>;
60 gpmc,num-cs = <8>; 64 gpmc,num-cs = <8>;
61 gpmc,num-waitpins = <2>; 65 gpmc,num-waitpins = <2>;
62 #address-cells = <2>; 66 #address-cells = <2>;
63 #size-cells = <1>; 67 #size-cells = <1>;
64 ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */ 68 ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */
65 elm_id = <&elm>; 69 elm_id = <&elm>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
66 72
67 nand@0,0 { 73 nand@0,0 {
68 reg = <0 0 0>; /* CS0, offset 0 */ 74 compatible = "ti,omap2-nand";
75 reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */
76 interrupt-parent = <&gpmc>;
77 interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;
69 nand-bus-width = <16>; 78 nand-bus-width = <16>;
70 ti,nand-ecc-opt = "bch8"; 79 ti,nand-ecc-opt = "bch8";
71 ti,nand-xfer-type = "polled"; 80 ti,nand-xfer-type = "polled";