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authorRex Zhu <Rex.Zhu@amd.com>2017-09-20 05:26:03 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 15:14:34 -0400
commit515113f5e5835ee3ecb00d3da292ca67b5e7a972 (patch)
treea3df44cad7a6ef3676a08c625c997d160dd63828
parent95175869bd309c77f8391c6ea2c2ba440d7f9af7 (diff)
drm/amd/powerplay: delete SMUM_READ_FIELD
repeated defining in hwmgr.h Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smumgr.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c6
4 files changed, 5 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index b742c22bb69b..ebe988b3ecdb 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -167,8 +167,6 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
167 (((value) & SMUM_FIELD_MASK(reg, field)) \ 167 (((value) & SMUM_FIELD_MASK(reg, field)) \
168 >> SMUM_FIELD_SHIFT(reg, field)) 168 >> SMUM_FIELD_SHIFT(reg, field))
169 169
170#define SMUM_READ_FIELD(device, reg, field) \
171 SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
172 170
173#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \ 171#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
174 SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 172 SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
index 445829d329d0..bad9bf2bcb5a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
@@ -219,7 +219,7 @@ int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
219 219
220 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); 220 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
221 221
222 ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); 222 ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
223 223
224 if (ret != 1) 224 if (ret != 1)
225 pr_info("\n failed to send message %x ret is %d\n", msg, ret); 225 pr_info("\n failed to send message %x ret is %d\n", msg, ret);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
index d0913a6696fd..c92ea38d2e15 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
@@ -866,7 +866,7 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
866 866
867 if (mclk_stutter_mode_threshold && 867 if (mclk_stutter_mode_threshold &&
868 (clock <= mclk_stutter_mode_threshold) && 868 (clock <= mclk_stutter_mode_threshold) &&
869 (SMUM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, 869 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
870 STUTTER_ENABLE) & 0x1)) 870 STUTTER_ENABLE) & 0x1))
871 mem_level->StutterEnable = true; 871 mem_level->StutterEnable = true;
872 872
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 89e2464860f0..2ae05bbdb974 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -172,7 +172,7 @@ int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
172 172
173 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); 173 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
174 174
175 ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); 175 ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
176 176
177 if (ret != 1) 177 if (ret != 1)
178 pr_info("\n failed to send pre message %x ret is %d \n", msg, ret); 178 pr_info("\n failed to send pre message %x ret is %d \n", msg, ret);
@@ -181,7 +181,7 @@ int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
181 181
182 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); 182 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
183 183
184 ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); 184 ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
185 185
186 if (ret != 1) 186 if (ret != 1)
187 pr_info("\n failed to send message %x ret is %d \n", msg, ret); 187 pr_info("\n failed to send message %x ret is %d \n", msg, ret);
@@ -224,7 +224,7 @@ int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)
224 224
225 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); 225 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
226 226
227 if (1 != SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP)) 227 if (1 != PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP))
228 pr_info("Failed to send Message.\n"); 228 pr_info("Failed to send Message.\n");
229 229
230 return 0; 230 return 0;