Merge branch 'drm-next-4.21' of git://people.freedesktop.org/~agd5f/linux into drm-next

amdgpu and amdkfd:
- Freesync support
- ABM support in DC
- KFD support for vega12 and polaris12
- Add sdma paging queue support for vega
- Use ACPI to query backlight range on supported platforms
- Clean up doorbell handling
- KFD fix for pasid handling under non-HWS
- Misc cleanups and fixes

scheduler:
- Revert "fix timeout handling v2"

radeon:
- Fix possible overflow on 32 bit

ttm:
- Fix for LRU handling for ghost objects

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130192505.2946-1-alexander.deucher@amd.com

103 files changed, 2895 insertions, 1461 deletions

diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 4b1501b4835b..8da2a178cf85 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -575,6 +575,13 @@ Explicit Fencing Properties
 .. kernel-doc:: drivers/gpu/drm/drm_atomic_uapi.c
    :doc: explicit fencing properties
 
+
+Variable Refresh Properties
+---------------------------
+
+.. kernel-doc:: drivers/gpu/drm/drm_connector.c
+   :doc: Variable refresh properties
+
 Existing KMS Properties
 -----------------------
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 42f882c633ee..c8ad6bf6618a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -81,6 +81,7 @@
 #include "amdgpu_job.h"
 #include "amdgpu_bo_list.h"
 #include "amdgpu_gem.h"
+#include "amdgpu_doorbell.h"
 
 #define MAX_GPU_INSTANCE                16
 
@@ -361,123 +362,6 @@ int amdgpu_fence_slab_init(void);
 void amdgpu_fence_slab_fini(void);
 
 /*
- * GPU doorbell structures, functions & helpers
- */
-typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
-{
-        AMDGPU_DOORBELL_KIQ                     = 0x000,
-        AMDGPU_DOORBELL_HIQ                     = 0x001,
-        AMDGPU_DOORBELL_DIQ                     = 0x002,
-        AMDGPU_DOORBELL_MEC_RING0               = 0x010,
-        AMDGPU_DOORBELL_MEC_RING1               = 0x011,
-        AMDGPU_DOORBELL_MEC_RING2               = 0x012,
-        AMDGPU_DOORBELL_MEC_RING3               = 0x013,
-        AMDGPU_DOORBELL_MEC_RING4               = 0x014,
-        AMDGPU_DOORBELL_MEC_RING5               = 0x015,
-        AMDGPU_DOORBELL_MEC_RING6               = 0x016,
-        AMDGPU_DOORBELL_MEC_RING7               = 0x017,
-        AMDGPU_DOORBELL_GFX_RING0               = 0x020,
-        AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,
-        AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,
-        AMDGPU_DOORBELL_IH                      = 0x1E8,
-        AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,
-        AMDGPU_DOORBELL_INVALID                 = 0xFFFF
-} AMDGPU_DOORBELL_ASSIGNMENT;
-
-struct amdgpu_doorbell {
-        /* doorbell mmio */
-        resource_size_t         base;
-        resource_size_t         size;
-        u32 __iomem             *ptr;
-        u32                     num_doorbells;  /* Number of doorbells actually reserved for amdgpu. */
-};
-
-/*
- * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
- */
-typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
-{
-        /*
-         * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
-         * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
-         *  Compute related doorbells are allocated from 0x00 to 0x8a
-         */
-
-
-        /* kernel scheduling */
-        AMDGPU_DOORBELL64_KIQ                     = 0x00,
-
-        /* HSA interface queue and debug queue */
-        AMDGPU_DOORBELL64_HIQ                     = 0x01,
-        AMDGPU_DOORBELL64_DIQ                     = 0x02,
-
-        /* Compute engines */
-        AMDGPU_DOORBELL64_MEC_RING0               = 0x03,
-        AMDGPU_DOORBELL64_MEC_RING1               = 0x04,
-        AMDGPU_DOORBELL64_MEC_RING2               = 0x05,
-        AMDGPU_DOORBELL64_MEC_RING3               = 0x06,
-        AMDGPU_DOORBELL64_MEC_RING4               = 0x07,
-        AMDGPU_DOORBELL64_MEC_RING5               = 0x08,
-        AMDGPU_DOORBELL64_MEC_RING6               = 0x09,
-        AMDGPU_DOORBELL64_MEC_RING7               = 0x0a,
-
-        /* User queue doorbell range (128 doorbells) */
-        AMDGPU_DOORBELL64_USERQUEUE_START         = 0x0b,
-        AMDGPU_DOORBELL64_USERQUEUE_END           = 0x8a,
-
-        /* Graphics engine */
-        AMDGPU_DOORBELL64_GFX_RING0               = 0x8b,
-
-        /*
-         * Other graphics doorbells can be allocated here: from 0x8c to 0xdf
-         * Graphics voltage island aperture 1
-         * default non-graphics QWORD index is 0xe0 - 0xFF inclusive
-         */
-
-        /* sDMA engines  reserved from 0xe0 -0xef  */
-        AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xE0,
-        AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xE1,
-        AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,
-        AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9,
-
-        /* For vega10 sriov, the sdma doorbell must be fixed as follow
-         * to keep the same setting with host driver, or it will
-         * happen conflicts
-         */
-        AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0            = 0xF0,
-        AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
-        AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1            = 0xF2,
-        AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
-
-        /* Interrupt handler */
-        AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
-        AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */
-        AMDGPU_DOORBELL64_IH_RING2                = 0xF6,  /* For page migration translation/invalidation log */
-
-        /* VCN engine use 32 bits doorbell  */
-        AMDGPU_DOORBELL64_VCN0_1                  = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
-        AMDGPU_DOORBELL64_VCN2_3                  = 0xF9,
-        AMDGPU_DOORBELL64_VCN4_5                  = 0xFA,
-        AMDGPU_DOORBELL64_VCN6_7                  = 0xFB,
-
-        /* overlap the doorbell assignment with VCN as they are  mutually exclusive
-         * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
-         */
-        AMDGPU_DOORBELL64_UVD_RING0_1             = 0xF8,
-        AMDGPU_DOORBELL64_UVD_RING2_3             = 0xF9,
-        AMDGPU_DOORBELL64_UVD_RING4_5             = 0xFA,
-        AMDGPU_DOORBELL64_UVD_RING6_7             = 0xFB,
-
-        AMDGPU_DOORBELL64_VCE_RING0_1             = 0xFC,
-        AMDGPU_DOORBELL64_VCE_RING2_3             = 0xFD,
-        AMDGPU_DOORBELL64_VCE_RING4_5             = 0xFE,
-        AMDGPU_DOORBELL64_VCE_RING6_7             = 0xFF,
-
-        AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,
-        AMDGPU_DOORBELL64_INVALID                 = 0xFFFF
-} AMDGPU_DOORBELL64_ASSIGNMENT;
-
-/*
  * IRQS.
  */
 
@@ -654,6 +538,8 @@ struct amdgpu_asic_funcs {
                                struct amdgpu_ring *ring);
         /* check if the asic needs a full reset of if soft reset will work */
         bool (*need_full_reset)(struct amdgpu_device *adev);
+        /* initialize doorbell layout for specific asic*/
+        void (*init_doorbell_index)(struct amdgpu_device *adev);
 };
 
 /*
@@ -1023,6 +909,8 @@ struct amdgpu_device {
         unsigned long last_mm_index;
         bool                            in_gpu_reset;
         struct mutex  lock_reset;
+        struct amdgpu_doorbell_index doorbell_index;
+        int asic_reset_res;
 };
 
 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -1047,11 +935,6 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
 
-u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
-void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
-u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
-void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
-
 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
 
@@ -1113,11 +996,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
 
-#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
-#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
-#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
-#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
-
 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
 
@@ -1159,6 +1037,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
+#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
 
 /* Common functions */
 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
@@ -1219,12 +1098,6 @@ void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
                              unsigned long arg);
 
-
-/*
- * functions used by amdgpu_xgmi.c
- */
-int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
-
 /*
  * functions used by amdgpu_encoder.c
  */
@@ -1252,6 +1125,9 @@ bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *ade
 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
                                                 u8 perf_req, bool advertise);
 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
+
+void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
+                struct amdgpu_dm_backlight_caps *caps);
 #else
 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 7f0afc526419..47db65926d71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -41,28 +41,21 @@ struct amdgpu_atif_notification_cfg {
 };
 
 struct amdgpu_atif_notifications {
-        bool display_switch;
-        bool expansion_mode_change;
         bool thermal_state;
         bool forced_power_state;
         bool system_power_state;
-        bool display_conf_change;
-        bool px_gfx_switch;
         bool brightness_change;
         bool dgpu_display_event;
+        bool gpu_package_power_limit;
 };
 
 struct amdgpu_atif_functions {
         bool system_params;
         bool sbios_requests;
-        bool select_active_disp;
-        bool lid_state;
-        bool get_tv_standard;
-        bool set_tv_standard;
-        bool get_panel_expansion_mode;
-        bool set_panel_expansion_mode;
         bool temperature_change;
-        bool graphics_device_types;
+        bool query_backlight_transfer_characteristics;
+        bool ready_to_undock;
+        bool external_gpu_information;
 };
 
 struct amdgpu_atif {
@@ -72,6 +65,7 @@ struct amdgpu_atif {
         struct amdgpu_atif_functions functions;
         struct amdgpu_atif_notification_cfg notification_cfg;
         struct amdgpu_encoder *encoder_for_bl;
+        struct amdgpu_dm_backlight_caps backlight_caps;
 };
 
 /* Call the ATIF method
@@ -137,15 +131,12 @@ static union acpi_object *amdgpu_atif_call(struct amdgpu_atif *atif,
  */
 static void amdgpu_atif_parse_notification(struct amdgpu_atif_notifications *n, u32 mask)
 {
-        n->display_switch = mask & ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED;
-        n->expansion_mode_change = mask & ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED;
         n->thermal_state = mask & ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED;
         n->forced_power_state = mask & ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED;
         n->system_power_state = mask & ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED;
-        n->display_conf_change = mask & ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED;
-        n->px_gfx_switch = mask & ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED;
         n->brightness_change = mask & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED;
         n->dgpu_display_event = mask & ATIF_DGPU_DISPLAY_EVENT_SUPPORTED;
+        n->gpu_package_power_limit = mask & ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST_SUPPORTED;
 }
 
 /**
@@ -162,14 +153,11 @@ static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mas
 {
         f->system_params = mask & ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED;
         f->sbios_requests = mask & ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED;
-        f->select_active_disp = mask & ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED;
-        f->lid_state = mask & ATIF_GET_LID_STATE_SUPPORTED;
-        f->get_tv_standard = mask & ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED;
-        f->set_tv_standard = mask & ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED;
-        f->get_panel_expansion_mode = mask & ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED;
-        f->set_panel_expansion_mode = mask & ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED;
         f->temperature_change = mask & ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED;
-        f->graphics_device_types = mask & ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED;
+        f->query_backlight_transfer_characteristics =
+                mask & ATIF_QUERY_BACKLIGHT_TRANSFER_CHARACTERISTICS_SUPPORTED;
+        f->ready_to_undock = mask & ATIF_READY_TO_UNDOCK_NOTIFICATION_SUPPORTED;
+        f->external_gpu_information = mask & ATIF_GET_EXTERNAL_GPU_INFORMATION_SUPPORTED;
 }
 
 /**
@@ -311,6 +299,65 @@ out:
 }
 
 /**
+ * amdgpu_atif_query_backlight_caps - get min and max backlight input signal
+ *
+ * @handle: acpi handle
+ *
+ * Execute the QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS ATIF function
+ * to determine the acceptable range of backlight values
+ *
+ * Backlight_caps.caps_valid will be set to true if the query is successful
+ *
+ * The input signals are in range 0-255
+ *
+ * This function assumes the display with backlight is the first LCD
+ *
+ * Returns 0 on success, error on failure.
+ */
+static int amdgpu_atif_query_backlight_caps(struct amdgpu_atif *atif)
+{
+        union acpi_object *info;
+        struct atif_qbtc_output characteristics;
+        struct atif_qbtc_arguments arguments;
+        struct acpi_buffer params;
+        size_t size;
+        int err = 0;
+
+        arguments.size = sizeof(arguments);
+        arguments.requested_display = ATIF_QBTC_REQUEST_LCD1;
+
+        params.length = sizeof(arguments);
+        params.pointer = (void *)&arguments;
+
+        info = amdgpu_atif_call(atif,
+                ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS,
+                &params);
+        if (!info) {
+                err = -EIO;
+                goto out;
+        }
+
+        size = *(u16 *) info->buffer.pointer;
+        if (size < 10) {
+                err = -EINVAL;
+                goto out;
+        }
+
+        memset(&characteristics, 0, sizeof(characteristics));
+        size = min(sizeof(characteristics), size);
+        memcpy(&characteristics, info->buffer.pointer, size);
+
+        atif->backlight_caps.caps_valid = true;
+        atif->backlight_caps.min_input_signal =
+                        characteristics.min_input_signal;
+        atif->backlight_caps.max_input_signal =
+                        characteristics.max_input_signal;
+out:
+        kfree(info);
+        return err;
+}
+
+/**
  * amdgpu_atif_get_sbios_requests - get requested sbios event
  *
  * @handle: acpi handle
@@ -799,6 +846,17 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
                 }
         }
 
+        if (atif->functions.query_backlight_transfer_characteristics) {
+                ret = amdgpu_atif_query_backlight_caps(atif);
+                if (ret) {
+                        DRM_DEBUG_DRIVER("Call to QUERY_BACKLIGHT_TRANSFER_CHARACTERISTICS failed: %d\n",
+                                        ret);
+                        atif->backlight_caps.caps_valid = false;
+                }
+        } else {
+                atif->backlight_caps.caps_valid = false;
+        }
+
 out:
         adev->acpi_nb.notifier_call = amdgpu_acpi_event;
         register_acpi_notifier(&adev->acpi_nb);
@@ -806,6 +864,18 @@ out:
         return ret;
 }
 
+void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
+                struct amdgpu_dm_backlight_caps *caps)
+{
+        if (!adev->atif) {
+                caps->caps_valid = false;
+                return;
+        }
+        caps->caps_valid = adev->atif->backlight_caps.caps_valid;
+        caps->min_input_signal = adev->atif->backlight_caps.min_input_signal;
+        caps->max_input_signal = adev->atif->backlight_caps.max_input_signal;
+}
+
 /**
  * amdgpu_acpi_fini - tear down driver acpi support
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index bcf1666fb31d..d693b8047653 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -73,9 +73,11 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
         case CHIP_FIJI:
         case CHIP_POLARIS10:
         case CHIP_POLARIS11:
+        case CHIP_POLARIS12:
                 kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
                 break;
         case CHIP_VEGA10:
+        case CHIP_VEGA12:
         case CHIP_VEGA20:
         case CHIP_RAVEN:
                 kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
@@ -179,25 +181,14 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                          * process in case of 64-bit doorbells so we
                          * can use each doorbell assignment twice.
                          */
-                        if (adev->asic_type == CHIP_VEGA10) {
-                                gpu_resources.sdma_doorbell[0][i] =
-                                        AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
-                                gpu_resources.sdma_doorbell[0][i+1] =
-                                        AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
-                                gpu_resources.sdma_doorbell[1][i] =
-                                        AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
-                                gpu_resources.sdma_doorbell[1][i+1] =
-                                        AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
-                        } else {
-                                gpu_resources.sdma_doorbell[0][i] =
-                                        AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
-                                gpu_resources.sdma_doorbell[0][i+1] =
-                                        AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
-                                gpu_resources.sdma_doorbell[1][i] =
-                                        AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
-                                gpu_resources.sdma_doorbell[1][i+1] =
-                                        AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
-                        }
+                        gpu_resources.sdma_doorbell[0][i] =
+                                adev->doorbell_index.sdma_engine0 + (i >> 1);
+                        gpu_resources.sdma_doorbell[0][i+1] =
+                                adev->doorbell_index.sdma_engine0 + 0x200 + (i >> 1);
+                        gpu_resources.sdma_doorbell[1][i] =
+                                adev->doorbell_index.sdma_engine1 + (i >> 1);
+                        gpu_resources.sdma_doorbell[1][i+1] =
+                                adev->doorbell_index.sdma_engine1 + 0x200 + (i >> 1);
                 }
                 /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
                  * SDMA, IH and VCN. So don't use them for the CP.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index df0a059565f9..f3129b912714 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -46,9 +46,9 @@
 /* Impose limit on how much memory KFD can use */
 static struct {
         uint64_t max_system_mem_limit;
-        uint64_t max_userptr_mem_limit;
+        uint64_t max_ttm_mem_limit;
         int64_t system_mem_used;
-        int64_t userptr_mem_used;
+        int64_t ttm_mem_used;
         spinlock_t mem_limit_lock;
 } kfd_mem_limit;
 
@@ -90,8 +90,8 @@ static bool check_if_add_bo_to_vm(struct amdgpu_vm *avm,
 }
 
 /* Set memory usage limits. Current, limits are
- *  System (kernel) memory - 3/8th System RAM
- *  Userptr memory - 3/4th System RAM
+ *  System (TTM + userptr) memory - 3/4th System RAM
+ *  TTM memory - 3/8th System RAM
  */
 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
 {
@@ -103,48 +103,54 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
         mem *= si.mem_unit;
 
         spin_lock_init(&kfd_mem_limit.mem_limit_lock);
-        kfd_mem_limit.max_system_mem_limit = (mem >> 1) - (mem >> 3);
-        kfd_mem_limit.max_userptr_mem_limit = mem - (mem >> 2);
-        pr_debug("Kernel memory limit %lluM, userptr limit %lluM\n",
+        kfd_mem_limit.max_system_mem_limit = (mem >> 1) + (mem >> 2);
+        kfd_mem_limit.max_ttm_mem_limit = (mem >> 1) - (mem >> 3);
+        pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
                 (kfd_mem_limit.max_system_mem_limit >> 20),
-                (kfd_mem_limit.max_userptr_mem_limit >> 20));
+                (kfd_mem_limit.max_ttm_mem_limit >> 20));
 }
 
 static int amdgpu_amdkfd_reserve_system_mem_limit(struct amdgpu_device *adev,
-                                              uint64_t size, u32 domain)
+                uint64_t size, u32 domain, bool sg)
 {
-        size_t acc_size;
+        size_t acc_size, system_mem_needed, ttm_mem_needed;
         int ret = 0;
 
         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
                                        sizeof(struct amdgpu_bo));
 
         spin_lock(&kfd_mem_limit.mem_limit_lock);
+
         if (domain == AMDGPU_GEM_DOMAIN_GTT) {
-                if (kfd_mem_limit.system_mem_used + (acc_size + size) >
-                        kfd_mem_limit.max_system_mem_limit) {
-                        ret = -ENOMEM;
-                        goto err_no_mem;
-                }
-                kfd_mem_limit.system_mem_used += (acc_size + size);
-        } else if (domain == AMDGPU_GEM_DOMAIN_CPU) {
-                if ((kfd_mem_limit.system_mem_used + acc_size >
-                        kfd_mem_limit.max_system_mem_limit) ||
-                        (kfd_mem_limit.userptr_mem_used + (size + acc_size) >
-                        kfd_mem_limit.max_userptr_mem_limit)) {
-                        ret = -ENOMEM;
-                        goto err_no_mem;
-                }
-                kfd_mem_limit.system_mem_used += acc_size;
-                kfd_mem_limit.userptr_mem_used += size;
+                /* TTM GTT memory */
+                system_mem_needed = acc_size + size;
+                ttm_mem_needed = acc_size + size;
+        } else if (domain == AMDGPU_GEM_DOMAIN_CPU && !sg) {
+                /* Userptr */
+                system_mem_needed = acc_size + size;
+                ttm_mem_needed = acc_size;
+        } else {
+                /* VRAM and SG */
+                system_mem_needed = acc_size;
+                ttm_mem_needed = acc_size;
         }
-err_no_mem:
+
+        if ((kfd_mem_limit.system_mem_used + system_mem_needed >
+                kfd_mem_limit.max_system_mem_limit) ||
+                (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
+                kfd_mem_limit.max_ttm_mem_limit))
+                ret = -ENOMEM;
+        else {
+                kfd_mem_limit.system_mem_used += system_mem_needed;
+                kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
+        }
+
         spin_unlock(&kfd_mem_limit.mem_limit_lock);
         return ret;
 }
 
 static void unreserve_system_mem_limit(struct amdgpu_device *adev,
-                                       uint64_t size, u32 domain)
+                uint64_t size, u32 domain, bool sg)
 {
         size_t acc_size;
 
@@ -154,14 +160,18 @@ static void unreserve_system_mem_limit(struct amdgpu_device *adev,
         spin_lock(&kfd_mem_limit.mem_limit_lock);
         if (domain == AMDGPU_GEM_DOMAIN_GTT) {
                 kfd_mem_limit.system_mem_used -= (acc_size + size);
-        } else if (domain == AMDGPU_GEM_DOMAIN_CPU) {
+                kfd_mem_limit.ttm_mem_used -= (acc_size + size);
+        } else if (domain == AMDGPU_GEM_DOMAIN_CPU && !sg) {
+                kfd_mem_limit.system_mem_used -= (acc_size + size);
+                kfd_mem_limit.ttm_mem_used -= acc_size;
+        } else {
                 kfd_mem_limit.system_mem_used -= acc_size;
-                kfd_mem_limit.userptr_mem_used -= size;
+                kfd_mem_limit.ttm_mem_used -= acc_size;
         }
         WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
                   "kfd system memory accounting unbalanced");
-        WARN_ONCE(kfd_mem_limit.userptr_mem_used < 0,
-                  "kfd userptr memory accounting unbalanced");
+        WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
+                  "kfd TTM memory accounting unbalanced");
 
         spin_unlock(&kfd_mem_limit.mem_limit_lock);
 }
@@ -171,16 +181,22 @@ void amdgpu_amdkfd_unreserve_system_memory_limit(struct amdgpu_bo *bo)
         spin_lock(&kfd_mem_limit.mem_limit_lock);
 
         if (bo->flags & AMDGPU_AMDKFD_USERPTR_BO) {
-                kfd_mem_limit.system_mem_used -= bo->tbo.acc_size;
-                kfd_mem_limit.userptr_mem_used -= amdgpu_bo_size(bo);
+                kfd_mem_limit.system_mem_used -=
+                        (bo->tbo.acc_size + amdgpu_bo_size(bo));
+                kfd_mem_limit.ttm_mem_used -= bo->tbo.acc_size;
         } else if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT) {
                 kfd_mem_limit.system_mem_used -=
                         (bo->tbo.acc_size + amdgpu_bo_size(bo));
+                kfd_mem_limit.ttm_mem_used -=
+                        (bo->tbo.acc_size + amdgpu_bo_size(bo));
+        } else {
+                kfd_mem_limit.system_mem_used -= bo->tbo.acc_size;
+                kfd_mem_limit.ttm_mem_used -= bo->tbo.acc_size;
         }
         WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
                   "kfd system memory accounting unbalanced");
-        WARN_ONCE(kfd_mem_limit.userptr_mem_used < 0,
-                  "kfd userptr memory accounting unbalanced");
+        WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
+                  "kfd TTM memory accounting unbalanced");
 
         spin_unlock(&kfd_mem_limit.mem_limit_lock);
 }
@@ -395,23 +411,6 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
         return 0;
 }
 
-static int sync_vm_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
-                         struct dma_fence *f)
-{
-        int ret = amdgpu_sync_fence(adev, sync, f, false);
-
-        /* Sync objects can't handle multiple GPUs (contexts) updating
-         * sync->last_vm_update. Fortunately we don't need it for
-         * KFD's purposes, so we can just drop that fence.
-         */
-        if (sync->last_vm_update) {
-                dma_fence_put(sync->last_vm_update);
-                sync->last_vm_update = NULL;
-        }
-
-        return ret;
-}
-
 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
 {
         struct amdgpu_bo *pd = vm->root.base.bo;
@@ -422,7 +421,7 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
         if (ret)
                 return ret;
 
-        return sync_vm_fence(adev, sync, vm->last_update);
+        return amdgpu_sync_fence(NULL, sync, vm->last_update, false);
 }
 
 /* add_bo_to_vm - Add a BO to a VM
@@ -826,7 +825,7 @@ static int unmap_bo_from_gpuvm(struct amdgpu_device *adev,
         /* Add the eviction fence back */
         amdgpu_bo_fence(pd, &vm->process_info->eviction_fence->base, true);
 
-        sync_vm_fence(adev, sync, bo_va->last_pt_update);
+        amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);
 
         return 0;
 }
@@ -851,7 +850,7 @@ static int update_gpuvm_pte(struct amdgpu_device *adev,
                 return ret;
         }
 
-        return sync_vm_fence(adev, sync, bo_va->last_pt_update);
+        return amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);
 }
 
 static int map_bo_to_gpuvm(struct amdgpu_device *adev,
@@ -901,6 +900,26 @@ static int process_validate_vms(struct amdkfd_process_info *process_info)
         return 0;
 }
 
+static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
+                                 struct amdgpu_sync *sync)
+{
+        struct amdgpu_vm *peer_vm;
+        int ret;
+
+        list_for_each_entry(peer_vm, &process_info->vm_list_head,
+                            vm_list_node) {
+                struct amdgpu_bo *pd = peer_vm->root.base.bo;
+
+                ret = amdgpu_sync_resv(NULL,
+                                        sync, pd->tbo.resv,
+                                        AMDGPU_FENCE_OWNER_UNDEFINED, false);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
 static int process_update_pds(struct amdkfd_process_info *process_info,
                               struct amdgpu_sync *sync)
 {
@@ -1199,7 +1218,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
         byte_align = (adev->family == AMDGPU_FAMILY_VI &&
                         adev->asic_type != CHIP_FIJI &&
                         adev->asic_type != CHIP_POLARIS10 &&
-                        adev->asic_type != CHIP_POLARIS11) ?
+                        adev->asic_type != CHIP_POLARIS11 &&
+                        adev->asic_type != CHIP_POLARIS12) ?
                         VI_BO_SIZE_ALIGN : 1;
 
         mapping_flags = AMDGPU_VM_PAGE_READABLE;
@@ -1215,10 +1235,11 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 
         amdgpu_sync_create(&(*mem)->sync);
 
-        ret = amdgpu_amdkfd_reserve_system_mem_limit(adev, size, alloc_domain);
+        ret = amdgpu_amdkfd_reserve_system_mem_limit(adev, size,
+                                                     alloc_domain, false);
         if (ret) {
                 pr_debug("Insufficient system memory\n");
-                goto err_reserve_system_mem;
+                goto err_reserve_limit;
         }
 
         pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
@@ -1266,10 +1287,10 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 allocate_init_user_pages_failed:
         amdgpu_bo_unref(&bo);
         /* Don't unreserve system mem limit twice */
-        goto err_reserve_system_mem;
+        goto err_reserve_limit;
 err_bo_create:
-        unreserve_system_mem_limit(adev, size, alloc_domain);
-err_reserve_system_mem:
+        unreserve_system_mem_limit(adev, size, alloc_domain, false);
+err_reserve_limit:
         mutex_destroy(&(*mem)->lock);
         kfree(*mem);
         return ret;
@@ -1405,7 +1426,8 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
          * the queues are still stopped and we can leave mapping for
          * the next restore worker
          */
-        if (bo->tbo.mem.mem_type == TTM_PL_SYSTEM)
+        if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
+            bo->tbo.mem.mem_type == TTM_PL_SYSTEM)
                 is_invalid_userptr = true;
 
         if (check_if_add_bo_to_vm(avm, mem)) {
@@ -2044,13 +2066,10 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
         if (ret)
                 goto validate_map_fail;
 
-        /* Wait for PD/PTs validate to finish */
-        /* FIXME: I think this isn't needed */
-        list_for_each_entry(peer_vm, &process_info->vm_list_head,
-                            vm_list_node) {
-                struct amdgpu_bo *bo = peer_vm->root.base.bo;
-
-                ttm_bo_wait(&bo->tbo, false, false);
+        ret = process_sync_pds_resv(process_info, &sync_obj);
+        if (ret) {
+                pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
+                goto validate_map_fail;
         }
 
         /* Validate BOs and map them to GPUVM (update VM page tables). */
@@ -2066,7 +2085,11 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
                         pr_debug("Memory eviction: Validate BOs failed. Try again\n");
                         goto validate_map_fail;
                 }
-
+                ret = amdgpu_sync_fence(NULL, &sync_obj, bo->tbo.moving, false);
+                if (ret) {
+                        pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
+                        goto validate_map_fail;
+                }
                 list_for_each_entry(bo_va_entry, &mem->bo_va_list,
                                     bo_list) {
                         ret = update_gpuvm_pte((struct amdgpu_device *)
@@ -2087,6 +2110,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
                 goto validate_map_fail;
         }
 
+        /* Wait for validate and PT updates to finish */
         amdgpu_sync_wait(&sync_obj, false);
 
         /* Release old eviction fence and create new one, because fence only
@@ -2105,10 +2129,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
         process_info->eviction_fence = new_fence;
         *ef = dma_fence_get(&new_fence->base);
 
-        /* Wait for validate to finish and attach new eviction fence */
-        list_for_each_entry(mem, &process_info->kfd_bo_list,
-                validate_list.head)
-                ttm_bo_wait(&mem->bo->tbo, false, false);
+        /* Attach new eviction fence to all BOs */
         list_for_each_entry(mem, &process_info->kfd_bo_list,
                 validate_list.head)
                 amdgpu_bo_fence(mem->bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 0c590ddf250a..5b550706ee76 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -43,7 +43,7 @@ int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo **bo
         r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
                                 domain, bo,
                                 NULL, &ptr);
-        if (!bo)
+        if (!*bo)
                 return -ENOMEM;
 
         memset(ptr, 0, size);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index f9b54236102d..95f4c4139fc6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -39,6 +39,7 @@ const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = {
         [AMDGPU_HW_IP_UVD_ENC]  =       1,
         [AMDGPU_HW_IP_VCN_DEC]  =       1,
         [AMDGPU_HW_IP_VCN_ENC]  =       1,
+        [AMDGPU_HW_IP_VCN_JPEG] =       1,
 };
 
 static int amdgput_ctx_total_num_entities(void)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 590588a82471..c75badfa5c4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -59,6 +59,8 @@
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_pm.h"
 
+#include "amdgpu_xgmi.h"
+
 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
@@ -513,6 +515,8 @@ void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
  */
 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 {
+        amdgpu_asic_init_doorbell_index(adev);
+
         /* No doorbell on SI hardware generation */
         if (adev->asic_type < CHIP_BONAIRE) {
                 adev->doorbell.base = 0;
@@ -530,10 +534,19 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 
         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
-                                             AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
+                                             adev->doorbell_index.max_assignment+1);
         if (adev->doorbell.num_doorbells == 0)
                 return -EINVAL;
 
+        /* For Vega, reserve and map two pages on doorbell BAR since SDMA
+         * paging queue doorbell use the second page. The
+         * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
+         * doorbells are in the first page. So with paging queue enabled,
+         * the max num_doorbells should + 1 page (0x400 in dword)
+         */
+        if (adev->asic_type >= CHIP_VEGA10)
+                adev->doorbell.num_doorbells += 0x400;
+
         adev->doorbell.ptr = ioremap(adev->doorbell.base,
                                      adev->doorbell.num_doorbells *
                                      sizeof(u32));
@@ -2458,9 +2471,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
 
-        /* doorbell bar mapping */
-        amdgpu_device_doorbell_init(adev);
-
         /* io port mapping */
         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
@@ -2479,6 +2489,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
         if (r)
                 return r;
 
+        /* doorbell bar mapping and doorbell index init*/
+        amdgpu_device_doorbell_init(adev);
+
         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
         /* this will fail for cards that aren't VGA class devices, just
          * ignore it */
@@ -3151,86 +3164,6 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
         return 0;
 }
 
-/**
- * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
- *
- * @adev: amdgpu device pointer
- *
- * attempt to do soft-reset or full-reset and reinitialize Asic
- * return 0 means succeeded otherwise failed
- */
-static int amdgpu_device_reset(struct amdgpu_device *adev)
-{
-        bool need_full_reset, vram_lost = 0;
-        int r;
-
-        need_full_reset = amdgpu_device_ip_need_full_reset(adev);
-
-        if (!need_full_reset) {
-                amdgpu_device_ip_pre_soft_reset(adev);
-                r = amdgpu_device_ip_soft_reset(adev);
-                amdgpu_device_ip_post_soft_reset(adev);
-                if (r || amdgpu_device_ip_check_soft_reset(adev)) {
-                        DRM_INFO("soft reset failed, will fallback to full reset!\n");
-                        need_full_reset = true;
-                }
-        }
-
-        if (need_full_reset) {
-                r = amdgpu_device_ip_suspend(adev);
-
-retry:
-                r = amdgpu_asic_reset(adev);
-                /* post card */
-                amdgpu_atom_asic_init(adev->mode_info.atom_context);
-
-                if (!r) {
-                        dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
-                        r = amdgpu_device_ip_resume_phase1(adev);
-                        if (r)
-                                goto out;
-
-                        vram_lost = amdgpu_device_check_vram_lost(adev);
-                        if (vram_lost) {
-                                DRM_ERROR("VRAM is lost!\n");
-                                atomic_inc(&adev->vram_lost_counter);
-                        }
-
-                        r = amdgpu_gtt_mgr_recover(
-                                &adev->mman.bdev.man[TTM_PL_TT]);
-                        if (r)
-                                goto out;
-
-                        r = amdgpu_device_fw_loading(adev);
-                        if (r)
-                                return r;
-
-                        r = amdgpu_device_ip_resume_phase2(adev);
-                        if (r)
-                                goto out;
-
-                        if (vram_lost)
-                                amdgpu_device_fill_reset_magic(adev);
-                }
-        }
-
-out:
-        if (!r) {
-                amdgpu_irq_gpu_reset_resume_helper(adev);
-                r = amdgpu_ib_ring_tests(adev);
-                if (r) {
-                        dev_err(adev->dev, "ib ring test failed (%d).\n", r);
-                        r = amdgpu_device_ip_suspend(adev);
-                        need_full_reset = true;
-                        goto retry;
-                }
-        }
-
-        if (!r)
-                r = amdgpu_device_recover_vram(adev);
-
-        return r;
-}
 
 /**
  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
@@ -3329,31 +3262,13 @@ disabled:
                 return false;
 }
 
-/**
- * amdgpu_device_gpu_recover - reset the asic and recover scheduler
- *
- * @adev: amdgpu device pointer
- * @job: which job trigger hang
- *
- * Attempt to reset the GPU if it has hung (all asics).
- * Returns 0 for success or an error on failure.
- */
-int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
-                              struct amdgpu_job *job)
-{
-        int i, r, resched;
 
-        dev_info(adev->dev, "GPU reset begin!\n");
-
-        mutex_lock(&adev->lock_reset);
-        atomic_inc(&adev->gpu_reset_counter);
-        adev->in_gpu_reset = 1;
-
-        /* Block kfd */
-        amdgpu_amdkfd_pre_reset(adev);
-
-        /* block TTM */
-        resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
+static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
+                                        struct amdgpu_job *job,
+                                        bool *need_full_reset_arg)
+{
+        int i, r = 0;
+        bool need_full_reset  = *need_full_reset_arg;
 
         /* block all schedulers and reset given job's ring */
         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
@@ -3373,10 +3288,123 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
                 amdgpu_fence_driver_force_completion(ring);
         }
 
-        if (amdgpu_sriov_vf(adev))
-                r = amdgpu_device_reset_sriov(adev, job ? false : true);
-        else
-                r = amdgpu_device_reset(adev);
+
+
+        if (!amdgpu_sriov_vf(adev)) {
+
+                if (!need_full_reset)
+                        need_full_reset = amdgpu_device_ip_need_full_reset(adev);
+
+                if (!need_full_reset) {
+                        amdgpu_device_ip_pre_soft_reset(adev);
+                        r = amdgpu_device_ip_soft_reset(adev);
+                        amdgpu_device_ip_post_soft_reset(adev);
+                        if (r || amdgpu_device_ip_check_soft_reset(adev)) {
+                                DRM_INFO("soft reset failed, will fallback to full reset!\n");
+                                need_full_reset = true;
+                        }
+                }
+
+                if (need_full_reset)
+                        r = amdgpu_device_ip_suspend(adev);
+
+                *need_full_reset_arg = need_full_reset;
+        }
+
+        return r;
+}
+
+static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
+                               struct list_head *device_list_handle,
+                               bool *need_full_reset_arg)
+{
+        struct amdgpu_device *tmp_adev = NULL;
+        bool need_full_reset = *need_full_reset_arg, vram_lost = false;
+        int r = 0;
+
+        /*
+         * ASIC reset has to be done on all HGMI hive nodes ASAP
+         * to allow proper links negotiation in FW (within 1 sec)
+         */
+        if (need_full_reset) {
+                list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+                        r = amdgpu_asic_reset(tmp_adev);
+                        if (r)
+                                DRM_WARN("ASIC reset failed with err r, %d for drm dev, %s",
+                                         r, tmp_adev->ddev->unique);
+                }
+        }
+
+
+        list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+                if (need_full_reset) {
+                        /* post card */
+                        if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
+                                DRM_WARN("asic atom init failed!");
+
+                        if (!r) {
+                                dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
+                                r = amdgpu_device_ip_resume_phase1(tmp_adev);
+                                if (r)
+                                        goto out;
+
+                                vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
+                                if (vram_lost) {
+                                        DRM_ERROR("VRAM is lost!\n");
+                                        atomic_inc(&tmp_adev->vram_lost_counter);
+                                }
+
+                                r = amdgpu_gtt_mgr_recover(
+                                        &tmp_adev->mman.bdev.man[TTM_PL_TT]);
+                                if (r)
+                                        goto out;
+
+                                r = amdgpu_device_fw_loading(tmp_adev);
+                                if (r)
+                                        return r;
+
+                                r = amdgpu_device_ip_resume_phase2(tmp_adev);
+                                if (r)
+                                        goto out;
+
+                                if (vram_lost)
+                                        amdgpu_device_fill_reset_magic(tmp_adev);
+
+                                /* Update PSP FW topology after reset */
+                                if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
+                                        r = amdgpu_xgmi_update_topology(hive, tmp_adev);
+                        }
+                }
+
+
+out:
+                if (!r) {
+                        amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
+                        r = amdgpu_ib_ring_tests(tmp_adev);
+                        if (r) {
+                                dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
+                                r = amdgpu_device_ip_suspend(tmp_adev);
+                                need_full_reset = true;
+                                r = -EAGAIN;
+                                goto end;
+                        }
+                }
+
+                if (!r)
+                        r = amdgpu_device_recover_vram(tmp_adev);
+                else
+                        tmp_adev->asic_reset_res = r;
+        }
+
+end:
+        *need_full_reset_arg = need_full_reset;
+        return r;
+}
+
+static void amdgpu_device_post_asic_reset(struct amdgpu_device *adev,
+                                          struct amdgpu_job *job)
+{
+        int i;
 
         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
                 struct amdgpu_ring *ring = adev->rings[i];
@@ -3388,7 +3416,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
                  * or all rings (in the case @job is NULL)
                  * after above amdgpu_reset accomplished
                  */
-                if ((!job || job->base.sched == &ring->sched) && !r)
+                if ((!job || job->base.sched == &ring->sched) && !adev->asic_reset_res)
                         drm_sched_job_recovery(&ring->sched);
 
                 kthread_unpark(ring->sched.thread);
@@ -3398,21 +3426,144 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
                 drm_helper_resume_force_mode(adev->ddev);
         }
 
-        ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
+        adev->asic_reset_res = 0;
+}
 
-        if (r) {
-                /* bad news, how to tell it to userspace ? */
-                dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
-                amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
-        } else {
-                dev_info(adev->dev, "GPU reset(%d) succeeded!\n",atomic_read(&adev->gpu_reset_counter));
-        }
+static void amdgpu_device_lock_adev(struct amdgpu_device *adev)
+{
+        mutex_lock(&adev->lock_reset);
+        atomic_inc(&adev->gpu_reset_counter);
+        adev->in_gpu_reset = 1;
+        /* Block kfd */
+        amdgpu_amdkfd_pre_reset(adev);
+}
 
+static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
+{
         /*unlock kfd */
         amdgpu_amdkfd_post_reset(adev);
         amdgpu_vf_error_trans_all(adev);
         adev->in_gpu_reset = 0;
         mutex_unlock(&adev->lock_reset);
+}
+
+
+/**
+ * amdgpu_device_gpu_recover - reset the asic and recover scheduler
+ *
+ * @adev: amdgpu device pointer
+ * @job: which job trigger hang
+ *
+ * Attempt to reset the GPU if it has hung (all asics).
+ * Attempt to do soft-reset or full-reset and reinitialize Asic
+ * Returns 0 for success or an error on failure.
+ */
+
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+                              struct amdgpu_job *job)
+{
+        int r;
+        struct amdgpu_hive_info *hive = NULL;
+        bool need_full_reset = false;
+        struct amdgpu_device *tmp_adev = NULL;
+        struct list_head device_list, *device_list_handle =  NULL;
+
+        INIT_LIST_HEAD(&device_list);
+
+        dev_info(adev->dev, "GPU reset begin!\n");
+
+        /*
+         * In case of XGMI hive disallow concurrent resets to be triggered
+         * by different nodes. No point also since the one node already executing
+         * reset will also reset all the other nodes in the hive.
+         */
+        hive = amdgpu_get_xgmi_hive(adev);
+        if (hive && adev->gmc.xgmi.num_physical_nodes > 1 &&
+            !mutex_trylock(&hive->hive_lock))
+                return 0;
+
+        /* Start with adev pre asic reset first for soft reset check.*/
+        amdgpu_device_lock_adev(adev);
+        r = amdgpu_device_pre_asic_reset(adev,
+                                         job,
+                                         &need_full_reset);
+        if (r) {
+                /*TODO Should we stop ?*/
+                DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
+                          r, adev->ddev->unique);
+                adev->asic_reset_res = r;
+        }
+
+        /* Build list of devices to reset */
+        if  (need_full_reset && adev->gmc.xgmi.num_physical_nodes > 1) {
+                if (!hive) {
+                        amdgpu_device_unlock_adev(adev);
+                        return -ENODEV;
+                }
+
+                /*
+                 * In case we are in XGMI hive mode device reset is done for all the
+                 * nodes in the hive to retrain all XGMI links and hence the reset
+                 * sequence is executed in loop on all nodes.
+                 */
+                device_list_handle = &hive->device_list;
+        } else {
+                list_add_tail(&adev->gmc.xgmi.head, &device_list);
+                device_list_handle = &device_list;
+        }
+
+retry:  /* Rest of adevs pre asic reset from XGMI hive. */
+        list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+
+                if (tmp_adev == adev)
+                        continue;
+
+                dev_info(tmp_adev->dev, "GPU reset begin for drm dev %s!\n", adev->ddev->unique);
+
+                amdgpu_device_lock_adev(tmp_adev);
+                r = amdgpu_device_pre_asic_reset(tmp_adev,
+                                                 NULL,
+                                                 &need_full_reset);
+                /*TODO Should we stop ?*/
+                if (r) {
+                        DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
+                                  r, tmp_adev->ddev->unique);
+                        tmp_adev->asic_reset_res = r;
+                }
+        }
+
+        /* Actual ASIC resets if needed.*/
+        /* TODO Implement XGMI hive reset logic for SRIOV */
+        if (amdgpu_sriov_vf(adev)) {
+                r = amdgpu_device_reset_sriov(adev, job ? false : true);
+                if (r)
+                        adev->asic_reset_res = r;
+        } else {
+                r  = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
+                if (r && r == -EAGAIN)
+                        goto retry;
+        }
+
+        /* Post ASIC reset for all devs .*/
+        list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+                amdgpu_device_post_asic_reset(tmp_adev, tmp_adev == adev ? job : NULL);
+
+                if (r) {
+                        /* bad news, how to tell it to userspace ? */
+                        dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
+                        amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
+                } else {
+                        dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
+                }
+
+                amdgpu_device_unlock_adev(tmp_adev);
+        }
+
+        if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
+                mutex_unlock(&hive->hive_lock);
+
+        if (r)
+                dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
         return r;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 686a26de50f9..15ce7e681d67 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -631,6 +631,11 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
                         drm_property_create_range(adev->ddev, 0, "max bpc", 8, 16);
                 if (!adev->mode_info.max_bpc_property)
                         return -ENOMEM;
+                adev->mode_info.abm_level_property =
+                        drm_property_create_range(adev->ddev, 0,
+                                                "abm level", 0, 4);
+                if (!adev->mode_info.abm_level_property)
+                        return -ENOMEM;
         }
 
         return 0;
@@ -857,7 +862,12 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
         if (in_vbl && (*vpos >= vbl_start)) {
                 vtotal = mode->crtc_vtotal;
-                *vpos = *vpos - vtotal;
+
+                /* With variable refresh rate displays the vpos can exceed
+                 * the vtotal value. Clamp to 0 to return -vbl_end instead
+                 * of guessing the remaining number of lines until scanout.
+                 */
+                *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
         }
 
         /* Correct for shifted end of vbl at vbl_end. */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
new file mode 100644
index 000000000000..be620b29f4aa
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * GPU doorbell structures, functions & helpers
+ */
+struct amdgpu_doorbell {
+        /* doorbell mmio */
+        resource_size_t         base;
+        resource_size_t         size;
+        u32 __iomem             *ptr;
+        u32                     num_doorbells;  /* Number of doorbells actually reserved for amdgpu. */
+};
+
+/* Reserved doorbells for amdgpu (including multimedia).
+ * KFD can use all the rest in the 2M doorbell bar.
+ * For asic before vega10, doorbell is 32-bit, so the
+ * index/offset is in dword. For vega10 and after, doorbell
+ * can be 64-bit, so the index defined is in qword.
+ */
+struct amdgpu_doorbell_index {
+        uint32_t kiq;
+        uint32_t mec_ring0;
+        uint32_t mec_ring1;
+        uint32_t mec_ring2;
+        uint32_t mec_ring3;
+        uint32_t mec_ring4;
+        uint32_t mec_ring5;
+        uint32_t mec_ring6;
+        uint32_t mec_ring7;
+        uint32_t userqueue_start;
+        uint32_t userqueue_end;
+        uint32_t gfx_ring0;
+        uint32_t sdma_engine0;
+        uint32_t sdma_engine1;
+        uint32_t sdma_engine2;
+        uint32_t sdma_engine3;
+        uint32_t sdma_engine4;
+        uint32_t sdma_engine5;
+        uint32_t sdma_engine6;
+        uint32_t sdma_engine7;
+        uint32_t ih;
+        union {
+                struct {
+                        uint32_t vcn_ring0_1;
+                        uint32_t vcn_ring2_3;
+                        uint32_t vcn_ring4_5;
+                        uint32_t vcn_ring6_7;
+                } vcn;
+                struct {
+                        uint32_t uvd_ring0_1;
+                        uint32_t uvd_ring2_3;
+                        uint32_t uvd_ring4_5;
+                        uint32_t uvd_ring6_7;
+                        uint32_t vce_ring0_1;
+                        uint32_t vce_ring2_3;
+                        uint32_t vce_ring4_5;
+                        uint32_t vce_ring6_7;
+                } uvd_vce;
+        };
+        uint32_t max_assignment;
+};
+
+typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
+{
+        AMDGPU_DOORBELL_KIQ                     = 0x000,
+        AMDGPU_DOORBELL_HIQ                     = 0x001,
+        AMDGPU_DOORBELL_DIQ                     = 0x002,
+        AMDGPU_DOORBELL_MEC_RING0               = 0x010,
+        AMDGPU_DOORBELL_MEC_RING1               = 0x011,
+        AMDGPU_DOORBELL_MEC_RING2               = 0x012,
+        AMDGPU_DOORBELL_MEC_RING3               = 0x013,
+        AMDGPU_DOORBELL_MEC_RING4               = 0x014,
+        AMDGPU_DOORBELL_MEC_RING5               = 0x015,
+        AMDGPU_DOORBELL_MEC_RING6               = 0x016,
+        AMDGPU_DOORBELL_MEC_RING7               = 0x017,
+        AMDGPU_DOORBELL_GFX_RING0               = 0x020,
+        AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,
+        AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,
+        AMDGPU_DOORBELL_IH                      = 0x1E8,
+        AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,
+        AMDGPU_DOORBELL_INVALID                 = 0xFFFF
+} AMDGPU_DOORBELL_ASSIGNMENT;
+
+typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
+{
+        /* Compute + GFX: 0~255 */
+        AMDGPU_VEGA20_DOORBELL_KIQ                     = 0x000,
+        AMDGPU_VEGA20_DOORBELL_HIQ                     = 0x001,
+        AMDGPU_VEGA20_DOORBELL_DIQ                     = 0x002,
+        AMDGPU_VEGA20_DOORBELL_MEC_RING0               = 0x003,
+        AMDGPU_VEGA20_DOORBELL_MEC_RING1               = 0x004,
+        AMDGPU_VEGA20_DOORBELL_MEC_RING2               = 0x005,
+        AMDGPU_VEGA20_DOORBELL_MEC_RING3               = 0x006,
+        AMDGPU_VEGA20_DOORBELL_MEC_RING4               = 0x007,
+        AMDGPU_VEGA20_DOORBELL_MEC_RING5               = 0x008,
+        AMDGPU_VEGA20_DOORBELL_MEC_RING6               = 0x009,
+        AMDGPU_VEGA20_DOORBELL_MEC_RING7               = 0x00A,
+        AMDGPU_VEGA20_DOORBELL_USERQUEUE_START         = 0x00B,
+        AMDGPU_VEGA20_DOORBELL_USERQUEUE_END           = 0x08A,
+        AMDGPU_VEGA20_DOORBELL_GFX_RING0               = 0x08B,
+        /* SDMA:256~335*/
+        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0            = 0x100,
+        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1            = 0x10A,
+        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2            = 0x114,
+        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3            = 0x11E,
+        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4            = 0x128,
+        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5            = 0x132,
+        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6            = 0x13C,
+        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7            = 0x146,
+        /* IH: 376~391 */
+        AMDGPU_VEGA20_DOORBELL_IH                      = 0x178,
+        /* MMSCH: 392~407
+         * overlap the doorbell assignment with VCN as they are  mutually exclusive
+         * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
+         */
+        AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
+        AMDGPU_VEGA20_DOORBELL64_VCN2_3                  = 0x189,
+        AMDGPU_VEGA20_DOORBELL64_VCN4_5                  = 0x18A,
+        AMDGPU_VEGA20_DOORBELL64_VCN6_7                  = 0x18B,
+
+        AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1             = 0x188,
+        AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3             = 0x189,
+        AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5             = 0x18A,
+        AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7             = 0x18B,
+
+        AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1             = 0x18C,
+        AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3             = 0x18D,
+        AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5             = 0x18E,
+        AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7             = 0x18F,
+        AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT            = 0x18F,
+        AMDGPU_VEGA20_DOORBELL_INVALID                   = 0xFFFF
+} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
+
+/*
+ * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
+ */
+typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
+{
+        /*
+         * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
+         * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
+         *  Compute related doorbells are allocated from 0x00 to 0x8a
+         */
+
+
+        /* kernel scheduling */
+        AMDGPU_DOORBELL64_KIQ                     = 0x00,
+
+        /* HSA interface queue and debug queue */
+        AMDGPU_DOORBELL64_HIQ                     = 0x01,
+        AMDGPU_DOORBELL64_DIQ                     = 0x02,
+
+        /* Compute engines */
+        AMDGPU_DOORBELL64_MEC_RING0               = 0x03,
+        AMDGPU_DOORBELL64_MEC_RING1               = 0x04,
+        AMDGPU_DOORBELL64_MEC_RING2               = 0x05,
+        AMDGPU_DOORBELL64_MEC_RING3               = 0x06,
+        AMDGPU_DOORBELL64_MEC_RING4               = 0x07,
+        AMDGPU_DOORBELL64_MEC_RING5               = 0x08,
+        AMDGPU_DOORBELL64_MEC_RING6               = 0x09,
+        AMDGPU_DOORBELL64_MEC_RING7               = 0x0a,
+
+        /* User queue doorbell range (128 doorbells) */
+        AMDGPU_DOORBELL64_USERQUEUE_START         = 0x0b,
+        AMDGPU_DOORBELL64_USERQUEUE_END           = 0x8a,
+
+        /* Graphics engine */
+        AMDGPU_DOORBELL64_GFX_RING0               = 0x8b,
+
+        /*
+         * Other graphics doorbells can be allocated here: from 0x8c to 0xdf
+         * Graphics voltage island aperture 1
+         * default non-graphics QWORD index is 0xe0 - 0xFF inclusive
+         */
+
+        /* For vega10 sriov, the sdma doorbell must be fixed as follow
+         * to keep the same setting with host driver, or it will
+         * happen conflicts
+         */
+        AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xF0,
+        AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
+        AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xF2,
+        AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
+
+        /* Interrupt handler */
+        AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
+        AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */
+        AMDGPU_DOORBELL64_IH_RING2                = 0xF6,  /* For page migration translation/invalidation log */
+
+        /* VCN engine use 32 bits doorbell  */
+        AMDGPU_DOORBELL64_VCN0_1                  = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
+        AMDGPU_DOORBELL64_VCN2_3                  = 0xF9,
+        AMDGPU_DOORBELL64_VCN4_5                  = 0xFA,
+        AMDGPU_DOORBELL64_VCN6_7                  = 0xFB,
+
+        /* overlap the doorbell assignment with VCN as they are  mutually exclusive
+         * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
+         */
+        AMDGPU_DOORBELL64_UVD_RING0_1             = 0xF8,
+        AMDGPU_DOORBELL64_UVD_RING2_3             = 0xF9,
+        AMDGPU_DOORBELL64_UVD_RING4_5             = 0xFA,
+        AMDGPU_DOORBELL64_UVD_RING6_7             = 0xFB,
+
+        AMDGPU_DOORBELL64_VCE_RING0_1             = 0xFC,
+        AMDGPU_DOORBELL64_VCE_RING2_3             = 0xFD,
+        AMDGPU_DOORBELL64_VCE_RING4_5             = 0xFE,
+        AMDGPU_DOORBELL64_VCE_RING6_7             = 0xFF,
+
+        AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,
+        AMDGPU_DOORBELL64_INVALID                 = 0xFFFF
+} AMDGPU_DOORBELL64_ASSIGNMENT;
+
+u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
+void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
+u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
+void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
+
+#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
+#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
+#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
+#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
+
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8de55f7f1a3a..90f474f98b6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -454,9 +454,10 @@ module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
 
 /**
  * DOC: param_buf_per_se (int)
- * Override the size of Off-Chip Pramater Cache per Shader Engine in Byte. The default is 0 (depending on gfx).
+ * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte.
+ * The default is 0 (depending on gfx).
  */
-MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
+MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
 
 /**
@@ -1220,9 +1221,6 @@ static struct drm_driver kms_driver = {
         .patchlevel = KMS_DRIVER_PATCHLEVEL,
 };
 
-static struct drm_driver *driver;
-static struct pci_driver *pdriver;
-
 static struct pci_driver amdgpu_kms_pci_driver = {
         .name = DRIVER_NAME,
         .id_table = pciidlist,
@@ -1252,16 +1250,14 @@ static int __init amdgpu_init(void)
                 goto error_fence;
 
         DRM_INFO("amdgpu kernel modesetting enabled.\n");
-        driver = &kms_driver;
-        pdriver = &amdgpu_kms_pci_driver;
-        driver->num_ioctls = amdgpu_max_kms_ioctl;
+        kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
         amdgpu_register_atpx_handler();
 
         /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
         amdgpu_amdkfd_init();
 
         /* let modprobe override vga console setting */
-        return pci_register_driver(pdriver);
+        return pci_register_driver(&amdgpu_kms_pci_driver);
 
 error_fence:
         amdgpu_sync_fini();
@@ -1273,7 +1269,7 @@ error_sync:
 static void __exit amdgpu_exit(void)
 {
         amdgpu_amdkfd_fini();
-        pci_unregister_driver(pdriver);
+        pci_unregister_driver(&amdgpu_kms_pci_driver);
         amdgpu_unregister_atpx_handler();
         amdgpu_sync_fini();
         amdgpu_fence_slab_fini();
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 6a70c0b7105f..97a60da62004 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -250,7 +250,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
         ring->adev = NULL;
         ring->ring_obj = NULL;
         ring->use_doorbell = true;
-        ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
+        ring->doorbell_index = adev->doorbell_index.kiq;
 
         r = amdgpu_gfx_kiq_acquire(adev, ring);
         if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 9b3164c0f861..bc62bf41b7e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -467,9 +467,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
         if (!info->return_size || !info->return_pointer)
                 return -EINVAL;
 
-        /* Ensure IB tests are run on ring */
-        flush_delayed_work(&adev->late_init_work);
-
         switch (info->query) {
         case AMDGPU_INFO_ACCEL_WORKING:
                 ui32 = adev->accel_working;
@@ -950,6 +947,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
         struct amdgpu_fpriv *fpriv;
         int r, pasid;
 
+        /* Ensure IB tests are run on ring */
+        flush_delayed_work(&adev->late_init_work);
+
         file_priv->driver_priv = NULL;
 
         r = pm_runtime_get_sync(dev->dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 0dc2c5c57015..aadd0fa42e43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -38,7 +38,6 @@
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_plane_helper.h>
-#include <drm/drm_fb_helper.h>
 #include <linux/i2c.h>
 #include <linux/i2c-algo-bit.h>
 #include <linux/hrtimer.h>
@@ -294,13 +293,6 @@ struct amdgpu_display_funcs {
                               uint16_t connector_object_id,
                               struct amdgpu_hpd *hpd,
                               struct amdgpu_router *router);
-        /* it is used to enter or exit into free sync mode */
-        int (*notify_freesync)(struct drm_device *dev, void *data,
-                               struct drm_file *filp);
-        /* it is used to allow enablement of freesync mode */
-        int (*set_freesync_property)(struct drm_connector *connector,
-                                     struct drm_property *property,
-                                     uint64_t val);
 
 
 };
@@ -340,6 +332,8 @@ struct amdgpu_mode_info {
         struct drm_property *dither_property;
         /* maximum number of bits per channel for monitor color */
         struct drm_property *max_bpc_property;
+        /* Adaptive Backlight Modulation (power feature) */
+        struct drm_property *abm_level_property;
         /* hardcoded DFP edid from BIOS */
         struct edid *bios_hardcoded_edid;
         int bios_hardcoded_edid_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 7235cd0b0fa9..1f61ed95727c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -33,6 +33,8 @@
 #include <linux/hwmon.h>
 #include <linux/hwmon-sysfs.h>
 #include <linux/nospec.h>
+#include "hwmgr.h"
+#define WIDTH_4K 3840
 
 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
 
@@ -1642,6 +1644,19 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
                 return 0;
 
+        /* Skip fan attributes on APU */
+        if ((adev->flags & AMD_IS_APU) &&
+            (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
+             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
+             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
+             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
+             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
+             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
+             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
+             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
+             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
+                return 0;
+
         /* Skip limit attributes if DPM is not enabled */
         if (!adev->pm.dpm_enabled &&
             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
@@ -1956,6 +1971,17 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
                 mutex_unlock(&adev->pm.mutex);
         }
+        /* enable/disable Low Memory PState for UVD (4k videos) */
+        if (adev->asic_type == CHIP_STONEY &&
+                adev->uvd.decode_image_width >= WIDTH_4K) {
+                struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
+
+                if (hwmgr && hwmgr->hwmgr_func &&
+                    hwmgr->hwmgr_func->update_nbdpm_pstate)
+                        hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
+                                                               !enable,
+                                                               true);
+        }
 }
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 69896f451e8a..4e5d13e41f6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -692,6 +692,8 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
         buf_sizes[0x1] = dpb_size;
         buf_sizes[0x2] = image_size;
         buf_sizes[0x4] = min_ctx_size;
+        /* store image width to adjust nb memory pstate */
+        adev->uvd.decode_image_width = width;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index a3ab1a41060f..5eb63288d157 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -65,6 +65,8 @@ struct amdgpu_uvd {
         struct drm_sched_entity entity;
         struct delayed_work     idle_work;
         unsigned                harvest_config;
+        /* store image width to adjust nb memory state */
+        unsigned                decode_image_width;
 };
 
 int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index cfee74732edb..462a04e0f5e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -334,7 +334,7 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
 
         if (adev->fw_vram_usage.va != NULL) {
                 adev->virt.fw_reserve.p_pf2vf =
-                        (struct amdgim_pf2vf_info_header *)(
+                        (struct amd_sriov_msg_pf2vf_info_header *)(
                         adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
                 AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
                 AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 0728fbc9a692..722deefc0a7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -63,8 +63,8 @@ struct amdgpu_virt_ops {
  * Firmware Reserve Frame buffer
  */
 struct amdgpu_virt_fw_reserve {
-        struct amdgim_pf2vf_info_header *p_pf2vf;
-        struct amdgim_vf2pf_info_header *p_vf2pf;
+        struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
+        struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
         unsigned int checksum_key;
 };
 /*
@@ -85,15 +85,17 @@ enum AMDGIM_FEATURE_FLAG {
         AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
 };
 
-struct amdgim_pf2vf_info_header {
+struct amd_sriov_msg_pf2vf_info_header {
         /* the total structure size in byte. */
         uint32_t size;
         /* version of this structure, written by the GIM */
         uint32_t version;
+        /* reserved */
+        uint32_t reserved[2];
 } __aligned(4);
 struct  amdgim_pf2vf_info_v1 {
         /* header contains size and version */
-        struct amdgim_pf2vf_info_header header;
+        struct amd_sriov_msg_pf2vf_info_header header;
         /* max_width * max_height */
         unsigned int uvd_enc_max_pixels_count;
         /* 16x16 pixels/sec, codec independent */
@@ -112,7 +114,7 @@ struct  amdgim_pf2vf_info_v1 {
 
 struct  amdgim_pf2vf_info_v2 {
         /* header contains size and version */
-        struct amdgim_pf2vf_info_header header;
+        struct amd_sriov_msg_pf2vf_info_header header;
         /* use private key from mailbox 2 to create chueksum */
         uint32_t checksum;
         /* The features flags of the GIM driver supports. */
@@ -137,20 +139,22 @@ struct  amdgim_pf2vf_info_v2 {
         uint64_t vcefw_kboffset;
         /* VCE FW size in KB */
         uint32_t vcefw_ksize;
-        uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amdgim_pf2vf_info_header)/sizeof(uint32_t)), 3)];
+        uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 3)];
 } __aligned(4);
 
 
-struct amdgim_vf2pf_info_header {
+struct amd_sriov_msg_vf2pf_info_header {
         /* the total structure size in byte. */
         uint32_t size;
         /*version of this structure, written by the guest */
         uint32_t version;
+        /* reserved */
+        uint32_t reserved[2];
 } __aligned(4);
 
 struct amdgim_vf2pf_info_v1 {
         /* header contains size and version */
-        struct amdgim_vf2pf_info_header header;
+        struct amd_sriov_msg_vf2pf_info_header header;
         /* driver version */
         char driver_version[64];
         /* driver certification, 1=WHQL, 0=None */
@@ -180,7 +184,7 @@ struct amdgim_vf2pf_info_v1 {
 
 struct amdgim_vf2pf_info_v2 {
         /* header contains size and version */
-        struct amdgim_vf2pf_info_header header;
+        struct amd_sriov_msg_vf2pf_info_header header;
         uint32_t checksum;
         /* driver version */
         uint8_t driver_version[64];
@@ -206,7 +210,7 @@ struct amdgim_vf2pf_info_v2 {
         uint32_t uvd_enc_usage;
         /* guest uvd engine usage percentage. 0xffff means N/A. */
         uint32_t uvd_enc_health;
-        uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amdgim_vf2pf_info_header)/sizeof(uint32_t)), 0)];
+        uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
 } __aligned(4);
 
 #define AMDGPU_FW_VRAM_VF2PF_VER 2
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 909216a9b447..fb37e69f1bba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -23,7 +23,7 @@
  */
 #include <linux/list.h>
 #include "amdgpu.h"
-#include "amdgpu_psp.h"
+#include "amdgpu_xgmi.h"
 
 
 static DEFINE_MUTEX(xgmi_mutex);
@@ -31,15 +31,16 @@ static DEFINE_MUTEX(xgmi_mutex);
 #define AMDGPU_MAX_XGMI_HIVE                    8
 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE         4
 
-struct amdgpu_hive_info {
-        uint64_t                hive_id;
-        struct list_head        device_list;
-};
-
 static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
 static unsigned hive_count = 0;
 
-static struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
+
+void *amdgpu_xgmi_hive_try_lock(struct amdgpu_hive_info *hive)
+{
+        return &hive->device_list;
+}
+
+struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
 {
         int i;
         struct amdgpu_hive_info *tmp;
@@ -58,15 +59,38 @@ static struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
         tmp = &xgmi_hives[hive_count++];
         tmp->hive_id = adev->gmc.xgmi.hive_id;
         INIT_LIST_HEAD(&tmp->device_list);
+        mutex_init(&tmp->hive_lock);
+
         return tmp;
 }
 
+int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev)
+{
+        int ret = -EINVAL;
+
+        /* Each psp need to set the latest topology */
+        ret = psp_xgmi_set_topology_info(&adev->psp,
+                                         hive->number_devices,
+                                         &hive->topology_info);
+        if (ret)
+                dev_err(adev->dev,
+                        "XGMI: Set topology failure on device %llx, hive %llx, ret %d",
+                        adev->gmc.xgmi.node_id,
+                        adev->gmc.xgmi.hive_id, ret);
+        else
+                dev_info(adev->dev, "XGMI: Add node %d to hive 0x%llx.\n",
+                         adev->gmc.xgmi.physical_node_id,
+                                 adev->gmc.xgmi.hive_id);
+
+        return ret;
+}
+
 int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
 {
-        struct psp_xgmi_topology_info *tmp_topology;
+        struct psp_xgmi_topology_info *hive_topology;
         struct amdgpu_hive_info *hive;
         struct amdgpu_xgmi      *entry;
-        struct amdgpu_device    *tmp_adev;
+        struct amdgpu_device *tmp_adev = NULL;
 
         int count = 0, ret = -EINVAL;
 
@@ -76,21 +100,21 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
         adev->gmc.xgmi.node_id = psp_xgmi_get_node_id(&adev->psp);
         adev->gmc.xgmi.hive_id = psp_xgmi_get_hive_id(&adev->psp);
 
-        tmp_topology = kzalloc(sizeof(struct psp_xgmi_topology_info), GFP_KERNEL);
-        if (!tmp_topology)
-                return -ENOMEM;
         mutex_lock(&xgmi_mutex);
         hive = amdgpu_get_xgmi_hive(adev);
         if (!hive)
                 goto exit;
 
+        hive_topology = &hive->topology_info;
+
         list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
         list_for_each_entry(entry, &hive->device_list, head)
-                tmp_topology->nodes[count++].node_id = entry->node_id;
+                hive_topology->nodes[count++].node_id = entry->node_id;
+        hive->number_devices = count;
 
         /* Each psp need to get the latest topology */
         list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
-                ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, tmp_topology);
+                ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, hive_topology);
                 if (ret) {
                         dev_err(tmp_adev->dev,
                                 "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
@@ -101,25 +125,13 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
                 }
         }
 
-        /* Each psp need to set the latest topology */
         list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
-                ret = psp_xgmi_set_topology_info(&tmp_adev->psp, count, tmp_topology);
-                if (ret) {
-                        dev_err(tmp_adev->dev,
-                                "XGMI: Set topology failure on device %llx, hive %llx, ret %d",
-                                tmp_adev->gmc.xgmi.node_id,
-                                tmp_adev->gmc.xgmi.hive_id, ret);
-                        /* To do : continue with some  node failed or disable the  whole  hive */
+                ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
+                if (ret)
                         break;
-                }
         }
-        if (!ret)
-                dev_info(adev->dev, "XGMI: Add node %d to hive 0x%llx.\n",
-                        adev->gmc.xgmi.physical_node_id,
-                        adev->gmc.xgmi.hive_id);
 
 exit:
         mutex_unlock(&xgmi_mutex);
-        kfree(tmp_topology);
         return ret;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
new file mode 100644
index 000000000000..6335bfdcc51d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __AMDGPU_XGMI_H__
+#define __AMDGPU_XGMI_H__
+
+#include "amdgpu_psp.h"
+
+struct amdgpu_hive_info {
+        uint64_t                hive_id;
+        struct list_head        device_list;
+        struct psp_xgmi_topology_info   topology_info;
+        int number_devices;
+        struct mutex hive_lock;
+};
+
+struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
+int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
+int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index f41f5f57e9f3..71c50d8900e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1755,6 +1755,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
         .flush_hdp = &cik_flush_hdp,
         .invalidate_hdp = &cik_invalidate_hdp,
         .need_full_reset = &cik_need_full_reset,
+        .init_doorbell_index = &legacy_doorbell_index_init,
 };
 
 static int cik_common_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
index e49c6f15a0a0..54c625a2e570 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik.h
@@ -30,4 +30,5 @@ void cik_srbm_select(struct amdgpu_device *adev,
                      u32 me, u32 pipe, u32 queue, u32 vmid);
 int cik_set_ip_blocks(struct amdgpu_device *adev);
 
+void legacy_doorbell_index_init(struct amdgpu_device *adev);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index f467b9bd090d..3a9fb6018c16 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4363,7 +4363,7 @@ static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 
         ring->ring_obj = NULL;
         ring->use_doorbell = true;
-        ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
+        ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 
         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index cb066a8dccd7..1454fc306783 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -44,7 +44,6 @@
 #include "gca/gfx_8_0_d.h"
 #include "gca/gfx_8_0_enum.h"
 #include "gca/gfx_8_0_sh_mask.h"
-#include "gca/gfx_8_0_enum.h"
 
 #include "dce/dce_10_0_d.h"
 #include "dce/dce_10_0_sh_mask.h"
@@ -1891,7 +1890,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 
         ring->ring_obj = NULL;
         ring->use_doorbell = true;
-        ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
+        ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
                                 + (ring_id * GFX8_MEC_HPD_SIZE);
         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
@@ -2002,7 +2001,7 @@ static int gfx_v8_0_sw_init(void *handle)
                 /* no gfx doorbells on iceland */
                 if (adev->asic_type != CHIP_TOPAZ) {
                         ring->use_doorbell = true;
-                        ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
+                        ring->doorbell_index = adev->doorbell_index.gfx_ring0;
                 }
 
                 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
@@ -4216,7 +4215,7 @@ static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu
 
         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
                                         DOORBELL_RANGE_LOWER,
-                                        AMDGPU_DOORBELL_GFX_RING0);
+                                        adev->doorbell_index.gfx_ring0);
         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
 
         WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
@@ -4645,8 +4644,8 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
 static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
 {
         if (adev->asic_type > CHIP_TONGA) {
-                WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2);
-                WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, AMDGPU_DOORBELL_MEC_RING7 << 2);
+                WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);
+                WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);
         }
         /* enable doorbells */
         WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c27caa144c57..af8ccb014be3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1566,7 +1566,7 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 
         ring->ring_obj = NULL;
         ring->use_doorbell = true;
-        ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
+        ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
                                 + (ring_id * GFX9_MEC_HPD_SIZE);
         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
@@ -1655,7 +1655,7 @@ static int gfx_v9_0_sw_init(void *handle)
                 else
                         sprintf(ring->name, "gfx_%d", i);
                 ring->use_doorbell = true;
-                ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
+                ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
                 r = amdgpu_ring_init(adev, ring, 1024,
                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
                 if (r)
@@ -2981,9 +2981,9 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
         /* enable the doorbell if requested */
         if (ring->use_doorbell) {
                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
-                                        (AMDGPU_DOORBELL64_KIQ *2) << 2);
+                                        (adev->doorbell_index.kiq * 2) << 2);
                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
-                                        (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
+                                        (adev->doorbell_index.userqueue_end * 2) << 2);
         }
 
         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 811231e4ec53..3a4e5d8d5162 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -338,9 +338,12 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
                 struct amdgpu_vmhub *hub = &adev->vmhub[i];
                 u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 
-                if (i == AMDGPU_GFXHUB && !adev->in_gpu_reset &&
-                    adev->gfx.kiq.ring.sched.ready &&
-                    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
+                /* This is necessary for a HW workaround under SRIOV as well
+                 * as GFXOFF under bare metal
+                 */
+                if (adev->gfx.kiq.ring.sched.ready &&
+                    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
+                    !adev->in_gpu_reset) {
                         uint32_t req = hub->vm_inv_eng0_req + eng;
                         uint32_t ack = hub->vm_inv_eng0_ack + eng;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 64e875d528dd..6a0fcd67662a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -37,7 +37,6 @@
 #include "gmc/gmc_8_2_sh_mask.h"
 #include "oss/oss_3_0_d.h"
 #include "oss/oss_3_0_sh_mask.h"
-#include "gca/gfx_8_0_sh_mask.h"
 #include "dce/dce_10_0_d.h"
 #include "dce/dce_10_0_sh_mask.h"
 #include "smu/smu_7_1_3_d.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 295c2205485a..d78b4306a36f 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -240,12 +240,9 @@ static int psp_v10_0_ring_stop(struct psp_context *psp,
                                enum psp_ring_type ring_type)
 {
         int ret = 0;
-        struct psp_ring *ring;
         unsigned int psp_ring_reg = 0;
         struct amdgpu_device *adev = psp->adev;
 
-        ring = &psp->km_ring;
-
         /* Write the ring destroy command to C2PMSG_64 */
         psp_ring_reg = 3 << 16;
         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 9cea0bbe4525..7efb823dd3b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -356,12 +356,9 @@ static int psp_v3_1_ring_stop(struct psp_context *psp,
                               enum psp_ring_type ring_type)
 {
         int ret = 0;
-        struct psp_ring *ring;
         unsigned int psp_ring_reg = 0;
         struct amdgpu_device *adev = psp->adev;
 
-        ring = &psp->km_ring;
-
         /* Write the ring destroy command to C2PMSG_64 */
         psp_ring_reg = 3 << 16;
         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
@@ -593,7 +590,7 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp)
         }
 
         /*send the mode 1 reset command*/
-        WREG32(offset, 0x70000);
+        WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 
         mdelay(1000);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index b6a25f92d566..1bccc5fe2d9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1146,7 +1146,7 @@ static int sdma_v3_0_sw_init(void *handle)
                 if (!amdgpu_sriov_vf(adev)) {
                         ring->use_doorbell = true;
                         ring->doorbell_index = (i == 0) ?
-                                AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
+                                adev->doorbell_index.sdma_engine0 : adev->doorbell_index.sdma_engine1;
                 } else {
                         ring->use_pollmem = true;
                 }
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index f4490cdd9804..4b6d3e5c821f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
                                         OFFSET, ring->doorbell_index);
         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
-        /* TODO: enable doorbell support */
-        /*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
-                                              ring->doorbell_index);*/
 
-        sdma_v4_0_ring_set_wptr(ring);
+        /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
+        sdma_v4_0_page_ring_set_wptr(ring);
 
         /* set minor_ptr_update to 0 after wptr programed */
         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
@@ -1449,23 +1447,46 @@ static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
 }
 
+static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
+{
+        uint fw_version = adev->sdma.instance[0].fw_version;
+
+        switch (adev->asic_type) {
+        case CHIP_VEGA10:
+                return fw_version >= 430;
+        case CHIP_VEGA12:
+                /*return fw_version >= 31;*/
+                return false;
+        case CHIP_VEGA20:
+                /*return fw_version >= 115;*/
+                return false;
+        default:
+                return false;
+        }
+}
+
 static int sdma_v4_0_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int r;
 
-        if (adev->asic_type == CHIP_RAVEN) {
+        if (adev->asic_type == CHIP_RAVEN)
                 adev->sdma.num_instances = 1;
-                adev->sdma.has_page_queue = false;
-        } else {
+        else
                 adev->sdma.num_instances = 2;
-                /* TODO: Page queue breaks driver reload under SRIOV */
-                if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
-                        adev->sdma.has_page_queue = false;
-                else if (adev->asic_type != CHIP_VEGA20 &&
-                                adev->asic_type != CHIP_VEGA12)
-                        adev->sdma.has_page_queue = true;
+
+        r = sdma_v4_0_init_microcode(adev);
+        if (r) {
+                DRM_ERROR("Failed to load sdma firmware!\n");
+                return r;
         }
 
+        /* TODO: Page queue breaks driver reload under SRIOV */
+        if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
+                adev->sdma.has_page_queue = false;
+        else if (sdma_v4_0_fw_support_paging_queue(adev))
+                adev->sdma.has_page_queue = true;
+
         sdma_v4_0_set_ring_funcs(adev);
         sdma_v4_0_set_buffer_funcs(adev);
         sdma_v4_0_set_vm_pte_funcs(adev);
@@ -1474,7 +1495,6 @@ static int sdma_v4_0_early_init(void *handle)
         return 0;
 }
 
-
 static int sdma_v4_0_sw_init(void *handle)
 {
         struct amdgpu_ring *ring;
@@ -1493,12 +1513,6 @@ static int sdma_v4_0_sw_init(void *handle)
         if (r)
                 return r;
 
-        r = sdma_v4_0_init_microcode(adev);
-        if (r) {
-                DRM_ERROR("Failed to load sdma firmware!\n");
-                return r;
-        }
-
         for (i = 0; i < adev->sdma.num_instances; i++) {
                 ring = &adev->sdma.instance[i].ring;
                 ring->ring_obj = NULL;
@@ -1507,15 +1521,10 @@ static int sdma_v4_0_sw_init(void *handle)
                 DRM_INFO("use_doorbell being set to: [%s]\n",
                                 ring->use_doorbell?"true":"false");
 
-                if (adev->asic_type == CHIP_VEGA10)
-                        ring->doorbell_index = (i == 0) ?
-                                (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
-                                : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
-                else
-                        ring->doorbell_index = (i == 0) ?
-                                (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
-                                : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
-
+                /* doorbell size is 2 dwords, get DWORD offset */
+                ring->doorbell_index = (i == 0) ?
+                        (adev->doorbell_index.sdma_engine0 << 1)
+                        : (adev->doorbell_index.sdma_engine1 << 1);
 
                 sprintf(ring->name, "sdma%d", i);
                 r = amdgpu_ring_init(adev, ring, 1024,
@@ -1529,7 +1538,15 @@ static int sdma_v4_0_sw_init(void *handle)
                 if (adev->sdma.has_page_queue) {
                         ring = &adev->sdma.instance[i].page;
                         ring->ring_obj = NULL;
-                        ring->use_doorbell = false;
+                        ring->use_doorbell = true;
+
+                        /* paging queue use same doorbell index/routing as gfx queue
+                         * with 0x400 (4096 dwords) offset on second doorbell page
+                         */
+                        ring->doorbell_index = (i == 0) ?
+                                (adev->doorbell_index.sdma_engine0 << 1)
+                                : (adev->doorbell_index.sdma_engine1 << 1);
+                        ring->doorbell_index += 0x400;
 
                         sprintf(ring->name, "page%d", i);
                         r = amdgpu_ring_init(adev, ring, 1024,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 4cc0dcb1a187..83624e150ca7 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -613,6 +613,24 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
         .flush_hdp = &soc15_flush_hdp,
         .invalidate_hdp = &soc15_invalidate_hdp,
         .need_full_reset = &soc15_need_full_reset,
+        .init_doorbell_index = &vega10_doorbell_index_init,
+};
+
+static const struct amdgpu_asic_funcs vega20_asic_funcs =
+{
+        .read_disabled_bios = &soc15_read_disabled_bios,
+        .read_bios_from_rom = &soc15_read_bios_from_rom,
+        .read_register = &soc15_read_register,
+        .reset = &soc15_asic_reset,
+        .set_vga_state = &soc15_vga_set_state,
+        .get_xclk = &soc15_get_xclk,
+        .set_uvd_clocks = &soc15_set_uvd_clocks,
+        .set_vce_clocks = &soc15_set_vce_clocks,
+        .get_config_memsize = &soc15_get_config_memsize,
+        .flush_hdp = &soc15_flush_hdp,
+        .invalidate_hdp = &soc15_invalidate_hdp,
+        .need_full_reset = &soc15_need_full_reset,
+        .init_doorbell_index = &vega20_doorbell_index_init,
 };
 
 static int soc15_common_early_init(void *handle)
@@ -632,11 +650,11 @@ static int soc15_common_early_init(void *handle)
         adev->se_cac_rreg = &soc15_se_cac_rreg;
         adev->se_cac_wreg = &soc15_se_cac_wreg;
 
-        adev->asic_funcs = &soc15_asic_funcs;
 
         adev->external_rev_id = 0xFF;
         switch (adev->asic_type) {
         case CHIP_VEGA10:
+                adev->asic_funcs = &soc15_asic_funcs;
                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                         AMD_CG_SUPPORT_GFX_MGLS |
                         AMD_CG_SUPPORT_GFX_RLC_LS |
@@ -660,6 +678,7 @@ static int soc15_common_early_init(void *handle)
                 adev->external_rev_id = 0x1;
                 break;
         case CHIP_VEGA12:
+                adev->asic_funcs = &soc15_asic_funcs;
                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                         AMD_CG_SUPPORT_GFX_MGLS |
                         AMD_CG_SUPPORT_GFX_CGCG |
@@ -682,6 +701,7 @@ static int soc15_common_early_init(void *handle)
                 adev->external_rev_id = adev->rev_id + 0x14;
                 break;
         case CHIP_VEGA20:
+                adev->asic_funcs = &vega20_asic_funcs;
                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                         AMD_CG_SUPPORT_GFX_MGLS |
                         AMD_CG_SUPPORT_GFX_CGCG |
@@ -704,6 +724,7 @@ static int soc15_common_early_init(void *handle)
                 adev->external_rev_id = adev->rev_id + 0x28;
                 break;
         case CHIP_RAVEN:
+                adev->asic_funcs = &soc15_asic_funcs;
                 if (adev->rev_id >= 0x8)
                         adev->external_rev_id = adev->rev_id + 0x81;
                 else if (adev->pdev->device == 0x15d8)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index f8ad7804dc40..a66c8bfbbaa6 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -58,4 +58,6 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
 int vega10_reg_base_init(struct amdgpu_device *adev);
 int vega20_reg_base_init(struct amdgpu_device *adev);
 
+void vega10_doorbell_index_init(struct amdgpu_device *adev);
+void vega20_doorbell_index_init(struct amdgpu_device *adev);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 3abffd06b5c7..dcdbb4d72472 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -322,7 +322,7 @@ static int tonga_ih_sw_init(void *handle)
                 return r;
 
         adev->irq.ih.use_doorbell = true;
-        adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH;
+        adev->irq.ih.doorbell_index = adev->doorbell_index.ih;
 
         r = amdgpu_irq_init(adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 90bbcee00f28..d69c8f6daaf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -116,16 +116,16 @@ static int uvd_v4_2_sw_init(void *handle)
         if (r)
                 return r;
 
-        r = amdgpu_uvd_resume(adev);
-        if (r)
-                return r;
-
         ring = &adev->uvd.inst->ring;
         sprintf(ring->name, "uvd");
         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
         if (r)
                 return r;
 
+        r = amdgpu_uvd_resume(adev);
+        if (r)
+                return r;
+
         r = amdgpu_uvd_entity_init(adev);
 
         return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 1c5e12703103..ee8cd06ddc38 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -113,16 +113,16 @@ static int uvd_v5_0_sw_init(void *handle)
         if (r)
                 return r;
 
-        r = amdgpu_uvd_resume(adev);
-        if (r)
-                return r;
-
         ring = &adev->uvd.inst->ring;
         sprintf(ring->name, "uvd");
         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
         if (r)
                 return r;
 
+        r = amdgpu_uvd_resume(adev);
+        if (r)
+                return r;
+
         r = amdgpu_uvd_entity_init(adev);
 
         return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index f184842ef2a2..d4f4a66f8324 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -400,16 +400,16 @@ static int uvd_v6_0_sw_init(void *handle)
                 DRM_INFO("UVD ENC is disabled\n");
         }
 
-        r = amdgpu_uvd_resume(adev);
-        if (r)
-                return r;
-
         ring = &adev->uvd.inst->ring;
         sprintf(ring->name, "uvd");
         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
         if (r)
                 return r;
 
+        r = amdgpu_uvd_resume(adev);
+        if (r)
+                return r;
+
         if (uvd_v6_0_enc_support(adev)) {
                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
                         ring = &adev->uvd.inst->ring_enc[i];
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 8a4595968d98..089645e78f98 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -430,10 +430,6 @@ static int uvd_v7_0_sw_init(void *handle)
                 DRM_INFO("PSP loading UVD firmware\n");
         }
 
-        r = amdgpu_uvd_resume(adev);
-        if (r)
-                return r;
-
         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
                 if (adev->uvd.harvest_config & (1 << j))
                         continue;
@@ -455,9 +451,9 @@ static int uvd_v7_0_sw_init(void *handle)
                                  * sriov, so set unused location for other unused rings.
                                  */
                                 if (i == 0)
-                                        ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
+                                        ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring0_1 * 2;
                                 else
-                                        ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
+                                        ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring2_3 * 2 + 1;
                         }
                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
                         if (r)
@@ -465,6 +461,10 @@ static int uvd_v7_0_sw_init(void *handle)
                 }
         }
 
+        r = amdgpu_uvd_resume(adev);
+        if (r)
+                return r;
+
         r = amdgpu_uvd_entity_init(adev);
         if (r)
                 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 3e84840859a7..2668effadd27 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -37,7 +37,6 @@
 #include "gca/gfx_8_0_d.h"
 #include "smu/smu_7_1_2_d.h"
 #include "smu/smu_7_1_2_sh_mask.h"
-#include "gca/gfx_8_0_d.h"
 #include "gca/gfx_8_0_sh_mask.h"
 #include "ivsrcid/ivsrcid_vislands30.h"
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 0054ba1b9a68..9fb34b7d8e03 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -466,9 +466,9 @@ static int vce_v4_0_sw_init(void *handle)
                          * so set unused location for other unused rings.
                          */
                         if (i == 0)
-                                ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING0_1 * 2;
+                                ring->doorbell_index = adev->doorbell_index.uvd_vce.vce_ring0_1 * 2;
                         else
-                                ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING2_3 * 2 + 1;
+                                ring->doorbell_index = adev->doorbell_index.uvd_vce.vce_ring2_3 * 2 + 1;
                 }
                 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
                 if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index a0fda6f9252a..d84b687240d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -385,7 +385,7 @@ static int vega10_ih_sw_init(void *handle)
                 return r;
 
         adev->irq.ih.use_doorbell = true;
-        adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1;
+        adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 
         r = amdgpu_irq_init(adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index c5c9b2bc190d..422674bb3cdf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -56,4 +56,32 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
         return 0;
 }
 
+void vega10_doorbell_index_init(struct amdgpu_device *adev)
+{
+        adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
+        adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
+        adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
+        adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2;
+        adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3;
+        adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4;
+        adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
+        adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
+        adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
+        adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL64_USERQUEUE_START;
+        adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
+        adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
+        adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL64_sDMA_ENGINE0;
+        adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL64_sDMA_ENGINE1;
+        adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
+        adev->doorbell_index.uvd_vce.uvd_ring0_1 = AMDGPU_DOORBELL64_UVD_RING0_1;
+        adev->doorbell_index.uvd_vce.uvd_ring2_3 = AMDGPU_DOORBELL64_UVD_RING2_3;
+        adev->doorbell_index.uvd_vce.uvd_ring4_5 = AMDGPU_DOORBELL64_UVD_RING4_5;
+        adev->doorbell_index.uvd_vce.uvd_ring6_7 = AMDGPU_DOORBELL64_UVD_RING6_7;
+        adev->doorbell_index.uvd_vce.vce_ring0_1 = AMDGPU_DOORBELL64_VCE_RING0_1;
+        adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3;
+        adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5;
+        adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
+        /* In unit of dword doorbell */
+        adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
+}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index d13fc4fcb517..edce413fda9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -54,4 +54,37 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
         return 0;
 }
 
+void vega20_doorbell_index_init(struct amdgpu_device *adev)
+{
+        adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ;
+        adev->doorbell_index.mec_ring0 = AMDGPU_VEGA20_DOORBELL_MEC_RING0;
+        adev->doorbell_index.mec_ring1 = AMDGPU_VEGA20_DOORBELL_MEC_RING1;
+        adev->doorbell_index.mec_ring2 = AMDGPU_VEGA20_DOORBELL_MEC_RING2;
+        adev->doorbell_index.mec_ring3 = AMDGPU_VEGA20_DOORBELL_MEC_RING3;
+        adev->doorbell_index.mec_ring4 = AMDGPU_VEGA20_DOORBELL_MEC_RING4;
+        adev->doorbell_index.mec_ring5 = AMDGPU_VEGA20_DOORBELL_MEC_RING5;
+        adev->doorbell_index.mec_ring6 = AMDGPU_VEGA20_DOORBELL_MEC_RING6;
+        adev->doorbell_index.mec_ring7 = AMDGPU_VEGA20_DOORBELL_MEC_RING7;
+        adev->doorbell_index.userqueue_start = AMDGPU_VEGA20_DOORBELL_USERQUEUE_START;
+        adev->doorbell_index.userqueue_end = AMDGPU_VEGA20_DOORBELL_USERQUEUE_END;
+        adev->doorbell_index.gfx_ring0 = AMDGPU_VEGA20_DOORBELL_GFX_RING0;
+        adev->doorbell_index.sdma_engine0 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0;
+        adev->doorbell_index.sdma_engine1 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1;
+        adev->doorbell_index.sdma_engine2 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2;
+        adev->doorbell_index.sdma_engine3 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3;
+        adev->doorbell_index.sdma_engine4 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4;
+        adev->doorbell_index.sdma_engine5 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5;
+        adev->doorbell_index.sdma_engine6 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6;
+        adev->doorbell_index.sdma_engine7 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7;
+        adev->doorbell_index.ih = AMDGPU_VEGA20_DOORBELL_IH;
+        adev->doorbell_index.uvd_vce.uvd_ring0_1 = AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1;
+        adev->doorbell_index.uvd_vce.uvd_ring2_3 = AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3;
+        adev->doorbell_index.uvd_vce.uvd_ring4_5 = AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5;
+        adev->doorbell_index.uvd_vce.uvd_ring6_7 = AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7;
+        adev->doorbell_index.uvd_vce.vce_ring0_1 = AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1;
+        adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3;
+        adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
+        adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
+        adev->doorbell_index.max_assignment = AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT << 1;
+}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 07880d35e9de..ff2906c215fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -955,6 +955,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
         .flush_hdp = &vi_flush_hdp,
         .invalidate_hdp = &vi_invalidate_hdp,
         .need_full_reset = &vi_need_full_reset,
+        .init_doorbell_index = &legacy_doorbell_index_init,
 };
 
 #define CZ_REV_BRISTOL(rev)      \
@@ -1712,3 +1713,21 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
 
         return 0;
 }
+
+void legacy_doorbell_index_init(struct amdgpu_device *adev)
+{
+        adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
+        adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
+        adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
+        adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
+        adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
+        adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
+        adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
+        adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
+        adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
+        adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
+        adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL_sDMA_ENGINE0;
+        adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL_sDMA_ENGINE1;
+        adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
+        adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 0429fe332269..8de0772f986c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -30,4 +30,5 @@ void vi_srbm_select(struct amdgpu_device *adev,
                     u32 me, u32 pipe, u32 queue, u32 vmid);
 int vi_set_ip_blocks(struct amdgpu_device *adev);
 
+void legacy_doorbell_index_init(struct amdgpu_device *adev);
 #endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 3783d122f283..c02adbbeef2a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -133,6 +133,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
 #define fiji_cache_info  carrizo_cache_info
 #define polaris10_cache_info carrizo_cache_info
 #define polaris11_cache_info carrizo_cache_info
+#define polaris12_cache_info carrizo_cache_info
 /* TODO - check & update Vega10 cache details */
 #define vega10_cache_info carrizo_cache_info
 #define raven_cache_info carrizo_cache_info
@@ -647,7 +648,12 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
                 pcache_info = polaris11_cache_info;
                 num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);
                 break;
+        case CHIP_POLARIS12:
+                pcache_info = polaris12_cache_info;
+                num_of_cache_types = ARRAY_SIZE(polaris12_cache_info);
+                break;
         case CHIP_VEGA10:
+        case CHIP_VEGA12:
         case CHIP_VEGA20:
                 pcache_info = vega10_cache_info;
                 num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index c004647c8cb4..9ed14a11afa2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -205,6 +205,22 @@ static const struct kfd_device_info polaris11_device_info = {
         .num_sdma_queues_per_engine = 2,
 };
 
+static const struct kfd_device_info polaris12_device_info = {
+        .asic_family = CHIP_POLARIS12,
+        .max_pasid_bits = 16,
+        .max_no_of_hqd  = 24,
+        .doorbell_size  = 4,
+        .ih_ring_entry_size = 4 * sizeof(uint32_t),
+        .event_interrupt_class = &event_interrupt_class_cik,
+        .num_of_watch_points = 4,
+        .mqd_size_aligned = MQD_SIZE_ALIGNED,
+        .supports_cwsr = true,
+        .needs_iommu_device = false,
+        .needs_pci_atomics = true,
+        .num_sdma_engines = 2,
+        .num_sdma_queues_per_engine = 2,
+};
+
 static const struct kfd_device_info vega10_device_info = {
         .asic_family = CHIP_VEGA10,
         .max_pasid_bits = 16,
@@ -237,6 +253,22 @@ static const struct kfd_device_info vega10_vf_device_info = {
         .num_sdma_queues_per_engine = 2,
 };
 
+static const struct kfd_device_info vega12_device_info = {
+        .asic_family = CHIP_VEGA12,
+        .max_pasid_bits = 16,
+        .max_no_of_hqd  = 24,
+        .doorbell_size  = 8,
+        .ih_ring_entry_size = 8 * sizeof(uint32_t),
+        .event_interrupt_class = &event_interrupt_class_v9,
+        .num_of_watch_points = 4,
+        .mqd_size_aligned = MQD_SIZE_ALIGNED,
+        .supports_cwsr = true,
+        .needs_iommu_device = false,
+        .needs_pci_atomics = false,
+        .num_sdma_engines = 2,
+        .num_sdma_queues_per_engine = 2,
+};
+
 static const struct kfd_device_info vega20_device_info = {
         .asic_family = CHIP_VEGA20,
         .max_pasid_bits = 16,
@@ -331,6 +363,14 @@ static const struct kfd_deviceid supported_devices[] = {
         { 0x67EB, &polaris11_device_info },     /* Polaris11 */
         { 0x67EF, &polaris11_device_info },     /* Polaris11 */
         { 0x67FF, &polaris11_device_info },     /* Polaris11 */
+        { 0x6980, &polaris12_device_info },     /* Polaris12 */
+        { 0x6981, &polaris12_device_info },     /* Polaris12 */
+        { 0x6985, &polaris12_device_info },     /* Polaris12 */
+        { 0x6986, &polaris12_device_info },     /* Polaris12 */
+        { 0x6987, &polaris12_device_info },     /* Polaris12 */
+        { 0x6995, &polaris12_device_info },     /* Polaris12 */
+        { 0x6997, &polaris12_device_info },     /* Polaris12 */
+        { 0x699F, &polaris12_device_info },     /* Polaris12 */
         { 0x6860, &vega10_device_info },        /* Vega10 */
         { 0x6861, &vega10_device_info },        /* Vega10 */
         { 0x6862, &vega10_device_info },        /* Vega10 */
@@ -340,6 +380,11 @@ static const struct kfd_deviceid supported_devices[] = {
         { 0x6868, &vega10_device_info },        /* Vega10 */
         { 0x686C, &vega10_vf_device_info },     /* Vega10  vf*/
         { 0x687F, &vega10_device_info },        /* Vega10 */
+        { 0x69A0, &vega12_device_info },        /* Vega12 */
+        { 0x69A1, &vega12_device_info },        /* Vega12 */
+        { 0x69A2, &vega12_device_info },        /* Vega12 */
+        { 0x69A3, &vega12_device_info },        /* Vega12 */
+        { 0x69AF, &vega12_device_info },        /* Vega12 */
         { 0x66a0, &vega20_device_info },        /* Vega20 */
         { 0x66a1, &vega20_device_info },        /* Vega20 */
         { 0x66a2, &vega20_device_info },        /* Vega20 */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index fb9d66ea13b7..8372556b52eb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1547,7 +1547,7 @@ static int get_wave_state(struct device_queue_manager *dqm,
                           u32 *ctl_stack_used_size,
                           u32 *save_area_used_size)
 {
-        struct mqd_manager *mqd;
+        struct mqd_manager *mqd_mgr;
         int r;
 
         dqm_lock(dqm);
@@ -1558,19 +1558,19 @@ static int get_wave_state(struct device_queue_manager *dqm,
                 goto dqm_unlock;
         }
 
-        mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
-        if (!mqd) {
+        mqd_mgr = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
+        if (!mqd_mgr) {
                 r = -ENOMEM;
                 goto dqm_unlock;
         }
 
-        if (!mqd->get_wave_state) {
+        if (!mqd_mgr->get_wave_state) {
                 r = -EINVAL;
                 goto dqm_unlock;
         }
 
-        r = mqd->get_wave_state(mqd, q->mqd, ctl_stack, ctl_stack_used_size,
-                                save_area_used_size);
+        r = mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack,
+                        ctl_stack_used_size, save_area_used_size);
 
 dqm_unlock:
         dqm_unlock(dqm);
@@ -1741,10 +1741,12 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
         case CHIP_FIJI:
         case CHIP_POLARIS10:
         case CHIP_POLARIS11:
+        case CHIP_POLARIS12:
                 device_queue_manager_init_vi_tonga(&dqm->asic_ops);
                 break;
 
         case CHIP_VEGA10:
+        case CHIP_VEGA12:
         case CHIP_VEGA20:
         case CHIP_RAVEN:
                 device_queue_manager_init_v9(&dqm->asic_ops);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c
index fd60a116be37..c3a5dcfe877a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c
@@ -24,7 +24,6 @@
 #include "kfd_device_queue_manager.h"
 #include "gca/gfx_8_0_enum.h"
 #include "gca/gfx_8_0_sh_mask.h"
-#include "gca/gfx_8_0_enum.h"
 #include "oss/oss_3_0_sh_mask.h"
 
 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 3d66cec414af..213ea5454d11 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -397,9 +397,11 @@ int kfd_init_apertures(struct kfd_process *process)
                         case CHIP_FIJI:
                         case CHIP_POLARIS10:
                         case CHIP_POLARIS11:
+                        case CHIP_POLARIS12:
                                 kfd_init_apertures_vi(pdd, id);
                                 break;
                         case CHIP_VEGA10:
+                        case CHIP_VEGA12:
                         case CHIP_VEGA20:
                         case CHIP_RAVEN:
                                 kfd_init_apertures_v9(pdd, id);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
index f836897bbf58..a85904ad0d5f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
@@ -23,7 +23,7 @@
 #include "kfd_priv.h"
 #include "kfd_events.h"
 #include "soc15_int.h"
-
+#include "kfd_device_queue_manager.h"
 
 static bool event_interrupt_isr_v9(struct kfd_dev *dev,
                                         const uint32_t *ih_ring_entry,
@@ -39,20 +39,39 @@ static bool event_interrupt_isr_v9(struct kfd_dev *dev,
             vmid > dev->vm_info.last_vmid_kfd)
                 return 0;
 
-        /* If there is no valid PASID, it's likely a firmware bug */
-        pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
-        if (WARN_ONCE(pasid == 0, "FW bug: No PASID in KFD interrupt"))
-                return 0;
-
         source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
         client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
+        pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
+
+        /* This is a known issue for gfx9. Under non HWS, pasid is not set
+         * in the interrupt payload, so we need to find out the pasid on our
+         * own.
+         */
+        if (!pasid && dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
+                const uint32_t pasid_mask = 0xffff;
 
-        pr_debug("client id 0x%x, source id %d, pasid 0x%x. raw data:\n",
-                 client_id, source_id, pasid);
+                *patched_flag = true;
+                memcpy(patched_ihre, ih_ring_entry,
+                                dev->device_info->ih_ring_entry_size);
+
+                pasid = dev->kfd2kgd->get_atc_vmid_pasid_mapping_pasid(
+                                dev->kgd, vmid);
+
+                /* Patch the pasid field */
+                patched_ihre[3] = cpu_to_le32((le32_to_cpu(patched_ihre[3])
+                                        & ~pasid_mask) | pasid);
+        }
+
+        pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",
+                 client_id, source_id, vmid, pasid);
         pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",
                  data[0], data[1], data[2], data[3],
                  data[4], data[5], data[6], data[7]);
 
+        /* If there is no valid PASID, it's likely a bug */
+        if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt"))
+                return 0;
+
         /* Interrupt types we care about: various signals and faults.
          * They will be forwarded to a work queue (see below).
          */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 6c31f7370193..f1596881f20a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -313,6 +313,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
         case CHIP_FIJI:
         case CHIP_POLARIS10:
         case CHIP_POLARIS11:
+        case CHIP_POLARIS12:
                 kernel_queue_init_vi(&kq->ops_asic_specific);
                 break;
 
@@ -322,6 +323,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
                 break;
 
         case CHIP_VEGA10:
+        case CHIP_VEGA12:
         case CHIP_VEGA20:
         case CHIP_RAVEN:
                 kernel_queue_init_v9(&kq->ops_asic_specific);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index 6910028010d6..aed9b9b82213 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -38,8 +38,10 @@ struct mqd_manager *mqd_manager_init(enum KFD_MQD_TYPE type,
         case CHIP_FIJI:
         case CHIP_POLARIS10:
         case CHIP_POLARIS11:
+        case CHIP_POLARIS12:
                 return mqd_manager_init_vi_tonga(type, dev);
         case CHIP_VEGA10:
+        case CHIP_VEGA12:
         case CHIP_VEGA20:
         case CHIP_RAVEN:
                 return mqd_manager_init_v9(type, dev);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index c6080ed3b6a7..045a229436a0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -226,9 +226,11 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
         case CHIP_FIJI:
         case CHIP_POLARIS10:
         case CHIP_POLARIS11:
+        case CHIP_POLARIS12:
                 pm->pmf = &kfd_vi_pm_funcs;
                 break;
         case CHIP_VEGA10:
+        case CHIP_VEGA12:
         case CHIP_VEGA20:
         case CHIP_RAVEN:
                 pm->pmf = &kfd_v9_pm_funcs;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index c73b4ff61f99..aa793fcbbdcc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1272,12 +1272,14 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
         case CHIP_FIJI:
         case CHIP_POLARIS10:
         case CHIP_POLARIS11:
+        case CHIP_POLARIS12:
                 pr_debug("Adding doorbell packet type capability\n");
                 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_1_0 <<
                         HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
                         HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
                 break;
         case CHIP_VEGA10:
+        case CHIP_VEGA12:
         case CHIP_VEGA20:
         case CHIP_RAVEN:
                 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
index c97dc9613325..cfde1568c79a 100644
--- a/drivers/gpu/drm/amd/display/Makefile
+++ b/drivers/gpu/drm/amd/display/Makefile
@@ -32,11 +32,12 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/inc
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/info_packet
+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/power
 
 #TODO: remove when Timing Sync feature is complete
 subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
 
-DAL_LIBS = amdgpu_dm dc modules/freesync modules/color modules/info_packet
+DAL_LIBS = amdgpu_dm dc modules/freesync modules/color modules/info_packet modules/power
 
 AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d8d0b206a79c..32e791d9b9a8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -38,7 +38,6 @@
 #include "amd_shared.h"
 #include "amdgpu_dm_irq.h"
 #include "dm_helpers.h"
-#include "dm_services_types.h"
 #include "amdgpu_dm_mst_types.h"
 #if defined(CONFIG_DEBUG_FS)
 #include "amdgpu_dm_debugfs.h"
@@ -72,6 +71,7 @@
 #endif
 
 #include "modules/inc/mod_freesync.h"
+#include "modules/power/power_helpers.h"
 
 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -643,6 +643,26 @@ static int dm_late_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+        struct dmcu_iram_parameters params;
+        unsigned int linear_lut[16];
+        int i;
+        struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
+        bool ret;
+
+        for (i = 0; i < 16; i++)
+                linear_lut[i] = 0xFFFF * i / 15;
+
+        params.set = 0;
+        params.backlight_ramping_start = 0xCCCC;
+        params.backlight_ramping_reduction = 0xCCCCCCCC;
+        params.backlight_lut_array_size = 16;
+        params.backlight_lut_array = linear_lut;
+
+        ret = dmcu_load_iram(dmcu, params);
+
+        if (!ret)
+                return -EINVAL;
+
         return detect_mst_link_for_all_connectors(adev->ddev);
 }
 
@@ -969,45 +989,6 @@ const struct amdgpu_ip_block_version dm_ip_block =
 };
 
 
-static struct drm_atomic_state *
-dm_atomic_state_alloc(struct drm_device *dev)
-{
-        struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
-
-        if (!state)
-                return NULL;
-
-        if (drm_atomic_state_init(dev, &state->base) < 0)
-                goto fail;
-
-        return &state->base;
-
-fail:
-        kfree(state);
-        return NULL;
-}
-
-static void
-dm_atomic_state_clear(struct drm_atomic_state *state)
-{
-        struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-
-        if (dm_state->context) {
-                dc_release_state(dm_state->context);
-                dm_state->context = NULL;
-        }
-
-        drm_atomic_state_default_clear(state);
-}
-
-static void
-dm_atomic_state_alloc_free(struct drm_atomic_state *state)
-{
-        struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-        drm_atomic_state_default_release(state);
-        kfree(dm_state);
-}
-
 /**
  * DOC: atomic
  *
@@ -1019,9 +1000,6 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
         .output_poll_changed = drm_fb_helper_output_poll_changed,
         .atomic_check = amdgpu_dm_atomic_check,
         .atomic_commit = amdgpu_dm_atomic_commit,
-        .atomic_state_alloc = dm_atomic_state_alloc,
-        .atomic_state_clear = dm_atomic_state_clear,
-        .atomic_state_free = dm_atomic_state_alloc_free
 };
 
 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
@@ -1543,8 +1521,117 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
 }
 #endif
 
+/*
+ * Acquires the lock for the atomic state object and returns
+ * the new atomic state.
+ *
+ * This should only be called during atomic check.
+ */
+static int dm_atomic_get_state(struct drm_atomic_state *state,
+                               struct dm_atomic_state **dm_state)
+{
+        struct drm_device *dev = state->dev;
+        struct amdgpu_device *adev = dev->dev_private;
+        struct amdgpu_display_manager *dm = &adev->dm;
+        struct drm_private_state *priv_state;
+        int ret;
+
+        if (*dm_state)
+                return 0;
+
+        ret = drm_modeset_lock(&dm->atomic_obj_lock, state->acquire_ctx);
+        if (ret)
+                return ret;
+
+        priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
+        if (IS_ERR(priv_state))
+                return PTR_ERR(priv_state);
+
+        *dm_state = to_dm_atomic_state(priv_state);
+
+        return 0;
+}
+
+struct dm_atomic_state *
+dm_atomic_get_new_state(struct drm_atomic_state *state)
+{
+        struct drm_device *dev = state->dev;
+        struct amdgpu_device *adev = dev->dev_private;
+        struct amdgpu_display_manager *dm = &adev->dm;
+        struct drm_private_obj *obj;
+        struct drm_private_state *new_obj_state;
+        int i;
+
+        for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
+                if (obj->funcs == dm->atomic_obj.funcs)
+                        return to_dm_atomic_state(new_obj_state);
+        }
+
+        return NULL;
+}
+
+struct dm_atomic_state *
+dm_atomic_get_old_state(struct drm_atomic_state *state)
+{
+        struct drm_device *dev = state->dev;
+        struct amdgpu_device *adev = dev->dev_private;
+        struct amdgpu_display_manager *dm = &adev->dm;
+        struct drm_private_obj *obj;
+        struct drm_private_state *old_obj_state;
+        int i;
+
+        for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
+                if (obj->funcs == dm->atomic_obj.funcs)
+                        return to_dm_atomic_state(old_obj_state);
+        }
+
+        return NULL;
+}
+
+static struct drm_private_state *
+dm_atomic_duplicate_state(struct drm_private_obj *obj)
+{
+        struct dm_atomic_state *old_state, *new_state;
+
+        new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
+        if (!new_state)
+                return NULL;
+
+        __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
+
+        new_state->context = dc_create_state();
+        if (!new_state->context) {
+                kfree(new_state);
+                return NULL;
+        }
+
+        old_state = to_dm_atomic_state(obj->state);
+        if (old_state && old_state->context)
+                dc_resource_state_copy_construct(old_state->context,
+                                                 new_state->context);
+
+        return &new_state->base;
+}
+
+static void dm_atomic_destroy_state(struct drm_private_obj *obj,
+                                    struct drm_private_state *state)
+{
+        struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
+
+        if (dm_state && dm_state->context)
+                dc_release_state(dm_state->context);
+
+        kfree(dm_state);
+}
+
+static struct drm_private_state_funcs dm_atomic_state_funcs = {
+        .atomic_duplicate_state = dm_atomic_duplicate_state,
+        .atomic_destroy_state = dm_atomic_destroy_state,
+};
+
 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
 {
+        struct dm_atomic_state *state;
         int r;
 
         adev->mode_info.mode_config_initialized = true;
@@ -1562,6 +1649,24 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
 
         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
 
+        drm_modeset_lock_init(&adev->dm.atomic_obj_lock);
+
+        state = kzalloc(sizeof(*state), GFP_KERNEL);
+        if (!state)
+                return -ENOMEM;
+
+        state->context = dc_create_state();
+        if (!state->context) {
+                kfree(state);
+                return -ENOMEM;
+        }
+
+        dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
+
+        drm_atomic_private_obj_init(&adev->dm.atomic_obj,
+                                    &state->base,
+                                    &dm_atomic_state_funcs);
+
         r = amdgpu_display_modeset_create_props(adev);
         if (r)
                 return r;
@@ -1569,27 +1674,60 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
         return 0;
 }
 
+#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
+#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
+
 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 
+static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
+{
+#if defined(CONFIG_ACPI)
+        struct amdgpu_dm_backlight_caps caps;
+
+        if (dm->backlight_caps.caps_valid)
+                return;
+
+        amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
+        if (caps.caps_valid) {
+                dm->backlight_caps.min_input_signal = caps.min_input_signal;
+                dm->backlight_caps.max_input_signal = caps.max_input_signal;
+                dm->backlight_caps.caps_valid = true;
+        } else {
+                dm->backlight_caps.min_input_signal =
+                                AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
+                dm->backlight_caps.max_input_signal =
+                                AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
+        }
+#else
+        dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
+        dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
+#endif
+}
+
 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
 {
         struct amdgpu_display_manager *dm = bl_get_data(bd);
+        struct amdgpu_dm_backlight_caps caps;
+        uint32_t brightness = bd->props.brightness;
 
-        /* backlight_pwm_u16_16 parameter is in unsigned 32 bit, 16 bit integer
-         * and 16 bit fractional, where 1.0 is max backlight value.
-         * bd->props.brightness is 8 bit format and needs to be converted by
-         * scaling via copy lower byte to upper byte of 16 bit value.
-         */
-        uint32_t brightness = bd->props.brightness * 0x101;
-
+        amdgpu_dm_update_backlight_caps(dm);
+        caps = dm->backlight_caps;
         /*
-         * PWM interperts 0 as 100% rather than 0% because of HW
-         * limitation for level 0.  So limiting minimum brightness level
-         * to 1.
+         * The brightness input is in the range 0-255
+         * It needs to be rescaled to be between the
+         * requested min and max input signal
+         *
+         * It also needs to be scaled up by 0x101 to
+         * match the DC interface which has a range of
+         * 0 to 0xffff
          */
-        if (bd->props.brightness < 1)
-                brightness = 0x101;
+        brightness =
+                brightness
+                * 0x101
+                * (caps.max_input_signal - caps.min_input_signal)
+                / AMDGPU_MAX_BL_LEVEL
+                + caps.min_input_signal * 0x101;
 
         if (dc_link_set_backlight_level(dm->backlight_link,
                         brightness, 0, 0))
@@ -1619,6 +1757,8 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
         char bl_name[16];
         struct backlight_properties props = { 0 };
 
+        amdgpu_dm_update_backlight_caps(dm);
+
         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
         props.brightness = AMDGPU_MAX_BL_LEVEL;
         props.type = BACKLIGHT_RAW;
@@ -1850,6 +1990,7 @@ fail:
 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
 {
         drm_mode_config_cleanup(dm->ddev);
+        drm_atomic_private_obj_fini(&dm->atomic_obj);
         return;
 }
 
@@ -1869,73 +2010,6 @@ static void dm_bandwidth_update(struct amdgpu_device *adev)
         /* TODO: implement later */
 }
 
-static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
-                                struct drm_file *filp)
-{
-        struct drm_atomic_state *state;
-        struct drm_modeset_acquire_ctx ctx;
-        struct drm_crtc *crtc;
-        struct drm_connector *connector;
-        struct drm_connector_state *old_con_state, *new_con_state;
-        int ret = 0;
-        uint8_t i;
-        bool enable = false;
-
-        drm_modeset_acquire_init(&ctx, 0);
-
-        state = drm_atomic_state_alloc(dev);
-        if (!state) {
-                ret = -ENOMEM;
-                goto out;
-        }
-        state->acquire_ctx = &ctx;
-
-retry:
-        drm_for_each_crtc(crtc, dev) {
-                ret = drm_atomic_add_affected_connectors(state, crtc);
-                if (ret)
-                        goto fail;
-
-                /* TODO rework amdgpu_dm_commit_planes so we don't need this */
-                ret = drm_atomic_add_affected_planes(state, crtc);
-                if (ret)
-                        goto fail;
-        }
-
-        for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
-                struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
-                struct drm_crtc_state *new_crtc_state;
-                struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
-                struct dm_crtc_state *dm_new_crtc_state;
-
-                if (!acrtc) {
-                        ASSERT(0);
-                        continue;
-                }
-
-                new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
-                dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-
-                dm_new_crtc_state->freesync_enabled = enable;
-        }
-
-        ret = drm_atomic_commit(state);
-
-fail:
-        if (ret == -EDEADLK) {
-                drm_atomic_state_clear(state);
-                drm_modeset_backoff(&ctx);
-                goto retry;
-        }
-
-        drm_atomic_state_put(state);
-
-out:
-        drm_modeset_drop_locks(&ctx);
-        drm_modeset_acquire_fini(&ctx);
-        return ret;
-}
-
 static const struct amdgpu_display_funcs dm_display_funcs = {
         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
@@ -1948,8 +2022,6 @@ static const struct amdgpu_display_funcs dm_display_funcs = {
                 dm_crtc_get_scanoutpos,/* called unconditionally */
         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
-        .notify_freesync = amdgpu_notify_freesync,
-
 };
 
 #if defined(CONFIG_DEBUG_KERNEL_DC)
@@ -2550,7 +2622,8 @@ static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_
 static void
 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
                                              const struct drm_display_mode *mode_in,
-                                             const struct drm_connector *connector)
+                                             const struct drm_connector *connector,
+                                             const struct dc_stream_state *old_stream)
 {
         struct dc_crtc_timing *timing_out = &stream->timing;
         const struct drm_display_info *info = &connector->display_info;
@@ -2576,7 +2649,18 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
                         connector);
         timing_out->scan_type = SCANNING_TYPE_NODATA;
         timing_out->hdmi_vic = 0;
-        timing_out->vic = drm_match_cea_mode(mode_in);
+
+        if(old_stream) {
+                timing_out->vic = old_stream->timing.vic;
+                timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
+                timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
+        } else {
+                timing_out->vic = drm_match_cea_mode(mode_in);
+                if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
+                        timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
+                if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
+                        timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
+        }
 
         timing_out->h_addressable = mode_in->crtc_hdisplay;
         timing_out->h_total = mode_in->crtc_htotal;
@@ -2592,10 +2676,6 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
         timing_out->pix_clk_khz = mode_in->crtc_clock;
         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
-        if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
-                timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
-        if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
-                timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
 
         stream->output_color_space = get_output_color_space(timing_out);
 
@@ -2758,13 +2838,18 @@ static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
 static struct dc_stream_state *
 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
                        const struct drm_display_mode *drm_mode,
-                       const struct dm_connector_state *dm_state)
+                       const struct dm_connector_state *dm_state,
+                       const struct dc_stream_state *old_stream)
 {
         struct drm_display_mode *preferred_mode = NULL;
         struct drm_connector *drm_connector;
         struct dc_stream_state *stream = NULL;
         struct drm_display_mode mode = *drm_mode;
         bool native_mode_found = false;
+        bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
+        int mode_refresh;
+        int preferred_refresh = 0;
+
         struct dc_sink *sink = NULL;
         if (aconnector == NULL) {
                 DRM_ERROR("aconnector is NULL!\n");
@@ -2803,6 +2888,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
                                 struct drm_display_mode,
                                 head);
 
+        mode_refresh = drm_mode_vrefresh(&mode);
+
         if (preferred_mode == NULL) {
                 /*
                  * This may not be an error, the use case is when we have no
@@ -2815,13 +2902,23 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
                 decide_crtc_timing_for_drm_display_mode(
                                 &mode, preferred_mode,
                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
+                preferred_refresh = drm_mode_vrefresh(preferred_mode);
         }
 
         if (!dm_state)
                 drm_mode_set_crtcinfo(&mode, 0);
 
-        fill_stream_properties_from_drm_display_mode(stream,
-                        &mode, &aconnector->base);
+        /*
+        * If scaling is enabled and refresh rate didn't change
+        * we copy the vic and polarities of the old timings
+        */
+        if (!scale || mode_refresh != preferred_refresh)
+                fill_stream_properties_from_drm_display_mode(stream,
+                        &mode, &aconnector->base, NULL);
+        else
+                fill_stream_properties_from_drm_display_mode(stream,
+                        &mode, &aconnector->base, old_stream);
+
         update_stream_scaling_settings(&mode, dm_state, stream);
 
         fill_audio_info(
@@ -2901,7 +2998,9 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
 
         state->adjust = cur->adjust;
         state->vrr_infopacket = cur->vrr_infopacket;
-        state->freesync_enabled = cur->freesync_enabled;
+        state->abm_level = cur->abm_level;
+        state->vrr_supported = cur->vrr_supported;
+        state->freesync_config = cur->freesync_config;
 
         /* TODO Duplicate dc_stream after objects are stream object is flattened */
 
@@ -2995,9 +3094,11 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
                         rmx_type = RMX_FULL;
                         break;
                 case DRM_MODE_SCALE_NONE:
-                default:
                         rmx_type = RMX_OFF;
                         break;
+                default:
+                        rmx_type = RMX_ASPECT;
+                        break;
                 }
 
                 if (dm_old_state->scaling == rmx_type)
@@ -3017,6 +3118,9 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
         } else if (property == adev->mode_info.max_bpc_property) {
                 dm_new_state->max_bpc = val;
                 ret = 0;
+        } else if (property == adev->mode_info.abm_level_property) {
+                dm_new_state->abm_level = val;
+                ret = 0;
         }
 
         return ret;
@@ -3062,7 +3166,11 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
         } else if (property == adev->mode_info.max_bpc_property) {
                 *val = dm_state->max_bpc;
                 ret = 0;
+        } else if (property == adev->mode_info.abm_level_property) {
+                *val = dm_state->abm_level;
+                ret = 0;
         }
+
         return ret;
 }
 
@@ -3102,7 +3210,7 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
         state = kzalloc(sizeof(*state), GFP_KERNEL);
 
         if (state) {
-                state->scaling = RMX_OFF;
+                state->scaling = RMX_ASPECT;
                 state->underscan_enable = false;
                 state->underscan_hborder = 0;
                 state->underscan_vborder = 0;
@@ -3126,7 +3234,7 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 
         new_state->freesync_capable = state->freesync_capable;
-        new_state->freesync_enable = state->freesync_enable;
+        new_state->abm_level = state->abm_level;
 
         return &new_state->base;
 }
@@ -3228,7 +3336,7 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec
                 goto fail;
         }
 
-        stream = create_stream_for_sink(aconnector, mode, NULL);
+        stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
         if (stream == NULL) {
                 DRM_ERROR("Failed to create stream for sink!\n");
                 goto fail;
@@ -3876,6 +3984,17 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
                                 adev->mode_info.max_bpc_property,
                                 0);
 
+        if (connector_type == DRM_MODE_CONNECTOR_eDP &&
+            dc_is_dmcu_initialized(adev->dm.dc)) {
+                drm_object_attach_property(&aconnector->base.base,
+                                adev->mode_info.abm_level_property, 0);
+        }
+
+        if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
+            connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+                drm_connector_attach_vrr_capable_property(
+                        &aconnector->base);
+        }
 }
 
 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
@@ -4252,6 +4371,91 @@ static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
                                                  acrtc->crtc_id);
 }
 
+struct dc_stream_status *dc_state_get_stream_status(
+        struct dc_state *state,
+        struct dc_stream_state *stream)
+{
+        uint8_t i;
+
+        for (i = 0; i < state->stream_count; i++) {
+                if (stream == state->streams[i])
+                        return &state->stream_status[i];
+        }
+
+        return NULL;
+}
+
+static void update_freesync_state_on_stream(
+        struct amdgpu_display_manager *dm,
+        struct dm_crtc_state *new_crtc_state,
+        struct dc_stream_state *new_stream)
+{
+        struct mod_vrr_params vrr = {0};
+        struct dc_info_packet vrr_infopacket = {0};
+        struct mod_freesync_config config = new_crtc_state->freesync_config;
+
+        if (!new_stream)
+                return;
+
+        /*
+         * TODO: Determine why min/max totals and vrefresh can be 0 here.
+         * For now it's sufficient to just guard against these conditions.
+         */
+
+        if (!new_stream->timing.h_total || !new_stream->timing.v_total)
+                return;
+
+        if (new_crtc_state->vrr_supported &&
+            config.min_refresh_in_uhz &&
+            config.max_refresh_in_uhz) {
+                config.state = new_crtc_state->base.vrr_enabled ?
+                        VRR_STATE_ACTIVE_VARIABLE :
+                        VRR_STATE_INACTIVE;
+        } else {
+                config.state = VRR_STATE_UNSUPPORTED;
+        }
+
+        mod_freesync_build_vrr_params(dm->freesync_module,
+                                      new_stream,
+                                      &config, &vrr);
+
+        mod_freesync_build_vrr_infopacket(
+                dm->freesync_module,
+                new_stream,
+                &vrr,
+                packet_type_vrr,
+                transfer_func_unknown,
+                &vrr_infopacket);
+
+        new_crtc_state->freesync_timing_changed =
+                (memcmp(&new_crtc_state->adjust,
+                        &vrr.adjust,
+                        sizeof(vrr.adjust)) != 0);
+
+        new_crtc_state->freesync_vrr_info_changed =
+                (memcmp(&new_crtc_state->vrr_infopacket,
+                        &vrr_infopacket,
+                        sizeof(vrr_infopacket)) != 0);
+
+        new_crtc_state->adjust = vrr.adjust;
+        new_crtc_state->vrr_infopacket = vrr_infopacket;
+
+        new_stream->adjust = new_crtc_state->adjust;
+        new_stream->vrr_infopacket = vrr_infopacket;
+
+        if (new_crtc_state->freesync_vrr_info_changed)
+                DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
+                              new_crtc_state->base.crtc->base.id,
+                              (int)new_crtc_state->base.vrr_enabled,
+                              (int)vrr.state);
+
+        if (new_crtc_state->freesync_timing_changed)
+                DRM_DEBUG_KMS("VRR timing update: crtc=%u min=%u max=%u\n",
+                              new_crtc_state->base.crtc->base.id,
+                              vrr.adjust.v_total_min,
+                              vrr.adjust.v_total_max);
+}
+
 /*
  * Executes flip
  *
@@ -4273,6 +4477,7 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
         struct dc_flip_addrs addr = { {0} };
         /* TODO eliminate or rename surface_update */
         struct dc_surface_update surface_updates[1] = { {0} };
+        struct dc_stream_update stream_update = {0};
         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
         struct dc_stream_status *stream_status;
 
@@ -4345,11 +4550,26 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
         }
         surface_updates->flip_addr = &addr;
 
+        if (acrtc_state->stream) {
+                update_freesync_state_on_stream(
+                        &adev->dm,
+                        acrtc_state,
+                        acrtc_state->stream);
+
+                if (acrtc_state->freesync_timing_changed)
+                        stream_update.adjust =
+                                &acrtc_state->stream->adjust;
+
+                if (acrtc_state->freesync_vrr_info_changed)
+                        stream_update.vrr_infopacket =
+                                &acrtc_state->stream->vrr_infopacket;
+        }
+
         dc_commit_updates_for_stream(adev->dm.dc,
                                              surface_updates,
                                              1,
                                              acrtc_state->stream,
-                                             NULL,
+                                             &stream_update,
                                              &surface_updates->surface,
                                              state);
 
@@ -4382,6 +4602,7 @@ static bool commit_planes_to_stream(
         struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
         struct dc_stream_update *stream_update =
                         kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
+        unsigned int abm_level;
 
         if (!stream_update) {
                 BREAK_TO_DEBUGGER();
@@ -4409,9 +4630,9 @@ static bool commit_planes_to_stream(
         stream_update->dst = dc_stream->dst;
         stream_update->out_transfer_func = dc_stream->out_transfer_func;
 
-        if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) {
-                stream_update->vrr_infopacket = &dc_stream->vrr_infopacket;
-                stream_update->adjust = &dc_stream->adjust;
+        if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
+                abm_level = dm_new_crtc_state->abm_level;
+                stream_update->abm_level = &abm_level;
         }
 
         for (i = 0; i < new_plane_count; i++) {
@@ -4455,6 +4676,7 @@ static bool commit_planes_to_stream(
 }
 
 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+                                    struct dc_state *dc_state,
                                     struct drm_device *dev,
                                     struct amdgpu_display_manager *dm,
                                     struct drm_crtc *pcrtc,
@@ -4471,7 +4693,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
         struct dm_crtc_state *dm_old_crtc_state =
                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
-        struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
         int planes_count = 0;
         unsigned long flags;
 
@@ -4532,7 +4753,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                                 crtc,
                                 fb,
                                 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
-                                dm_state->context);
+                                dc_state);
                 }
 
         }
@@ -4549,15 +4770,14 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
                 }
 
-                dc_stream_attach->adjust = acrtc_state->adjust;
-                dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket;
+                dc_stream_attach->abm_level = acrtc_state->abm_level;
 
                 if (false == commit_planes_to_stream(dm->dc,
                                                         plane_states_constructed,
                                                         planes_count,
                                                         acrtc_state,
                                                         dm_old_crtc_state,
-                                                        dm_state->context))
+                                                        dc_state))
                         dm_error("%s: Failed to attach plane!\n", __func__);
         } else {
                 /*TODO BUG Here should go disable planes on CRTC. */
@@ -4625,6 +4845,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
         struct amdgpu_device *adev = dev->dev_private;
         struct amdgpu_display_manager *dm = &adev->dm;
         struct dm_atomic_state *dm_state;
+        struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
         uint32_t i, j;
         struct drm_crtc *crtc;
         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
@@ -4637,7 +4858,16 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 
         drm_atomic_helper_update_legacy_modeset_state(dev, state);
 
-        dm_state = to_dm_atomic_state(state);
+        dm_state = dm_atomic_get_new_state(state);
+        if (dm_state && dm_state->context) {
+                dc_state = dm_state->context;
+        } else {
+                /* No state changes, retain current state. */
+                dc_state_temp = dc_create_state();
+                ASSERT(dc_state_temp);
+                dc_state = dc_state_temp;
+                dc_resource_state_copy_construct_current(dm->dc, dc_state);
+        }
 
         /* update changed items */
         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -4710,9 +4940,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                 }
         } /* for_each_crtc_in_state() */
 
-        if (dm_state->context) {
-                dm_enable_per_frame_crtc_master_sync(dm_state->context);
-                WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
+        if (dc_state) {
+                dm_enable_per_frame_crtc_master_sync(dc_state);
+                WARN_ON(!dc_commit_state(dm->dc, dc_state));
         }
 
         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
@@ -4725,13 +4955,17 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                                         dc_stream_get_status(dm_new_crtc_state->stream);
 
                         if (!status)
+                                status = dc_state_get_stream_status(dc_state,
+                                                                    dm_new_crtc_state->stream);
+
+                        if (!status)
                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
                         else
                                 acrtc->otg_inst = status->primary_otg_inst;
                 }
         }
 
-        /* Handle scaling and underscan changes*/
+        /* Handle scaling, underscan, and abm changes*/
         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
@@ -4747,11 +4981,14 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
                         continue;
 
-                /* Skip anything that is not scaling or underscan changes */
-                if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
-                        continue;
 
                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+                dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+
+                /* Skip anything that is not scaling or underscan changes */
+                if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
+                                (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
+                        continue;
 
                 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
                                 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
@@ -4763,8 +5000,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                 WARN_ON(!status);
                 WARN_ON(!status->plane_count);
 
-                dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust;
-                dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket;
+                dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
 
                 /*TODO How it works with MPO ?*/
                 if (!commit_planes_to_stream(
@@ -4773,7 +5009,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                                 status->plane_count,
                                 dm_new_crtc_state,
                                 to_dm_crtc_state(old_crtc_state),
-                                dm_state->context))
+                                dc_state))
                         dm_error("%s: Failed to update stream scaling!\n", __func__);
         }
 
@@ -4806,7 +5042,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
 
                 if (dm_new_crtc_state->stream)
-                        amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
+                        amdgpu_dm_commit_planes(state, dc_state, dev,
+                                                dm, crtc, &wait_for_vblank);
         }
 
 
@@ -4846,6 +5083,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
         for (i = 0; i < crtc_disable_count; i++)
                 pm_runtime_put_autosuspend(dev->dev);
         pm_runtime_mark_last_busy(dev->dev);
+
+        if (dc_state_temp)
+                dc_release_state(dc_state_temp);
 }
 
 
@@ -4989,20 +5229,18 @@ static int do_aquire_global_lock(struct drm_device *dev,
         return ret < 0 ? ret : 0;
 }
 
-void set_freesync_on_stream(struct amdgpu_display_manager *dm,
-                            struct dm_crtc_state *new_crtc_state,
-                            struct dm_connector_state *new_con_state,
-                            struct dc_stream_state *new_stream)
+static void get_freesync_config_for_crtc(
+        struct dm_crtc_state *new_crtc_state,
+        struct dm_connector_state *new_con_state)
 {
         struct mod_freesync_config config = {0};
-        struct mod_vrr_params vrr = {0};
-        struct dc_info_packet vrr_infopacket = {0};
         struct amdgpu_dm_connector *aconnector =
                         to_amdgpu_dm_connector(new_con_state->base.connector);
 
-        if (new_con_state->freesync_capable &&
-            new_con_state->freesync_enable) {
-                config.state = new_crtc_state->freesync_enabled ?
+        new_crtc_state->vrr_supported = new_con_state->freesync_capable;
+
+        if (new_con_state->freesync_capable) {
+                config.state = new_crtc_state->base.vrr_enabled ?
                                 VRR_STATE_ACTIVE_VARIABLE :
                                 VRR_STATE_INACTIVE;
                 config.min_refresh_in_uhz =
@@ -5012,19 +5250,18 @@ void set_freesync_on_stream(struct amdgpu_display_manager *dm,
                 config.vsif_supported = true;
         }
 
-        mod_freesync_build_vrr_params(dm->freesync_module,
-                                      new_stream,
-                                      &config, &vrr);
+        new_crtc_state->freesync_config = config;
+}
 
-        mod_freesync_build_vrr_infopacket(dm->freesync_module,
-                                          new_stream,
-                                          &vrr,
-                                          packet_type_fs1,
-                                          NULL,
-                                          &vrr_infopacket);
+static void reset_freesync_config_for_crtc(
+        struct dm_crtc_state *new_crtc_state)
+{
+        new_crtc_state->vrr_supported = false;
 
-        new_crtc_state->adjust = vrr.adjust;
-        new_crtc_state->vrr_infopacket = vrr_infopacket;
+        memset(&new_crtc_state->adjust, 0,
+               sizeof(new_crtc_state->adjust));
+        memset(&new_crtc_state->vrr_infopacket, 0,
+               sizeof(new_crtc_state->vrr_infopacket));
 }
 
 static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
@@ -5032,11 +5269,11 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
                                  bool enable,
                                  bool *lock_and_validation_needed)
 {
+        struct dm_atomic_state *dm_state = NULL;
         struct drm_crtc *crtc;
         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
         int i;
         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
-        struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
         struct dc_stream_state *new_stream;
         int ret = 0;
 
@@ -5084,7 +5321,8 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
 
                         new_stream = create_stream_for_sink(aconnector,
                                                              &new_crtc_state->mode,
-                                                            dm_new_conn_state);
+                                                            dm_new_conn_state,
+                                                            dm_old_crtc_state->stream);
 
                         /*
                          * we can have no stream on ACTION_SET if a display
@@ -5099,8 +5337,7 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
                                 break;
                         }
 
-                        set_freesync_on_stream(dm, dm_new_crtc_state,
-                                               dm_new_conn_state, new_stream);
+                        dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
 
                         if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
                             dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
@@ -5110,9 +5347,6 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
                         }
                 }
 
-                if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled)
-                        new_crtc_state->mode_changed = true;
-
                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
                         goto next_crtc;
 
@@ -5134,6 +5368,10 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
                         if (!dm_old_crtc_state->stream)
                                 goto next_crtc;
 
+                        ret = dm_atomic_get_state(state, &dm_state);
+                        if (ret)
+                                goto fail;
+
                         DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
                                         crtc->base.id);
 
@@ -5149,6 +5387,8 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
                         dc_stream_release(dm_old_crtc_state->stream);
                         dm_new_crtc_state->stream = NULL;
 
+                        reset_freesync_config_for_crtc(dm_new_crtc_state);
+
                         *lock_and_validation_needed = true;
 
                 } else {/* Add stream for any updated/enabled CRTC */
@@ -5168,6 +5408,10 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
 
                                 WARN_ON(dm_new_crtc_state->stream);
 
+                                ret = dm_atomic_get_state(state, &dm_state);
+                                if (ret)
+                                        goto fail;
+
                                 dm_new_crtc_state->stream = new_stream;
 
                                 dc_stream_retain(new_stream);
@@ -5226,7 +5470,9 @@ next_crtc:
                         amdgpu_dm_set_ctm(dm_new_crtc_state);
                 }
 
-
+                /* Update Freesync settings. */
+                get_freesync_config_for_crtc(dm_new_crtc_state,
+                                             dm_new_conn_state);
         }
 
         return ret;
@@ -5242,12 +5488,13 @@ static int dm_update_planes_state(struct dc *dc,
                                   bool enable,
                                   bool *lock_and_validation_needed)
 {
+
+        struct dm_atomic_state *dm_state = NULL;
         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
         struct drm_plane *plane;
         struct drm_plane_state *old_plane_state, *new_plane_state;
         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
-        struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
         int i ;
         /* TODO return page_flip_needed() function */
@@ -5285,6 +5532,10 @@ static int dm_update_planes_state(struct dc *dc,
                         DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
                                         plane->base.id, old_plane_crtc->base.id);
 
+                        ret = dm_atomic_get_state(state, &dm_state);
+                        if (ret)
+                                return ret;
+
                         if (!dc_remove_plane_from_context(
                                         dc,
                                         dm_old_crtc_state->stream,
@@ -5339,6 +5590,12 @@ static int dm_update_planes_state(struct dc *dc,
                                 return ret;
                         }
 
+                        ret = dm_atomic_get_state(state, &dm_state);
+                        if (ret) {
+                                dc_plane_state_release(dc_new_plane_state);
+                                return ret;
+                        }
+
                         /*
                          * Any atomic check errors that occur after this will
                          * not need a release. The plane state will be attached
@@ -5370,11 +5627,14 @@ static int dm_update_planes_state(struct dc *dc,
 
         return ret;
 }
-enum surface_update_type dm_determine_update_type_for_commit(struct dc *dc, struct drm_atomic_state *state)
-{
-
 
-        int i, j, num_plane;
+static int
+dm_determine_update_type_for_commit(struct dc *dc,
+                                    struct drm_atomic_state *state,
+                                    enum surface_update_type *out_type)
+{
+        struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
+        int i, j, num_plane, ret = 0;
         struct drm_plane_state *old_plane_state, *new_plane_state;
         struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
@@ -5394,7 +5654,7 @@ enum surface_update_type dm_determine_update_type_for_commit(struct dc *dc, stru
                 DRM_ERROR("Plane or surface update failed to allocate");
                 /* Set type to FULL to avoid crashing in DC*/
                 update_type = UPDATE_TYPE_FULL;
-                goto ret;
+                goto cleanup;
         }
 
         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -5448,27 +5708,40 @@ enum surface_update_type dm_determine_update_type_for_commit(struct dc *dc, stru
                         }
 
                         if (num_plane > 0) {
-                                status = dc_stream_get_status(new_dm_crtc_state->stream);
+                                ret = dm_atomic_get_state(state, &dm_state);
+                                if (ret)
+                                        goto cleanup;
+
+                                old_dm_state = dm_atomic_get_old_state(state);
+                                if (!old_dm_state) {
+                                        ret = -EINVAL;
+                                        goto cleanup;
+                                }
+
+                                status = dc_state_get_stream_status(old_dm_state->context,
+                                                                    new_dm_crtc_state->stream);
+
                                 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
                                                                                   &stream_update, status);
 
                                 if (update_type > UPDATE_TYPE_MED) {
                                         update_type = UPDATE_TYPE_FULL;
-                                        goto ret;
+                                        goto cleanup;
                                 }
                         }
 
                 } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) {
                         update_type = UPDATE_TYPE_FULL;
-                        goto ret;
+                        goto cleanup;
                 }
         }
 
-ret:
+cleanup:
         kfree(updates);
         kfree(surface);
 
-        return update_type;
+        *out_type = update_type;
+        return ret;
 }
 
 /**
@@ -5500,8 +5773,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
                                   struct drm_atomic_state *state)
 {
         struct amdgpu_device *adev = dev->dev_private;
+        struct dm_atomic_state *dm_state = NULL;
         struct dc *dc = adev->dm.dc;
-        struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
         struct drm_connector *connector;
         struct drm_connector_state *old_con_state, *new_con_state;
         struct drm_crtc *crtc;
@@ -5522,12 +5795,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
                 goto fail;
 
         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-                struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-                struct dm_crtc_state *dm_old_crtc_state  = to_dm_crtc_state(old_crtc_state);
-
                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
                     !new_crtc_state->color_mgmt_changed &&
-                    (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled))
+                    !new_crtc_state->vrr_enabled)
                         continue;
 
                 if (!new_crtc_state->enable)
@@ -5542,10 +5812,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
                         goto fail;
         }
 
-        dm_state->context = dc_create_state();
-        ASSERT(dm_state->context);
-        dc_resource_state_copy_construct_current(dc, dm_state->context);
-
         /* Remove exiting planes if they are modified */
         ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
         if (ret) {
@@ -5598,7 +5864,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
                 lock_and_validation_needed = true;
         }
 
-        update_type = dm_determine_update_type_for_commit(dc, state);
+        ret = dm_determine_update_type_for_commit(dc, state, &update_type);
+        if (ret)
+                goto fail;
 
         if (overall_update_type < update_type)
                 overall_update_type = update_type;
@@ -5616,6 +5884,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 
 
         if (overall_update_type > UPDATE_TYPE_FAST) {
+                ret = dm_atomic_get_state(state, &dm_state);
+                if (ret)
+                        goto fail;
 
                 ret = do_aquire_global_lock(dev, state);
                 if (ret)
@@ -5670,14 +5941,15 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
         struct detailed_data_monitor_range *range;
         struct amdgpu_dm_connector *amdgpu_dm_connector =
                         to_amdgpu_dm_connector(connector);
-        struct dm_connector_state *dm_con_state;
+        struct dm_connector_state *dm_con_state = NULL;
 
         struct drm_device *dev = connector->dev;
         struct amdgpu_device *adev = dev->dev_private;
+        bool freesync_capable = false;
 
         if (!connector->state) {
                 DRM_ERROR("%s - Connector has no state", __func__);
-                return;
+                goto update;
         }
 
         if (!edid) {
@@ -5687,9 +5959,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
                 amdgpu_dm_connector->max_vfreq = 0;
                 amdgpu_dm_connector->pixel_clock_mhz = 0;
 
-                dm_con_state->freesync_capable = false;
-                dm_con_state->freesync_enable = false;
-                return;
+                goto update;
         }
 
         dm_con_state = to_dm_connector_state(connector->state);
@@ -5697,10 +5967,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
         edid_check_required = false;
         if (!amdgpu_dm_connector->dc_sink) {
                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
-                return;
+                goto update;
         }
         if (!adev->dm.freesync_module)
-                return;
+                goto update;
         /*
          * if edid non zero restrict freesync only for dp and edp
          */
@@ -5712,7 +5982,6 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
                                                 amdgpu_dm_connector);
                 }
         }
-        dm_con_state->freesync_capable = false;
         if (edid_check_required == true && (edid->version > 1 ||
            (edid->version == 1 && edid->revision > 1))) {
                 for (i = 0; i < 4; i++) {
@@ -5744,8 +6013,16 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
                 if (amdgpu_dm_connector->max_vfreq -
                     amdgpu_dm_connector->min_vfreq > 10) {
 
-                        dm_con_state->freesync_capable = true;
+                        freesync_capable = true;
                 }
         }
+
+update:
+        if (dm_con_state)
+                dm_con_state->freesync_capable = freesync_capable;
+
+        if (connector->vrr_capable_property)
+                drm_connector_set_vrr_capable_property(connector,
+                                                       freesync_capable);
 }
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 607c3cdd7d0c..4326dc256491 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -84,6 +84,18 @@ struct dm_comressor_info {
 };
 
 /**
+ * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI
+ * @min_input_signal: minimum possible input in range 0-255
+ * @max_input_signal: maximum possible input in range 0-255
+ * @caps_valid: true if these values are from the ACPI interface
+ */
+struct amdgpu_dm_backlight_caps {
+        int min_input_signal;
+        int max_input_signal;
+        bool caps_valid;
+};
+
+/**
  * struct amdgpu_display_manager - Central amdgpu display manager device
  *
  * @dc: Display Core control structure
@@ -112,6 +124,17 @@ struct amdgpu_display_manager {
         u16 display_indexes_num;
 
         /**
+         * @atomic_obj
+         *
+         * In combination with &dm_atomic_state it helps manage
+         * global atomic state that doesn't map cleanly into existing
+         * drm resources, like &dc_context.
+         */
+        struct drm_private_obj atomic_obj;
+
+        struct drm_modeset_lock atomic_obj_lock;
+
+        /**
          * @irq_handler_list_low_tab:
          *
          * Low priority IRQ handler table.
@@ -158,6 +181,7 @@ struct amdgpu_display_manager {
         struct backlight_device *backlight_dev;
 
         const struct dc_link *backlight_link;
+        struct amdgpu_dm_backlight_caps backlight_caps;
 
         struct mod_freesync *freesync_module;
 
@@ -231,15 +255,21 @@ struct dm_crtc_state {
         int crc_skip_count;
         bool crc_enabled;
 
-        bool freesync_enabled;
+        bool freesync_timing_changed;
+        bool freesync_vrr_info_changed;
+
+        bool vrr_supported;
+        struct mod_freesync_config freesync_config;
         struct dc_crtc_timing_adjust adjust;
         struct dc_info_packet vrr_infopacket;
+
+        int abm_level;
 };
 
 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
 
 struct dm_atomic_state {
-        struct drm_atomic_state base;
+        struct drm_private_state base;
 
         struct dc_state *context;
 };
@@ -254,8 +284,8 @@ struct dm_connector_state {
         uint8_t underscan_hborder;
         uint8_t max_bpc;
         bool underscan_enable;
-        bool freesync_enable;
         bool freesync_capable;
+        uint8_t abm_level;
 };
 
 #define to_dm_connector_state(x)\
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 3279e26c3440..dba6b57830c7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -328,7 +328,7 @@ void dc_stream_set_dither_option(struct dc_stream_state *stream,
                 enum dc_dither_option option)
 {
         struct bit_depth_reduction_params params;
-        struct dc_link *link = stream->status.link;
+        struct dc_link *link = stream->sink->link;
         struct pipe_ctx *pipes = NULL;
         int i;
 
@@ -1686,6 +1686,15 @@ void dc_resume(struct dc *dc)
                 core_link_resume(dc->links[i]);
 }
 
+bool dc_is_dmcu_initialized(struct dc *dc)
+{
+        struct dmcu *dmcu = dc->res_pool->dmcu;
+
+        if (dmcu)
+                return dmcu->funcs->is_dmcu_initialized(dmcu);
+        return false;
+}
+
 bool dc_submit_i2c(
                 struct dc *dc,
                 uint32_t link_index,
@@ -1810,4 +1819,4 @@ void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx
         info->dcfClockDeepSleep                 = (unsigned int)state->bw.dcn.clk.dcfclk_deep_sleep_khz;
         info->fClock                                    = (unsigned int)state->bw.dcn.clk.fclk_khz;
         info->phyClock                                  = (unsigned int)state->bw.dcn.clk.phyclk_khz;
-}
\ No newline at end of file
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 7ee9c033acbd..948596a02392 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1396,8 +1396,6 @@ static enum dc_status enable_link_dp(
         else
                 status = DC_FAIL_DP_LINK_TRAINING;
 
-        enable_stream_features(pipe_ctx);
-
         return status;
 }
 
@@ -2175,11 +2173,11 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
                         backlight_pwm_u16_16, backlight_pwm_u16_16);
 
         if (dc_is_embedded_signal(link->connector_signal)) {
-                if (stream != NULL) {
-                        for (i = 0; i < MAX_PIPES; i++) {
+                for (i = 0; i < MAX_PIPES; i++) {
+                        if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
                                 if (core_dc->current_state->res_ctx.
-                                                pipe_ctx[i].stream
-                                                == stream)
+                                                pipe_ctx[i].stream->sink->link
+                                                == link)
                                         /* DMCU -1 for all controller id values,
                                          * therefore +1 here
                                          */
@@ -2218,7 +2216,7 @@ bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
         struct dc  *core_dc = link->ctx->dc;
         struct dmcu *dmcu = core_dc->res_pool->dmcu;
 
-        if (dmcu != NULL && link->psr_enabled)
+        if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)
                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
 
         return true;
@@ -2594,6 +2592,9 @@ void core_link_enable_stream(
                 core_dc->hwss.unblank_stream(pipe_ctx,
                         &pipe_ctx->stream->sink->link->cur_link_settings);
 
+                if (dc_is_dp_signal(pipe_ctx->stream->signal))
+                        enable_stream_features(pipe_ctx);
+
                 dc_link_set_backlight_level(pipe_ctx->stream->sink->link,
                                 pipe_ctx->stream->bl_pwm_level,
                                 0,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index d91df5ef0cb3..4d1f8ac069c1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2371,11 +2371,22 @@ static bool retrieve_link_cap(struct dc_link *link)
                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
 
                 if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
-                        core_link_read_dpcd(
+                        uint8_t ext_cap_data[16];
+
+                        memset(ext_cap_data, '\0', sizeof(ext_cap_data));
+                        for (i = 0; i < read_dpcd_retry_cnt; i++) {
+                                status = core_link_read_dpcd(
                                 link,
                                 DP_DP13_DPCD_REV,
-                                dpcd_data,
-                                sizeof(dpcd_data));
+                                ext_cap_data,
+                                sizeof(ext_cap_data));
+                                if (status == DC_OK) {
+                                        memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
+                                        break;
+                                }
+                        }
+                        if (status != DC_OK)
+                                dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
                 }
         }
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index fc65b0055167..0bb844a7b990 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -478,10 +478,29 @@ static enum pixel_format convert_pixel_format_to_dalsurface(
         return dal_pixel_format;
 }
 
-static void rect_swap_helper(struct rect *rect)
-{
-        swap(rect->height, rect->width);
-        swap(rect->x, rect->y);
+static inline void get_vp_scan_direction(
+        enum dc_rotation_angle rotation,
+        bool horizontal_mirror,
+        bool *orthogonal_rotation,
+        bool *flip_vert_scan_dir,
+        bool *flip_horz_scan_dir)
+{
+        *orthogonal_rotation = false;
+        *flip_vert_scan_dir = false;
+        *flip_horz_scan_dir = false;
+        if (rotation == ROTATION_ANGLE_180) {
+                *flip_vert_scan_dir = true;
+                *flip_horz_scan_dir = true;
+        } else if (rotation == ROTATION_ANGLE_90) {
+                *orthogonal_rotation = true;
+                *flip_horz_scan_dir = true;
+        } else if (rotation == ROTATION_ANGLE_270) {
+                *orthogonal_rotation = true;
+                *flip_vert_scan_dir = true;
+        }
+
+        if (horizontal_mirror)
+                *flip_horz_scan_dir = !*flip_horz_scan_dir;
 }
 
 static void calculate_viewport(struct pipe_ctx *pipe_ctx)
@@ -490,33 +509,14 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
         const struct dc_stream_state *stream = pipe_ctx->stream;
         struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
         struct rect surf_src = plane_state->src_rect;
-        struct rect clip = { 0 };
+        struct rect clip, dest;
         int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
                         || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
         bool pri_split = pipe_ctx->bottom_pipe &&
                         pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
         bool sec_split = pipe_ctx->top_pipe &&
                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
-        bool flip_vert_scan_dir = false, flip_horz_scan_dir = false;
-
-
-        /*
-         * We need take horizontal mirror into account. On an unrotated surface this means
-         * that the viewport offset is actually the offset from the other side of source
-         * image so we have to subtract the right edge of the viewport from the right edge of
-         * the source window. Similar to mirror we need to take into account how offset is
-         * affected for 270/180 rotations
-         */
-        if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_180) {
-                flip_vert_scan_dir = true;
-                flip_horz_scan_dir = true;
-        } else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90)
-                flip_vert_scan_dir = true;
-        else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
-                flip_horz_scan_dir = true;
-
-        if (pipe_ctx->plane_state->horizontal_mirror)
-                flip_horz_scan_dir = !flip_horz_scan_dir;
+        bool orthogonal_rotation, flip_y_start, flip_x_start;
 
         if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
                 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
@@ -524,13 +524,10 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
                 sec_split = false;
         }
 
-        if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
-                        pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
-                rect_swap_helper(&surf_src);
-
         /* The actual clip is an intersection between stream
          * source and surface clip
          */
+        dest = plane_state->dst_rect;
         clip.x = stream->src.x > plane_state->clip_rect.x ?
                         stream->src.x : plane_state->clip_rect.x;
 
@@ -547,66 +544,77 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
                         stream->src.y + stream->src.height - clip.y :
                         plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
 
-        /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
-         * note: surf_src.ofs should be added after rotation/mirror offset direction
-         *       adjustment since it is already in viewport space
-         * num_pixels = clip.num_pix * scl_ratio
+        /*
+         * Need to calculate how scan origin is shifted in vp space
+         * to correctly rotate clip and dst
          */
-        data->viewport.x = (clip.x - plane_state->dst_rect.x) *
-                        surf_src.width / plane_state->dst_rect.width;
-        data->viewport.width = clip.width *
-                        surf_src.width / plane_state->dst_rect.width;
-
-        data->viewport.y = (clip.y - plane_state->dst_rect.y) *
-                        surf_src.height / plane_state->dst_rect.height;
-        data->viewport.height = clip.height *
-                        surf_src.height / plane_state->dst_rect.height;
+        get_vp_scan_direction(
+                        plane_state->rotation,
+                        plane_state->horizontal_mirror,
+                        &orthogonal_rotation,
+                        &flip_y_start,
+                        &flip_x_start);
 
-        if (flip_vert_scan_dir)
-                data->viewport.y = surf_src.height - data->viewport.y - data->viewport.height;
-        if (flip_horz_scan_dir)
-                data->viewport.x = surf_src.width - data->viewport.x - data->viewport.width;
+        if (orthogonal_rotation) {
+                swap(clip.x, clip.y);
+                swap(clip.width, clip.height);
+                swap(dest.x, dest.y);
+                swap(dest.width, dest.height);
+        }
+        if (flip_x_start) {
+                clip.x = dest.x + dest.width - clip.x - clip.width;
+                dest.x = 0;
+        }
+        if (flip_y_start) {
+                clip.y = dest.y + dest.height - clip.y - clip.height;
+                dest.y = 0;
+        }
 
-        data->viewport.x += surf_src.x;
-        data->viewport.y += surf_src.y;
+        /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
+         * num_pixels = clip.num_pix * scl_ratio
+         */
+        data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
+        data->viewport.width = clip.width * surf_src.width / dest.width;
+
+        data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
+        data->viewport.height = clip.height * surf_src.height / dest.height;
+
+        /* Handle split */
+        if (pri_split || sec_split) {
+                if (orthogonal_rotation) {
+                        if (flip_y_start != pri_split)
+                                data->viewport.height /= 2;
+                        else {
+                                data->viewport.y +=  data->viewport.height / 2;
+                                /* Ceil offset pipe */
+                                data->viewport.height = (data->viewport.height + 1) / 2;
+                        }
+                } else {
+                        if (flip_x_start != pri_split)
+                                data->viewport.width /= 2;
+                        else {
+                                data->viewport.x +=  data->viewport.width / 2;
+                                /* Ceil offset pipe */
+                                data->viewport.width = (data->viewport.width + 1) / 2;
+                        }
+                }
+        }
 
         /* Round down, compensate in init */
         data->viewport_c.x = data->viewport.x / vpc_div;
         data->viewport_c.y = data->viewport.y / vpc_div;
-        data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
-                        dc_fixpt_half : dc_fixpt_zero;
-        data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
-                        dc_fixpt_half : dc_fixpt_zero;
+        data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
+        data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
+
         /* Round up, assume original video size always even dimensions */
         data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
         data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
-
-        /* Handle hsplit */
-        if (sec_split) {
-                data->viewport.x +=  data->viewport.width / 2;
-                data->viewport_c.x +=  data->viewport_c.width / 2;
-                /* Ceil offset pipe */
-                data->viewport.width = (data->viewport.width + 1) / 2;
-                data->viewport_c.width = (data->viewport_c.width + 1) / 2;
-        } else if (pri_split) {
-                if (data->viewport.width > 1)
-                        data->viewport.width /= 2;
-                if (data->viewport_c.width > 1)
-                        data->viewport_c.width /= 2;
-        }
-
-        if (plane_state->rotation == ROTATION_ANGLE_90 ||
-                        plane_state->rotation == ROTATION_ANGLE_270) {
-                rect_swap_helper(&data->viewport_c);
-                rect_swap_helper(&data->viewport);
-        }
 }
 
-static void calculate_recout(struct pipe_ctx *pipe_ctx, struct rect *recout_full)
+static void calculate_recout(struct pipe_ctx *pipe_ctx)
 {
         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
         const struct dc_stream_state *stream = pipe_ctx->stream;
-        struct rect surf_src = plane_state->src_rect;
         struct rect surf_clip = plane_state->clip_rect;
         bool pri_split = pipe_ctx->bottom_pipe &&
                         pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
@@ -614,10 +622,6 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct rect *recout_full
                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
         bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
 
-        if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
-                        pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
-                rect_swap_helper(&surf_src);
-
         pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
         if (stream->src.x < surf_clip.x)
                 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
@@ -646,7 +650,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct rect *recout_full
                         stream->dst.y + stream->dst.height
                                                 - pipe_ctx->plane_res.scl_data.recout.y;
 
-        /* Handle h & vsplit */
+        /* Handle h & v split, handle rotation using viewport */
         if (sec_split && top_bottom_split) {
                 pipe_ctx->plane_res.scl_data.recout.y +=
                                 pipe_ctx->plane_res.scl_data.recout.height / 2;
@@ -655,44 +659,14 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct rect *recout_full
                                 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
         } else if (pri_split && top_bottom_split)
                 pipe_ctx->plane_res.scl_data.recout.height /= 2;
-        else if (pri_split || sec_split) {
-                /* HMirror XOR Secondary_pipe XOR Rotation_180 */
-                bool right_view = (sec_split != plane_state->horizontal_mirror) !=
-                                        (plane_state->rotation == ROTATION_ANGLE_180);
-
-                if (plane_state->rotation == ROTATION_ANGLE_90
-                                || plane_state->rotation == ROTATION_ANGLE_270)
-                        /* Secondary_pipe XOR Rotation_270 */
-                        right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
-
-                if (right_view) {
-                        pipe_ctx->plane_res.scl_data.recout.x +=
-                                        pipe_ctx->plane_res.scl_data.recout.width / 2;
-                        /* Ceil offset pipe */
-                        pipe_ctx->plane_res.scl_data.recout.width =
-                                        (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
-                } else {
-                        if (pipe_ctx->plane_res.scl_data.recout.width > 1)
-                                pipe_ctx->plane_res.scl_data.recout.width /= 2;
-                }
-        }
-        /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
-         *                      * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
-         *                      ratio)
-         */
-        recout_full->x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
-                                        * stream->dst.width / stream->src.width -
-                        surf_src.x * plane_state->dst_rect.width / surf_src.width
-                                        * stream->dst.width / stream->src.width;
-        recout_full->y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
-                                        * stream->dst.height / stream->src.height -
-                        surf_src.y * plane_state->dst_rect.height / surf_src.height
-                                        * stream->dst.height / stream->src.height;
-
-        recout_full->width = plane_state->dst_rect.width
-                                        * stream->dst.width / stream->src.width;
-        recout_full->height = plane_state->dst_rect.height
-                                        * stream->dst.height / stream->src.height;
+        else if (sec_split) {
+                pipe_ctx->plane_res.scl_data.recout.x +=
+                                pipe_ctx->plane_res.scl_data.recout.width / 2;
+                /* Ceil offset pipe */
+                pipe_ctx->plane_res.scl_data.recout.width =
+                                (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
+        } else if (pri_split)
+                pipe_ctx->plane_res.scl_data.recout.width /= 2;
 }
 
 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
@@ -705,9 +679,10 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
         const int out_w = stream->dst.width;
         const int out_h = stream->dst.height;
 
+        /*Swap surf_src height and width since scaling ratios are in recout rotation*/
         if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
                         pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
-                rect_swap_helper(&surf_src);
+                swap(surf_src.height, surf_src.width);
 
         pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
                                         surf_src.width,
@@ -744,351 +719,202 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
                         pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
 }
 
-static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct rect *recout_full)
+static inline void adjust_vp_and_init_for_seamless_clip(
+                bool flip_scan_dir,
+                int recout_skip,
+                int src_size,
+                int taps,
+                struct fixed31_32 ratio,
+                struct fixed31_32 *init,
+                int *vp_offset,
+                int *vp_size)
 {
-        struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
-        struct rect src = pipe_ctx->plane_state->src_rect;
-        int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
-                        || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
-        bool flip_vert_scan_dir = false, flip_horz_scan_dir = false;
-
-        /*
-         * Need to calculate the scan direction for viewport to make adjustments
-         */
-        if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_180) {
-                flip_vert_scan_dir = true;
-                flip_horz_scan_dir = true;
-        } else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90)
-                flip_vert_scan_dir = true;
-        else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
-                flip_horz_scan_dir = true;
-
-        if (pipe_ctx->plane_state->horizontal_mirror)
-                        flip_horz_scan_dir = !flip_horz_scan_dir;
-
-        if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
-                        pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
-                rect_swap_helper(&src);
-                rect_swap_helper(&data->viewport_c);
-                rect_swap_helper(&data->viewport);
-        }
-
-        /*
-         * Init calculated according to formula:
-         *      init = (scaling_ratio + number_of_taps + 1) / 2
-         *      init_bot = init + scaling_ratio
-         *      init_c = init + truncated_vp_c_offset(from calculate viewport)
-         */
-        data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
-                        dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
-
-        data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
-                        dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
-
-        data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
-                        dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
-
-        data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
-                        dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
-
-        if (!flip_horz_scan_dir) {
+        if (!flip_scan_dir) {
                 /* Adjust for viewport end clip-off */
-                if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
-                        int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
-                        int int_part = dc_fixpt_floor(
-                                        dc_fixpt_sub(data->inits.h, data->ratios.horz));
-
-                        int_part = int_part > 0 ? int_part : 0;
-                        data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
-                }
-                if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
-                        int vp_clip = (src.x + src.width) / vpc_div -
-                                        data->viewport_c.width - data->viewport_c.x;
-                        int int_part = dc_fixpt_floor(
-                                        dc_fixpt_sub(data->inits.h_c, data->ratios.horz_c));
+                if ((*vp_offset + *vp_size) < src_size) {
+                        int vp_clip = src_size - *vp_size - *vp_offset;
+                        int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
 
                         int_part = int_part > 0 ? int_part : 0;
-                        data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
+                        *vp_size += int_part < vp_clip ? int_part : vp_clip;
                 }
 
                 /* Adjust for non-0 viewport offset */
-                if (data->viewport.x) {
-                        int int_part;
-
-                        data->inits.h = dc_fixpt_add(data->inits.h, dc_fixpt_mul_int(
-                                        data->ratios.horz, data->recout.x - recout_full->x));
-                        int_part = dc_fixpt_floor(data->inits.h) - data->viewport.x;
-                        if (int_part < data->taps.h_taps) {
-                                int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
-                                                        (data->taps.h_taps - int_part) : data->viewport.x;
-                                data->viewport.x -= int_adj;
-                                data->viewport.width += int_adj;
-                                int_part += int_adj;
-                        } else if (int_part > data->taps.h_taps) {
-                                data->viewport.x += int_part - data->taps.h_taps;
-                                data->viewport.width -= int_part - data->taps.h_taps;
-                                int_part = data->taps.h_taps;
-                        }
-                        data->inits.h.value &= 0xffffffff;
-                        data->inits.h = dc_fixpt_add_int(data->inits.h, int_part);
-                }
-
-                if (data->viewport_c.x) {
+                if (*vp_offset) {
                         int int_part;
 
-                        data->inits.h_c = dc_fixpt_add(data->inits.h_c, dc_fixpt_mul_int(
-                                        data->ratios.horz_c, data->recout.x - recout_full->x));
-                        int_part = dc_fixpt_floor(data->inits.h_c) - data->viewport_c.x;
-                        if (int_part < data->taps.h_taps_c) {
-                                int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
-                                                (data->taps.h_taps_c - int_part) : data->viewport_c.x;
-                                data->viewport_c.x -= int_adj;
-                                data->viewport_c.width += int_adj;
+                        *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
+                        int_part = dc_fixpt_floor(*init) - *vp_offset;
+                        if (int_part < taps) {
+                                int int_adj = *vp_offset >= (taps - int_part) ?
+                                                        (taps - int_part) : *vp_offset;
+                                *vp_offset -= int_adj;
+                                *vp_size += int_adj;
                                 int_part += int_adj;
-                        } else if (int_part > data->taps.h_taps_c) {
-                                data->viewport_c.x += int_part - data->taps.h_taps_c;
-                                data->viewport_c.width -= int_part - data->taps.h_taps_c;
-                                int_part = data->taps.h_taps_c;
+                        } else if (int_part > taps) {
+                                *vp_offset += int_part - taps;
+                                *vp_size -= int_part - taps;
+                                int_part = taps;
                         }
-                        data->inits.h_c.value &= 0xffffffff;
-                        data->inits.h_c = dc_fixpt_add_int(data->inits.h_c, int_part);
+                        init->value &= 0xffffffff;
+                        *init = dc_fixpt_add_int(*init, int_part);
                 }
         } else {
                 /* Adjust for non-0 viewport offset */
-                if (data->viewport.x) {
-                        int int_part = dc_fixpt_floor(
-                                        dc_fixpt_sub(data->inits.h, data->ratios.horz));
+                if (*vp_offset) {
+                        int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
 
                         int_part = int_part > 0 ? int_part : 0;
-                        data->viewport.width += int_part < data->viewport.x ? int_part : data->viewport.x;
-                        data->viewport.x -= int_part < data->viewport.x ? int_part : data->viewport.x;
-                }
-                if (data->viewport_c.x) {
-                        int int_part = dc_fixpt_floor(
-                                        dc_fixpt_sub(data->inits.h_c, data->ratios.horz_c));
-
-                        int_part = int_part > 0 ? int_part : 0;
-                        data->viewport_c.width += int_part < data->viewport_c.x ? int_part : data->viewport_c.x;
-                        data->viewport_c.x -= int_part < data->viewport_c.x ? int_part : data->viewport_c.x;
+                        *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
+                        *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
                 }
 
                 /* Adjust for viewport end clip-off */
-                if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
+                if ((*vp_offset + *vp_size) < src_size) {
                         int int_part;
-                        int end_offset = src.x + src.width
-                                        - data->viewport.x - data->viewport.width;
+                        int end_offset = src_size - *vp_offset - *vp_size;
 
                         /*
                          * this is init if vp had no offset, keep in mind this is from the
                          * right side of vp due to scan direction
                          */
-                        data->inits.h = dc_fixpt_add(data->inits.h, dc_fixpt_mul_int(
-                                        data->ratios.horz, data->recout.x - recout_full->x));
+                        *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
                         /*
                          * this is the difference between first pixel of viewport available to read
                          * and init position, takning into account scan direction
                          */
-                        int_part = dc_fixpt_floor(data->inits.h) - end_offset;
-                        if (int_part < data->taps.h_taps) {
-                                int int_adj = end_offset >= (data->taps.h_taps - int_part) ?
-                                                        (data->taps.h_taps - int_part) : end_offset;
-                                data->viewport.width += int_adj;
+                        int_part = dc_fixpt_floor(*init) - end_offset;
+                        if (int_part < taps) {
+                                int int_adj = end_offset >= (taps - int_part) ?
+                                                        (taps - int_part) : end_offset;
+                                *vp_size += int_adj;
                                 int_part += int_adj;
-                        } else if (int_part > data->taps.h_taps) {
-                                data->viewport.width += int_part - data->taps.h_taps;
-                                int_part = data->taps.h_taps;
+                        } else if (int_part > taps) {
+                                *vp_size += int_part - taps;
+                                int_part = taps;
                         }
-                        data->inits.h.value &= 0xffffffff;
-                        data->inits.h = dc_fixpt_add_int(data->inits.h, int_part);
+                        init->value &= 0xffffffff;
+                        *init = dc_fixpt_add_int(*init, int_part);
                 }
-
-                if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
-                        int int_part;
-                        int end_offset = (src.x + src.width) / vpc_div
-                                        - data->viewport_c.x - data->viewport_c.width;
-
-                        /*
-                         * this is init if vp had no offset, keep in mind this is from the
-                         * right side of vp due to scan direction
-                         */
-                        data->inits.h_c = dc_fixpt_add(data->inits.h_c, dc_fixpt_mul_int(
-                                        data->ratios.horz_c, data->recout.x - recout_full->x));
-                        /*
-                         * this is the difference between first pixel of viewport available to read
-                         * and init position, takning into account scan direction
-                         */
-                        int_part = dc_fixpt_floor(data->inits.h_c) - end_offset;
-                        if (int_part < data->taps.h_taps_c) {
-                                int int_adj = end_offset >= (data->taps.h_taps_c - int_part) ?
-                                                        (data->taps.h_taps_c - int_part) : end_offset;
-                                data->viewport_c.width += int_adj;
-                                int_part += int_adj;
-                        } else if (int_part > data->taps.h_taps_c) {
-                                data->viewport_c.width += int_part - data->taps.h_taps_c;
-                                int_part = data->taps.h_taps_c;
-                        }
-                        data->inits.h_c.value &= 0xffffffff;
-                        data->inits.h_c = dc_fixpt_add_int(data->inits.h_c, int_part);
-                }
-
         }
-        if (!flip_vert_scan_dir) {
-                /* Adjust for viewport end clip-off */
-                if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
-                        int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
-                        int int_part = dc_fixpt_floor(
-                                        dc_fixpt_sub(data->inits.v, data->ratios.vert));
-
-                        int_part = int_part > 0 ? int_part : 0;
-                        data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
-                }
-                if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
-                        int vp_clip = (src.y + src.height) / vpc_div -
-                                        data->viewport_c.height - data->viewport_c.y;
-                        int int_part = dc_fixpt_floor(
-                                        dc_fixpt_sub(data->inits.v_c, data->ratios.vert_c));
-
-                        int_part = int_part > 0 ? int_part : 0;
-                        data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
-                }
-
-                /* Adjust for non-0 viewport offset */
-                if (data->viewport.y) {
-                        int int_part;
-
-                        data->inits.v = dc_fixpt_add(data->inits.v, dc_fixpt_mul_int(
-                                        data->ratios.vert, data->recout.y - recout_full->y));
-                        int_part = dc_fixpt_floor(data->inits.v) - data->viewport.y;
-                        if (int_part < data->taps.v_taps) {
-                                int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
-                                                        (data->taps.v_taps - int_part) : data->viewport.y;
-                                data->viewport.y -= int_adj;
-                                data->viewport.height += int_adj;
-                                int_part += int_adj;
-                        } else if (int_part > data->taps.v_taps) {
-                                data->viewport.y += int_part - data->taps.v_taps;
-                                data->viewport.height -= int_part - data->taps.v_taps;
-                                int_part = data->taps.v_taps;
-                        }
-                        data->inits.v.value &= 0xffffffff;
-                        data->inits.v = dc_fixpt_add_int(data->inits.v, int_part);
-                }
-
-                if (data->viewport_c.y) {
-                        int int_part;
+}
 
-                        data->inits.v_c = dc_fixpt_add(data->inits.v_c, dc_fixpt_mul_int(
-                                        data->ratios.vert_c, data->recout.y - recout_full->y));
-                        int_part = dc_fixpt_floor(data->inits.v_c) - data->viewport_c.y;
-                        if (int_part < data->taps.v_taps_c) {
-                                int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
-                                                (data->taps.v_taps_c - int_part) : data->viewport_c.y;
-                                data->viewport_c.y -= int_adj;
-                                data->viewport_c.height += int_adj;
-                                int_part += int_adj;
-                        } else if (int_part > data->taps.v_taps_c) {
-                                data->viewport_c.y += int_part - data->taps.v_taps_c;
-                                data->viewport_c.height -= int_part - data->taps.v_taps_c;
-                                int_part = data->taps.v_taps_c;
-                        }
-                        data->inits.v_c.value &= 0xffffffff;
-                        data->inits.v_c = dc_fixpt_add_int(data->inits.v_c, int_part);
-                }
-        } else {
-                /* Adjust for non-0 viewport offset */
-                if (data->viewport.y) {
-                        int int_part = dc_fixpt_floor(
-                                        dc_fixpt_sub(data->inits.v, data->ratios.vert));
+static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
+{
+        const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+        const struct dc_stream_state *stream = pipe_ctx->stream;
+        struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
+        struct rect src = pipe_ctx->plane_state->src_rect;
+        int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
+        int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
+                        || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
+        bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
 
-                        int_part = int_part > 0 ? int_part : 0;
-                        data->viewport.height += int_part < data->viewport.y ? int_part : data->viewport.y;
-                        data->viewport.y -= int_part < data->viewport.y ? int_part : data->viewport.y;
-                }
-                if (data->viewport_c.y) {
-                        int int_part = dc_fixpt_floor(
-                                        dc_fixpt_sub(data->inits.v_c, data->ratios.vert_c));
+        /*
+         * Need to calculate the scan direction for viewport to make adjustments
+         */
+        get_vp_scan_direction(
+                        plane_state->rotation,
+                        plane_state->horizontal_mirror,
+                        &orthogonal_rotation,
+                        &flip_vert_scan_dir,
+                        &flip_horz_scan_dir);
+
+        /* Calculate src rect rotation adjusted to recout space */
+        surf_size_h = src.x + src.width;
+        surf_size_v = src.y + src.height;
+        if (flip_horz_scan_dir)
+                src.x = 0;
+        if (flip_vert_scan_dir)
+                src.y = 0;
+        if (orthogonal_rotation) {
+                swap(src.x, src.y);
+                swap(src.width, src.height);
+        }
 
-                        int_part = int_part > 0 ? int_part : 0;
-                        data->viewport_c.height += int_part < data->viewport_c.y ? int_part : data->viewport_c.y;
-                        data->viewport_c.y -= int_part < data->viewport_c.y ? int_part : data->viewport_c.y;
-                }
+        /* Recout matching initial vp offset = recout_offset - (stream dst offset +
+         *                      ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
+         *                      - (surf surf_src offset * 1/ full scl ratio))
+         */
+        recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
+                                        * stream->dst.width / stream->src.width -
+                                        src.x * plane_state->dst_rect.width / src.width
+                                        * stream->dst.width / stream->src.width);
+        recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
+                                        * stream->dst.height / stream->src.height -
+                                        src.y * plane_state->dst_rect.height / src.height
+                                        * stream->dst.height / stream->src.height);
+        if (orthogonal_rotation)
+                swap(recout_skip_h, recout_skip_v);
+        /*
+         * Init calculated according to formula:
+         *      init = (scaling_ratio + number_of_taps + 1) / 2
+         *      init_bot = init + scaling_ratio
+         *      init_c = init + truncated_vp_c_offset(from calculate viewport)
+         */
+        data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
+                        dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
 
-                /* Adjust for viewport end clip-off */
-                if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
-                        int int_part;
-                        int end_offset = src.y + src.height
-                                        - data->viewport.y - data->viewport.height;
+        data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
+                        dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
 
-                        /*
-                         * this is init if vp had no offset, keep in mind this is from the
-                         * right side of vp due to scan direction
-                         */
-                        data->inits.v = dc_fixpt_add(data->inits.v, dc_fixpt_mul_int(
-                                        data->ratios.vert, data->recout.y - recout_full->y));
-                        /*
-                         * this is the difference between first pixel of viewport available to read
-                         * and init position, taking into account scan direction
-                         */
-                        int_part = dc_fixpt_floor(data->inits.v) - end_offset;
-                        if (int_part < data->taps.v_taps) {
-                                int int_adj = end_offset >= (data->taps.v_taps - int_part) ?
-                                                        (data->taps.v_taps - int_part) : end_offset;
-                                data->viewport.height += int_adj;
-                                int_part += int_adj;
-                        } else if (int_part > data->taps.v_taps) {
-                                data->viewport.height += int_part - data->taps.v_taps;
-                                int_part = data->taps.v_taps;
-                        }
-                        data->inits.v.value &= 0xffffffff;
-                        data->inits.v = dc_fixpt_add_int(data->inits.v, int_part);
-                }
+        data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
+                        dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
 
-                if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
-                        int int_part;
-                        int end_offset = (src.y + src.height) / vpc_div
-                                        - data->viewport_c.y - data->viewport_c.height;
+        data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
+                        dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
 
-                        /*
-                         * this is init if vp had no offset, keep in mind this is from the
-                         * right side of vp due to scan direction
-                         */
-                        data->inits.v_c = dc_fixpt_add(data->inits.v_c, dc_fixpt_mul_int(
-                                        data->ratios.vert_c, data->recout.y - recout_full->y));
-                        /*
-                         * this is the difference between first pixel of viewport available to read
-                         * and init position, taking into account scan direction
-                         */
-                        int_part = dc_fixpt_floor(data->inits.v_c) - end_offset;
-                        if (int_part < data->taps.v_taps_c) {
-                                int int_adj = end_offset >= (data->taps.v_taps_c - int_part) ?
-                                                        (data->taps.v_taps_c - int_part) : end_offset;
-                                data->viewport_c.height += int_adj;
-                                int_part += int_adj;
-                        } else if (int_part > data->taps.v_taps_c) {
-                                data->viewport_c.height += int_part - data->taps.v_taps_c;
-                                int_part = data->taps.v_taps_c;
-                        }
-                        data->inits.v_c.value &= 0xffffffff;
-                        data->inits.v_c = dc_fixpt_add_int(data->inits.v_c, int_part);
-                }
-        }
+        /*
+         * Taps, inits and scaling ratios are in recout space need to rotate
+         * to viewport rotation before adjustment
+         */
+        adjust_vp_and_init_for_seamless_clip(
+                        flip_horz_scan_dir,
+                        recout_skip_h,
+                        surf_size_h,
+                        orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
+                        orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
+                        orthogonal_rotation ? &data->inits.v : &data->inits.h,
+                        &data->viewport.x,
+                        &data->viewport.width);
+        adjust_vp_and_init_for_seamless_clip(
+                        flip_horz_scan_dir,
+                        recout_skip_h,
+                        surf_size_h / vpc_div,
+                        orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
+                        orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
+                        orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
+                        &data->viewport_c.x,
+                        &data->viewport_c.width);
+        adjust_vp_and_init_for_seamless_clip(
+                        flip_vert_scan_dir,
+                        recout_skip_v,
+                        surf_size_v,
+                        orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
+                        orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
+                        orthogonal_rotation ? &data->inits.h : &data->inits.v,
+                        &data->viewport.y,
+                        &data->viewport.height);
+        adjust_vp_and_init_for_seamless_clip(
+                        flip_vert_scan_dir,
+                        recout_skip_v,
+                        surf_size_v / vpc_div,
+                        orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
+                        orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
+                        orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
+                        &data->viewport_c.y,
+                        &data->viewport_c.height);
 
         /* Interlaced inits based on final vert inits */
         data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
         data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
 
-        if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
-                        pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
-                rect_swap_helper(&data->viewport_c);
-                rect_swap_helper(&data->viewport);
-        }
 }
 
 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 {
         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
-        struct rect recout_full = { 0 };
         bool res = false;
         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
         /* Important: scaling ratio calculation requires pixel format,
@@ -1105,7 +931,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
         if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
                 return false;
 
-        calculate_recout(pipe_ctx, &recout_full);
+        calculate_recout(pipe_ctx);
 
         /**
          * Setting line buffer pixel depth to 24bpp yields banding
@@ -1146,7 +972,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 
         if (res)
                 /* May need to re-check lb size after this in some obscure scenario */
-                calculate_inits_and_adj_vp(pipe_ctx, &recout_full);
+                calculate_inits_and_adj_vp(pipe_ctx);
 
         DC_LOG_SCALER(
                                 "%s: Viewport:\nheight:%d width:%d x:%d "
@@ -1356,6 +1182,9 @@ bool dc_add_plane_to_context(
                 return false;
         }
 
+        tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
+        ASSERT(tail_pipe);
+
         free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -1373,10 +1202,6 @@ bool dc_add_plane_to_context(
         free_pipe->plane_state = plane_state;
 
         if (head_pipe != free_pipe) {
-
-                tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
-                ASSERT(tail_pipe);
-
                 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
                 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
                 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
@@ -1796,11 +1621,11 @@ enum dc_status dc_add_stream_to_ctx(
                 struct dc_state *new_ctx,
                 struct dc_stream_state *stream)
 {
-        struct dc_context *dc_ctx = dc->ctx;
         enum dc_status res;
+        DC_LOGGER_INIT(dc->ctx->logger);
 
         if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
-                DC_ERROR("Max streams reached, can't add stream %p !\n", stream);
+                DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
                 return DC_ERROR_UNEXPECTED;
         }
 
@@ -1810,7 +1635,7 @@ enum dc_status dc_add_stream_to_ctx(
 
         res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
         if (res != DC_OK)
-                DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res);
+                DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
 
         return res;
 }
@@ -1976,6 +1801,8 @@ enum dc_status resource_map_pool_resources(
                 }
         */
 
+        calculate_phy_pix_clks(stream);
+
         /* acquire new resources */
         pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index e113439aaa86..780838a05f44 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -100,8 +100,6 @@ static void construct(struct dc_stream_state *stream,
         /* EDID CAP translation for HDMI 2.0 */
         stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
 
-        stream->status.link = stream->sink->link;
-
         update_stream_signal(stream);
 
         stream->out_transfer_func = dc_create_transfer_func();
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index d16a20c84792..dea8bc39c688 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -36,9 +36,10 @@
 
 #include "inc/hw_sequencer.h"
 #include "inc/compressor.h"
+#include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.04"
+#define DC_VER "3.2.06"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
@@ -47,13 +48,6 @@
 /*******************************************************************************
  * Display Core Interfaces
  ******************************************************************************/
-struct dmcu_version {
-        unsigned int date;
-        unsigned int month;
-        unsigned int year;
-        unsigned int interface_version;
-};
-
 struct dc_versions {
         const char *dc_ver;
         struct dmcu_version dmcu_version;
@@ -748,5 +742,6 @@ void dc_set_power_state(
                 struct dc *dc,
                 enum dc_acpi_cm_power_state power_state);
 void dc_resume(struct dc *dc);
+bool dc_is_dmcu_initialized(struct dc *dc);
 
 #endif /* DC_INTERFACE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index c5bd1fbb6982..771d9f17e26e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -104,8 +104,6 @@ struct dc_stream_state {
         bool dpms_off;
         bool apply_edp_fast_boot_optimization;
 
-        struct dc_stream_status status;
-
         struct dc_cursor_attributes cursor_attributes;
         struct dc_cursor_position cursor_position;
         uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
index 9a28a04417d1..bd22f51813bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
@@ -94,7 +94,7 @@ static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
 /*ClocksStatePerformance*/
 { .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
 
-static int dentist_get_divider_from_did(int did)
+int dentist_get_divider_from_did(int did)
 {
         if (did < DENTIST_BASE_DID_1)
                 did = DENTIST_BASE_DID_1;
@@ -277,7 +277,8 @@ static int dce_set_clock(
         if (requested_clk_khz == 0)
                 clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 
-        dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
+        if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
+                dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
 
         return actual_clock;
 }
@@ -324,9 +325,11 @@ int dce112_set_clock(struct clk_mgr *clk_mgr, int requested_clk_khz)
         bp->funcs->set_dce_clock(bp, &dce_clk_params);
 
         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
-                if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
-                        dmcu->funcs->set_psr_wait_loop(dmcu,
-                                        actual_clock / 1000 / 7);
+                if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+                        if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
+                                dmcu->funcs->set_psr_wait_loop(dmcu,
+                                                actual_clock / 1000 / 7);
+                }
         }
 
         clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;
@@ -588,6 +591,8 @@ static void dce11_pplib_apply_display_requirements(
                         dc,
                         context->bw.dce.sclk_khz);
 
+        pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz;
+
         pp_display_cfg->min_engine_clock_deep_sleep_khz
                         = context->bw.dce.sclk_deep_sleep_khz;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
index 046077797416..3bceb31d910d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
@@ -165,4 +165,6 @@ struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx);
 
 void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);
 
+int dentist_get_divider_from_did(int did);
+
 #endif /* _DCE_CLK_MGR_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index c47c81883d3c..cce0d18f91da 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -908,7 +908,6 @@ static void dce110_stream_encoder_dp_blank(
         struct stream_encoder *enc)
 {
         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-        uint32_t retries = 0;
         uint32_t  reg1 = 0;
         uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 
@@ -926,30 +925,28 @@ static void dce110_stream_encoder_dp_blank(
          * (2 = start of the next vertical blank) */
         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
         /* Larger delay to wait until VBLANK - use max retry of
-        * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
-        * a little more because we may not trust delay accuracy.
-        */
+         * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
+         * a little more because we may not trust delay accuracy.
+         */
         max_retries = DP_BLANK_MAX_RETRY * 150;
 
         /* disable DP stream */
         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 
         /* the encoder stops sending the video stream
-        * at the start of the vertical blanking.
-        * Poll for DP_VID_STREAM_STATUS == 0
-        */
+         * at the start of the vertical blanking.
+         * Poll for DP_VID_STREAM_STATUS == 0
+         */
 
         REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
                         0,
                         10, max_retries);
 
-        ASSERT(retries <= max_retries);
-
         /* Tell the DP encoder to ignore timing from CRTC, must be done after
-        * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
-        * complete, stream status will be stuck in video stream enabled state,
-        * i.e. DP_VID_STREAM_STATUS stuck at 1.
-        */
+         * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
+         * complete, stream status will be stuck in video stream enabled state,
+         * i.e. DP_VID_STREAM_STATUS stuck at 1.
+         */
 
         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 9724a17e352b..2f062bacd78a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2282,7 +2282,7 @@ static void dce110_enable_per_frame_crtc_position_reset(
         int i;
 
         gsl_params.gsl_group = 0;
-        gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst;
+        gsl_params.gsl_master = 0;
 
         for (i = 0; i < group_size; i++)
                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 6d40b3d54ac1..cdd1d6b7b9f2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -41,7 +41,6 @@
 #include "dce/dce_mem_input.h"
 #include "dce/dce_link_encoder.h"
 #include "dce/dce_stream_encoder.h"
-#include "dce/dce_mem_input.h"
 #include "dce/dce_ipp.h"
 #include "dce/dce_transform.h"
 #include "dce/dce_opp.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
index 20f531d27e2b..f9d7d2c26cc2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
@@ -223,7 +223,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
                         &dc->res_pool->pp_smu_req;
         struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
         struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
-        struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
+        uint32_t requested_dcf_clock_in_khz = 0;
         bool send_request_to_increase = false;
         bool send_request_to_lower = false;
         int display_count;
@@ -263,8 +263,6 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
         // F Clock
         if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr->clks.fclk_khz)) {
                 clk_mgr->clks.fclk_khz = new_clocks->fclk_khz;
-                clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_FCLK;
-                clock_voltage_req.clocks_in_khz = new_clocks->fclk_khz;
                 smu_req.hard_min_fclk_mhz = new_clocks->fclk_khz / 1000;
 
                 notify_hard_min_fclk_to_smu(pp_smu, new_clocks->fclk_khz);
@@ -293,10 +291,9 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
          */
         if (send_request_to_increase) {
                 /*use dcfclk to request voltage*/
-                clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
-                clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
+                requested_dcf_clock_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
 
-                notify_hard_min_dcfclk_to_smu(pp_smu, clock_voltage_req.clocks_in_khz);
+                notify_hard_min_dcfclk_to_smu(pp_smu, requested_dcf_clock_in_khz);
 
                 if (pp_smu->set_display_requirement)
                         pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
@@ -317,10 +314,9 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
 
         if (!send_request_to_increase && send_request_to_lower) {
                 /*use dcfclk to request voltage*/
-                clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
-                clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
+                requested_dcf_clock_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
 
-                notify_hard_min_dcfclk_to_smu(pp_smu, clock_voltage_req.clocks_in_khz);
+                notify_hard_min_dcfclk_to_smu(pp_smu, requested_dcf_clock_in_khz);
 
                 if (pp_smu->set_display_requirement)
                         pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 4254e7e1a509..c7d1e678ebf5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -100,7 +100,7 @@ bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
         REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL,
                         DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, &enable);
 
-        return true ? false : enable;
+        return enable ? true : false;
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 74132a1f3046..345af015d061 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -99,6 +99,14 @@ static unsigned int hubp1_get_underflow_status(struct hubp *hubp)
         return hubp_underflow;
 }
 
+
+void hubp1_clear_underflow(struct hubp *hubp)
+{
+        struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+
+        REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
+}
+
 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
 {
         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
@@ -565,19 +573,6 @@ void hubp1_program_deadline(
                 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
                 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
 
-        if (REG(PREFETCH_SETTINS))
-                REG_SET_2(PREFETCH_SETTINS, 0,
-                        DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
-                        VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
-        else
-                REG_SET_2(PREFETCH_SETTINGS, 0,
-                        DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
-                        VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
-
-        REG_SET_2(VBLANK_PARAMETERS_0, 0,
-                DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
-                DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
-
         REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
                 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
 
@@ -585,9 +580,6 @@ void hubp1_program_deadline(
         REG_SET(VBLANK_PARAMETERS_1, 0,
                 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
 
-        REG_SET(VBLANK_PARAMETERS_3, 0,
-                REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
-
         if (REG(NOM_PARAMETERS_0))
                 REG_SET(NOM_PARAMETERS_0, 0,
                         DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
@@ -602,27 +594,13 @@ void hubp1_program_deadline(
         REG_SET(NOM_PARAMETERS_5, 0,
                 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
 
-        REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
-                REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
-                REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
-
         REG_SET_2(PER_LINE_DELIVERY, 0,
                 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
                 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
 
-        if (REG(PREFETCH_SETTINS_C))
-                REG_SET(PREFETCH_SETTINS_C, 0,
-                        VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
-        else
-                REG_SET(PREFETCH_SETTINGS_C, 0,
-                        VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
-
         REG_SET(VBLANK_PARAMETERS_2, 0,
                 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
 
-        REG_SET(VBLANK_PARAMETERS_4, 0,
-                REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
-
         if (REG(NOM_PARAMETERS_2))
                 REG_SET(NOM_PARAMETERS_2, 0,
                         DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
@@ -642,10 +620,6 @@ void hubp1_program_deadline(
                 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
                 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
 
-        REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
-                MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
-                QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
-
         /* TTU - per luma/chroma */
         /* Assumed surf0 is luma and 1 is chroma */
 
@@ -654,25 +628,15 @@ void hubp1_program_deadline(
                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
 
-        REG_SET(DCN_SURF0_TTU_CNTL1, 0,
-                REFCYC_PER_REQ_DELIVERY_PRE,
-                ttu_attr->refcyc_per_req_delivery_pre_l);
-
         REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
 
-        REG_SET(DCN_SURF1_TTU_CNTL1, 0,
-                REFCYC_PER_REQ_DELIVERY_PRE,
-                ttu_attr->refcyc_per_req_delivery_pre_c);
-
         REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
-        REG_SET(DCN_CUR0_TTU_CNTL1, 0,
-                REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
 }
 
 static void hubp1_setup(
@@ -690,6 +654,48 @@ static void hubp1_setup(
         hubp1_vready_workaround(hubp, pipe_dest);
 }
 
+static void hubp1_setup_interdependent(
+                struct hubp *hubp,
+                struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
+                struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
+{
+        struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+
+        REG_SET_2(PREFETCH_SETTINS, 0,
+                DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
+                VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
+
+        REG_SET(PREFETCH_SETTINS_C, 0,
+                VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
+
+        REG_SET_2(VBLANK_PARAMETERS_0, 0,
+                DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
+                DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
+
+        REG_SET(VBLANK_PARAMETERS_3, 0,
+                REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
+
+        REG_SET(VBLANK_PARAMETERS_4, 0,
+                REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
+
+        REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
+                REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
+                REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
+
+        REG_SET(DCN_SURF0_TTU_CNTL1, 0,
+                REFCYC_PER_REQ_DELIVERY_PRE,
+                ttu_attr->refcyc_per_req_delivery_pre_l);
+        REG_SET(DCN_SURF1_TTU_CNTL1, 0,
+                REFCYC_PER_REQ_DELIVERY_PRE,
+                ttu_attr->refcyc_per_req_delivery_pre_c);
+        REG_SET(DCN_CUR0_TTU_CNTL1, 0,
+                REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
+
+        REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
+                MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
+                QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
+}
+
 bool hubp1_is_flip_pending(struct hubp *hubp)
 {
         uint32_t flip_pending = 0;
@@ -1178,6 +1184,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = {
                         hubp1_program_surface_config,
         .hubp_is_flip_pending = hubp1_is_flip_pending,
         .hubp_setup = hubp1_setup,
+        .hubp_setup_interdependent = hubp1_setup_interdependent,
         .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings,
         .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings,
         .set_blank = hubp1_set_blank,
@@ -1190,6 +1197,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = {
         .hubp_clk_cntl = hubp1_clk_cntl,
         .hubp_vtg_sel = hubp1_vtg_sel,
         .hubp_read_state = hubp1_read_state,
+        .hubp_clear_underflow = hubp1_clear_underflow,
         .hubp_disable_control =  hubp1_disable_control,
         .hubp_get_underflow_status = hubp1_get_underflow_status,
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index 4890273b632b..62d4232e7796 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -251,6 +251,7 @@
         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
+        HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
@@ -435,6 +436,7 @@
         type HUBP_NO_OUTSTANDING_REQ;\
         type HUBP_VTG_SEL;\
         type HUBP_UNDERFLOW_STATUS;\
+        type HUBP_UNDERFLOW_CLEAR;\
         type NUM_PIPES;\
         type NUM_BANKS;\
         type PIPE_INTERLEAVE;\
@@ -739,6 +741,7 @@ void dcn10_hubp_construct(
         const struct dcn_mi_mask *hubp_mask);
 
 void hubp1_read_state(struct hubp *hubp);
+void hubp1_clear_underflow(struct hubp *hubp);
 
 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 87495dea45ec..0bd33a713836 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1227,7 +1227,8 @@ static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
                 tf = plane_state->in_transfer_func;
 
         if (plane_state->gamma_correction &&
-                !plane_state->gamma_correction->is_identity
+                !dpp_base->ctx->dc->debug.always_use_regamma
+                && !plane_state->gamma_correction->is_identity
                         && dce_use_lut(plane_state->format))
                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
 
@@ -1400,7 +1401,7 @@ static void dcn10_enable_per_frame_crtc_position_reset(
                 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
                         grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
                                         grouped_pipes[i]->stream_res.tg,
-                                        grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
+                                        0,
                                         &grouped_pipes[i]->stream->triggered_crtc_reset);
 
         DC_SYNC_INFO("Waiting for trigger\n");
@@ -1770,7 +1771,7 @@ bool is_rgb_cspace(enum dc_color_space output_color_space)
         }
 }
 
-static void dcn10_get_surface_visual_confirm_color(
+void dcn10_get_surface_visual_confirm_color(
                 const struct pipe_ctx *pipe_ctx,
                 struct tg_color *color)
 {
@@ -1806,7 +1807,7 @@ static void dcn10_get_surface_visual_confirm_color(
         }
 }
 
-static void dcn10_get_hdr_visual_confirm_color(
+void dcn10_get_hdr_visual_confirm_color(
                 struct pipe_ctx *pipe_ctx,
                 struct tg_color *color)
 {
@@ -2067,6 +2068,10 @@ void update_dchubp_dpp(
                         &pipe_ctx->ttu_regs,
                         &pipe_ctx->rq_regs,
                         &pipe_ctx->pipe_dlg_param);
+                hubp->funcs->hubp_setup_interdependent(
+                        hubp,
+                        &pipe_ctx->dlg_regs,
+                        &pipe_ctx->ttu_regs);
         }
 
         size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
@@ -2337,6 +2342,32 @@ static void dcn10_apply_ctx_for_surface(
 
         dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
 
+        if (top_pipe_to_program->plane_state &&
+                        top_pipe_to_program->plane_state->update_flags.bits.full_update)
+                for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                        struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+                        /* Skip inactive pipes and ones already updated */
+                        if (!pipe_ctx->stream || pipe_ctx->stream == stream)
+                                continue;
+
+                        pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
+
+                        pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
+                                pipe_ctx->plane_res.hubp,
+                                &pipe_ctx->dlg_regs,
+                                &pipe_ctx->ttu_regs);
+                }
+
+        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+                if (!pipe_ctx->stream || pipe_ctx->stream == stream)
+                        continue;
+
+                dcn10_pipe_control_lock(dc, pipe_ctx, false);
+        }
+
         if (num_planes == 0)
                 false_optc_underflow_wa(dc, stream, tg);
 
@@ -2710,6 +2741,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
         .set_avmute = dce110_set_avmute,
         .log_hw_state = dcn10_log_hw_state,
         .get_hw_state = dcn10_get_hw_state,
+        .clear_status_bits = dcn10_clear_status_bits,
         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
         .edp_backlight_control = hwss_edp_backlight_control,
         .edp_power_control = hwss_edp_power_control,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 5e5610c9e600..f8eea10e4c64 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -51,6 +51,8 @@ void dcn10_get_hw_state(
                 char *pBuf, unsigned int bufSize,
                 unsigned int mask);
 
+void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
+
 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
 
 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
@@ -61,6 +63,14 @@ void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp);
 
 void set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
 
+void dcn10_get_surface_visual_confirm_color(
+                const struct pipe_ctx *pipe_ctx,
+                struct tg_color *color);
+
+void dcn10_get_hdr_visual_confirm_color(
+                struct pipe_ctx *pipe_ctx,
+                struct tg_color *color);
+
 void update_dchubp_dpp(
         struct dc *dc,
         struct pipe_ctx *pipe_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index 64158900730f..211bb240a720 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -454,12 +454,6 @@ static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int
 
                         remaining_buffer -= chars_printed;
                         pBuf += chars_printed;
-
-                        // Clear underflow for debug purposes
-                        // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
-                        // This function is called only from Windows or Diags test environment, hence it's safe to clear
-                        // it from here without affecting the original intent.
-                        tg->funcs->clear_optc_underflow(tg);
                 }
         }
 
@@ -484,6 +478,59 @@ static unsigned int dcn10_get_clock_states(struct dc *dc, char *pBuf, unsigned i
         return chars_printed;
 }
 
+static void dcn10_clear_otpc_underflow(struct dc *dc)
+{
+        struct resource_pool *pool = dc->res_pool;
+        int i;
+
+        for (i = 0; i < pool->timing_generator_count; i++) {
+                struct timing_generator *tg = pool->timing_generators[i];
+                struct dcn_otg_state s = {0};
+
+                optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+
+                if (s.otg_enabled & 1)
+                        tg->funcs->clear_optc_underflow(tg);
+        }
+}
+
+static void dcn10_clear_hubp_underflow(struct dc *dc)
+{
+        struct resource_pool *pool = dc->res_pool;
+        int i;
+
+        for (i = 0; i < pool->pipe_count; i++) {
+                struct hubp *hubp = pool->hubps[i];
+                struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
+
+                hubp->funcs->hubp_read_state(hubp);
+
+                if (!s->blank_en)
+                        hubp->funcs->hubp_clear_underflow(hubp);
+        }
+}
+
+void dcn10_clear_status_bits(struct dc *dc, unsigned int mask)
+{
+        /*
+         *  Mask Format
+         *  Bit 0 - 31: Status bit to clear
+         *
+         *  Mask = 0x0 means clear all status bits
+         */
+        const unsigned int DC_HW_STATE_MASK_HUBP_UNDERFLOW      = 0x1;
+        const unsigned int DC_HW_STATE_MASK_OTPC_UNDERFLOW      = 0x2;
+
+        if (mask == 0x0)
+                mask = 0xFFFFFFFF;
+
+        if (mask & DC_HW_STATE_MASK_HUBP_UNDERFLOW)
+                dcn10_clear_hubp_underflow(dc);
+
+        if (mask & DC_HW_STATE_MASK_OTPC_UNDERFLOW)
+                dcn10_clear_otpc_underflow(dc);
+}
+
 void dcn10_get_hw_state(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask)
 {
         /*
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 7d1f66797cb3..7c138615f17d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -335,9 +335,8 @@ void optc1_program_timing(
         /* Enable stereo - only when we need to pack 3D frame. Other types
          * of stereo handled in explicit call
          */
-        h_div_2 = (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ?
-                        1 : 0;
 
+        h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing);
         REG_UPDATE(OTG_H_TIMING_CNTL,
                         OTG_H_TIMING_DIV_BY2, h_div_2);
 
@@ -360,20 +359,19 @@ void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enab
 static void optc1_unblank_crtc(struct timing_generator *optc)
 {
         struct optc *optc1 = DCN10TG_FROM_TG(optc);
-        uint32_t vertical_interrupt_enable = 0;
-
-        REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
-                        OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &vertical_interrupt_enable);
-
-        /* temporary work around for vertical interrupt, once vertical interrupt enabled,
-         * this check will be removed.
-         */
-        if (vertical_interrupt_enable)
-                optc1_set_blank_data_double_buffer(optc, true);
 
         REG_UPDATE_2(OTG_BLANK_CONTROL,
                         OTG_BLANK_DATA_EN, 0,
                         OTG_BLANK_DE_MODE, 0);
+
+        /* W/A for automated testing
+         * Automated testing will fail underflow test as there
+         * sporadic underflows which occur during the optc blank
+         * sequence.  As a w/a, clear underflow on unblank.
+         * This prevents the failure, but will not mask actual
+         * underflow that affect real use cases.
+         */
+        optc1_clear_optc_underflow(optc);
 }
 
 /**
@@ -1422,3 +1420,9 @@ void dcn10_timing_generator_init(struct optc *optc1)
         optc1->min_h_sync_width = 8;
         optc1->min_v_sync_width = 1;
 }
+
+bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
+{
+        return timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index c1b114209fe8..8bacf0b6e27e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -565,4 +565,6 @@ bool optc1_configure_crc(struct timing_generator *optc,
 bool optc1_get_crc(struct timing_generator *optc,
                     uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
 
+bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
+
 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 6f9078f3c4d3..b8b5525a389a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -766,7 +766,6 @@ void enc1_stream_encoder_dp_blank(
         struct stream_encoder *enc)
 {
         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
-        uint32_t retries = 0;
         uint32_t  reg1 = 0;
         uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 
@@ -803,8 +802,6 @@ void enc1_stream_encoder_dp_blank(
                         0,
                         10, max_retries);
 
-        ASSERT(retries <= max_retries);
-
         /* Tell the DP encoder to ignore timing from CRTC, must be done after
          * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
          * complete, stream status will be stuck in video stream enabled state,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
index 4550747fb61c..cb85eaa9857f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
@@ -32,6 +32,13 @@ enum dmcu_state {
         DMCU_RUNNING = 1
 };
 
+struct dmcu_version {
+        unsigned int date;
+        unsigned int month;
+        unsigned int year;
+        unsigned int interface_version;
+};
+
 struct dmcu {
         struct dc_context *ctx;
         const struct dmcu_funcs *funcs;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 334c48cdafdc..04c6989aac58 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -63,6 +63,11 @@ struct hubp_funcs {
                         struct _vcs_dpi_display_rq_regs_st *rq_regs,
                         struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
 
+        void (*hubp_setup_interdependent)(
+                        struct hubp *hubp,
+                        struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
+                        struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
+
         void (*dcc_control)(struct hubp *hubp, bool enable,
                         bool independent_64b_blks);
         void (*mem_program_viewport)(
@@ -121,6 +126,7 @@ struct hubp_funcs {
         void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
         void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
         void (*hubp_read_state)(struct hubp *hubp);
+        void (*hubp_clear_underflow)(struct hubp *hubp);
         void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);
         unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index e9b702ce02dd..d6a85f48b6d1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -200,6 +200,7 @@ struct hw_sequencer_funcs {
         void (*log_hw_state)(struct dc *dc,
                 struct dc_log_buffer_ctx *log_ctx);
         void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask);
+        void (*clear_status_bits)(struct dc *dc, unsigned int mask);
 
         void (*wait_for_mpcc_disconnect)(struct dc *dc,
                         struct resource_pool *res_pool,
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 7480f072c375..bbecbaefb741 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -813,20 +813,26 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
         const struct hw_x_point *coord_x = coordinate_x;
         struct fixed31_32 scaledX = dc_fixpt_zero;
         struct fixed31_32 scaledX1 = dc_fixpt_zero;
-        struct fixed31_32 max_display = dc_fixpt_from_int(fs_params->max_display);
-        struct fixed31_32 min_display = dc_fixpt_from_fraction(fs_params->min_display, 10000);
-        struct fixed31_32 max_content = dc_fixpt_from_int(fs_params->max_content);
-        struct fixed31_32 min_content = dc_fixpt_from_fraction(fs_params->min_content, 10000);
+        struct fixed31_32 max_display;
+        struct fixed31_32 min_display;
+        struct fixed31_32 max_content;
+        struct fixed31_32 min_content;
         struct fixed31_32 clip = dc_fixpt_one;
         struct fixed31_32 output;
         bool use_eetf = false;
         bool is_clipped = false;
-        struct fixed31_32 sdr_white_level = dc_fixpt_from_int(fs_params->sdr_white_level);
+        struct fixed31_32 sdr_white_level;
 
         if (fs_params == NULL || fs_params->max_content == 0 ||
                         fs_params->max_display == 0)
                 return false;
 
+        max_display = dc_fixpt_from_int(fs_params->max_display);
+        min_display = dc_fixpt_from_fraction(fs_params->min_display, 10000);
+        max_content = dc_fixpt_from_int(fs_params->max_content);
+        min_content = dc_fixpt_from_fraction(fs_params->min_content, 10000);
+        sdr_white_level = dc_fixpt_from_int(fs_params->sdr_white_level);
+
         if (fs_params->min_display > 1000) // cap at 0.1 at the bottom
                 min_display = dc_fixpt_from_fraction(1, 10);
         if (fs_params->max_display < 100) // cap at 100 at the top
diff --git a/drivers/gpu/drm/amd/display/modules/power/Makefile b/drivers/gpu/drm/amd/display/modules/power/Makefile
new file mode 100644
index 000000000000..87851f892a52
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/modules/power/Makefile
@@ -0,0 +1,31 @@
+#
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+#
+# Makefile for the 'power' sub-module of DAL.
+#
+
+MOD_POWER = power_helpers.o
+
+AMD_DAL_MOD_POWER = $(addprefix $(AMDDALPATH)/modules/power/,$(MOD_POWER))
+#$(info ************  DAL POWER MODULE MAKEFILE ************)
+
+AMD_DISPLAY_FILES += $(AMD_DAL_MOD_POWER)
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
new file mode 100644
index 000000000000..00f63b7dd32f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -0,0 +1,326 @@
+/* Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "power_helpers.h"
+#include "dc/inc/hw/dmcu.h"
+
+#define DIV_ROUNDUP(a, b) (((a)+((b)/2))/(b))
+
+/* Possible Min Reduction config from least aggressive to most aggressive
+ *  0    1     2     3     4     5     6     7     8     9     10    11   12
+ * 100  98.0 94.1  94.1  85.1  80.3  75.3  69.4  60.0  57.6  50.2  49.8  40.0 %
+ */
+static const unsigned char min_reduction_table[13] = {
+0xff, 0xfa, 0xf0, 0xf0, 0xd9, 0xcd, 0xc0, 0xb1, 0x99, 0x93, 0x80, 0x82, 0x66};
+
+/* Possible Max Reduction configs from least aggressive to most aggressive
+ *  0    1     2     3     4     5     6     7     8     9     10    11   12
+ * 96.1 89.8 85.1  80.3  69.4  64.7  64.7  50.2  39.6  30.2  30.2  30.2  19.6 %
+ */
+static const unsigned char max_reduction_table[13] = {
+0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32};
+
+/* Predefined ABM configuration sets. We may have different configuration sets
+ * in order to satisfy different power/quality requirements.
+ */
+static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_level] = {
+/*  ABM Level 1,    ABM Level 2,    ABM Level 3,    ABM Level 4 */
+{       2,              5,              7,              8       },      /* Default - Medium aggressiveness */
+{       2,              5,              8,              11      },      /* Alt #1  - Increased aggressiveness */
+{       0,              2,              4,              8       },      /* Alt #2  - Minimal aggressiveness */
+{       3,              6,              10,             12      },      /* Alt #3  - Super aggressiveness */
+};
+
+#define NUM_AMBI_LEVEL    5
+#define NUM_AGGR_LEVEL    4
+#define NUM_POWER_FN_SEGS 8
+#define NUM_BL_CURVE_SEGS 16
+
+/* NOTE: iRAM is 256B in size */
+struct iram_table_v_2 {
+        /* flags                      */
+        uint16_t flags;                                                 /* 0x00 U16  */
+
+        /* parameters for ABM2.0 algorithm */
+        uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x02 U0.8 */
+        uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x16 U0.8 */
+        uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];        /* 0x2a U2.6 */
+        uint8_t bright_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];        /* 0x3e U2.6 */
+        uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x52 U2.6 */
+        uint8_t dark_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x66 U2.6 */
+        uint8_t iir_curve[NUM_AMBI_LEVEL];                              /* 0x7a U0.8 */
+        uint8_t deviation_gain;                                         /* 0x7f U0.8 */
+
+        /* parameters for crgb conversion */
+        uint16_t crgb_thresh[NUM_POWER_FN_SEGS];                        /* 0x80 U3.13 */
+        uint16_t crgb_offset[NUM_POWER_FN_SEGS];                        /* 0x90 U1.15 */
+        uint16_t crgb_slope[NUM_POWER_FN_SEGS];                         /* 0xa0 U4.12 */
+
+        /* parameters for custom curve */
+        /* thresholds for brightness --> backlight */
+        uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS];               /* 0xb0 U16.0 */
+        /* offsets for brightness --> backlight */
+        uint16_t backlight_offsets[NUM_BL_CURVE_SEGS];                  /* 0xd0 U16.0 */
+
+        /* For reading PSR State directly from IRAM */
+        uint8_t psr_state;                                              /* 0xf0       */
+        uint8_t dmcu_interface_version;                                 /* 0xf1       */
+        uint8_t dmcu_date_version_year_b0;                              /* 0xf2       */
+        uint8_t dmcu_date_version_year_b1;                              /* 0xf3       */
+        uint8_t dmcu_date_version_month;                                /* 0xf4       */
+        uint8_t dmcu_date_version_day;                                  /* 0xf5       */
+        uint8_t dmcu_state;                                             /* 0xf6       */
+
+        uint16_t blRampReduction;                                       /* 0xf7       */
+        uint16_t blRampStart;                                           /* 0xf9       */
+        uint8_t dummy5;                                                 /* 0xfb       */
+        uint8_t dummy6;                                                 /* 0xfc       */
+        uint8_t dummy7;                                                 /* 0xfd       */
+        uint8_t dummy8;                                                 /* 0xfe       */
+        uint8_t dummy9;                                                 /* 0xff       */
+};
+
+static uint16_t backlight_8_to_16(unsigned int backlight_8bit)
+{
+        return (uint16_t)(backlight_8bit * 0x101);
+}
+
+static void fill_backlight_transform_table(struct dmcu_iram_parameters params,
+                struct iram_table_v_2 *table)
+{
+        unsigned int i;
+        unsigned int num_entries = NUM_BL_CURVE_SEGS;
+        unsigned int query_input_8bit;
+        unsigned int query_output_8bit;
+        unsigned int lut_index;
+
+        table->backlight_thresholds[0] = 0;
+        table->backlight_offsets[0] = params.backlight_lut_array[0];
+        table->backlight_thresholds[num_entries-1] = 0xFFFF;
+        table->backlight_offsets[num_entries-1] =
+                params.backlight_lut_array[params.backlight_lut_array_size - 1];
+
+        /* Setup all brightness levels between 0% and 100% exclusive
+         * Fills brightness-to-backlight transform table. Backlight custom curve
+         * describes transform from brightness to backlight. It will be defined
+         * as set of thresholds and set of offsets, together, implying
+         * extrapolation of custom curve into 16 uniformly spanned linear
+         * segments.  Each threshold/offset represented by 16 bit entry in
+         * format U4.10.
+         */
+        for (i = 1; i+1 < num_entries; i++) {
+                query_input_8bit = DIV_ROUNDUP((i * 256), num_entries);
+
+                lut_index = (params.backlight_lut_array_size - 1) * i / (num_entries - 1);
+                ASSERT(lut_index < params.backlight_lut_array_size);
+                query_output_8bit = params.backlight_lut_array[lut_index] >> 8;
+
+                table->backlight_thresholds[i] =
+                                backlight_8_to_16(query_input_8bit);
+                table->backlight_offsets[i] =
+                                backlight_8_to_16(query_output_8bit);
+        }
+}
+
+bool dmcu_load_iram(struct dmcu *dmcu,
+        struct dmcu_iram_parameters params)
+{
+        struct iram_table_v_2 ram_table;
+        unsigned int set = params.set;
+
+        if (dmcu == NULL)
+                return false;
+
+        if (!dmcu->funcs->is_dmcu_initialized(dmcu))
+                return true;
+
+        memset(&ram_table, 0, sizeof(ram_table));
+
+        ram_table.flags = 0x0;
+        ram_table.deviation_gain = 0xb3;
+
+        ram_table.blRampReduction =
+                cpu_to_be16(params.backlight_ramping_reduction);
+        ram_table.blRampStart =
+                cpu_to_be16(params.backlight_ramping_start);
+
+        ram_table.min_reduction[0][0] = min_reduction_table[abm_config[set][0]];
+        ram_table.min_reduction[1][0] = min_reduction_table[abm_config[set][0]];
+        ram_table.min_reduction[2][0] = min_reduction_table[abm_config[set][0]];
+        ram_table.min_reduction[3][0] = min_reduction_table[abm_config[set][0]];
+        ram_table.min_reduction[4][0] = min_reduction_table[abm_config[set][0]];
+        ram_table.max_reduction[0][0] = max_reduction_table[abm_config[set][0]];
+        ram_table.max_reduction[1][0] = max_reduction_table[abm_config[set][0]];
+        ram_table.max_reduction[2][0] = max_reduction_table[abm_config[set][0]];
+        ram_table.max_reduction[3][0] = max_reduction_table[abm_config[set][0]];
+        ram_table.max_reduction[4][0] = max_reduction_table[abm_config[set][0]];
+
+        ram_table.min_reduction[0][1] = min_reduction_table[abm_config[set][1]];
+        ram_table.min_reduction[1][1] = min_reduction_table[abm_config[set][1]];
+        ram_table.min_reduction[2][1] = min_reduction_table[abm_config[set][1]];
+        ram_table.min_reduction[3][1] = min_reduction_table[abm_config[set][1]];
+        ram_table.min_reduction[4][1] = min_reduction_table[abm_config[set][1]];
+        ram_table.max_reduction[0][1] = max_reduction_table[abm_config[set][1]];
+        ram_table.max_reduction[1][1] = max_reduction_table[abm_config[set][1]];
+        ram_table.max_reduction[2][1] = max_reduction_table[abm_config[set][1]];
+        ram_table.max_reduction[3][1] = max_reduction_table[abm_config[set][1]];
+        ram_table.max_reduction[4][1] = max_reduction_table[abm_config[set][1]];
+
+        ram_table.min_reduction[0][2] = min_reduction_table[abm_config[set][2]];
+        ram_table.min_reduction[1][2] = min_reduction_table[abm_config[set][2]];
+        ram_table.min_reduction[2][2] = min_reduction_table[abm_config[set][2]];
+        ram_table.min_reduction[3][2] = min_reduction_table[abm_config[set][2]];
+        ram_table.min_reduction[4][2] = min_reduction_table[abm_config[set][2]];
+        ram_table.max_reduction[0][2] = max_reduction_table[abm_config[set][2]];
+        ram_table.max_reduction[1][2] = max_reduction_table[abm_config[set][2]];
+        ram_table.max_reduction[2][2] = max_reduction_table[abm_config[set][2]];
+        ram_table.max_reduction[3][2] = max_reduction_table[abm_config[set][2]];
+        ram_table.max_reduction[4][2] = max_reduction_table[abm_config[set][2]];
+
+        ram_table.min_reduction[0][3] = min_reduction_table[abm_config[set][3]];
+        ram_table.min_reduction[1][3] = min_reduction_table[abm_config[set][3]];
+        ram_table.min_reduction[2][3] = min_reduction_table[abm_config[set][3]];
+        ram_table.min_reduction[3][3] = min_reduction_table[abm_config[set][3]];
+        ram_table.min_reduction[4][3] = min_reduction_table[abm_config[set][3]];
+        ram_table.max_reduction[0][3] = max_reduction_table[abm_config[set][3]];
+        ram_table.max_reduction[1][3] = max_reduction_table[abm_config[set][3]];
+        ram_table.max_reduction[2][3] = max_reduction_table[abm_config[set][3]];
+        ram_table.max_reduction[3][3] = max_reduction_table[abm_config[set][3]];
+        ram_table.max_reduction[4][3] = max_reduction_table[abm_config[set][3]];
+
+        ram_table.bright_pos_gain[0][0] = 0x20;
+        ram_table.bright_pos_gain[0][1] = 0x20;
+        ram_table.bright_pos_gain[0][2] = 0x20;
+        ram_table.bright_pos_gain[0][3] = 0x20;
+        ram_table.bright_pos_gain[1][0] = 0x20;
+        ram_table.bright_pos_gain[1][1] = 0x20;
+        ram_table.bright_pos_gain[1][2] = 0x20;
+        ram_table.bright_pos_gain[1][3] = 0x20;
+        ram_table.bright_pos_gain[2][0] = 0x20;
+        ram_table.bright_pos_gain[2][1] = 0x20;
+        ram_table.bright_pos_gain[2][2] = 0x20;
+        ram_table.bright_pos_gain[2][3] = 0x20;
+        ram_table.bright_pos_gain[3][0] = 0x20;
+        ram_table.bright_pos_gain[3][1] = 0x20;
+        ram_table.bright_pos_gain[3][2] = 0x20;
+        ram_table.bright_pos_gain[3][3] = 0x20;
+        ram_table.bright_pos_gain[4][0] = 0x20;
+        ram_table.bright_pos_gain[4][1] = 0x20;
+        ram_table.bright_pos_gain[4][2] = 0x20;
+        ram_table.bright_pos_gain[4][3] = 0x20;
+        ram_table.bright_neg_gain[0][1] = 0x00;
+        ram_table.bright_neg_gain[0][2] = 0x00;
+        ram_table.bright_neg_gain[0][3] = 0x00;
+        ram_table.bright_neg_gain[1][0] = 0x00;
+        ram_table.bright_neg_gain[1][1] = 0x00;
+        ram_table.bright_neg_gain[1][2] = 0x00;
+        ram_table.bright_neg_gain[1][3] = 0x00;
+        ram_table.bright_neg_gain[2][0] = 0x00;
+        ram_table.bright_neg_gain[2][1] = 0x00;
+        ram_table.bright_neg_gain[2][2] = 0x00;
+        ram_table.bright_neg_gain[2][3] = 0x00;
+        ram_table.bright_neg_gain[3][0] = 0x00;
+        ram_table.bright_neg_gain[3][1] = 0x00;
+        ram_table.bright_neg_gain[3][2] = 0x00;
+        ram_table.bright_neg_gain[3][3] = 0x00;
+        ram_table.bright_neg_gain[4][0] = 0x00;
+        ram_table.bright_neg_gain[4][1] = 0x00;
+        ram_table.bright_neg_gain[4][2] = 0x00;
+        ram_table.bright_neg_gain[4][3] = 0x00;
+        ram_table.dark_pos_gain[0][0] = 0x00;
+        ram_table.dark_pos_gain[0][1] = 0x00;
+        ram_table.dark_pos_gain[0][2] = 0x00;
+        ram_table.dark_pos_gain[0][3] = 0x00;
+        ram_table.dark_pos_gain[1][0] = 0x00;
+        ram_table.dark_pos_gain[1][1] = 0x00;
+        ram_table.dark_pos_gain[1][2] = 0x00;
+        ram_table.dark_pos_gain[1][3] = 0x00;
+        ram_table.dark_pos_gain[2][0] = 0x00;
+        ram_table.dark_pos_gain[2][1] = 0x00;
+        ram_table.dark_pos_gain[2][2] = 0x00;
+        ram_table.dark_pos_gain[2][3] = 0x00;
+        ram_table.dark_pos_gain[3][0] = 0x00;
+        ram_table.dark_pos_gain[3][1] = 0x00;
+        ram_table.dark_pos_gain[3][2] = 0x00;
+        ram_table.dark_pos_gain[3][3] = 0x00;
+        ram_table.dark_pos_gain[4][0] = 0x00;
+        ram_table.dark_pos_gain[4][1] = 0x00;
+        ram_table.dark_pos_gain[4][2] = 0x00;
+        ram_table.dark_pos_gain[4][3] = 0x00;
+        ram_table.dark_neg_gain[0][0] = 0x00;
+        ram_table.dark_neg_gain[0][1] = 0x00;
+        ram_table.dark_neg_gain[0][2] = 0x00;
+        ram_table.dark_neg_gain[0][3] = 0x00;
+        ram_table.dark_neg_gain[1][0] = 0x00;
+        ram_table.dark_neg_gain[1][1] = 0x00;
+        ram_table.dark_neg_gain[1][2] = 0x00;
+        ram_table.dark_neg_gain[1][3] = 0x00;
+        ram_table.dark_neg_gain[2][0] = 0x00;
+        ram_table.dark_neg_gain[2][1] = 0x00;
+        ram_table.dark_neg_gain[2][2] = 0x00;
+        ram_table.dark_neg_gain[2][3] = 0x00;
+        ram_table.dark_neg_gain[3][0] = 0x00;
+        ram_table.dark_neg_gain[3][1] = 0x00;
+        ram_table.dark_neg_gain[3][2] = 0x00;
+        ram_table.dark_neg_gain[3][3] = 0x00;
+        ram_table.dark_neg_gain[4][0] = 0x00;
+        ram_table.dark_neg_gain[4][1] = 0x00;
+        ram_table.dark_neg_gain[4][2] = 0x00;
+        ram_table.dark_neg_gain[4][3] = 0x00;
+        ram_table.iir_curve[0] = 0x65;
+        ram_table.iir_curve[1] = 0x65;
+        ram_table.iir_curve[2] = 0x65;
+        ram_table.iir_curve[3] = 0x65;
+        ram_table.iir_curve[4] = 0x65;
+        ram_table.crgb_thresh[0] = cpu_to_be16(0x13b6);
+        ram_table.crgb_thresh[1] = cpu_to_be16(0x1648);
+        ram_table.crgb_thresh[2] = cpu_to_be16(0x18e3);
+        ram_table.crgb_thresh[3] = cpu_to_be16(0x1b41);
+        ram_table.crgb_thresh[4] = cpu_to_be16(0x1d46);
+        ram_table.crgb_thresh[5] = cpu_to_be16(0x1f21);
+        ram_table.crgb_thresh[6] = cpu_to_be16(0x2167);
+        ram_table.crgb_thresh[7] = cpu_to_be16(0x2384);
+        ram_table.crgb_offset[0] = cpu_to_be16(0x2999);
+        ram_table.crgb_offset[1] = cpu_to_be16(0x3999);
+        ram_table.crgb_offset[2] = cpu_to_be16(0x4666);
+        ram_table.crgb_offset[3] = cpu_to_be16(0x5999);
+        ram_table.crgb_offset[4] = cpu_to_be16(0x6333);
+        ram_table.crgb_offset[5] = cpu_to_be16(0x7800);
+        ram_table.crgb_offset[6] = cpu_to_be16(0x8c00);
+        ram_table.crgb_offset[7] = cpu_to_be16(0xa000);
+        ram_table.crgb_slope[0]  = cpu_to_be16(0x3147);
+        ram_table.crgb_slope[1]  = cpu_to_be16(0x2978);
+        ram_table.crgb_slope[2]  = cpu_to_be16(0x23a2);
+        ram_table.crgb_slope[3]  = cpu_to_be16(0x1f55);
+        ram_table.crgb_slope[4]  = cpu_to_be16(0x1c63);
+        ram_table.crgb_slope[5]  = cpu_to_be16(0x1a0f);
+        ram_table.crgb_slope[6]  = cpu_to_be16(0x178d);
+        ram_table.crgb_slope[7]  = cpu_to_be16(0x15ab);
+
+        fill_backlight_transform_table(
+                        params, &ram_table);
+
+        return dmcu->funcs->load_iram(
+                        dmcu, 0, (char *)(&ram_table), sizeof(ram_table));
+}
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
new file mode 100644
index 000000000000..da5df00fedce
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
@@ -0,0 +1,47 @@
+/* Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef MODULES_POWER_POWER_HELPERS_H_
+#define MODULES_POWER_POWER_HELPERS_H_
+
+#include "dc/inc/hw/dmcu.h"
+
+
+enum abm_defines {
+        abm_defines_max_level = 4,
+        abm_defines_max_config = 4,
+};
+
+struct dmcu_iram_parameters {
+        unsigned int *backlight_lut_array;
+        unsigned int backlight_lut_array_size;
+        unsigned int backlight_ramping_reduction;
+        unsigned int backlight_ramping_start;
+        unsigned int set;
+};
+
+bool dmcu_load_iram(struct dmcu *dmcu,
+                struct dmcu_iram_parameters params);
+
+#endif /* MODULES_POWER_POWER_HELPERS_H_ */
diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/include/amd_acpi.h
index 9b9699fc433f..c72cbfe8f684 100644
--- a/drivers/gpu/drm/amd/include/amd_acpi.h
+++ b/drivers/gpu/drm/amd/include/amd_acpi.h
@@ -52,6 +52,30 @@ struct atif_sbios_requests {
         u8 backlight_level;     /* panel backlight level (0-255) */
 } __packed;
 
+struct atif_qbtc_arguments {
+        u16 size;               /* structure size in bytes (includes size field) */
+        u8 requested_display;   /* which display is requested */
+} __packed;
+
+#define ATIF_QBTC_MAX_DATA_POINTS 99
+
+struct atif_qbtc_data_point {
+        u8 luminance;           /* luminance in percent */
+        u8 ipnut_signal;        /* input signal in range 0-255 */
+} __packed;
+
+struct atif_qbtc_output {
+        u16 size;               /* structure size in bytes (includes size field) */
+        u16 flags;              /* all zeroes */
+        u8 error_code;          /* error code */
+        u8 ac_level;            /* default brightness on AC power */
+        u8 dc_level;            /* default brightness on DC power */
+        u8 min_input_signal;    /* max input signal in range 0-255 */
+        u8 max_input_signal;    /* min input signal in range 0-255 */
+        u8 number_of_points;    /* number of data points */
+        struct atif_qbtc_data_point data_points[ATIF_QBTC_MAX_DATA_POINTS];
+} __packed;
+
 #define ATIF_NOTIFY_MASK        0x3
 #define ATIF_NOTIFY_NONE        0
 #define ATIF_NOTIFY_81          1
@@ -126,26 +150,18 @@ struct atcs_pref_req_output {
  * DWORD - supported functions bit vector
  */
 /* Notifications mask */
-#       define ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED               (1 << 0)
-#       define ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED        (1 << 1)
 #       define ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED         (1 << 2)
 #       define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED    (1 << 3)
 #       define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED   (1 << 4)
-#       define ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED          (1 << 5)
-#       define ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED                (1 << 6)
 #       define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED      (1 << 7)
 #       define ATIF_DGPU_DISPLAY_EVENT_SUPPORTED                   (1 << 8)
+#       define ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST_SUPPORTED      (1 << 12)
 /* supported functions vector */
 #       define ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED               (1 << 0)
 #       define ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED            (1 << 1)
-#       define ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED              (1 << 2)
-#       define ATIF_GET_LID_STATE_SUPPORTED                       (1 << 3)
-#       define ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED           (1 << 4)
-#       define ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED             (1 << 5)
-#       define ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED  (1 << 6)
-#       define ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED    (1 << 7)
 #       define ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED     (1 << 12)
-#       define ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED           (1 << 14)
+#       define ATIF_QUERY_BACKLIGHT_TRANSFER_CHARACTERISTICS_SUPPORTED (1 << 15)
+#       define ATIF_READY_TO_UNDOCK_NOTIFICATION_SUPPORTED        (1 << 16)
 #       define ATIF_GET_EXTERNAL_GPU_INFORMATION_SUPPORTED        (1 << 20)
 #define ATIF_FUNCTION_GET_SYSTEM_PARAMETERS                        0x1
 /* ARG0: ATIF_FUNCTION_GET_SYSTEM_PARAMETERS
@@ -170,6 +186,10 @@ struct atcs_pref_req_output {
  * n (0xd0-0xd9) is specified in notify command code.
  * bit 2:
  * 1 - lid changes not reported though int10
+ * bit 3:
+ * 1 - system bios controls overclocking
+ * bit 4:
+ * 1 - enable overclocking
  */
 #define ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS                     0x2
 /* ARG0: ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS
@@ -177,28 +197,23 @@ struct atcs_pref_req_output {
  * OUTPUT:
  * WORD  - structure size in bytes (includes size field)
  * DWORD - pending sbios requests
- * BYTE  - panel expansion mode
+ * BYTE  - reserved (all zeroes)
  * BYTE  - thermal state: target gfx controller
  * BYTE  - thermal state: state id (0: exit state, non-0: state)
  * BYTE  - forced power state: target gfx controller
- * BYTE  - forced power state: state id
+ * BYTE  - forced power state: state id (0: forced state, non-0: state)
  * BYTE  - system power source
  * BYTE  - panel backlight level (0-255)
+ * BYTE  - GPU package power limit: target gfx controller
+ * DWORD - GPU package power limit: value (24:8 fractional format, Watts)
  */
 /* pending sbios requests */
-#       define ATIF_DISPLAY_SWITCH_REQUEST                         (1 << 0)
-#       define ATIF_EXPANSION_MODE_CHANGE_REQUEST                  (1 << 1)
 #       define ATIF_THERMAL_STATE_CHANGE_REQUEST                   (1 << 2)
 #       define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST              (1 << 3)
 #       define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST             (1 << 4)
-#       define ATIF_DISPLAY_CONF_CHANGE_REQUEST                    (1 << 5)
-#       define ATIF_PX_GFX_SWITCH_REQUEST                          (1 << 6)
 #       define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST                (1 << 7)
 #       define ATIF_DGPU_DISPLAY_EVENT                             (1 << 8)
-/* panel expansion mode */
-#       define ATIF_PANEL_EXPANSION_DISABLE                        0
-#       define ATIF_PANEL_EXPANSION_FULL                           1
-#       define ATIF_PANEL_EXPANSION_ASPECT                         2
+#       define ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST                (1 << 12)
 /* target gfx controller */
 #       define ATIF_TARGET_GFX_SINGLE                              0
 #       define ATIF_TARGET_GFX_PX_IGPU                             1
@@ -208,76 +223,6 @@ struct atcs_pref_req_output {
 #       define ATIF_POWER_SOURCE_DC                                2
 #       define ATIF_POWER_SOURCE_RESTRICTED_AC_1                   3
 #       define ATIF_POWER_SOURCE_RESTRICTED_AC_2                   4
-#define ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS                       0x3
-/* ARG0: ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - selected displays
- * WORD  - connected displays
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - selected displays
- */
-#       define ATIF_LCD1                                           (1 << 0)
-#       define ATIF_CRT1                                           (1 << 1)
-#       define ATIF_TV                                             (1 << 2)
-#       define ATIF_DFP1                                           (1 << 3)
-#       define ATIF_CRT2                                           (1 << 4)
-#       define ATIF_LCD2                                           (1 << 5)
-#       define ATIF_DFP2                                           (1 << 7)
-#       define ATIF_CV                                             (1 << 8)
-#       define ATIF_DFP3                                           (1 << 9)
-#       define ATIF_DFP4                                           (1 << 10)
-#       define ATIF_DFP5                                           (1 << 11)
-#       define ATIF_DFP6                                           (1 << 12)
-#define ATIF_FUNCTION_GET_LID_STATE                                0x4
-/* ARG0: ATIF_FUNCTION_GET_LID_STATE
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - lid state (0: open, 1: closed)
- *
- * GET_LID_STATE only works at boot and resume, for general lid
- * status, use the kernel provided status
- */
-#define ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS                    0x5
-/* ARG0: ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - 0
- * BYTE  - TV standard
- */
-#       define ATIF_TV_STD_NTSC                                    0
-#       define ATIF_TV_STD_PAL                                     1
-#       define ATIF_TV_STD_PALM                                    2
-#       define ATIF_TV_STD_PAL60                                   3
-#       define ATIF_TV_STD_NTSCJ                                   4
-#       define ATIF_TV_STD_PALCN                                   5
-#       define ATIF_TV_STD_PALN                                    6
-#       define ATIF_TV_STD_SCART_RGB                               9
-#define ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS                      0x6
-/* ARG0: ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - 0
- * BYTE  - TV standard
- * OUTPUT: none
- */
-#define ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS           0x7
-/* ARG0: ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - panel expansion mode
- */
-#define ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS             0x8
-/* ARG0: ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - panel expansion mode
- * OUTPUT: none
- */
 #define ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION              0xD
 /* ARG0: ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION
  * ARG1:
@@ -286,21 +231,43 @@ struct atcs_pref_req_output {
  * BYTE  - current temperature (degress Celsius)
  * OUTPUT: none
  */
-#define ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES                    0xF
-/* ARG0: ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES
- * ARG1: none
+#define ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS    0x10
+/* ARG0: ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS
+ * ARG1:
+ * WORD  - structure size in bytes (includes size field)
+ * BYTE  - requested display
  * OUTPUT:
- * WORD  - number of gfx devices
- * WORD  - device structure size in bytes (excludes device size field)
- * DWORD - flags         \
- * WORD  - bus number     } repeated structure
- * WORD  - device number /
+ * WORD  - structure size in bytes (includes size field)
+ * WORD  - flags (currently all 16 bits are reserved)
+ * BYTE  - error code (on failure, disregard all below fields)
+ * BYTE  - AC level (default brightness in percent when machine has full power)
+ * BYTE  - DC level (default brightness in percent when machine is on battery)
+ * BYTE  - min input signal, in range 0-255, corresponding to 0% backlight
+ * BYTE  - max input signal, in range 0-255, corresponding to 100% backlight
+ * BYTE  - number of reported data points
+ * BYTE  - luminance level in percent  \ repeated structure
+ * BYTE  - input signal in range 0-255 / does not have entries for 0% and 100%
+ */
+/* requested display */
+#       define ATIF_QBTC_REQUEST_LCD1                              0
+#       define ATIF_QBTC_REQUEST_CRT1                              1
+#       define ATIF_QBTC_REQUEST_DFP1                              3
+#       define ATIF_QBTC_REQUEST_CRT2                              4
+#       define ATIF_QBTC_REQUEST_LCD2                              5
+#       define ATIF_QBTC_REQUEST_DFP2                              7
+#       define ATIF_QBTC_REQUEST_DFP3                              9
+#       define ATIF_QBTC_REQUEST_DFP4                              10
+#       define ATIF_QBTC_REQUEST_DFP5                              11
+#       define ATIF_QBTC_REQUEST_DFP6                              12
+/* error code */
+#       define ATIF_QBTC_ERROR_CODE_SUCCESS                        0
+#       define ATIF_QBTC_ERROR_CODE_FAILURE                        1
+#       define ATIF_QBTC_ERROR_CODE_DEVICE_NOT_SUPPORTED           2
+#define ATIF_FUNCTION_READY_TO_UNDOCK_NOTIFICATION                 0x11
+/* ARG0: ATIF_FUNCTION_READY_TO_UNDOCK_NOTIFICATION
+ * ARG1: none
+ * OUTPUT: none
  */
-/* flags */
-#       define ATIF_PX_REMOVABLE_GRAPHICS_DEVICE                   (1 << 0)
-#       define ATIF_XGP_PORT                                       (1 << 1)
-#       define ATIF_VGA_ENABLED_GRAPHICS_DEVICE                    (1 << 2)
-#       define ATIF_XGP_PORT_IN_DOCK                               (1 << 3)
 #define ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION                 0x15
 /* ARG0: ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION
  * ARG1: none
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index d6aa1d414320..b68c2e0fef01 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -300,7 +300,7 @@ static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
 
@@ -387,7 +387,7 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
                 return 0;
 
         if (hwmgr->hwmgr_func->get_sclk == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -405,7 +405,7 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
                 return 0;
 
         if (hwmgr->hwmgr_func->get_mclk == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -422,7 +422,7 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
                 return;
 
         if (hwmgr->hwmgr_func->powergate_vce == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -438,7 +438,7 @@ static void pp_dpm_powergate_uvd(void *handle, bool gate)
                 return;
 
         if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -505,7 +505,7 @@ static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
                 return;
 
         if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -522,7 +522,7 @@ static uint32_t pp_dpm_get_fan_control_mode(void *handle)
                 return 0;
 
         if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -540,7 +540,7 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -558,7 +558,7 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
 
@@ -594,7 +594,7 @@ static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -720,7 +720,7 @@ static int pp_dpm_force_clock_level(void *handle,
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->force_clock_level == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
 
@@ -745,7 +745,7 @@ static int pp_dpm_print_clock_levels(void *handle,
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -763,7 +763,7 @@ static int pp_dpm_get_sclk_od(void *handle)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -781,7 +781,7 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
 
@@ -800,7 +800,7 @@ static int pp_dpm_get_mclk_od(void *handle)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -818,7 +818,7 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
         mutex_lock(&hwmgr->smu_lock);
@@ -878,7 +878,7 @@ static int pp_get_power_profile_mode(void *handle, char *buf)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return snprintf(buf, PAGE_SIZE, "\n");
         }
 
@@ -894,7 +894,7 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
                 return ret;
 
         if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return ret;
         }
 
@@ -917,7 +917,7 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return -EINVAL;
         }
 
@@ -935,7 +935,7 @@ static int pp_dpm_switch_power_profile(void *handle,
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return -EINVAL;
         }
 
@@ -972,7 +972,7 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->set_power_limit == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return -EINVAL;
         }
 
@@ -1212,7 +1212,7 @@ static int pp_dpm_powergate_mmhub(void *handle)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->powergate_mmhub == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
 
@@ -1227,7 +1227,7 @@ static int pp_dpm_powergate_gfx(void *handle, bool gate)
                 return 0;
 
         if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return 0;
         }
 
@@ -1242,7 +1242,7 @@ static void pp_dpm_powergate_acp(void *handle, bool gate)
                 return;
 
         if (hwmgr->hwmgr_func->powergate_acp == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return;
         }
 
@@ -1257,7 +1257,7 @@ static void pp_dpm_powergate_sdma(void *handle, bool gate)
                 return;
 
         if (hwmgr->hwmgr_func->powergate_sdma == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return;
         }
 
@@ -1303,7 +1303,7 @@ static int pp_notify_smu_enable_pwe(void *handle)
                 return -EINVAL;
 
         if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) {
-                pr_info("%s was not implemented.\n", __func__);
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
                 return -EINVAL;;
         }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 88f6b35ea6fe..5dcd21d29dbf 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -269,7 +269,7 @@ static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
                                         hwmgr->dyn_state.mvdd_dependency_on_mclk);
 
                 PP_ASSERT_WITH_CODE((0 == result),
-                                "Failed to retrieve SVI2 MVDD table from dependancy table.",
+                                "Failed to retrieve SVI2 MVDD table from dependency table.",
                                 return result;);
         }
 
@@ -288,7 +288,7 @@ static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
                         result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
                                         hwmgr->dyn_state.vddci_dependency_on_mclk);
                 PP_ASSERT_WITH_CODE((0 == result),
-                                "Failed to retrieve SVI2 VDDCI table from dependancy table.",
+                                "Failed to retrieve SVI2 VDDCI table from dependency table.",
                                 return result);
         }
 
@@ -317,7 +317,7 @@ static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
                                 table_info->vddc_lookup_table);
 
                 PP_ASSERT_WITH_CODE((0 == result),
-                        "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;);
+                        "Failed to retrieve SVI2 VDDC table from dependency table.", return result;);
         }
 
         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index fef111ddb736..553a203ac47c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1228,17 +1228,14 @@ static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
 
 static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
 {
-        if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
-                smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);
+        if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
-        }
         return 0;
 }
 
 static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
 {
         if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
-                smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);
                 return smum_send_msg_to_smc_with_parameter(
                         hwmgr,
                         PPSMC_MSG_UVDPowerON,
@@ -1995,6 +1992,7 @@ static const struct pp_hwmgr_func smu8_hwmgr_funcs = {
         .power_state_set = smu8_set_power_state_tasks,
         .dynamic_state_management_disable = smu8_disable_dpm_tasks,
         .notify_cac_buffer_info = smu8_notify_cac_buffer_info,
+        .update_nbdpm_pstate = smu8_nbdpm_pstate_enable_disable,
         .get_thermal_temperature_range = smu8_get_thermal_temperature_range,
 };
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 07d180ce4d18..fb0f96f7cdbc 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -317,6 +317,9 @@ struct pp_hwmgr_func {
                                         uint32_t mc_addr_low,
                                         uint32_t mc_addr_hi,
                                         uint32_t size);
+        int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
+                                        bool enable,
+                                        bool lock);
         int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
                                         struct PP_TemperatureRange *range);
         int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index 86ac33922b09..30a6d1edd5fe 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -433,6 +433,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
                 ret = drm_atomic_set_mode_prop_for_crtc(state, mode);
                 drm_property_blob_put(mode);
                 return ret;
+        } else if (property == config->prop_vrr_enabled) {
+                state->vrr_enabled = val;
         } else if (property == config->degamma_lut_property) {
                 ret = drm_atomic_replace_property_blob_from_id(dev,
                                         &state->degamma_lut,
@@ -491,6 +493,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
                 *val = state->active;
         else if (property == config->prop_mode_id)
                 *val = (state->mode_blob) ? state->mode_blob->base.id : 0;
+        else if (property == config->prop_vrr_enabled)
+                *val = state->vrr_enabled;
         else if (property == config->degamma_lut_property)
                 *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0;
         else if (property == config->ctm_property)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index fa9baacc863b..da8ae80c2750 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1279,6 +1279,105 @@ int drm_mode_create_scaling_mode_property(struct drm_device *dev)
 EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
 
 /**
+ * DOC: Variable refresh properties
+ *
+ * Variable refresh rate capable displays can dynamically adjust their
+ * refresh rate by extending the duration of their vertical front porch
+ * until page flip or timeout occurs. This can reduce or remove stuttering
+ * and latency in scenarios where the page flip does not align with the
+ * vblank interval.
+ *
+ * An example scenario would be an application flipping at a constant rate
+ * of 48Hz on a 60Hz display. The page flip will frequently miss the vblank
+ * interval and the same contents will be displayed twice. This can be
+ * observed as stuttering for content with motion.
+ *
+ * If variable refresh rate was active on a display that supported a
+ * variable refresh range from 35Hz to 60Hz no stuttering would be observable
+ * for the example scenario. The minimum supported variable refresh rate of
+ * 35Hz is below the page flip frequency and the vertical front porch can
+ * be extended until the page flip occurs. The vblank interval will be
+ * directly aligned to the page flip rate.
+ *
+ * Not all userspace content is suitable for use with variable refresh rate.
+ * Large and frequent changes in vertical front porch duration may worsen
+ * perceived stuttering for input sensitive applications.
+ *
+ * Panel brightness will also vary with vertical front porch duration. Some
+ * panels may have noticeable differences in brightness between the minimum
+ * vertical front porch duration and the maximum vertical front porch duration.
+ * Large and frequent changes in vertical front porch duration may produce
+ * observable flickering for such panels.
+ *
+ * Userspace control for variable refresh rate is supported via properties
+ * on the &drm_connector and &drm_crtc objects.
+ *
+ * "vrr_capable":
+ *      Optional &drm_connector boolean property that drivers should attach
+ *      with drm_connector_attach_vrr_capable_property() on connectors that
+ *      could support variable refresh rates. Drivers should update the
+ *      property value by calling drm_connector_set_vrr_capable_property().
+ *
+ *      Absence of the property should indicate absence of support.
+ *
+ * "vrr_enabled":
+ *      Default &drm_crtc boolean property that notifies the driver that the
+ *      content on the CRTC is suitable for variable refresh rate presentation.
+ *      The driver will take this property as a hint to enable variable
+ *      refresh rate support if the receiver supports it, ie. if the
+ *      "vrr_capable" property is true on the &drm_connector object. The
+ *      vertical front porch duration will be extended until page-flip or
+ *      timeout when enabled.
+ *
+ *      The minimum vertical front porch duration is defined as the vertical
+ *      front porch duration for the current mode.
+ *
+ *      The maximum vertical front porch duration is greater than or equal to
+ *      the minimum vertical front porch duration. The duration is derived
+ *      from the minimum supported variable refresh rate for the connector.
+ *
+ *      The driver may place further restrictions within these minimum
+ *      and maximum bounds.
+ *
+ *      The semantics for the vertical blank timestamp differ when
+ *      variable refresh rate is active. The vertical blank timestamp
+ *      is defined to be an estimate using the current mode's fixed
+ *      refresh rate timings. The semantics for the page-flip event
+ *      timestamp remain the same.
+ */
+
+/**
+ * drm_connector_attach_vrr_capable_property - creates the
+ * vrr_capable property
+ * @connector: connector to create the vrr_capable property on.
+ *
+ * This is used by atomic drivers to add support for querying
+ * variable refresh rate capability for a connector.
+ *
+ * Returns:
+ * Zero on success, negative errono on failure.
+ */
+int drm_connector_attach_vrr_capable_property(
+        struct drm_connector *connector)
+{
+        struct drm_device *dev = connector->dev;
+        struct drm_property *prop;
+
+        if (!connector->vrr_capable_property) {
+                prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE,
+                        "vrr_capable");
+                if (!prop)
+                        return -ENOMEM;
+
+                connector->vrr_capable_property = prop;
+                drm_object_attach_property(&connector->base, prop, 0);
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL(drm_connector_attach_vrr_capable_property);
+
+/**
  * drm_connector_attach_scaling_mode_property - attach atomic scaling mode property
  * @connector: connector to attach scaling mode property on.
  * @scaling_mode_mask: or'ed mask of BIT(%DRM_MODE_SCALE_\*).
@@ -1641,6 +1740,24 @@ int drm_connector_attach_max_bpc_property(struct drm_connector *connector,
 EXPORT_SYMBOL(drm_connector_attach_max_bpc_property);
 
 /**
+ * drm_connector_set_vrr_capable_property - sets the variable refresh rate
+ * capable property for a connector
+ * @connector: drm connector
+ * @capable: True if the connector is variable refresh rate capable
+ *
+ * Should be used by atomic drivers to update the indicated support for
+ * variable refresh rate over a connector.
+ */
+void drm_connector_set_vrr_capable_property(
+                struct drm_connector *connector, bool capable)
+{
+        drm_object_property_set_value(&connector->base,
+                                      connector->vrr_capable_property,
+                                      capable);
+}
+EXPORT_SYMBOL(drm_connector_set_vrr_capable_property);
+
+/**
  * drm_connector_init_panel_orientation_property -
  *      initialize the connecters panel_orientation property
  * @connector: connector for which to init the panel-orientation property.
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 268a182ae189..6f8ddfcfaba5 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -340,6 +340,8 @@ int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc,
                 drm_object_attach_property(&crtc->base, config->prop_mode_id, 0);
                 drm_object_attach_property(&crtc->base,
                                            config->prop_out_fence_ptr, 0);
+                drm_object_attach_property(&crtc->base,
+                                           config->prop_vrr_enabled, 0);
         }
 
         return 0;
diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c
index ee80788f2c40..5670c67f28d4 100644
--- a/drivers/gpu/drm/drm_mode_config.c
+++ b/drivers/gpu/drm/drm_mode_config.c
@@ -310,6 +310,12 @@ static int drm_mode_create_standard_properties(struct drm_device *dev)
                 return -ENOMEM;
         dev->mode_config.prop_mode_id = prop;
 
+        prop = drm_property_create_bool(dev, 0,
+                        "VRR_ENABLED");
+        if (!prop)
+                return -ENOMEM;
+        dev->mode_config.prop_vrr_enabled = prop;
+
         prop = drm_property_create(dev,
                         DRM_MODE_PROP_BLOB,
                         "DEGAMMA_LUT", 0);
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
index fed11ece0de6..a3d2ca07a058 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -946,7 +946,7 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
                 bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE;
 
         if (mem) {
-                addr = mem->start << PAGE_SHIFT;
+                addr = (u64)mem->start << PAGE_SHIFT;
                 if (mem->mem_type != TTM_PL_SYSTEM) {
                         bo_va->flags |= RADEON_VM_PAGE_VALID;
                 }
diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
index 18ebbb05762e..9d4cd196037a 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -60,6 +60,8 @@
 
 static void drm_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb);
 
+static void drm_sched_expel_job_unlocked(struct drm_sched_job *s_job);
+
 /**
  * drm_sched_rq_init - initialize a given run queue struct
  *
@@ -228,7 +230,7 @@ static void drm_sched_job_finish(struct work_struct *work)
 
         spin_lock(&sched->job_list_lock);
         /* remove job from ring_mirror_list */
-        list_del(&s_job->node);
+        list_del_init(&s_job->node);
         /* queue TDR for next job */
         drm_sched_start_timeout(sched);
         spin_unlock(&sched->job_list_lock);
@@ -261,40 +263,15 @@ static void drm_sched_job_timedout(struct work_struct *work)
 {
         struct drm_gpu_scheduler *sched;
         struct drm_sched_job *job;
-        int r;
 
         sched = container_of(work, struct drm_gpu_scheduler, work_tdr.work);
-
-        spin_lock(&sched->job_list_lock);
-        list_for_each_entry_reverse(job, &sched->ring_mirror_list, node) {
-                struct drm_sched_fence *fence = job->s_fence;
-
-                if (!dma_fence_remove_callback(fence->parent, &fence->cb))
-                        goto already_signaled;
-        }
-
         job = list_first_entry_or_null(&sched->ring_mirror_list,
                                        struct drm_sched_job, node);
-        spin_unlock(&sched->job_list_lock);
 
         if (job)
-                sched->ops->timedout_job(job);
+                job->sched->ops->timedout_job(job);
 
         spin_lock(&sched->job_list_lock);
-        list_for_each_entry(job, &sched->ring_mirror_list, node) {
-                struct drm_sched_fence *fence = job->s_fence;
-
-                if (!fence->parent || !list_empty(&fence->cb.node))
-                        continue;
-
-                r = dma_fence_add_callback(fence->parent, &fence->cb,
-                                           drm_sched_process_job);
-                if (r)
-                        drm_sched_process_job(fence->parent, &fence->cb);
-
-already_signaled:
-                ;
-        }
         drm_sched_start_timeout(sched);
         spin_unlock(&sched->job_list_lock);
 }
@@ -391,6 +368,8 @@ void drm_sched_job_recovery(struct drm_gpu_scheduler *sched)
                                           r);
                         dma_fence_put(fence);
                 } else {
+                        if (s_fence->finished.error < 0)
+                                drm_sched_expel_job_unlocked(s_job);
                         drm_sched_process_job(NULL, &s_fence->cb);
                 }
                 spin_lock(&sched->job_list_lock);
@@ -595,6 +574,8 @@ static int drm_sched_main(void *param)
                                           r);
                         dma_fence_put(fence);
                 } else {
+                        if (s_fence->finished.error < 0)
+                                drm_sched_expel_job_unlocked(sched_job);
                         drm_sched_process_job(NULL, &s_fence->cb);
                 }
 
@@ -603,6 +584,15 @@ static int drm_sched_main(void *param)
         return 0;
 }
 
+static void drm_sched_expel_job_unlocked(struct drm_sched_job *s_job)
+{
+        struct drm_gpu_scheduler *sched = s_job->sched;
+
+        spin_lock(&sched->job_list_lock);
+        list_del_init(&s_job->node);
+        spin_unlock(&sched->job_list_lock);
+}
+
 /**
  * drm_sched_init - Init a gpu scheduler instance
  *
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index ba80150d1052..895d77d799e4 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -492,8 +492,10 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo,
         if (!fbo)
                 return -ENOMEM;
 
-        ttm_bo_get(bo);
         fbo->base = *bo;
+        fbo->base.mem.placement |= TTM_PL_FLAG_NO_EVICT;
+
+        ttm_bo_get(bo);
         fbo->bo = bo;
 
         /**
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 665b9cae7f43..9be2181b3ed7 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -972,6 +972,17 @@ struct drm_connector {
         struct drm_property *scaling_mode_property;
 
         /**
+         * @vrr_capable_property: Optional property to help userspace
+         * query hardware support for variable refresh rate on a connector.
+         * connector. Drivers can add the property to a connector by
+         * calling drm_connector_attach_vrr_capable_property().
+         *
+         * This should be updated only by calling
+         * drm_connector_set_vrr_capable_property().
+         */
+        struct drm_property *vrr_capable_property;
+
+        /**
          * @content_protection_property: DRM ENUM property for content
          * protection. See drm_connector_attach_content_protection_property().
          */
@@ -1245,6 +1256,8 @@ int drm_mode_create_scaling_mode_property(struct drm_device *dev);
 int drm_connector_attach_content_type_property(struct drm_connector *dev);
 int drm_connector_attach_scaling_mode_property(struct drm_connector *connector,
                                                u32 scaling_mode_mask);
+int drm_connector_attach_vrr_capable_property(
+                struct drm_connector *connector);
 int drm_connector_attach_content_protection_property(
                 struct drm_connector *connector);
 int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
@@ -1261,6 +1274,8 @@ int drm_connector_update_edid_property(struct drm_connector *connector,
                                        const struct edid *edid);
 void drm_connector_set_link_status_property(struct drm_connector *connector,
                                             uint64_t link_status);
+void drm_connector_set_vrr_capable_property(
+                struct drm_connector *connector, bool capable);
 int drm_connector_init_panel_orientation_property(
         struct drm_connector *connector, int width, int height);
 int drm_connector_attach_max_bpc_property(struct drm_connector *connector,
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index b21437bc95bf..39c3900aab3c 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -291,6 +291,15 @@ struct drm_crtc_state {
         u32 pageflip_flags;
 
         /**
+         * @vrr_enabled:
+         *
+         * Indicates if variable refresh rate should be enabled for the CRTC.
+         * Support for the requested vrr state will depend on driver and
+         * hardware capabiltiy - lacking support is not treated as failure.
+         */
+        bool vrr_enabled;
+
+        /**
          * @event:
          *
          * Optional pointer to a DRM event to signal upon completion of the
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index 5dbeabdbaf91..9db59a1caf5b 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -645,6 +645,11 @@ struct drm_mode_config {
          * connectors must be of and active must be set to disabled, too.
          */
         struct drm_property *prop_mode_id;
+        /**
+         * @prop_vrr_enabled: Default atomic CRTC property to indicate
+         * whether variable refresh rate should be enabled on the CRTC.
+         */
+        struct drm_property *prop_vrr_enabled;
 
         /**
          * @dvi_i_subconnector_property: Optional DVI-I property to